Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : rv_plic_reg_top
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.38 100.00 70.00 99.52 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_rv_plic_0/rtl/rv_plic_reg_top.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.top_earlgrey.u_rv_plic.u_reg 92.38 100.00 70.00 99.52 100.00

Line Coverage for Module : rv_plic_reg_top
Line No.TotalCoveredPercent
TOTAL15601560100.00
ALWAYS6844100.00
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CONT_ASSIGN1659311100.00
CONT_ASSIGN1662711100.00
CONT_ASSIGN1664111100.00
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WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_rv_plic_0/rtl/rv_plic_reg_top.sv' or '../src/lowrisc_opentitan_top_earlgrey_rv_plic_0/rtl/rv_plic_reg_top.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
68 1 1
69 1 1
70 1 1
71 1 1
MISSING_ELSE
77 1 1
89 1 1
90 1 1
118 1 1
119 1 1
16579 1 1
16593 1 1
16627 1 1
16641 1 1
16647 1 1
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16650 1 1
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19314 1 1
19315 1 1
19316 1 1
19317 1 1
19318 1 1
19319 1 1
19320 1 1
19321 1 1
19322 1 1
19323 1 1
19324 1 1
19325 1 1
19326 1 1
19327 1 1
19328 1 1
19329 1 1
19330 1 1
19331 1 1
19332 1 1
19333 1 1
19334 1 1
19335 1 1
19336 1 1
19337 1 1
19338 1 1
19339 1 1
19340 1 1
19341 1 1
19342 1 1
19343 1 1
19347 1 1
19348 1 1
19349 1 1
19350 1 1
19351 1 1
19352 1 1
19353 1 1
19354 1 1
19355 1 1
19356 1 1
19357 1 1
19358 1 1
19359 1 1
19360 1 1
19361 1 1
19362 1 1
19363 1 1
19364 1 1
19365 1 1
19366 1 1
19367 1 1
19368 1 1
19369 1 1
19370 1 1
19371 1 1
19372 1 1
19376 1 1
19380 1 1
19384 1 1
19388 1 1
19402 unreachable
19410 1 1
19411 1 1


Cond Coverage for Module : rv_plic_reg_top
TotalCoveredPercent
Conditions2023141670.00
Logical2023141670.00
Non-Logical00
Event00

This module contains a very large number of conditions, so the report has been split into multiple pages, by source line number. Click on the line number range in the table below to see the condition coverage for that section of the module.
Line numbersPercent
58-1683898.48
16839-1685644.58
16856-1726370.80
17266-1800875.00

Branch Coverage for Module : rv_plic_reg_top
Line No.TotalCoveredPercent
Branches 208 207 99.52
TERNARY 16852 2 2 100.00
IF 68 3 3 100.00
CASE 18222 203 202 99.51

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_rv_plic_0/rtl/rv_plic_reg_top.sv' or '../src/lowrisc_opentitan_top_earlgrey_rv_plic_0/rtl/rv_plic_reg_top.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 16852 ((reg_re || reg_we)) ?

Branches:
-1-StatusTests
1 Covered T6,T20,T21
0 Covered T4,T5,T6


LineNo. Expression -1-: 68 if ((!rst_ni)) -2-: 70 if ((intg_err || reg_we_err))

Branches:
-1--2-StatusTests
1 - Covered T4,T5,T6
0 1 Covered T389,T390,T391
0 0 Covered T4,T5,T6


LineNo. Expression -1-: 18222 case (1'b1)

Branches:
-1-StatusTests
addr_hit[0] Covered T6,T20,T21
addr_hit[1] Covered T20,T21,T132
addr_hit[2] Covered T20,T21,T132
addr_hit[3] Covered T20,T21,T132
addr_hit[4] Covered T20,T21,T132
addr_hit[5] Covered T20,T21,T132
addr_hit[6] Covered T20,T21,T132
addr_hit[7] Covered T20,T21,T132
addr_hit[8] Covered T20,T21,T132
addr_hit[9] Covered T20,T21,T132
addr_hit[10] Covered T271,T299,T170
addr_hit[11] Covered T271,T299,T170
addr_hit[12] Covered T271,T299,T170
addr_hit[13] Covered T271,T299,T170
addr_hit[14] Covered T271,T299,T170
addr_hit[15] Covered T271,T299,T170
addr_hit[16] Covered T271,T299,T170
addr_hit[17] Covered T271,T299,T170
addr_hit[18] Covered T271,T299,T170
addr_hit[19] Covered T82,T271,T170
addr_hit[20] Covered T82,T271,T170
addr_hit[21] Covered T82,T271,T170
addr_hit[22] Covered T82,T271,T170
addr_hit[23] Covered T82,T271,T170
addr_hit[24] Covered T82,T271,T170
addr_hit[25] Covered T82,T271,T170
addr_hit[26] Covered T82,T271,T170
addr_hit[27] Covered T82,T271,T170
addr_hit[28] Covered T6,T45,T271
addr_hit[29] Covered T6,T45,T271
addr_hit[30] Covered T6,T45,T271
addr_hit[31] Covered T6,T45,T271
addr_hit[32] Covered T6,T45,T271
addr_hit[33] Covered T6,T45,T271
addr_hit[34] Covered T6,T45,T271
addr_hit[35] Covered T6,T45,T271
addr_hit[36] Covered T6,T45,T271
addr_hit[37] Covered T271,T170,T157
addr_hit[38] Covered T271,T170,T157
addr_hit[39] Covered T271,T170,T157
addr_hit[40] Covered T271,T170,T157
addr_hit[41] Covered T271,T170,T157
addr_hit[42] Covered T271,T170,T157
addr_hit[43] Covered T271,T170,T157
addr_hit[44] Covered T271,T170,T157
addr_hit[45] Covered T271,T170,T157
addr_hit[46] Covered T271,T170,T157
addr_hit[47] Covered T271,T170,T157
addr_hit[48] Covered T271,T170,T157
addr_hit[49] Covered T271,T170,T157
addr_hit[50] Covered T271,T170,T157
addr_hit[51] Covered T271,T170,T157
addr_hit[52] Covered T271,T170,T157
addr_hit[53] Covered T271,T170,T157
addr_hit[54] Covered T271,T170,T157
addr_hit[55] Covered T271,T170,T157
addr_hit[56] Covered T271,T170,T157
addr_hit[57] Covered T271,T170,T157
addr_hit[58] Covered T271,T170,T157
addr_hit[59] Covered T271,T170,T157
addr_hit[60] Covered T271,T170,T157
addr_hit[61] Covered T271,T170,T157
addr_hit[62] Covered T271,T170,T157
addr_hit[63] Covered T271,T170,T157
addr_hit[64] Covered T271,T170,T157
addr_hit[65] Covered T271,T170,T157
addr_hit[66] Covered T271,T170,T157
addr_hit[67] Covered T271,T170,T157
addr_hit[68] Covered T271,T170,T157
addr_hit[69] Covered T271,T170,T157
addr_hit[70] Covered T271,T170,T157
addr_hit[71] Covered T271,T170,T157
addr_hit[72] Covered T271,T170,T157
addr_hit[73] Covered T271,T170,T157
addr_hit[74] Covered T271,T170,T157
addr_hit[75] Covered T271,T170,T157
addr_hit[76] Covered T271,T170,T157
addr_hit[77] Covered T271,T170,T157
addr_hit[78] Covered T271,T170,T157
addr_hit[79] Covered T271,T170,T157
addr_hit[80] Covered T271,T170,T157
addr_hit[81] Covered T271,T170,T157
addr_hit[82] Covered T271,T170,T157
addr_hit[83] Covered T271,T170,T157
addr_hit[84] Covered T271,T170,T157
addr_hit[85] Covered T271,T170,T157
addr_hit[86] Covered T271,T170,T157
addr_hit[87] Covered T271,T170,T157
addr_hit[88] Covered T271,T170,T157
addr_hit[89] Covered T271,T170,T157
addr_hit[90] Covered T271,T170,T157
addr_hit[91] Covered T271,T170,T157
addr_hit[92] Covered T271,T170,T157
addr_hit[93] Covered T271,T170,T157
addr_hit[94] Covered T271,T170,T157
addr_hit[95] Covered T271,T170,T157
addr_hit[96] Covered T271,T170,T157
addr_hit[97] Covered T271,T170,T157
addr_hit[98] Covered T271,T170,T157
addr_hit[99] Covered T271,T170,T157
addr_hit[100] Covered T271,T170,T157
addr_hit[101] Covered T228,T271,T170
addr_hit[102] Covered T228,T271,T170
addr_hit[103] Covered T271,T170,T157
addr_hit[104] Covered T228,T271,T170
addr_hit[105] Covered T228,T271,T170
addr_hit[106] Covered T228,T271,T170
addr_hit[107] Covered T271,T170,T157
addr_hit[108] Covered T271,T170,T157
addr_hit[109] Covered T271,T170,T157
addr_hit[110] Covered T271,T170,T157
addr_hit[111] Covered T271,T170,T157
addr_hit[112] Covered T271,T170,T157
addr_hit[113] Covered T271,T170,T157
addr_hit[114] Covered T271,T170,T157
addr_hit[115] Covered T271,T170,T157
addr_hit[116] Covered T271,T170,T157
addr_hit[117] Covered T271,T170,T157
addr_hit[118] Covered T271,T170,T157
addr_hit[119] Covered T271,T170,T157
addr_hit[120] Covered T271,T170,T157
addr_hit[121] Covered T271,T170,T157
addr_hit[122] Covered T271,T170,T157
addr_hit[123] Covered T271,T170,T157
addr_hit[124] Covered T271,T170,T157
addr_hit[125] Covered T271,T170,T157
addr_hit[126] Covered T271,T170,T157
addr_hit[127] Covered T17,T19,T31
addr_hit[128] Covered T17,T19,T31
addr_hit[129] Covered T17,T19,T31
addr_hit[130] Covered T17,T19,T31
addr_hit[131] Covered T271,T170,T157
addr_hit[132] Covered T271,T170,T157
addr_hit[133] Covered T271,T170,T157
addr_hit[134] Covered T271,T170,T157
addr_hit[135] Covered T271,T170,T157
addr_hit[136] Covered T271,T170,T157
addr_hit[137] Covered T271,T170,T157
addr_hit[138] Covered T271,T170,T157
addr_hit[139] Covered T271,T170,T157
addr_hit[140] Covered T271,T170,T157
addr_hit[141] Covered T271,T170,T157
addr_hit[142] Covered T271,T170,T157
addr_hit[143] Covered T271,T170,T157
addr_hit[144] Covered T271,T170,T157
addr_hit[145] Covered T271,T170,T157
addr_hit[146] Covered T271,T170,T157
addr_hit[147] Covered T271,T170,T157
addr_hit[148] Covered T271,T170,T157
addr_hit[149] Covered T271,T170,T157
addr_hit[150] Covered T271,T170,T157
addr_hit[151] Covered T271,T170,T157
addr_hit[152] Covered T271,T170,T157
addr_hit[153] Covered T90,T344,T345
addr_hit[154] Covered T271,T170,T157
addr_hit[155] Covered T271,T170,T157
addr_hit[156] Covered T17,T19,T31
addr_hit[157] Covered T17,T19,T31
addr_hit[158] Covered T271,T170,T157
addr_hit[159] Covered T271,T170,T157
addr_hit[160] Covered T91,T271,T170
addr_hit[161] Covered T91,T271,T170
addr_hit[162] Covered T91,T271,T170
addr_hit[163] Covered T91,T271,T170
addr_hit[164] Covered T91,T271,T170
addr_hit[165] Covered T271,T170,T157
addr_hit[166] Covered T171,T172,T173
addr_hit[167] Covered T171,T172,T173
addr_hit[168] Covered T271,T170,T157
addr_hit[169] Covered T271,T170,T157
addr_hit[170] Covered T271,T170,T157
addr_hit[171] Covered T271,T170,T157
addr_hit[172] Covered T271,T170,T157
addr_hit[173] Covered T271,T170,T157
addr_hit[174] Covered T271,T170,T157
addr_hit[175] Covered T271,T170,T157
addr_hit[176] Covered T271,T170,T157
addr_hit[177] Covered T271,T170,T157
addr_hit[178] Covered T271,T170,T157
addr_hit[179] Covered T271,T170,T157
addr_hit[180] Covered T271,T170,T157
addr_hit[181] Covered T271,T170,T157
addr_hit[182] Covered T271,T170,T157
addr_hit[183] Covered T271,T170,T157
addr_hit[184] Covered T271,T170,T157
addr_hit[185] Covered T271,T170,T157
addr_hit[186] Covered T28
addr_hit[187] Covered T28
addr_hit[188] Covered T28
addr_hit[189] Covered T28
addr_hit[190] Covered T28,T392,T393
addr_hit[191] Covered T28
addr_hit[192] Covered T6,T20,T21
addr_hit[193] Covered T6,T45,T271
addr_hit[194] Covered T271,T170,T157
addr_hit[195] Covered T17,T19,T31
addr_hit[196] Covered T17,T19,T31
addr_hit[197] Covered T91,T171,T172
addr_hit[198] Covered T6,T20,T21
addr_hit[199] Covered T6,T20,T21
addr_hit[200] Covered T271,T272,T28
addr_hit[201] Covered T28,T123,T124
default Not Covered


Assert Coverage for Module : rv_plic_reg_top
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
en2addrHit 470097304 35308 0 0
reAfterRv 470097304 35308 0 0
rePulse 470097304 14401 0 0
wePulse 470097304 20907 0 0


en2addrHit
NameAttemptsReal SuccessesFailuresIncomplete
Total 470097304 35308 0 0
T6 197158 46 0 0
T17 221235 44 0 0
T18 219998 0 0 0
T19 261468 44 0 0
T20 218705 46 0 0
T21 663418 48 0 0
T31 261526 44 0 0
T82 0 48 0 0
T91 217010 110 0 0
T101 193763 0 0 0
T132 212915 46 0 0
T228 0 19 0 0

reAfterRv
NameAttemptsReal SuccessesFailuresIncomplete
Total 470097304 35308 0 0
T6 197158 46 0 0
T17 221235 44 0 0
T18 219998 0 0 0
T19 261468 44 0 0
T20 218705 46 0 0
T21 663418 48 0 0
T31 261526 44 0 0
T82 0 48 0 0
T91 217010 110 0 0
T101 193763 0 0 0
T132 212915 46 0 0
T228 0 19 0 0

rePulse
NameAttemptsReal SuccessesFailuresIncomplete
Total 470097304 14401 0 0
T6 197158 18 0 0
T17 221235 14 0 0
T18 219998 0 0 0
T19 261468 14 0 0
T20 218705 18 0 0
T21 663418 19 0 0
T31 261526 14 0 0
T82 0 19 0 0
T91 217010 52 0 0
T101 193763 0 0 0
T132 212915 18 0 0
T228 0 7 0 0

wePulse
NameAttemptsReal SuccessesFailuresIncomplete
Total 470097304 20907 0 0
T6 197158 28 0 0
T17 221235 30 0 0
T18 219998 0 0 0
T19 261468 30 0 0
T20 218705 28 0 0
T21 663418 29 0 0
T31 261526 30 0 0
T82 0 29 0 0
T91 217010 58 0 0
T101 193763 0 0 0
T132 212915 28 0 0
T228 0 12 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%