Module Definition
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Module : prim_mubi4_sync
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_por_scanmode_sync 100.00 100.00



Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_por_scanmode_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.83 99.34 100.00 100.00 100.00 u_pinmux_strap_sampling


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Assert Coverage for Module : prim_mubi4_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 992 992 0 0
OutputsKnown_A 117723188 117066068 0 0
gen_no_flops.OutputDelay_A 117723188 117066068 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 992 992 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0
T19 1 1 0 0
T20 1 1 0 0
T21 1 1 0 0
T91 1 1 0 0
T132 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 117723188 117066068 0 0
T4 323164 322582 0 0
T5 12018 11213 0 0
T6 48177 47689 0 0
T17 54365 53833 0 0
T18 54140 53551 0 0
T19 64088 63494 0 0
T20 53509 52859 0 0
T21 160005 159597 0 0
T91 58261 57822 0 0
T132 51963 51468 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 117723188 117066068 0 0
T4 323164 322582 0 0
T5 12018 11213 0 0
T6 48177 47689 0 0
T17 54365 53833 0 0
T18 54140 53551 0 0
T19 64088 63494 0 0
T20 53509 52859 0 0
T21 160005 159597 0 0
T91 58261 57822 0 0
T132 51963 51468 0 0

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_por_scanmode_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
NumCopiesMustBeGreaterZero_A 992 992 0 0
OutputsKnown_A 117723188 117066068 0 0
gen_no_flops.OutputDelay_A 117723188 117066068 0 0


NumCopiesMustBeGreaterZero_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 992 992 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0
T19 1 1 0 0
T20 1 1 0 0
T21 1 1 0 0
T91 1 1 0 0
T132 1 1 0 0

OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 117723188 117066068 0 0
T4 323164 322582 0 0
T5 12018 11213 0 0
T6 48177 47689 0 0
T17 54365 53833 0 0
T18 54140 53551 0 0
T19 64088 63494 0 0
T20 53509 52859 0 0
T21 160005 159597 0 0
T91 58261 57822 0 0
T132 51963 51468 0 0

gen_no_flops.OutputDelay_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 117723188 117066068 0 0
T4 323164 322582 0 0
T5 12018 11213 0 0
T6 48177 47689 0 0
T17 54365 53833 0 0
T18 54140 53551 0 0
T19 64088 63494 0 0
T20 53509 52859 0 0
T21 160005 159597 0 0
T91 58261 57822 0 0
T132 51963 51468 0 0

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