Unified Coverage Report :: Module :: prim_reg_cdc

Module : prim_reg_cdc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.25	100.00	89.01			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_1_cdc	44.06	45.45	30.77			50.00	50.00
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_2_cdc	44.06	45.45	30.77			50.00	50.00
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_3_cdc	44.06	45.45	30.77			50.00	50.00
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_6_cdc	44.06	45.45	30.77			50.00	50.00
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_1_cdc	45.45	45.45	36.36			50.00	50.00
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_2_cdc	45.45	45.45	36.36			50.00	50.00
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_3_cdc	45.45	45.45	36.36			50.00	50.00
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_6_cdc	45.45	45.45	36.36			50.00	50.00
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_0_cdc	45.45	45.45	36.36			50.00	50.00
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_2_cdc	45.45	45.45	36.36			50.00	50.00
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_3_cdc	45.45	45.45	36.36			50.00	50.00
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_4_cdc	45.45	45.45	36.36			50.00	50.00
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_5_cdc	45.45	45.45	36.36			50.00	50.00
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_6_cdc	45.45	45.45	36.36			50.00	50.00
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_7_cdc	45.45	45.45	36.36			50.00	50.00
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_0_cdc	95.45	90.91	90.91			100.00	100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_7_cdc	95.45	90.91	90.91			100.00	100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_cause_cdc	96.43	100.00	85.71			100.00	100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_4_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_5_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_1_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_0_cdc	98.08	100.00	92.31			100.00	100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_4_cdc	98.08	100.00	92.31			100.00	100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_5_cdc	98.08	100.00	92.31			100.00	100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_7_cdc	98.08	100.00	92.31			100.00	100.00

Line Coverage for Module : prim_reg_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Module : prim_reg_cdc ( parameter DataWidth=2,ResetVal=0,BitMask=3,DstWrReq=0,TxnWidth=3 + DataWidth=11,ResetVal=0,BitMask=1793,DstWrReq=1,TxnWidth=3 + DataWidth=4,ResetVal=9,BitMask=15,DstWrReq=1,TxnWidth=3 + DataWidth=20,ResetVal,BitMask=1048575,DstWrReq=0,TxnWidth=3 + DataWidth=18,ResetVal=118010,BitMask=262143,DstWrReq=0,TxnWidth=3 + DataWidth=16,ResetVal,BitMask=65535,DstWrReq=0,TxnWidth=3 + DataWidth=12,ResetVal=0,BitMask=4095,DstWrReq=0,TxnWidth=3 + DataWidth=8,ResetVal,BitMask=255,DstWrReq=0,TxnWidth=3 + DataWidth=14,ResetVal=0,BitMask=16383,DstWrReq=0,TxnWidth=3 + DataWidth=17,ResetVal=2000,BitMask=131071,DstWrReq=0,TxnWidth=3 + DataWidth=7,ResetVal=0,BitMask=119,DstWrReq=0,TxnWidth=3 + DataWidth=5,ResetVal=0,BitMask=31,DstWrReq=0,TxnWidth=3 + DataWidth=32,ResetVal,BitMask,DstWrReq=0,TxnWidth=3 + DataWidth=4,ResetVal=0,BitMask=15,DstWrReq=0,TxnWidth=3 + DataWidth=28,ResetVal=0,BitMask=268374015,DstWrReq=1,TxnWidth=3 + DataWidth=9,ResetVal=0,BitMask=511,DstWrReq=0,TxnWidth=3 + DataWidth=9,ResetVal=0,BitMask=511,DstWrReq=1,TxnWidth=3 + DataWidth=5,ResetVal=0,BitMask=31,DstWrReq=1,TxnWidth=3 + DataWidth=6,ResetVal=0,BitMask=63,DstWrReq=0,TxnWidth=3 + DataWidth=8,ResetVal=0,BitMask=255,DstWrReq=1,TxnWidth=3 + DataWidth=13,ResetVal=0,BitMask=8191,DstWrReq=0,TxnWidth=3 + DataWidth=32,ResetVal=0,BitMask=-1,DstWrReq=1,TxnWidth=3 )
Cond Coverage for Module self-instances :

SCORE	COND
45.45	36.36

tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_0_cdc

SCORE	COND
97.73	90.91

tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_1_cdc

SCORE	COND
45.45	36.36

tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_2_cdc

SCORE	COND
45.45	36.36

tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_3_cdc

SCORE	COND
45.45	36.36

tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_4_cdc

SCORE	COND
45.45	36.36

tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_5_cdc

SCORE	COND
45.45	36.36

tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_6_cdc

SCORE	COND
45.45	36.36

tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_7_cdc

SCORE	COND
95.45	90.91

tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_0_cdc

SCORE	COND
45.45	36.36

tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_1_cdc

SCORE	COND
45.45	36.36

tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_2_cdc

SCORE	COND
45.45	36.36

tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_3_cdc

SCORE	COND
97.73	90.91

tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_4_cdc

SCORE	COND
97.73	90.91

tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_5_cdc

SCORE	COND
45.45	36.36

tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_6_cdc

SCORE	COND
95.45	90.91

tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_7_cdc

SCORE	COND
96.43	85.71

tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_cause_cdc

	Total	Covered	Percent
Conditions	14	12	85.71
Logical	14	12	85.71
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T8,T1,T2

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T8,T1,T2
1	1	Covered	T8,T1,T2

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T1,T2,T3
1	0	Covered	T8,T1,T2

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T8,T1,T2
1	1	Covered	T8,T1,T2

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Cond Coverage for Module : prim_reg_cdc ( parameter DataWidth=1,ResetVal=0,BitMask=1,DstWrReq=0,TxnWidth=3 + DataWidth=1,ResetVal=0,BitMask=1,DstWrReq=1,TxnWidth=3 )
Cond Coverage for Module self-instances :

SCORE	COND
98.08	92.31

tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_0_cdc

SCORE	COND
44.06	30.77

tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_1_cdc

SCORE	COND
44.06	30.77

tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_2_cdc

SCORE	COND
44.06	30.77

tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_3_cdc

SCORE	COND
98.08	92.31

tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_4_cdc

SCORE	COND
98.08	92.31

tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_5_cdc

SCORE	COND
44.06	30.77

tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_6_cdc

SCORE	COND
98.08	92.31

tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_7_cdc

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       123
 EXPRESSION (src_wd_i & BitMask)
             ----1---   ---2---

-1-	-2-	Status	Tests
0	-	Covered	T1,T2,T3
1	-	Covered	T1,T2,T3

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Module : prim_reg_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T8,T1,T2
0	0	1	Covered	T8,T1,T2
0	0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T8,T1,T2
0	0	1	Covered	T8,T1,T2
0	0	0	Covered	T4,T5,T6

---

Assert Coverage for Module : prim_reg_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	2147483647	33106	0	0
DstReqKnown_A	36905075	32172050	0	0
SrcAckBusyChk_A	2147483647	93	0	0
SrcBusyKnown_A	2147483647	2147483647	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	33106	0	0
T1	0	1144	0	0
T2	0	1461	0	0
T3	186060	1625	0	0
T7	0	1622	0	0
T8	0	344	0	0
T9	0	304	0	0
T10	0	338	0	0
T11	45335	2906	0	0
T12	0	2842	0	0
T13	0	935	0	0
T14	20173	1071	0	0
T15	0	3763	0	0
T16	0	3156	0	0
T111	59747	0	0	0
T126	0	1540	0	0
T142	0	1533	0	0
T143	0	2205	0	0
T199	124087	0	0	0
T238	80647	0	0	0
T273	23465	0	0	0
T296	64487	0	0	0
T370	58556	0	0	0
T424	0	3621	0	0
T425	0	1002	0	0
T426	20334	0	0	0
T427	100263	0	0	0
T428	21754	0	0	0
T429	56359	0	0	0
T430	19876	0	0	0
T431	50955	0	0	0
T432	161984	0	0	0
T433	313046	0	0	0
T434	67612	0	0	0
T435	66886	0	0	0
T436	246622	0	0	0
T437	41434	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36905075	32172050	0	0
T4	72625	68325	0	0
T5	6725	2425	0	0
T6	15925	11625	0	0
T17	20100	15725	0	0
T18	18450	14150	0	0
T19	20850	16525	0	0
T20	16175	11825	0	0
T21	39450	35125	0	0
T91	18025	13700	0	0
T132	16750	12400	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	93	0	0
T1	0	3	0	0
T2	0	3	0	0
T3	186060	5	0	0
T7	0	5	0	0
T8	0	1	0	0
T9	0	1	0	0
T10	0	1	0	0
T11	45335	8	0	0
T12	0	8	0	0
T13	0	3	0	0
T14	20173	3	0	0
T15	0	10	0	0
T16	0	10	0	0
T111	59747	0	0	0
T126	0	5	0	0
T142	0	5	0	0
T143	0	5	0	0
T199	124087	0	0	0
T238	80647	0	0	0
T273	23465	0	0	0
T296	64487	0	0	0
T370	58556	0	0	0
T424	0	10	0	0
T425	0	3	0	0
T426	20334	0	0	0
T427	100263	0	0	0
T428	21754	0	0	0
T429	56359	0	0	0
T430	19876	0	0	0
T431	50955	0	0	0
T432	161984	0	0	0
T433	313046	0	0	0
T434	67612	0	0	0
T435	66886	0	0	0
T436	246622	0	0	0
T437	41434	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T4	8079100	8064550	0	0
T5	300450	280325	0	0
T6	1204425	1192225	0	0
T17	1359125	1345825	0	0
T18	1353500	1338775	0	0
T19	1602200	1587350	0	0
T20	1337725	1321475	0	0
T21	4000125	3989925	0	0
T91	1456525	1445550	0	0
T132	1299075	1286700	0	0