SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
91.90 | 80.00 | 100.00 | 95.71 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
tb.dut | 92.83 | 80.00 | 100.00 | 98.48 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
92.83 | 80.00 | 100.00 | 98.48 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
86.97 | 90.77 | 80.03 | 90.28 | 92.11 | 81.66 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
tb |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
top_earlgrey | 85.77 | 90.59 | 78.43 | 90.19 | 91.78 | 77.87 | |
u_ast | 86.67 | 86.67 | |||||
u_padring | 99.04 | 99.21 | 99.81 | 96.57 | 99.60 | 100.00 | |
u_prim_usb_diff_rx | 96.30 | 100.00 | 88.89 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 25 | 20 | 80.00 | |
CONT_ASSIGN | 282 | 1 | 1 | 100.00 |
CONT_ASSIGN | 283 | 1 | 1 | 100.00 |
CONT_ASSIGN | 857 | 1 | 0 | 0.00 |
CONT_ASSIGN | 870 | 1 | 0 | 0.00 |
CONT_ASSIGN | 899 | 1 | 0 | 0.00 |
CONT_ASSIGN | 907 | 1 | 0 | 0.00 |
CONT_ASSIGN | 914 | 1 | 1 | 100.00 |
CONT_ASSIGN | 917 | 1 | 1 | 100.00 |
CONT_ASSIGN | 923 | 1 | 1 | 100.00 |
CONT_ASSIGN | 925 | 1 | 1 | 100.00 |
CONT_ASSIGN | 929 | 1 | 0 | 0.00 |
CONT_ASSIGN | 932 | 1 | 1 | 100.00 |
CONT_ASSIGN | 1097 | 1 | 1 | 100.00 |
CONT_ASSIGN | 1098 | 1 | 1 | 100.00 |
CONT_ASSIGN | 1099 | 1 | 1 | 100.00 |
CONT_ASSIGN | 1100 | 1 | 1 | 100.00 |
CONT_ASSIGN | 1107 | 1 | 1 | 100.00 |
CONT_ASSIGN | 1124 | 1 | 1 | 100.00 |
CONT_ASSIGN | 1125 | 1 | 1 | 100.00 |
CONT_ASSIGN | 1126 | 1 | 1 | 100.00 |
CONT_ASSIGN | 1127 | 1 | 1 | 100.00 |
CONT_ASSIGN | 1131 | 1 | 1 | 100.00 |
CONT_ASSIGN | 1132 | 1 | 1 | 100.00 |
CONT_ASSIGN | 1133 | 1 | 1 | 100.00 |
CONT_ASSIGN | 1134 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
282 | 1 | 1 | |
283 | 1 | 1 | |
857 | 0 | 1 | |
870 | 0 | 1 | |
899 | 0 | 1 | |
907 | 0 | 1 | |
914 | 1 | 1 | |
917 | 1 | 1 | |
923 | 1 | 1 | |
925 | 1 | 1 | |
929 | 0 | 1 | |
932 | 1 | 1 | |
1097 | 1 | 1 | |
1098 | 1 | 1 | |
1099 | 1 | 1 | |
1100 | 1 | 1 | |
1107 | 1 | 1 | |
1124 | 1 | 1 | |
1125 | 1 | 1 | |
1126 | 1 | 1 | |
1127 | 1 | 1 | |
1131 | 1 | 1 | |
1132 | 1 | 1 | |
1133 | 1 | 1 | |
1134 | 1 | 1 |
Total | Covered | Percent | |
---|---|---|---|
Conditions | 2 | 2 | 100.00 |
Logical | 2 | 2 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 |
LINE 79 EXPRESSION (tb.dut.top_earlgrey.u_pwrmgr_aon.pwr_rst_o.reset_cause == LowPwrEntry) -----------------------------------1-----------------------------------
-1- | Status | Tests |
---|---|---|
0 | Covered | T4,T5,T6 |
1 | Covered | T90,T344,T249 |
Total | Covered | Percent | |
---|---|---|---|
Totals | 70 | 64 | 91.43 |
Total Bits | 140 | 134 | 95.71 |
Total Bits 0->1 | 70 | 70 | 100.00 |
Total Bits 1->0 | 70 | 64 | 91.43 |
Ports | 70 | 64 | 91.43 |
Port Bits | 140 | 134 | 95.71 |
Port Bits 0->1 | 70 | 70 | 100.00 |
Port Bits 1->0 | 70 | 64 | 91.43 |
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
POR_N | Yes | Yes | T36,T37,T38 | Yes | T4,T5,T6 | INOUT |
USB_P | Yes | Yes | T47,T49,T119 | Yes | T47,T49,T119 | INOUT |
USB_N | Yes | Yes | T47,T49,T1 | Yes | T47,T49,T1 | INOUT |
CC1 | No | No | Yes | T39,T40,T41 | INOUT | |
CC2 | No | No | Yes | T39,T40,T41 | INOUT | |
FLASH_TEST_VOLT | No | No | Yes | T39,T40,T41 | INOUT | |
FLASH_TEST_MODE0 | No | No | Yes | T39,T40,T41 | INOUT | |
FLASH_TEST_MODE1 | No | No | Yes | T39,T40,T41 | INOUT | |
OTP_EXT_VOLT | No | No | Yes | T39,T40,T41 | INOUT | |
SPI_HOST_D0 | Yes | Yes | T42,T43,T44 | Yes | T42,T43,T44 | INOUT |
SPI_HOST_D1 | Yes | Yes | T42,T43,T44 | Yes | T42,T43,T44 | INOUT |
SPI_HOST_D2 | Yes | Yes | T42,T43,T155 | Yes | T42,T43,T155 | INOUT |
SPI_HOST_D3 | Yes | Yes | T42,T43,T155 | Yes | T42,T43,T155 | INOUT |
SPI_HOST_CLK | Yes | Yes | T42,T43,T44 | Yes | T42,T43,T44 | INOUT |
SPI_HOST_CS_L | Yes | Yes | T42,T43,T44 | Yes | T39,T42,T43 | INOUT |
SPI_DEV_D0 | Yes | Yes | T38,T83,T81 | Yes | T38,T83,T81 | INOUT |
SPI_DEV_D1 | Yes | Yes | T38,T83,T81 | Yes | T38,T83,T81 | INOUT |
SPI_DEV_D2 | Yes | Yes | T42,T43,T155 | Yes | T42,T43,T155 | INOUT |
SPI_DEV_D3 | Yes | Yes | T42,T43,T155 | Yes | T42,T43,T155 | INOUT |
SPI_DEV_CLK | Yes | Yes | T38,T83,T81 | Yes | T38,T83,T81 | INOUT |
SPI_DEV_CS_L | Yes | Yes | T38,T83,T81 | Yes | T38,T83,T81 | INOUT |
IOR8 | Yes | Yes | T51,T256,T40 | Yes | T1,T2,T51 | INOUT |
IOR9 | Yes | Yes | T51,T256,T52 | Yes | T67,T1,T68 | INOUT |
IOA0 | Yes | Yes | T6,T45,T46 | Yes | T6,T45,T46 | INOUT |
IOA1 | Yes | Yes | T6,T45,T46 | Yes | T6,T45,T46 | INOUT |
IOA2 | Yes | Yes | T46,T56,T57 | Yes | T46,T39,T56 | INOUT |
IOA3 | Yes | Yes | T46,T56,T57 | Yes | T46,T56,T57 | INOUT |
IOA4 | Yes | Yes | T82,T46,T56 | Yes | T82,T46,T39 | INOUT |
IOA5 | Yes | Yes | T82,T46,T56 | Yes | T82,T46,T56 | INOUT |
IOA6 | Yes | Yes | T46,T56,T57 | Yes | T46,T56,T57 | INOUT |
IOA7 | Yes | Yes | T46,T70,T56 | Yes | T46,T70,T56 | INOUT |
IOA8 | Yes | Yes | T46,T56,T233 | Yes | T46,T56,T233 | INOUT |
IOB0 | Yes | Yes | T65,T66,T60 | Yes | T39,T65,T41 | INOUT |
IOB1 | Yes | Yes | T65,T66,T60 | Yes | T39,T65,T66 | INOUT |
IOB2 | Yes | Yes | T60,T61,T62 | Yes | T60,T61,T62 | INOUT |
IOB3 | Yes | Yes | T51,T256,T52 | Yes | T256,T40,T52 | INOUT |
IOB4 | Yes | Yes | T299,T300,T348 | Yes | T299,T300,T39 | INOUT |
IOB5 | Yes | Yes | T299,T300,T348 | Yes | T299,T300,T348 | INOUT |
IOB6 | Yes | Yes | T46,T56,T57 | Yes | T46,T56,T57 | INOUT |
IOB7 | Yes | Yes | T46,T56,T57 | Yes | T46,T67,T56 | INOUT |
IOB8 | Yes | Yes | T46,T56,T57 | Yes | T46,T56,T57 | INOUT |
IOB9 | Yes | Yes | T228,T46,T229 | Yes | T228,T46,T229 | INOUT |
IOB10 | Yes | Yes | T228,T46,T313 | Yes | T228,T46,T313 | INOUT |
IOB11 | Yes | Yes | T46,T313,T56 | Yes | T46,T313,T56 | INOUT |
IOB12 | Yes | Yes | T46,T313,T56 | Yes | T46,T313,T56 | INOUT |
IOC0 | Yes | Yes | T4,T76,T38 | Yes | T38,T73,T83 | INOUT |
IOC1 | Yes | Yes | T38,T83,T81 | Yes | T38,T83,T81 | INOUT |
IOC2 | Yes | Yes | T38,T83,T81 | Yes | T38,T83,T81 | INOUT |
IOC3 | Yes | Yes | T20,T21,T132 | Yes | T20,T21,T132 | INOUT |
IOC4 | Yes | Yes | T4,T20,T21 | Yes | T4,T20,T21 | INOUT |
IOC5 | Yes | Yes | T248,T30,T128 | Yes | T248,T30,T128 | INOUT |
IOC6 | Yes | Yes | T5,T82,T36 | Yes | T5,T82,T36 | INOUT |
IOC7 | Yes | Yes | T256,T52,T53 | Yes | T47,T49,T51 | INOUT |
IOC8 | Yes | Yes | T248,T30,T128 | Yes | T248,T30,T128 | INOUT |
IOC9 | Yes | Yes | T46,T67,T56 | Yes | T46,T67,T56 | INOUT |
IOC10 | Yes | Yes | T46,T313,T56 | Yes | T46,T313,T39 | INOUT |
IOC11 | Yes | Yes | T46,T313,T56 | Yes | T46,T313,T56 | INOUT |
IOC12 | Yes | Yes | T46,T313,T56 | Yes | T46,T313,T56 | INOUT |
IOR0 | Yes | Yes | T5,T36,T80 | Yes | T5,T36,T80 | INOUT |
IOR1 | Yes | Yes | T5,T36,T80 | Yes | T5,T36,T80 | INOUT |
IOR2 | Yes | Yes | T5,T36,T80 | Yes | T5,T36,T80 | INOUT |
IOR3 | Yes | Yes | T5,T36,T80 | Yes | T5,T36,T80 | INOUT |
IOR4 | Yes | Yes | T36,T78,T79 | Yes | T5,T36,T80 | INOUT |
IOR5 | Yes | Yes | T46,T56,T57 | Yes | T46,T39,T56 | INOUT |
IOR6 | Yes | Yes | T46,T56,T57 | Yes | T46,T56,T57 | INOUT |
IOR7 | Yes | Yes | T46,T56,T57 | Yes | T46,T56,T57 | INOUT |
IOR10 | Yes | Yes | T46,T56,T57 | Yes | T46,T39,T56 | INOUT |
IOR11 | Yes | Yes | T46,T56,T57 | Yes | T46,T56,T57 | INOUT |
IOR12 | Yes | Yes | T46,T56,T57 | Yes | T46,T56,T57 | INOUT |
IOR13 | Yes | Yes | T46,T56,T351 | Yes | T46,T56,T351 | INOUT |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 25 | 20 | 80.00 | |
CONT_ASSIGN | 282 | 1 | 1 | 100.00 |
CONT_ASSIGN | 283 | 1 | 1 | 100.00 |
CONT_ASSIGN | 857 | 1 | 0 | 0.00 |
CONT_ASSIGN | 870 | 1 | 0 | 0.00 |
CONT_ASSIGN | 899 | 1 | 0 | 0.00 |
CONT_ASSIGN | 907 | 1 | 0 | 0.00 |
CONT_ASSIGN | 914 | 1 | 1 | 100.00 |
CONT_ASSIGN | 917 | 1 | 1 | 100.00 |
CONT_ASSIGN | 923 | 1 | 1 | 100.00 |
CONT_ASSIGN | 925 | 1 | 1 | 100.00 |
CONT_ASSIGN | 929 | 1 | 0 | 0.00 |
CONT_ASSIGN | 932 | 1 | 1 | 100.00 |
CONT_ASSIGN | 1097 | 1 | 1 | 100.00 |
CONT_ASSIGN | 1098 | 1 | 1 | 100.00 |
CONT_ASSIGN | 1099 | 1 | 1 | 100.00 |
CONT_ASSIGN | 1100 | 1 | 1 | 100.00 |
CONT_ASSIGN | 1107 | 1 | 1 | 100.00 |
CONT_ASSIGN | 1124 | 1 | 1 | 100.00 |
CONT_ASSIGN | 1125 | 1 | 1 | 100.00 |
CONT_ASSIGN | 1126 | 1 | 1 | 100.00 |
CONT_ASSIGN | 1127 | 1 | 1 | 100.00 |
CONT_ASSIGN | 1131 | 1 | 1 | 100.00 |
CONT_ASSIGN | 1132 | 1 | 1 | 100.00 |
CONT_ASSIGN | 1133 | 1 | 1 | 100.00 |
CONT_ASSIGN | 1134 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
282 | 1 | 1 | |
283 | 1 | 1 | |
857 | 0 | 1 | |
870 | 0 | 1 | |
899 | 0 | 1 | |
907 | 0 | 1 | |
914 | 1 | 1 | |
917 | 1 | 1 | |
923 | 1 | 1 | |
925 | 1 | 1 | |
929 | 0 | 1 | |
932 | 1 | 1 | |
1097 | 1 | 1 | |
1098 | 1 | 1 | |
1099 | 1 | 1 | |
1100 | 1 | 1 | |
1107 | 1 | 1 | |
1124 | 1 | 1 | |
1125 | 1 | 1 | |
1126 | 1 | 1 | |
1127 | 1 | 1 | |
1131 | 1 | 1 | |
1132 | 1 | 1 | |
1133 | 1 | 1 | |
1134 | 1 | 1 |
Total | Covered | Percent | |
---|---|---|---|
Conditions | 2 | 2 | 100.00 |
Logical | 2 | 2 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 |
LINE 79 EXPRESSION (tb.dut.top_earlgrey.u_pwrmgr_aon.pwr_rst_o.reset_cause == LowPwrEntry) -----------------------------------1-----------------------------------
-1- | Status | Tests |
---|---|---|
0 | Covered | T4,T5,T6 |
1 | Covered | T90,T344,T249 |
Total | Covered | Percent | |
---|---|---|---|
Totals | 66 | 64 | 96.97 |
Total Bits | 132 | 130 | 98.48 |
Total Bits 0->1 | 66 | 66 | 100.00 |
Total Bits 1->0 | 66 | 64 | 96.97 |
Ports | 66 | 64 | 96.97 |
Port Bits | 132 | 130 | 98.48 |
Port Bits 0->1 | 66 | 66 | 100.00 |
Port Bits 1->0 | 66 | 64 | 96.97 |
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction | Exclude Annotation |
POR_N | Yes | Yes | T36,T37,T38 | Yes | T4,T5,T6 | INOUT | |
USB_P | Yes | Yes | T47,T49,T119 | Yes | T47,T49,T119 | INOUT | |
USB_N | Yes | Yes | T47,T49,T1 | Yes | T47,T49,T1 | INOUT | |
CC1 | No | No | Yes | T39,T40,T41 | INOUT | ||
CC2 | No | No | Yes | T39,T40,T41 | INOUT | ||
FLASH_TEST_VOLT[0:0] | Excluded | Excluded | Excluded | INOUT | [LOW_RISK] Covered via connectivity. Cannot be covered in open source DV due to behavioral models of AST and flash. Must be covered in vendor closed source DV. | ||
FLASH_TEST_MODE0[0:0] | Excluded | Excluded | Excluded | INOUT | [LOW_RISK] Covered via connectivity. Cannot be covered in open source DV due to behavioral models of AST and flash. Must be covered in vendor closed source DV. | ||
FLASH_TEST_MODE1[0:0] | Excluded | Excluded | Excluded | INOUT | [LOW_RISK] Covered via connectivity. Cannot be covered in open source DV due to behavioral models of AST and flash. Must be covered in vendor closed source DV. | ||
OTP_EXT_VOLT[0:0] | Excluded | Excluded | Excluded | INOUT | [LOW_RISK] Covered via connectivity. Cannot be covered in open source DV due to behavioral models of AST and OTP. Must be covered in vendor closed source DV. | ||
SPI_HOST_D0 | Yes | Yes | T42,T43,T44 | Yes | T42,T43,T44 | INOUT | |
SPI_HOST_D1 | Yes | Yes | T42,T43,T44 | Yes | T42,T43,T44 | INOUT | |
SPI_HOST_D2 | Yes | Yes | T42,T43,T155 | Yes | T42,T43,T155 | INOUT | |
SPI_HOST_D3 | Yes | Yes | T42,T43,T155 | Yes | T42,T43,T155 | INOUT | |
SPI_HOST_CLK | Yes | Yes | T42,T43,T44 | Yes | T42,T43,T44 | INOUT | |
SPI_HOST_CS_L | Yes | Yes | T42,T43,T44 | Yes | T39,T42,T43 | INOUT | |
SPI_DEV_D0 | Yes | Yes | T38,T83,T81 | Yes | T38,T83,T81 | INOUT | |
SPI_DEV_D1 | Yes | Yes | T38,T83,T81 | Yes | T38,T83,T81 | INOUT | |
SPI_DEV_D2 | Yes | Yes | T42,T43,T155 | Yes | T42,T43,T155 | INOUT | |
SPI_DEV_D3 | Yes | Yes | T42,T43,T155 | Yes | T42,T43,T155 | INOUT | |
SPI_DEV_CLK | Yes | Yes | T38,T83,T81 | Yes | T38,T83,T81 | INOUT | |
SPI_DEV_CS_L | Yes | Yes | T38,T83,T81 | Yes | T38,T83,T81 | INOUT | |
IOR8 | Yes | Yes | T51,T256,T40 | Yes | T1,T2,T51 | INOUT | |
IOR9 | Yes | Yes | T51,T256,T52 | Yes | T67,T1,T68 | INOUT | |
IOA0 | Yes | Yes | T6,T45,T46 | Yes | T6,T45,T46 | INOUT | |
IOA1 | Yes | Yes | T6,T45,T46 | Yes | T6,T45,T46 | INOUT | |
IOA2 | Yes | Yes | T46,T56,T57 | Yes | T46,T39,T56 | INOUT | |
IOA3 | Yes | Yes | T46,T56,T57 | Yes | T46,T56,T57 | INOUT | |
IOA4 | Yes | Yes | T82,T46,T56 | Yes | T82,T46,T39 | INOUT | |
IOA5 | Yes | Yes | T82,T46,T56 | Yes | T82,T46,T56 | INOUT | |
IOA6 | Yes | Yes | T46,T56,T57 | Yes | T46,T56,T57 | INOUT | |
IOA7 | Yes | Yes | T46,T70,T56 | Yes | T46,T70,T56 | INOUT | |
IOA8 | Yes | Yes | T46,T56,T233 | Yes | T46,T56,T233 | INOUT | |
IOB0 | Yes | Yes | T65,T66,T60 | Yes | T39,T65,T41 | INOUT | |
IOB1 | Yes | Yes | T65,T66,T60 | Yes | T39,T65,T66 | INOUT | |
IOB2 | Yes | Yes | T60,T61,T62 | Yes | T60,T61,T62 | INOUT | |
IOB3 | Yes | Yes | T51,T256,T52 | Yes | T256,T40,T52 | INOUT | |
IOB4 | Yes | Yes | T299,T300,T348 | Yes | T299,T300,T39 | INOUT | |
IOB5 | Yes | Yes | T299,T300,T348 | Yes | T299,T300,T348 | INOUT | |
IOB6 | Yes | Yes | T46,T56,T57 | Yes | T46,T56,T57 | INOUT | |
IOB7 | Yes | Yes | T46,T56,T57 | Yes | T46,T67,T56 | INOUT | |
IOB8 | Yes | Yes | T46,T56,T57 | Yes | T46,T56,T57 | INOUT | |
IOB9 | Yes | Yes | T228,T46,T229 | Yes | T228,T46,T229 | INOUT | |
IOB10 | Yes | Yes | T228,T46,T313 | Yes | T228,T46,T313 | INOUT | |
IOB11 | Yes | Yes | T46,T313,T56 | Yes | T46,T313,T56 | INOUT | |
IOB12 | Yes | Yes | T46,T313,T56 | Yes | T46,T313,T56 | INOUT | |
IOC0 | Yes | Yes | T4,T76,T38 | Yes | T38,T73,T83 | INOUT | |
IOC1 | Yes | Yes | T38,T83,T81 | Yes | T38,T83,T81 | INOUT | |
IOC2 | Yes | Yes | T38,T83,T81 | Yes | T38,T83,T81 | INOUT | |
IOC3 | Yes | Yes | T20,T21,T132 | Yes | T20,T21,T132 | INOUT | |
IOC4 | Yes | Yes | T4,T20,T21 | Yes | T4,T20,T21 | INOUT | |
IOC5 | Yes | Yes | T248,T30,T128 | Yes | T248,T30,T128 | INOUT | |
IOC6 | Yes | Yes | T5,T82,T36 | Yes | T5,T82,T36 | INOUT | |
IOC7 | Yes | Yes | T256,T52,T53 | Yes | T47,T49,T51 | INOUT | |
IOC8 | Yes | Yes | T248,T30,T128 | Yes | T248,T30,T128 | INOUT | |
IOC9 | Yes | Yes | T46,T67,T56 | Yes | T46,T67,T56 | INOUT | |
IOC10 | Yes | Yes | T46,T313,T56 | Yes | T46,T313,T39 | INOUT | |
IOC11 | Yes | Yes | T46,T313,T56 | Yes | T46,T313,T56 | INOUT | |
IOC12 | Yes | Yes | T46,T313,T56 | Yes | T46,T313,T56 | INOUT | |
IOR0 | Yes | Yes | T5,T36,T80 | Yes | T5,T36,T80 | INOUT | |
IOR1 | Yes | Yes | T5,T36,T80 | Yes | T5,T36,T80 | INOUT | |
IOR2 | Yes | Yes | T5,T36,T80 | Yes | T5,T36,T80 | INOUT | |
IOR3 | Yes | Yes | T5,T36,T80 | Yes | T5,T36,T80 | INOUT | |
IOR4 | Yes | Yes | T36,T78,T79 | Yes | T5,T36,T80 | INOUT | |
IOR5 | Yes | Yes | T46,T56,T57 | Yes | T46,T39,T56 | INOUT | |
IOR6 | Yes | Yes | T46,T56,T57 | Yes | T46,T56,T57 | INOUT | |
IOR7 | Yes | Yes | T46,T56,T57 | Yes | T46,T56,T57 | INOUT | |
IOR10 | Yes | Yes | T46,T56,T57 | Yes | T46,T39,T56 | INOUT | |
IOR11 | Yes | Yes | T46,T56,T57 | Yes | T46,T56,T57 | INOUT | |
IOR12 | Yes | Yes | T46,T56,T57 | Yes | T46,T56,T57 | INOUT | |
IOR13 | Yes | Yes | T46,T56,T351 | Yes | T46,T56,T351 | INOUT |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |