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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
86.33 90.77 80.03 90.28 92.11 81.66 83.11


Total test records in report: 992
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T582 /workspace/coverage/default/2.chip_sw_hmac_enc_idle.103995970 Jul 01 01:24:49 PM PDT 24 Jul 01 01:28:46 PM PDT 24 2653754768 ps
T397 /workspace/coverage/default/1.rom_e2e_asm_init_dev.2015844862 Jul 01 01:25:40 PM PDT 24 Jul 01 02:32:36 PM PDT 24 15773483665 ps
T198 /workspace/coverage/default/0.chip_sw_otp_ctrl_escalation.4055138467 Jul 01 01:04:56 PM PDT 24 Jul 01 01:14:23 PM PDT 24 4211457798 ps
T75 /workspace/coverage/default/1.rom_e2e_shutdown_exception_c.3570812097 Jul 01 01:22:27 PM PDT 24 Jul 01 02:26:36 PM PDT 24 14607430740 ps
T68 /workspace/coverage/default/2.chip_sw_sysrst_ctrl_ulp_z3_wakeup.1428096055 Jul 01 01:22:13 PM PDT 24 Jul 01 01:32:17 PM PDT 24 5367220550 ps
T583 /workspace/coverage/default/0.chip_sw_entropy_src_ast_rng_req.1134647005 Jul 01 01:05:54 PM PDT 24 Jul 01 01:11:08 PM PDT 24 2994440160 ps
T233 /workspace/coverage/default/2.chip_sw_i2c_host_tx_rx.2781014417 Jul 01 01:21:55 PM PDT 24 Jul 01 01:33:41 PM PDT 24 4965525150 ps
T318 /workspace/coverage/default/1.chip_sw_keymgr_sideload_kmac.972296888 Jul 01 01:13:41 PM PDT 24 Jul 01 01:58:55 PM PDT 24 11786834712 ps
T584 /workspace/coverage/default/2.chip_sw_aes_enc_jitter_en_reduced_freq.1472308707 Jul 01 01:28:07 PM PDT 24 Jul 01 01:32:31 PM PDT 24 2926242329 ps
T585 /workspace/coverage/default/0.chip_sw_hmac_enc.1440648243 Jul 01 01:08:12 PM PDT 24 Jul 01 01:13:18 PM PDT 24 2968013020 ps
T476 /workspace/coverage/default/26.chip_sw_all_escalation_resets.216065633 Jul 01 01:35:26 PM PDT 24 Jul 01 01:45:26 PM PDT 24 4267773916 ps
T411 /workspace/coverage/default/0.chip_sw_edn_entropy_reqs.2501261489 Jul 01 01:06:23 PM PDT 24 Jul 01 01:27:37 PM PDT 24 6333956036 ps
T586 /workspace/coverage/default/1.chip_sw_otp_ctrl_smoketest.3901008843 Jul 01 01:20:30 PM PDT 24 Jul 01 01:24:31 PM PDT 24 2270263060 ps
T587 /workspace/coverage/default/0.chip_sw_clkmgr_jitter_frequency.3594178022 Jul 01 01:04:40 PM PDT 24 Jul 01 01:11:25 PM PDT 24 3126129128 ps
T474 /workspace/coverage/default/43.chip_sw_all_escalation_resets.951812319 Jul 01 01:35:57 PM PDT 24 Jul 01 01:45:18 PM PDT 24 5152317480 ps
T588 /workspace/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.2670142828 Jul 01 01:06:04 PM PDT 24 Jul 01 01:24:34 PM PDT 24 6863550576 ps
T589 /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_rma.3938315887 Jul 01 01:08:48 PM PDT 24 Jul 01 01:33:32 PM PDT 24 7929812992 ps
T590 /workspace/coverage/default/0.rom_e2e_asm_init_dev.1242345563 Jul 01 01:11:01 PM PDT 24 Jul 01 02:33:21 PM PDT 24 15321063289 ps
T224 /workspace/coverage/default/1.chip_sw_all_escalation_resets.3326896538 Jul 01 01:06:48 PM PDT 24 Jul 01 01:19:48 PM PDT 24 5155340690 ps
T591 /workspace/coverage/default/1.chip_sw_entropy_src_ast_rng_req.1665835650 Jul 01 01:12:53 PM PDT 24 Jul 01 01:15:49 PM PDT 24 2860014198 ps
T479 /workspace/coverage/default/85.chip_sw_all_escalation_resets.1267274833 Jul 01 01:40:44 PM PDT 24 Jul 01 01:50:58 PM PDT 24 5421847882 ps
T33 /workspace/coverage/default/1.chip_sw_alert_handler_entropy.3175066504 Jul 01 01:13:42 PM PDT 24 Jul 01 01:19:31 PM PDT 24 3518251423 ps
T592 /workspace/coverage/default/2.rom_keymgr_functest.783199954 Jul 01 01:29:40 PM PDT 24 Jul 01 01:40:29 PM PDT 24 3919603332 ps
T412 /workspace/coverage/default/0.chip_sw_kmac_entropy.1324216229 Jul 01 01:05:55 PM PDT 24 Jul 01 01:10:31 PM PDT 24 2846801800 ps
T593 /workspace/coverage/default/1.chip_sw_pwrmgr_wdog_reset.1583073246 Jul 01 01:14:23 PM PDT 24 Jul 01 01:21:28 PM PDT 24 3805334842 ps
T486 /workspace/coverage/default/70.chip_sw_alert_handler_lpg_sleep_mode_alerts.849094757 Jul 01 01:39:35 PM PDT 24 Jul 01 01:44:56 PM PDT 24 3190590240 ps
T322 /workspace/coverage/default/2.chip_sw_keymgr_sideload_otbn.3229346547 Jul 01 01:28:10 PM PDT 24 Jul 01 02:36:22 PM PDT 24 18816767994 ps
T594 /workspace/coverage/default/13.chip_sw_all_escalation_resets.2112840160 Jul 01 01:34:13 PM PDT 24 Jul 01 01:43:32 PM PDT 24 5913865396 ps
T595 /workspace/coverage/default/0.chip_sw_lc_ctrl_transition.1945669245 Jul 01 01:03:52 PM PDT 24 Jul 01 01:26:11 PM PDT 24 10581085390 ps
T333 /workspace/coverage/default/79.chip_sw_alert_handler_lpg_sleep_mode_alerts.2656876787 Jul 01 01:40:29 PM PDT 24 Jul 01 01:46:51 PM PDT 24 4276609160 ps
T596 /workspace/coverage/default/2.chip_sw_keymgr_sideload_kmac.2378667020 Jul 01 01:24:07 PM PDT 24 Jul 01 01:56:07 PM PDT 24 9695629584 ps
T351 /workspace/coverage/default/0.chip_sw_pwrmgr_b2b_sleep_reset_req.668751598 Jul 01 01:04:13 PM PDT 24 Jul 01 01:41:00 PM PDT 24 29156045731 ps
T597 /workspace/coverage/default/2.chip_sw_uart_tx_rx_idx3.2842960387 Jul 01 01:19:51 PM PDT 24 Jul 01 01:31:56 PM PDT 24 4429149340 ps
T598 /workspace/coverage/default/0.chip_sw_lc_walkthrough_prodend.2474682272 Jul 01 01:05:13 PM PDT 24 Jul 01 01:25:32 PM PDT 24 10613935854 ps
T599 /workspace/coverage/default/2.chip_sw_aon_timer_sleep_wdog_sleep_pause.3211736231 Jul 01 01:25:49 PM PDT 24 Jul 01 01:35:23 PM PDT 24 7629542428 ps
T600 /workspace/coverage/default/1.chip_sw_otbn_smoketest.1561321561 Jul 01 01:18:47 PM PDT 24 Jul 01 02:00:52 PM PDT 24 11176699880 ps
T230 /workspace/coverage/default/2.chip_sw_rstmgr_alert_info.2650762988 Jul 01 01:23:37 PM PDT 24 Jul 01 01:47:45 PM PDT 24 8783332956 ps
T515 /workspace/coverage/default/67.chip_sw_alert_handler_lpg_sleep_mode_alerts.2557681452 Jul 01 01:38:29 PM PDT 24 Jul 01 01:45:07 PM PDT 24 3775509600 ps
T379 /workspace/coverage/default/2.chip_sw_rstmgr_rst_cnsty_escalation.643061152 Jul 01 01:19:25 PM PDT 24 Jul 01 01:28:17 PM PDT 24 5564688864 ps
T57 /workspace/coverage/default/1.chip_sw_gpio_smoketest.4107385221 Jul 01 01:20:05 PM PDT 24 Jul 01 01:23:15 PM PDT 24 2738452414 ps
T601 /workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.1074264545 Jul 01 01:13:43 PM PDT 24 Jul 01 01:36:58 PM PDT 24 11241379086 ps
T602 /workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq.1393437944 Jul 01 01:09:23 PM PDT 24 Jul 01 01:19:03 PM PDT 24 3561788964 ps
T603 /workspace/coverage/default/1.rom_keymgr_functest.160811130 Jul 01 01:18:58 PM PDT 24 Jul 01 01:27:11 PM PDT 24 3670031488 ps
T334 /workspace/coverage/default/74.chip_sw_all_escalation_resets.3560544783 Jul 01 01:40:28 PM PDT 24 Jul 01 01:48:46 PM PDT 24 4699484532 ps
T604 /workspace/coverage/default/1.chip_sw_csrng_kat_test.3966433955 Jul 01 01:12:34 PM PDT 24 Jul 01 01:16:22 PM PDT 24 2606540672 ps
T210 /workspace/coverage/default/1.chip_sw_lc_ctrl_program_error.243786209 Jul 01 01:17:05 PM PDT 24 Jul 01 01:25:29 PM PDT 24 4199838228 ps
T2 /workspace/coverage/default/0.chip_sw_sleep_pin_wake.4060895116 Jul 01 01:03:28 PM PDT 24 Jul 01 01:09:07 PM PDT 24 3232330250 ps
T444 /workspace/coverage/default/2.chip_sw_lc_walkthrough_testunlocks.3341828104 Jul 01 01:24:46 PM PDT 24 Jul 01 02:08:07 PM PDT 24 22833315000 ps
T445 /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.3526401922 Jul 01 01:25:34 PM PDT 24 Jul 01 01:50:26 PM PDT 24 13521030771 ps
T446 /workspace/coverage/default/15.chip_sw_all_escalation_resets.373110796 Jul 01 01:33:25 PM PDT 24 Jul 01 01:49:07 PM PDT 24 4995467976 ps
T447 /workspace/coverage/default/2.chip_sw_flash_ctrl_idle_low_power.699273200 Jul 01 01:21:50 PM PDT 24 Jul 01 01:28:13 PM PDT 24 3279624860 ps
T448 /workspace/coverage/default/0.chip_sw_flash_ctrl_access.3171806062 Jul 01 01:09:30 PM PDT 24 Jul 01 01:27:13 PM PDT 24 5753624136 ps
T9 /workspace/coverage/default/0.chip_rv_dm_ndm_reset_req.341697705 Jul 01 01:06:09 PM PDT 24 Jul 01 01:15:38 PM PDT 24 3743559368 ps
T449 /workspace/coverage/default/2.chip_sw_otbn_smoketest.2890368375 Jul 01 01:30:27 PM PDT 24 Jul 01 02:03:43 PM PDT 24 10244443520 ps
T450 /workspace/coverage/default/1.chip_sw_entropy_src_kat_test.4204418247 Jul 01 01:13:26 PM PDT 24 Jul 01 01:18:07 PM PDT 24 2693297660 ps
T400 /workspace/coverage/default/2.chip_sw_rv_core_ibex_lockstep_glitch.2445134836 Jul 01 01:28:53 PM PDT 24 Jul 01 01:31:22 PM PDT 24 3237881824 ps
T605 /workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_reset_reqs.1221488275 Jul 01 01:25:27 PM PDT 24 Jul 01 02:02:20 PM PDT 24 21039521134 ps
T606 /workspace/coverage/default/3.chip_sw_lc_ctrl_transition.3955200869 Jul 01 01:30:51 PM PDT 24 Jul 01 01:41:22 PM PDT 24 7115443958 ps
T607 /workspace/coverage/default/1.chip_sw_edn_auto_mode.1609124220 Jul 01 01:12:04 PM PDT 24 Jul 01 01:34:10 PM PDT 24 4511826552 ps
T608 /workspace/coverage/default/2.chip_sw_lc_ctrl_transition.2511166970 Jul 01 01:22:18 PM PDT 24 Jul 01 01:29:37 PM PDT 24 5662359074 ps
T609 /workspace/coverage/default/0.rom_keymgr_functest.893161586 Jul 01 01:10:48 PM PDT 24 Jul 01 01:20:20 PM PDT 24 5167416440 ps
T390 /workspace/coverage/default/6.chip_sw_alert_handler_lpg_sleep_mode_alerts.1863365736 Jul 01 01:32:49 PM PDT 24 Jul 01 01:39:52 PM PDT 24 3704820512 ps
T206 /workspace/coverage/default/0.chip_sw_otp_ctrl_vendor_test_csr_access.3270566895 Jul 01 01:05:50 PM PDT 24 Jul 01 01:10:56 PM PDT 24 3240906176 ps
T352 /workspace/coverage/default/2.chip_sw_pwrmgr_b2b_sleep_reset_req.959039654 Jul 01 01:26:33 PM PDT 24 Jul 01 02:21:44 PM PDT 24 31188886809 ps
T610 /workspace/coverage/default/2.chip_sw_csrng_smoketest.239129945 Jul 01 01:32:27 PM PDT 24 Jul 01 01:36:57 PM PDT 24 2847333258 ps
T611 /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_dev.2679713285 Jul 01 01:21:41 PM PDT 24 Jul 01 01:43:17 PM PDT 24 8043091514 ps
T192 /workspace/coverage/default/0.chip_sw_usb_ast_clk_calib.1960007556 Jul 01 01:08:07 PM PDT 24 Jul 01 01:16:17 PM PDT 24 2979875706 ps
T612 /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_por_reset.451304438 Jul 01 01:09:26 PM PDT 24 Jul 01 01:20:21 PM PDT 24 8348752808 ps
T613 /workspace/coverage/default/0.rom_e2e_asm_init_prod_end.406587739 Jul 01 01:11:33 PM PDT 24 Jul 01 02:13:25 PM PDT 24 16021991552 ps
T364 /workspace/coverage/default/2.chip_sw_pwrmgr_lowpower_cancel.2792416028 Jul 01 01:26:52 PM PDT 24 Jul 01 01:35:28 PM PDT 24 4317465368 ps
T408 /workspace/coverage/default/64.chip_sw_alert_handler_lpg_sleep_mode_alerts.2067948249 Jul 01 01:38:12 PM PDT 24 Jul 01 01:46:13 PM PDT 24 3535800440 ps
T325 /workspace/coverage/default/0.chip_sw_lc_walkthrough_rma.2812913866 Jul 01 01:04:54 PM PDT 24 Jul 01 02:30:31 PM PDT 24 45943824554 ps
T614 /workspace/coverage/default/1.chip_sw_flash_ctrl_write_clear.3224359091 Jul 01 01:17:44 PM PDT 24 Jul 01 01:24:56 PM PDT 24 3356122040 ps
T615 /workspace/coverage/default/1.rom_e2e_asm_init_prod.1596714858 Jul 01 01:25:38 PM PDT 24 Jul 01 02:27:01 PM PDT 24 16024065152 ps
T478 /workspace/coverage/default/16.chip_sw_all_escalation_resets.3310267815 Jul 01 01:34:11 PM PDT 24 Jul 01 01:44:44 PM PDT 24 4542030090 ps
T51 /workspace/coverage/default/0.chip_sw_sysrst_ctrl_ec_rst_l.3483575025 Jul 01 01:04:11 PM PDT 24 Jul 01 01:59:59 PM PDT 24 20955692087 ps
T368 /workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.3119220571 Jul 01 01:05:06 PM PDT 24 Jul 01 01:16:31 PM PDT 24 5052087729 ps
T616 /workspace/coverage/default/2.chip_sw_kmac_idle.282872781 Jul 01 01:24:19 PM PDT 24 Jul 01 01:28:08 PM PDT 24 2932212258 ps
T167 /workspace/coverage/default/0.chip_sw_clkmgr_off_peri.40592480 Jul 01 01:08:26 PM PDT 24 Jul 01 01:33:24 PM PDT 24 10286770242 ps
T617 /workspace/coverage/default/0.chip_sw_alert_handler_ping_ok.2419798523 Jul 01 01:08:13 PM PDT 24 Jul 01 01:30:03 PM PDT 24 7203205372 ps
T618 /workspace/coverage/default/1.chip_sw_aes_enc_jitter_en_reduced_freq.3774070038 Jul 01 01:18:46 PM PDT 24 Jul 01 01:22:57 PM PDT 24 2990521301 ps
T619 /workspace/coverage/default/0.rom_e2e_static_critical.1559559622 Jul 01 01:12:57 PM PDT 24 Jul 01 02:24:09 PM PDT 24 16802828460 ps
T620 /workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_scramble.729644276 Jul 01 01:03:20 PM PDT 24 Jul 01 01:11:38 PM PDT 24 6900970800 ps
T621 /workspace/coverage/default/2.chip_sw_example_manufacturer.2607413012 Jul 01 01:19:24 PM PDT 24 Jul 01 01:22:41 PM PDT 24 3170951260 ps
T622 /workspace/coverage/default/1.chip_sw_sleep_sram_ret_contents_scramble.604446963 Jul 01 01:14:58 PM PDT 24 Jul 01 01:31:18 PM PDT 24 9167872416 ps
T488 /workspace/coverage/default/70.chip_sw_all_escalation_resets.902704349 Jul 01 01:39:02 PM PDT 24 Jul 01 01:49:22 PM PDT 24 4297909394 ps
T343 /workspace/coverage/default/28.chip_sw_all_escalation_resets.1683212138 Jul 01 01:36:24 PM PDT 24 Jul 01 01:48:55 PM PDT 24 6047155944 ps
T221 /workspace/coverage/default/1.chip_sw_rv_core_ibex_icache_invalidate.3481455950 Jul 01 01:17:27 PM PDT 24 Jul 01 01:22:05 PM PDT 24 3063585745 ps
T530 /workspace/coverage/default/3.chip_sw_all_escalation_resets.2615702071 Jul 01 01:29:55 PM PDT 24 Jul 01 01:39:12 PM PDT 24 4951602072 ps
T623 /workspace/coverage/default/2.chip_sw_pwrmgr_usb_clk_disabled_when_active.3389489788 Jul 01 01:22:03 PM PDT 24 Jul 01 01:28:54 PM PDT 24 4480019120 ps
T256 /workspace/coverage/default/1.chip_sw_sysrst_ctrl_in_irq.2269720794 Jul 01 01:11:47 PM PDT 24 Jul 01 01:21:35 PM PDT 24 4772558849 ps
T202 /workspace/coverage/default/41.chip_sw_alert_handler_lpg_sleep_mode_alerts.2224625539 Jul 01 01:35:49 PM PDT 24 Jul 01 01:43:21 PM PDT 24 3485472216 ps
T205 /workspace/coverage/default/49.chip_sw_alert_handler_lpg_sleep_mode_alerts.4270589816 Jul 01 01:36:18 PM PDT 24 Jul 01 01:42:41 PM PDT 24 3856349176 ps
T314 /workspace/coverage/default/0.chip_sw_sleep_pwm_pulses.2364096325 Jul 01 01:04:13 PM PDT 24 Jul 01 01:24:49 PM PDT 24 9660073368 ps
T624 /workspace/coverage/default/0.chip_sw_example_flash.453655132 Jul 01 01:05:06 PM PDT 24 Jul 01 01:10:17 PM PDT 24 2423168680 ps
T625 /workspace/coverage/default/0.chip_sw_hmac_smoketest.1248510147 Jul 01 01:05:20 PM PDT 24 Jul 01 01:10:38 PM PDT 24 3528747242 ps
T626 /workspace/coverage/default/0.chip_sw_keymgr_key_derivation.3815456772 Jul 01 01:05:35 PM PDT 24 Jul 01 01:51:04 PM PDT 24 10475223224 ps
T627 /workspace/coverage/default/0.chip_sw_kmac_mode_cshake.3105408945 Jul 01 01:04:29 PM PDT 24 Jul 01 01:07:37 PM PDT 24 3286010426 ps
T628 /workspace/coverage/default/1.chip_sw_pwrmgr_smoketest.2696647918 Jul 01 01:19:04 PM PDT 24 Jul 01 01:24:06 PM PDT 24 5276220792 ps
T517 /workspace/coverage/default/72.chip_sw_alert_handler_lpg_sleep_mode_alerts.2254001242 Jul 01 01:39:02 PM PDT 24 Jul 01 01:44:36 PM PDT 24 3306035908 ps
T460 /workspace/coverage/default/8.chip_sw_all_escalation_resets.2524857035 Jul 01 01:33:58 PM PDT 24 Jul 01 01:44:02 PM PDT 24 4429706256 ps
T629 /workspace/coverage/default/1.chip_sw_flash_ctrl_idle_low_power.4171181162 Jul 01 01:13:11 PM PDT 24 Jul 01 01:20:50 PM PDT 24 3555122570 ps
T28 /workspace/coverage/default/0.chip_jtag_csr_rw.2010792444 Jul 01 12:56:46 PM PDT 24 Jul 01 01:30:38 PM PDT 24 18567590572 ps
T242 /workspace/coverage/default/2.chip_sw_alert_handler_lpg_clkoff.2844583059 Jul 01 01:24:45 PM PDT 24 Jul 01 01:57:12 PM PDT 24 8785496644 ps
T513 /workspace/coverage/default/17.chip_sw_alert_handler_lpg_sleep_mode_alerts.1199874818 Jul 01 01:34:51 PM PDT 24 Jul 01 01:40:53 PM PDT 24 3343504670 ps
T630 /workspace/coverage/default/2.chip_sw_otp_ctrl_smoketest.463284931 Jul 01 01:29:44 PM PDT 24 Jul 01 01:33:26 PM PDT 24 2409795280 ps
T348 /workspace/coverage/default/2.chip_sw_uart_tx_rx_idx1.3937781201 Jul 01 01:20:05 PM PDT 24 Jul 01 01:33:31 PM PDT 24 4307947900 ps
T533 /workspace/coverage/default/35.chip_sw_all_escalation_resets.2414668024 Jul 01 01:35:41 PM PDT 24 Jul 01 01:44:50 PM PDT 24 4252177408 ps
T485 /workspace/coverage/default/87.chip_sw_alert_handler_lpg_sleep_mode_alerts.3907196677 Jul 01 01:41:39 PM PDT 24 Jul 01 01:47:44 PM PDT 24 3356783584 ps
T419 /workspace/coverage/default/69.chip_sw_all_escalation_resets.3276351554 Jul 01 01:38:57 PM PDT 24 Jul 01 01:50:47 PM PDT 24 5798755370 ps
T631 /workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_invalid_meas.3557748511 Jul 01 01:11:05 PM PDT 24 Jul 01 02:28:14 PM PDT 24 14910523188 ps
T413 /workspace/coverage/default/2.chip_sw_edn_entropy_reqs_jitter.863056041 Jul 01 01:23:49 PM PDT 24 Jul 01 01:45:46 PM PDT 24 6961320743 ps
T197 /workspace/coverage/default/2.chip_sw_exit_test_unlocked_bootstrap.3320745253 Jul 01 01:20:42 PM PDT 24 Jul 01 04:34:52 PM PDT 24 58969820998 ps
T336 /workspace/coverage/default/1.chip_sw_pattgen_ios.1566334947 Jul 01 01:06:34 PM PDT 24 Jul 01 01:11:27 PM PDT 24 2257848250 ps
T632 /workspace/coverage/default/45.chip_sw_all_escalation_resets.2378346948 Jul 01 01:37:10 PM PDT 24 Jul 01 01:45:58 PM PDT 24 4386665272 ps
T335 /workspace/coverage/default/4.chip_sw_uart_rand_baudrate.3878353017 Jul 01 01:32:13 PM PDT 24 Jul 01 02:00:45 PM PDT 24 8467062592 ps
T633 /workspace/coverage/default/2.chip_sw_clkmgr_off_hmac_trans.1566528764 Jul 01 01:25:53 PM PDT 24 Jul 01 01:33:41 PM PDT 24 4841843784 ps
T634 /workspace/coverage/default/1.chip_sw_clkmgr_off_kmac_trans.2485354736 Jul 01 01:16:20 PM PDT 24 Jul 01 01:22:34 PM PDT 24 4286941400 ps
T635 /workspace/coverage/default/8.chip_sw_csrng_edn_concurrency.4186626699 Jul 01 01:32:57 PM PDT 24 Jul 01 02:20:00 PM PDT 24 9897891934 ps
T414 /workspace/coverage/default/1.chip_sw_edn_entropy_reqs_jitter.3697811248 Jul 01 01:13:02 PM PDT 24 Jul 01 01:26:48 PM PDT 24 6024596739 ps
T86 /workspace/coverage/default/1.chip_sw_pwrmgr_full_aon_reset.916477683 Jul 01 01:13:19 PM PDT 24 Jul 01 01:20:57 PM PDT 24 7822299434 ps
T529 /workspace/coverage/default/66.chip_sw_alert_handler_lpg_sleep_mode_alerts.2363235816 Jul 01 01:38:15 PM PDT 24 Jul 01 01:43:59 PM PDT 24 3777709400 ps
T270 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.1463101942 Jul 01 01:13:18 PM PDT 24 Jul 01 02:50:55 PM PDT 24 23571474094 ps
T164 /workspace/coverage/default/39.chip_sw_all_escalation_resets.1759078979 Jul 01 01:36:18 PM PDT 24 Jul 01 01:47:28 PM PDT 24 5748874340 ps
T636 /workspace/coverage/default/2.chip_sw_alert_handler_escalation.4225707700 Jul 01 01:24:07 PM PDT 24 Jul 01 01:34:25 PM PDT 24 5456634008 ps
T477 /workspace/coverage/default/13.chip_sw_alert_handler_lpg_sleep_mode_alerts.2941116818 Jul 01 01:34:15 PM PDT 24 Jul 01 01:42:04 PM PDT 24 3613203020 ps
T510 /workspace/coverage/default/85.chip_sw_alert_handler_lpg_sleep_mode_alerts.1123985604 Jul 01 01:40:11 PM PDT 24 Jul 01 01:47:47 PM PDT 24 3381142120 ps
T637 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.1972148916 Jul 01 01:05:51 PM PDT 24 Jul 01 01:17:49 PM PDT 24 5138961880 ps
T638 /workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_reset_reqs.4147165903 Jul 01 01:09:02 PM PDT 24 Jul 01 02:01:01 PM PDT 24 28147341053 ps
T639 /workspace/coverage/default/2.chip_sw_keymgr_key_derivation.1839891366 Jul 01 01:25:22 PM PDT 24 Jul 01 01:48:21 PM PDT 24 6308592344 ps
T163 /workspace/coverage/default/2.chip_sw_kmac_app_rom.1818995318 Jul 01 01:25:00 PM PDT 24 Jul 01 01:29:25 PM PDT 24 2980887762 ps
T640 /workspace/coverage/default/2.chip_tap_straps_dev.1039505463 Jul 01 01:25:54 PM PDT 24 Jul 01 01:28:47 PM PDT 24 3080911666 ps
T457 /workspace/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.733618881 Jul 01 01:22:10 PM PDT 24 Jul 01 01:24:14 PM PDT 24 2390491050 ps
T641 /workspace/coverage/default/47.chip_sw_alert_handler_lpg_sleep_mode_alerts.1736329777 Jul 01 01:37:20 PM PDT 24 Jul 01 01:45:24 PM PDT 24 3977603368 ps
T642 /workspace/coverage/default/2.rom_e2e_asm_init_dev.1945295442 Jul 01 01:33:31 PM PDT 24 Jul 01 02:37:50 PM PDT 24 16338299769 ps
T643 /workspace/coverage/default/1.rom_e2e_asm_init_prod_end.2387544966 Jul 01 01:22:53 PM PDT 24 Jul 01 02:35:42 PM PDT 24 15808457642 ps
T644 /workspace/coverage/default/0.chip_sw_rv_core_ibex_rnd.1337356024 Jul 01 01:04:35 PM PDT 24 Jul 01 01:22:06 PM PDT 24 4850594400 ps
T207 /workspace/coverage/default/1.chip_sw_otp_ctrl_vendor_test_csr_access.2108904399 Jul 01 01:11:25 PM PDT 24 Jul 01 01:14:48 PM PDT 24 2974395809 ps
T375 /workspace/coverage/default/32.chip_sw_all_escalation_resets.1542300636 Jul 01 01:36:47 PM PDT 24 Jul 01 01:47:45 PM PDT 24 4895651680 ps
T645 /workspace/coverage/default/1.chip_sw_alert_handler_lpg_reset_toggle.2776315376 Jul 01 01:12:13 PM PDT 24 Jul 01 01:43:00 PM PDT 24 8186372392 ps
T646 /workspace/coverage/default/1.chip_sw_edn_entropy_reqs.3638223589 Jul 01 01:15:27 PM PDT 24 Jul 01 01:30:54 PM PDT 24 5684701720 ps
T647 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_lc.833280492 Jul 01 01:04:53 PM PDT 24 Jul 01 01:24:10 PM PDT 24 12460685515 ps
T648 /workspace/coverage/default/0.chip_sw_hmac_enc_jitter_en_reduced_freq.1728802647 Jul 01 01:03:56 PM PDT 24 Jul 01 01:07:35 PM PDT 24 2371254111 ps
T649 /workspace/coverage/default/52.chip_sw_alert_handler_lpg_sleep_mode_alerts.2792443793 Jul 01 01:38:33 PM PDT 24 Jul 01 01:44:48 PM PDT 24 3814716288 ps
T518 /workspace/coverage/default/19.chip_sw_alert_handler_lpg_sleep_mode_alerts.2050107397 Jul 01 01:34:46 PM PDT 24 Jul 01 01:41:54 PM PDT 24 3922939556 ps
T43 /workspace/coverage/default/2.chip_sw_spi_device_pass_through_collision.2333826537 Jul 01 01:22:11 PM PDT 24 Jul 01 01:32:48 PM PDT 24 4425029669 ps
T378 /workspace/coverage/default/29.chip_sw_alert_handler_lpg_sleep_mode_alerts.661148164 Jul 01 01:36:18 PM PDT 24 Jul 01 01:44:28 PM PDT 24 3449899420 ps
T123 /workspace/coverage/default/1.chip_sw_alert_test.2483223985 Jul 01 01:12:56 PM PDT 24 Jul 01 01:19:32 PM PDT 24 3081572800 ps
T650 /workspace/coverage/default/4.chip_tap_straps_prod.4209421735 Jul 01 01:30:59 PM PDT 24 Jul 01 01:33:49 PM PDT 24 2485045291 ps
T129 /workspace/coverage/default/4.chip_tap_straps_dev.2531195429 Jul 01 01:31:04 PM PDT 24 Jul 01 01:56:45 PM PDT 24 16187159838 ps
T651 /workspace/coverage/default/1.chip_sw_flash_ctrl_clock_freqs.3481254490 Jul 01 01:11:43 PM PDT 24 Jul 01 01:34:58 PM PDT 24 5803228531 ps
T652 /workspace/coverage/default/1.chip_sw_rv_core_ibex_rnd.1802728669 Jul 01 01:11:14 PM PDT 24 Jul 01 01:27:53 PM PDT 24 5312142896 ps
T653 /workspace/coverage/default/2.chip_sw_hmac_enc_jitter_en.333917800 Jul 01 01:26:33 PM PDT 24 Jul 01 01:32:22 PM PDT 24 3659326154 ps
T44 /workspace/coverage/default/0.chip_sw_spi_host_tx_rx.811045527 Jul 01 01:03:57 PM PDT 24 Jul 01 01:09:58 PM PDT 24 2601020028 ps
T654 /workspace/coverage/default/1.chip_tap_straps_prod.3802348059 Jul 01 01:19:10 PM PDT 24 Jul 01 01:34:26 PM PDT 24 8752735457 ps
T655 /workspace/coverage/default/2.chip_sw_hmac_smoketest.4007930501 Jul 01 01:31:41 PM PDT 24 Jul 01 01:37:58 PM PDT 24 3272403200 ps
T656 /workspace/coverage/default/7.chip_sw_lc_ctrl_transition.3722621397 Jul 01 01:32:10 PM PDT 24 Jul 01 01:42:24 PM PDT 24 6169139694 ps
T360 /workspace/coverage/default/2.chip_sw_entropy_src_csrng.2036567702 Jul 01 01:25:12 PM PDT 24 Jul 01 01:58:12 PM PDT 24 7969639008 ps
T234 /workspace/coverage/default/0.chip_sw_i2c_host_tx_rx.1763771564 Jul 01 01:05:55 PM PDT 24 Jul 01 01:21:16 PM PDT 24 5340038786 ps
T657 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.1157937437 Jul 01 01:10:37 PM PDT 24 Jul 01 02:23:23 PM PDT 24 15372723648 ps
T658 /workspace/coverage/default/4.chip_sw_csrng_edn_concurrency.3580733072 Jul 01 01:32:31 PM PDT 24 Jul 01 03:09:54 PM PDT 24 27378264356 ps
T119 /workspace/coverage/default/0.chip_sw_usbdev_pullup.605483585 Jul 01 01:06:06 PM PDT 24 Jul 01 01:11:54 PM PDT 24 3384955688 ps
T659 /workspace/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.3926987618 Jul 01 01:28:15 PM PDT 24 Jul 01 01:48:34 PM PDT 24 7682060864 ps
T349 /workspace/coverage/default/6.chip_sw_uart_rand_baudrate.1150905404 Jul 01 01:36:30 PM PDT 24 Jul 01 02:02:00 PM PDT 24 8893811460 ps
T660 /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.4278885812 Jul 01 01:16:46 PM PDT 24 Jul 01 01:26:58 PM PDT 24 4801115000 ps
T661 /workspace/coverage/default/0.chip_sw_rstmgr_sw_req.3525665837 Jul 01 01:04:48 PM PDT 24 Jul 01 01:14:27 PM PDT 24 3648766950 ps
T662 /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.2775674314 Jul 01 01:16:35 PM PDT 24 Jul 01 01:29:44 PM PDT 24 4153498244 ps
T663 /workspace/coverage/default/2.chip_sw_aes_smoketest.3475198366 Jul 01 01:29:17 PM PDT 24 Jul 01 01:33:15 PM PDT 24 2867463198 ps
T189 /workspace/coverage/default/2.chip_sw_sram_ctrl_execution_main.2547915593 Jul 01 01:25:36 PM PDT 24 Jul 01 01:38:45 PM PDT 24 8372165195 ps
T155 /workspace/coverage/default/1.chip_sw_spi_device_pass_through.2633532555 Jul 01 01:07:46 PM PDT 24 Jul 01 01:20:01 PM PDT 24 6133941941 ps
T100 /workspace/coverage/default/2.chip_sw_power_sleep_load.3428926430 Jul 01 01:30:06 PM PDT 24 Jul 01 01:38:34 PM PDT 24 5121593592 ps
T193 /workspace/coverage/default/2.chip_plic_all_irqs_20.99670882 Jul 01 01:28:09 PM PDT 24 Jul 01 01:42:28 PM PDT 24 4689665230 ps
T356 /workspace/coverage/default/2.chip_sw_pwrmgr_all_reset_reqs.4060110217 Jul 01 01:22:49 PM PDT 24 Jul 01 01:52:53 PM PDT 24 12443100425 ps
T226 /workspace/coverage/default/1.chip_plic_all_irqs_0.519835196 Jul 01 01:17:05 PM PDT 24 Jul 01 01:33:37 PM PDT 24 6636409250 ps
T664 /workspace/coverage/default/12.chip_sw_uart_rand_baudrate.2025173312 Jul 01 01:33:01 PM PDT 24 Jul 01 02:08:49 PM PDT 24 13448501072 ps
T665 /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_power_glitch_reset.1619883623 Jul 01 01:22:48 PM PDT 24 Jul 01 01:29:20 PM PDT 24 5812475484 ps
T508 /workspace/coverage/default/71.chip_sw_all_escalation_resets.1562928817 Jul 01 01:41:09 PM PDT 24 Jul 01 01:50:42 PM PDT 24 5137765792 ps
T340 /workspace/coverage/default/73.chip_sw_alert_handler_lpg_sleep_mode_alerts.1215535826 Jul 01 01:39:13 PM PDT 24 Jul 01 01:46:06 PM PDT 24 4098732600 ps
T415 /workspace/coverage/default/0.chip_sw_edn_boot_mode.2823333721 Jul 01 01:06:56 PM PDT 24 Jul 01 01:19:11 PM PDT 24 3497045260 ps
T3 /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_wake_ups.964605871 Jul 01 01:16:57 PM PDT 24 Jul 01 01:51:49 PM PDT 24 22823863454 ps
T426 /workspace/coverage/default/1.chip_sw_hmac_enc_jitter_en.3964348583 Jul 01 01:13:25 PM PDT 24 Jul 01 01:17:24 PM PDT 24 3146836916 ps
T111 /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.2302407612 Jul 01 01:03:32 PM PDT 24 Jul 01 01:08:45 PM PDT 24 4545700940 ps
T199 /workspace/coverage/default/2.chip_sw_alert_handler_reverse_ping_in_deep_sleep.1846510758 Jul 01 01:24:58 PM PDT 24 Jul 01 05:11:27 PM PDT 24 255700688216 ps
T427 /workspace/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en.1550951839 Jul 01 01:04:15 PM PDT 24 Jul 01 01:24:21 PM PDT 24 6203368618 ps
T273 /workspace/coverage/default/0.chip_sw_rv_timer_smoketest.380998479 Jul 01 01:07:28 PM PDT 24 Jul 01 01:11:57 PM PDT 24 2982403192 ps
T428 /workspace/coverage/default/2.chip_sw_csrng_kat_test.816569896 Jul 01 01:24:59 PM PDT 24 Jul 01 01:29:33 PM PDT 24 2240064712 ps
T238 /workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx2.236993380 Jul 01 01:04:52 PM PDT 24 Jul 01 01:18:41 PM PDT 24 5225773304 ps
T370 /workspace/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en.3473526771 Jul 01 01:22:15 PM PDT 24 Jul 01 01:37:04 PM PDT 24 4097178420 ps
T429 /workspace/coverage/default/4.chip_sw_lc_ctrl_transition.4210617488 Jul 01 01:31:53 PM PDT 24 Jul 01 01:42:15 PM PDT 24 7135411579 ps
T168 /workspace/coverage/default/2.chip_jtag_csr_rw.3044963439 Jul 01 01:19:41 PM PDT 24 Jul 01 01:29:49 PM PDT 24 5930011616 ps
T666 /workspace/coverage/default/1.chip_sw_clkmgr_off_aes_trans.2386693897 Jul 01 01:15:34 PM PDT 24 Jul 01 01:24:52 PM PDT 24 4895435648 ps
T54 /workspace/coverage/default/0.chip_sw_usbdev_setuprx.2404947402 Jul 01 01:04:39 PM PDT 24 Jul 01 01:16:29 PM PDT 24 3348103392 ps
T667 /workspace/coverage/default/0.chip_sw_pwrmgr_wdog_reset.778229837 Jul 01 01:03:47 PM PDT 24 Jul 01 01:13:32 PM PDT 24 4122502120 ps
T668 /workspace/coverage/default/4.chip_sw_aon_timer_sleep_wdog_sleep_pause.3870273433 Jul 01 01:31:24 PM PDT 24 Jul 01 01:37:31 PM PDT 24 5922805376 ps
T386 /workspace/coverage/default/94.chip_sw_all_escalation_resets.2467992978 Jul 01 01:41:06 PM PDT 24 Jul 01 01:51:26 PM PDT 24 4382965516 ps
T669 /workspace/coverage/default/2.chip_sw_aes_enc_jitter_en.2849076484 Jul 01 01:24:12 PM PDT 24 Jul 01 01:30:21 PM PDT 24 3404134537 ps
T211 /workspace/coverage/default/0.chip_sw_lc_ctrl_program_error.3902474554 Jul 01 01:04:00 PM PDT 24 Jul 01 01:10:10 PM PDT 24 4350423418 ps
T490 /workspace/coverage/default/82.chip_sw_alert_handler_lpg_sleep_mode_alerts.2331529725 Jul 01 01:40:17 PM PDT 24 Jul 01 01:47:19 PM PDT 24 3698052744 ps
T670 /workspace/coverage/default/0.chip_sw_example_rom.440460502 Jul 01 01:02:36 PM PDT 24 Jul 01 01:04:44 PM PDT 24 2391098360 ps
T671 /workspace/coverage/default/77.chip_sw_all_escalation_resets.2490083906 Jul 01 01:39:52 PM PDT 24 Jul 01 01:50:00 PM PDT 24 4839825692 ps
T672 /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.313111776 Jul 01 01:15:37 PM PDT 24 Jul 01 01:28:54 PM PDT 24 4272827232 ps
T40 /workspace/coverage/default/2.chip_sw_sleep_pin_mio_dio_val.964174650 Jul 01 01:20:04 PM PDT 24 Jul 01 01:25:25 PM PDT 24 3221372213 ps
T673 /workspace/coverage/default/2.chip_sw_clkmgr_off_peri.3949581434 Jul 01 01:26:17 PM PDT 24 Jul 01 01:50:52 PM PDT 24 10460331736 ps
T290 /workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.2964783589 Jul 01 01:27:58 PM PDT 24 Jul 01 01:38:11 PM PDT 24 5725740701 ps
T380 /workspace/coverage/default/1.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.1745521060 Jul 01 01:17:14 PM PDT 24 Jul 01 01:26:32 PM PDT 24 6817629176 ps
T312 /workspace/coverage/default/2.chip_sw_rv_core_ibex_nmi_irq.2819928208 Jul 01 01:24:07 PM PDT 24 Jul 01 01:39:00 PM PDT 24 5415912410 ps
T674 /workspace/coverage/default/1.chip_sw_sleep_sram_ret_contents_no_scramble.1697597228 Jul 01 01:15:15 PM PDT 24 Jul 01 01:26:07 PM PDT 24 7300894940 ps
T675 /workspace/coverage/default/0.chip_sw_csrng_fuse_en_sw_app_read_test.2162500634 Jul 01 01:04:44 PM PDT 24 Jul 01 01:12:46 PM PDT 24 3849034410 ps
T458 /workspace/coverage/default/0.rom_volatile_raw_unlock.1705000790 Jul 01 01:07:22 PM PDT 24 Jul 01 01:09:19 PM PDT 24 2663694645 ps
T237 /workspace/coverage/default/1.chip_sw_i2c_host_tx_rx_idx1.1835096334 Jul 01 01:12:09 PM PDT 24 Jul 01 01:26:01 PM PDT 24 5412597464 ps
T218 /workspace/coverage/default/0.chip_sw_lc_ctrl_raw_to_scrap.1157344135 Jul 01 01:06:46 PM PDT 24 Jul 01 01:09:07 PM PDT 24 2601012118 ps
T291 /workspace/coverage/default/1.chip_sw_otbn_mem_scramble.1026709274 Jul 01 01:10:51 PM PDT 24 Jul 01 01:19:34 PM PDT 24 3653349752 ps
T52 /workspace/coverage/default/0.chip_sw_sysrst_ctrl_reset.791999631 Jul 01 01:03:13 PM PDT 24 Jul 01 01:35:29 PM PDT 24 22752989470 ps
T541 /workspace/coverage/default/21.chip_sw_all_escalation_resets.2472714706 Jul 01 01:34:58 PM PDT 24 Jul 01 01:46:06 PM PDT 24 4518325684 ps
T676 /workspace/coverage/default/9.chip_sw_lc_ctrl_transition.2747083030 Jul 01 01:32:45 PM PDT 24 Jul 01 01:45:03 PM PDT 24 7410511236 ps
T677 /workspace/coverage/default/1.chip_sw_aon_timer_wdog_bite_reset.2093260112 Jul 01 01:11:01 PM PDT 24 Jul 01 01:24:20 PM PDT 24 8724626636 ps
T678 /workspace/coverage/default/0.rom_e2e_smoke.3428697088 Jul 01 01:11:31 PM PDT 24 Jul 01 02:25:49 PM PDT 24 14768317608 ps
T53 /workspace/coverage/default/2.chip_sw_sysrst_ctrl_reset.2365237759 Jul 01 01:22:38 PM PDT 24 Jul 01 01:57:46 PM PDT 24 22875530928 ps
T679 /workspace/coverage/default/0.chip_sw_aon_timer_smoketest.4152116001 Jul 01 01:10:42 PM PDT 24 Jul 01 01:15:18 PM PDT 24 2771461352 ps
T680 /workspace/coverage/default/32.chip_sw_alert_handler_lpg_sleep_mode_alerts.2680419172 Jul 01 01:37:43 PM PDT 24 Jul 01 01:45:58 PM PDT 24 4010931656 ps
T462 /workspace/coverage/default/72.chip_sw_all_escalation_resets.520928957 Jul 01 01:41:12 PM PDT 24 Jul 01 01:54:03 PM PDT 24 5470270876 ps
T681 /workspace/coverage/default/2.chip_sw_flash_scrambling_smoketest.530544858 Jul 01 01:33:31 PM PDT 24 Jul 01 01:38:41 PM PDT 24 2844514804 ps
T58 /workspace/coverage/default/2.chip_sw_gpio.3374354210 Jul 01 01:20:46 PM PDT 24 Jul 01 01:31:48 PM PDT 24 3516139666 ps
T682 /workspace/coverage/default/0.chip_sw_alert_handler_escalation.1663349261 Jul 01 01:05:07 PM PDT 24 Jul 01 01:14:31 PM PDT 24 5336215652 ps
T683 /workspace/coverage/default/0.chip_sw_edn_entropy_reqs_jitter.2024902287 Jul 01 01:07:57 PM PDT 24 Jul 01 01:24:16 PM PDT 24 7557325537 ps
T255 /workspace/coverage/default/0.chip_sw_uart_tx_rx_bootstrap.1248898261 Jul 01 01:07:07 PM PDT 24 Jul 01 05:54:41 PM PDT 24 78787115668 ps
T684 /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_wake_5_bug.1302358603 Jul 01 01:27:08 PM PDT 24 Jul 01 01:35:03 PM PDT 24 5877577280 ps
T392 /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_disabled.1149287243 Jul 01 01:08:41 PM PDT 24 Jul 01 01:13:34 PM PDT 24 3658616456 ps
T685 /workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_no_scramble.4182261873 Jul 01 01:26:02 PM PDT 24 Jul 01 01:41:06 PM PDT 24 6974815360 ps
T686 /workspace/coverage/default/1.chip_sw_pwrmgr_all_reset_reqs.1923445179 Jul 01 01:10:25 PM PDT 24 Jul 01 01:36:50 PM PDT 24 9146347252 ps
T687 /workspace/coverage/default/0.chip_sw_aes_idle.4178073695 Jul 01 01:05:11 PM PDT 24 Jul 01 01:10:30 PM PDT 24 2810357400 ps
T688 /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.3564674283 Jul 01 01:16:24 PM PDT 24 Jul 01 01:27:14 PM PDT 24 3749406132 ps
T538 /workspace/coverage/default/15.chip_sw_alert_handler_lpg_sleep_mode_alerts.25702572 Jul 01 01:36:01 PM PDT 24 Jul 01 01:44:28 PM PDT 24 3451539860 ps
T470 /workspace/coverage/default/60.chip_sw_all_escalation_resets.1374990337 Jul 01 01:40:50 PM PDT 24 Jul 01 01:48:39 PM PDT 24 5281390058 ps
T689 /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.2455107384 Jul 01 01:15:48 PM PDT 24 Jul 01 01:41:49 PM PDT 24 14282890892 ps
T690 /workspace/coverage/default/2.chip_sw_entropy_src_ast_rng_req.2212619695 Jul 01 01:24:34 PM PDT 24 Jul 01 01:28:25 PM PDT 24 3270476208 ps
T361 /workspace/coverage/default/1.chip_sw_entropy_src_csrng.3856826843 Jul 01 01:15:43 PM PDT 24 Jul 01 01:47:43 PM PDT 24 7879069160 ps
T691 /workspace/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en.2553837523 Jul 01 01:03:53 PM PDT 24 Jul 01 01:10:04 PM PDT 24 3399136986 ps
T692 /workspace/coverage/default/1.chip_sw_flash_ctrl_mem_protection.738162895 Jul 01 01:19:42 PM PDT 24 Jul 01 01:44:09 PM PDT 24 5547764920 ps
T459 /workspace/coverage/default/0.chip_sw_lc_ctrl_rma_to_scrap.823678011 Jul 01 01:08:26 PM PDT 24 Jul 01 01:13:21 PM PDT 24 3659840767 ps
T328 /workspace/coverage/default/2.chip_sw_lc_walkthrough_prod.3753671299 Jul 01 01:21:30 PM PDT 24 Jul 01 03:07:03 PM PDT 24 50283067098 ps
T398 /workspace/coverage/default/0.chip_sw_rv_core_ibex_lockstep_glitch.449314670 Jul 01 01:05:19 PM PDT 24 Jul 01 01:08:25 PM PDT 24 2536503584 ps
T693 /workspace/coverage/default/2.chip_sw_lc_walkthrough_prodend.2199933755 Jul 01 01:22:58 PM PDT 24 Jul 01 01:44:08 PM PDT 24 8174184714 ps
T694 /workspace/coverage/default/2.chip_sw_inject_scramble_seed.400100722 Jul 01 01:20:17 PM PDT 24 Jul 01 04:35:23 PM PDT 24 64065491556 ps
T695 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.2569926404 Jul 01 01:31:44 PM PDT 24 Jul 01 01:45:05 PM PDT 24 4330459170 ps
T190 /workspace/coverage/default/0.chip_sw_sram_ctrl_execution_main.4129575472 Jul 01 01:04:22 PM PDT 24 Jul 01 01:21:23 PM PDT 24 8441567212 ps
T475 /workspace/coverage/default/89.chip_sw_alert_handler_lpg_sleep_mode_alerts.2199263587 Jul 01 01:41:19 PM PDT 24 Jul 01 01:49:12 PM PDT 24 4150471400 ps
T696 /workspace/coverage/default/99.chip_sw_all_escalation_resets.3463753283 Jul 01 01:42:38 PM PDT 24 Jul 01 01:53:14 PM PDT 24 6038908424 ps
T697 /workspace/coverage/default/17.chip_sw_uart_rand_baudrate.1353474163 Jul 01 01:34:19 PM PDT 24 Jul 01 01:43:26 PM PDT 24 4245677612 ps
T7 /workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_wake_ups.630091274 Jul 01 01:06:44 PM PDT 24 Jul 01 01:15:13 PM PDT 24 7404942500 ps
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