Module Definition
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Line Coverage for Module : prim_fifo_sync
Line No.TotalCoveredPercent
TOTAL44100.00
CONT_ASSIGN4411100.00
CONT_ASSIGN4511100.00
CONT_ASSIGN4811100.00
CONT_ASSIGN4911100.00
CONT_ASSIGN5300
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
44 1 1
45 1 1
48 1 1
49 1 1
53 unreachable


Assert Coverage for Module : prim_fifo_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 2147483647 180101427 0 0
DepthKnown_A 2147483647 2147483647 0 0
RvalidKnown_A 2147483647 2147483647 0 0
WreadyKnown_A 2147483647 2147483647 0 0
gen_passthru_fifo.paramCheckPass 10060 10060 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 180101427 0 0
T4 938060 27537 0 0
T5 1155920 339705 0 0
T6 822090 39392 0 0
T17 2826970 104009 0 0
T18 3896200 147616 0 0
T19 3225940 96383 0 0
T31 2967510 1823712 0 0
T114 2930320 108786 0 0
T142 837720 27591 0 0
T165 658480 18828 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T4 938060 937550 0 0
T5 1155920 1155330 0 0
T6 822090 821580 0 0
T17 2826970 2825950 0 0
T18 3896200 3895580 0 0
T19 3225940 3223620 0 0
T31 2967510 2967450 0 0
T114 2930320 2929230 0 0
T142 837720 837210 0 0
T165 658480 657970 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T4 938060 937550 0 0
T5 1155920 1155330 0 0
T6 822090 821580 0 0
T17 2826970 2825950 0 0
T18 3896200 3895580 0 0
T19 3225940 3223620 0 0
T31 2967510 2967450 0 0
T114 2930320 2929230 0 0
T142 837720 837210 0 0
T165 658480 657970 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T4 938060 937550 0 0
T5 1155920 1155330 0 0
T6 822090 821580 0 0
T17 2826970 2825950 0 0
T18 3896200 3895580 0 0
T19 3225940 3223620 0 0
T31 2967510 2967450 0 0
T114 2930320 2929230 0 0
T142 837720 837210 0 0
T165 658480 657970 0 0

gen_passthru_fifo.paramCheckPass
NameAttemptsReal SuccessesFailuresIncomplete
Total 10060 10060 0 0
T4 10 10 0 0
T5 10 10 0 0
T6 10 10 0 0
T17 10 10 0 0
T18 10 10 0 0
T19 10 10 0 0
T31 10 10 0 0
T114 10 10 0 0
T142 10 10 0 0
T165 10 10 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%