Unified Coverage Report :: Module Instance :: tb.dut.top_earlgrey.u_uart0.uart_core.u_uart_txfifo

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	508532396	57935860	0	0
DepthKnown_A	508532396	508426140	0	0
RvalidKnown_A	508532396	508426140	0	0
WreadyKnown_A	508532396	508426140	0	0
gen_passthru_fifo.paramCheckPass	1006	1006	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	508532396	57935860	0	0
T4	93806	9879	0	0
T5	115592	128421	0	0
T6	82209	17571	0	0
T17	282697	36987	0	0
T18	389620	36016	0	0
T19	322594	31499	0	0
T31	296751	404280	0	0
T114	293032	38538	0	0
T142	83772	9994	0	0
T165	65848	6666	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	508532396	508426140	0	0
T4	93806	93755	0	0
T5	115592	115533	0	0
T6	82209	82158	0	0
T17	282697	282595	0	0
T18	389620	389558	0	0
T19	322594	322362	0	0
T31	296751	296745	0	0
T114	293032	292923	0	0
T142	83772	83721	0	0
T165	65848	65797	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	508532396	508426140	0	0
T4	93806	93755	0	0
T5	115592	115533	0	0
T6	82209	82158	0	0
T17	282697	282595	0	0
T18	389620	389558	0	0
T19	322594	322362	0	0
T31	296751	296745	0	0
T114	293032	292923	0	0
T142	83772	83721	0	0
T165	65848	65797	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	508532396	508426140	0	0
T4	93806	93755	0	0
T5	115592	115533	0	0
T6	82209	82158	0	0
T17	282697	282595	0	0
T18	389620	389558	0	0
T19	322594	322362	0	0
T31	296751	296745	0	0
T114	293032	292923	0	0
T142	83772	83721	0	0
T165	65848	65797	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1006	1006	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T31	1	1	0	0
T114	1	1	0	0
T142	1	1	0	0
T165	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	2	50.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	0	0.00
CONT_ASSIGN	49	1	0	0.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	0	1
49	0	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	508532396	45048059	0	0
DepthKnown_A	508532396	508426140	0	0
RvalidKnown_A	508532396	508426140	0	0
WreadyKnown_A	508532396	508426140	0	0
gen_passthru_fifo.paramCheckPass	1006	1006	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	508532396	45048059	0	0
T4	93806	7850	0	0
T5	115592	96613	0	0
T6	82209	10288	0	0
T17	282697	27486	0	0
T18	389620	31834	0	0
T19	322594	25769	0	0
T31	296751	385610	0	0
T114	293032	28894	0	0
T142	83772	7443	0	0
T165	65848	4731	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	508532396	508426140	0	0
T4	93806	93755	0	0
T5	115592	115533	0	0
T6	82209	82158	0	0
T17	282697	282595	0	0
T18	389620	389558	0	0
T19	322594	322362	0	0
T31	296751	296745	0	0
T114	293032	292923	0	0
T142	83772	83721	0	0
T165	65848	65797	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	508532396	508426140	0	0
T4	93806	93755	0	0
T5	115592	115533	0	0
T6	82209	82158	0	0
T17	282697	282595	0	0
T18	389620	389558	0	0
T19	322594	322362	0	0
T31	296751	296745	0	0
T114	293032	292923	0	0
T142	83772	83721	0	0
T165	65848	65797	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	508532396	508426140	0	0
T4	93806	93755	0	0
T5	115592	115533	0	0
T6	82209	82158	0	0
T17	282697	282595	0	0
T18	389620	389558	0	0
T19	322594	322362	0	0
T31	296751	296745	0	0
T114	293032	292923	0	0
T142	83772	83721	0	0
T165	65848	65797	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1006	1006	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T31	1	1	0	0
T114	1	1	0	0
T142	1	1	0	0
T165	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	508532396	41539240	0	0
DepthKnown_A	508532396	508426140	0	0
RvalidKnown_A	508532396	508426140	0	0
WreadyKnown_A	508532396	508426140	0	0
gen_passthru_fifo.paramCheckPass	1006	1006	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	508532396	41539240	0	0
T4	93806	4949	0	0
T5	115592	57668	0	0
T6	82209	6044	0	0
T17	282697	19655	0	0
T18	389620	39879	0	0
T19	322594	19664	0	0
T31	296751	517044	0	0
T114	293032	20567	0	0
T142	83772	5116	0	0
T165	65848	3748	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	508532396	508426140	0	0
T4	93806	93755	0	0
T5	115592	115533	0	0
T6	82209	82158	0	0
T17	282697	282595	0	0
T18	389620	389558	0	0
T19	322594	322362	0	0
T31	296751	296745	0	0
T114	293032	292923	0	0
T142	83772	83721	0	0
T165	65848	65797	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	508532396	508426140	0	0
T4	93806	93755	0	0
T5	115592	115533	0	0
T6	82209	82158	0	0
T17	282697	282595	0	0
T18	389620	389558	0	0
T19	322594	322362	0	0
T31	296751	296745	0	0
T114	293032	292923	0	0
T142	83772	83721	0	0
T165	65848	65797	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	508532396	508426140	0	0
T4	93806	93755	0	0
T5	115592	115533	0	0
T6	82209	82158	0	0
T17	282697	282595	0	0
T18	389620	389558	0	0
T19	322594	322362	0	0
T31	296751	296745	0	0
T114	293032	292923	0	0
T142	83772	83721	0	0
T165	65848	65797	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1006	1006	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T31	1	1	0	0
T114	1	1	0	0
T142	1	1	0	0
T165	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	508532396	35316716	0	0
DepthKnown_A	508532396	508426140	0	0
RvalidKnown_A	508532396	508426140	0	0
WreadyKnown_A	508532396	508426140	0	0
gen_passthru_fifo.paramCheckPass	1006	1006	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	508532396	35316716	0	0
T4	93806	4807	0	0
T5	115592	56131	0	0
T6	82209	5297	0	0
T17	282697	19277	0	0
T18	389620	39663	0	0
T19	322594	19255	0	0
T31	296751	516722	0	0
T114	293032	20183	0	0
T142	83772	4986	0	0
T165	65848	3631	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	508532396	508426140	0	0
T4	93806	93755	0	0
T5	115592	115533	0	0
T6	82209	82158	0	0
T17	282697	282595	0	0
T18	389620	389558	0	0
T19	322594	322362	0	0
T31	296751	296745	0	0
T114	293032	292923	0	0
T142	83772	83721	0	0
T165	65848	65797	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	508532396	508426140	0	0
T4	93806	93755	0	0
T5	115592	115533	0	0
T6	82209	82158	0	0
T17	282697	282595	0	0
T18	389620	389558	0	0
T19	322594	322362	0	0
T31	296751	296745	0	0
T114	293032	292923	0	0
T142	83772	83721	0	0
T165	65848	65797	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	508532396	508426140	0	0
T4	93806	93755	0	0
T5	115592	115533	0	0
T6	82209	82158	0	0
T17	282697	282595	0	0
T18	389620	389558	0	0
T19	322594	322362	0	0
T31	296751	296745	0	0
T114	293032	292923	0	0
T142	83772	83721	0	0
T165	65848	65797	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1006	1006	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T31	1	1	0	0
T114	1	1	0	0
T142	1	1	0	0
T165	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	508532396	65388	0	0
DepthKnown_A	508532396	508426140	0	0
RvalidKnown_A	508532396	508426140	0	0
WreadyKnown_A	508532396	508426140	0	0
gen_passthru_fifo.paramCheckPass	1006	1006	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	508532396	65388	0	0
T4	93806	13	0	0
T5	115592	218	0	0
T6	82209	48	0	0
T17	282697	151	0	0
T18	389620	56	0	0
T19	322594	49	0	0
T31	296751	14	0	0
T114	293032	151	0	0
T142	83772	13	0	0
T165	65848	13	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	508532396	508426140	0	0
T4	93806	93755	0	0
T5	115592	115533	0	0
T6	82209	82158	0	0
T17	282697	282595	0	0
T18	389620	389558	0	0
T19	322594	322362	0	0
T31	296751	296745	0	0
T114	293032	292923	0	0
T142	83772	83721	0	0
T165	65848	65797	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	508532396	508426140	0	0
T4	93806	93755	0	0
T5	115592	115533	0	0
T6	82209	82158	0	0
T17	282697	282595	0	0
T18	389620	389558	0	0
T19	322594	322362	0	0
T31	296751	296745	0	0
T114	293032	292923	0	0
T142	83772	83721	0	0
T165	65848	65797	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	508532396	508426140	0	0
T4	93806	93755	0	0
T5	115592	115533	0	0
T6	82209	82158	0	0
T17	282697	282595	0	0
T18	389620	389558	0	0
T19	322594	322362	0	0
T31	296751	296745	0	0
T114	293032	292923	0	0
T142	83772	83721	0	0
T165	65848	65797	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1006	1006	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T31	1	1	0	0
T114	1	1	0	0
T142	1	1	0	0
T165	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	508532396	65388	0	0
DepthKnown_A	508532396	508426140	0	0
RvalidKnown_A	508532396	508426140	0	0
WreadyKnown_A	508532396	508426140	0	0
gen_passthru_fifo.paramCheckPass	1006	1006	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	508532396	65388	0	0
T4	93806	13	0	0
T5	115592	218	0	0
T6	82209	48	0	0
T17	282697	151	0	0
T18	389620	56	0	0
T19	322594	49	0	0
T31	296751	14	0	0
T114	293032	151	0	0
T142	83772	13	0	0
T165	65848	13	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	508532396	508426140	0	0
T4	93806	93755	0	0
T5	115592	115533	0	0
T6	82209	82158	0	0
T17	282697	282595	0	0
T18	389620	389558	0	0
T19	322594	322362	0	0
T31	296751	296745	0	0
T114	293032	292923	0	0
T142	83772	83721	0	0
T165	65848	65797	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	508532396	508426140	0	0
T4	93806	93755	0	0
T5	115592	115533	0	0
T6	82209	82158	0	0
T17	282697	282595	0	0
T18	389620	389558	0	0
T19	322594	322362	0	0
T31	296751	296745	0	0
T114	293032	292923	0	0
T142	83772	83721	0	0
T165	65848	65797	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	508532396	508426140	0	0
T4	93806	93755	0	0
T5	115592	115533	0	0
T6	82209	82158	0	0
T17	282697	282595	0	0
T18	389620	389558	0	0
T19	322594	322362	0	0
T31	296751	296745	0	0
T114	293032	292923	0	0
T142	83772	83721	0	0
T165	65848	65797	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1006	1006	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T31	1	1	0	0
T114	1	1	0	0
T142	1	1	0	0
T165	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	508532396	51869	0	0
DepthKnown_A	508532396	508426140	0	0
RvalidKnown_A	508532396	508426140	0	0
WreadyKnown_A	508532396	508426140	0	0
gen_passthru_fifo.paramCheckPass	1006	1006	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	508532396	51869	0	0
T4	93806	12	0	0
T5	115592	191	0	0
T6	82209	13	0	0
T17	282697	95	0	0
T18	389620	55	0	0
T19	322594	46	0	0
T31	296751	13	0	0
T114	293032	95	0	0
T142	83772	12	0	0
T165	65848	12	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	508532396	508426140	0	0
T4	93806	93755	0	0
T5	115592	115533	0	0
T6	82209	82158	0	0
T17	282697	282595	0	0
T18	389620	389558	0	0
T19	322594	322362	0	0
T31	296751	296745	0	0
T114	293032	292923	0	0
T142	83772	83721	0	0
T165	65848	65797	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	508532396	508426140	0	0
T4	93806	93755	0	0
T5	115592	115533	0	0
T6	82209	82158	0	0
T17	282697	282595	0	0
T18	389620	389558	0	0
T19	322594	322362	0	0
T31	296751	296745	0	0
T114	293032	292923	0	0
T142	83772	83721	0	0
T165	65848	65797	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	508532396	508426140	0	0
T4	93806	93755	0	0
T5	115592	115533	0	0
T6	82209	82158	0	0
T17	282697	282595	0	0
T18	389620	389558	0	0
T19	322594	322362	0	0
T31	296751	296745	0	0
T114	293032	292923	0	0
T142	83772	83721	0	0
T165	65848	65797	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1006	1006	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T31	1	1	0	0
T114	1	1	0	0
T142	1	1	0	0
T165	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	508532396	51869	0	0
DepthKnown_A	508532396	508426140	0	0
RvalidKnown_A	508532396	508426140	0	0
WreadyKnown_A	508532396	508426140	0	0
gen_passthru_fifo.paramCheckPass	1006	1006	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	508532396	51869	0	0
T4	93806	12	0	0
T5	115592	191	0	0
T6	82209	13	0	0
T17	282697	95	0	0
T18	389620	55	0	0
T19	322594	46	0	0
T31	296751	13	0	0
T114	293032	95	0	0
T142	83772	12	0	0
T165	65848	12	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	508532396	508426140	0	0
T4	93806	93755	0	0
T5	115592	115533	0	0
T6	82209	82158	0	0
T17	282697	282595	0	0
T18	389620	389558	0	0
T19	322594	322362	0	0
T31	296751	296745	0	0
T114	293032	292923	0	0
T142	83772	83721	0	0
T165	65848	65797	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	508532396	508426140	0	0
T4	93806	93755	0	0
T5	115592	115533	0	0
T6	82209	82158	0	0
T17	282697	282595	0	0
T18	389620	389558	0	0
T19	322594	322362	0	0
T31	296751	296745	0	0
T114	293032	292923	0	0
T142	83772	83721	0	0
T165	65848	65797	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	508532396	508426140	0	0
T4	93806	93755	0	0
T5	115592	115533	0	0
T6	82209	82158	0	0
T17	282697	282595	0	0
T18	389620	389558	0	0
T19	322594	322362	0	0
T31	296751	296745	0	0
T114	293032	292923	0	0
T142	83772	83721	0	0
T165	65848	65797	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1006	1006	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T31	1	1	0	0
T114	1	1	0	0
T142	1	1	0	0
T165	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	508532396	13519	0	0
DepthKnown_A	508532396	508426140	0	0
RvalidKnown_A	508532396	508426140	0	0
WreadyKnown_A	508532396	508426140	0	0
gen_passthru_fifo.paramCheckPass	1006	1006	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	508532396	13519	0	0
T4	93806	1	0	0
T5	115592	27	0	0
T6	82209	35	0	0
T17	282697	56	0	0
T18	389620	1	0	0
T19	322594	3	0	0
T31	296751	1	0	0
T114	293032	56	0	0
T142	83772	1	0	0
T165	65848	1	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	508532396	508426140	0	0
T4	93806	93755	0	0
T5	115592	115533	0	0
T6	82209	82158	0	0
T17	282697	282595	0	0
T18	389620	389558	0	0
T19	322594	322362	0	0
T31	296751	296745	0	0
T114	293032	292923	0	0
T142	83772	83721	0	0
T165	65848	65797	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	508532396	508426140	0	0
T4	93806	93755	0	0
T5	115592	115533	0	0
T6	82209	82158	0	0
T17	282697	282595	0	0
T18	389620	389558	0	0
T19	322594	322362	0	0
T31	296751	296745	0	0
T114	293032	292923	0	0
T142	83772	83721	0	0
T165	65848	65797	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	508532396	508426140	0	0
T4	93806	93755	0	0
T5	115592	115533	0	0
T6	82209	82158	0	0
T17	282697	282595	0	0
T18	389620	389558	0	0
T19	322594	322362	0	0
T31	296751	296745	0	0
T114	293032	292923	0	0
T142	83772	83721	0	0
T165	65848	65797	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1006	1006	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T31	1	1	0	0
T114	1	1	0	0
T142	1	1	0	0
T165	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	508532396	13519	0	0
DepthKnown_A	508532396	508426140	0	0
RvalidKnown_A	508532396	508426140	0	0
WreadyKnown_A	508532396	508426140	0	0
gen_passthru_fifo.paramCheckPass	1006	1006	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	508532396	13519	0	0
T4	93806	1	0	0
T5	115592	27	0	0
T6	82209	35	0	0
T17	282697	56	0	0
T18	389620	1	0	0
T19	322594	3	0	0
T31	296751	1	0	0
T114	293032	56	0	0
T142	83772	1	0	0
T165	65848	1	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	508532396	508426140	0	0
T4	93806	93755	0	0
T5	115592	115533	0	0
T6	82209	82158	0	0
T17	282697	282595	0	0
T18	389620	389558	0	0
T19	322594	322362	0	0
T31	296751	296745	0	0
T114	293032	292923	0	0
T142	83772	83721	0	0
T165	65848	65797	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	508532396	508426140	0	0
T4	93806	93755	0	0
T5	115592	115533	0	0
T6	82209	82158	0	0
T17	282697	282595	0	0
T18	389620	389558	0	0
T19	322594	322362	0	0
T31	296751	296745	0	0
T114	293032	292923	0	0
T142	83772	83721	0	0
T165	65848	65797	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	508532396	508426140	0	0
T4	93806	93755	0	0
T5	115592	115533	0	0
T6	82209	82158	0	0
T17	282697	282595	0	0
T18	389620	389558	0	0
T19	322594	322362	0	0
T31	296751	296745	0	0
T114	293032	292923	0	0
T142	83772	83721	0	0
T165	65848	65797	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1006	1006	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T31	1	1	0	0
T114	1	1	0	0
T142	1	1	0	0
T165	1	1	0	0