Unified Coverage Report :: Module :: prim_lc_sync

Module : prim_lc_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_dft_en	100.00	100.00					100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_hw_debug_en	100.00	100.00					100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_check_byp_en	100.00	100.00					100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_escalate_en	100.00	100.00					100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_or_hardened.u_prim_lc_sync_a	100.00	100.00					100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_or_hardened.u_prim_lc_sync_b	100.00	100.00					100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_pinmux_hw_debug_en	100.00	100.00					100.00
tb.dut.top_earlgrey.u_rv_core_ibex.u_lc_sync	100.00	100.00					100.00
tb.dut.top_earlgrey.u_rv_core_ibex.u_pwrmgr_sync	100.00	100.00					100.00

---

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_dft_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.41	99.34	100.00			98.31	100.00	u_pinmux_strap_sampling

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[3].u_prim_buf	100.00	100.00
gen_flops.u_prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_hw_debug_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.41	99.34	100.00			98.31	100.00	u_pinmux_strap_sampling

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_flops.u_prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_check_byp_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.41	99.34	100.00			98.31	100.00	u_pinmux_strap_sampling

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_flops.u_prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_escalate_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.41	99.34	100.00			98.31	100.00	u_pinmux_strap_sampling

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_flops.u_prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_or_hardened.u_prim_lc_sync_a

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00				100.00	u_prim_lc_or_hardened

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[3].u_prim_buf	100.00	100.00
gen_buffs[2].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[2].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[2].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[2].gen_bits[3].u_prim_buf	100.00	100.00
gen_buffs[3].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[3].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[3].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[3].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_or_hardened.u_prim_lc_sync_b

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00				100.00	u_prim_lc_or_hardened

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[3].u_prim_buf	100.00	100.00
gen_buffs[2].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[2].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[2].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[2].gen_bits[3].u_prim_buf	100.00	100.00
gen_buffs[3].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[3].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[3].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[3].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_pinmux_hw_debug_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.41	99.34	100.00			98.31	100.00	u_pinmux_strap_sampling

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[3].u_prim_buf	100.00	100.00
gen_buffs[2].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[2].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[2].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[2].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_lc_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
88.03	95.29	89.29	87.38		100.00	68.18	u_rv_core_ibex

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_flops.u_prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_pwrmgr_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
88.03	95.29	89.29	87.38		100.00	68.18	u_rv_core_ibex

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_flops.u_prim_flop_2sync	100.00	100.00				100.00

Line Coverage for Module : prim_lc_sync ( parameter NumCopies=1,AsyncOn=1,ResetValueIsOn=0,LcResetValue=10 )
Line Coverage for Module self-instances :

SCORE	LINE
100.00	100.00

tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_hw_debug_en

SCORE	LINE
100.00	100.00

tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_check_byp_en

SCORE	LINE
100.00	100.00

tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_escalate_en

SCORE	LINE
100.00	100.00

tb.dut.top_earlgrey.u_rv_core_ibex.u_lc_sync

SCORE	LINE
100.00	100.00

tb.dut.top_earlgrey.u_rv_core_ibex.u_pwrmgr_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	68	1	1	100.00
CONT_ASSIGN	106	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
68	1	1
106	1	1

---

Line Coverage for Module : prim_lc_sync ( parameter NumCopies=3,AsyncOn=0,ResetValueIsOn=0,LcResetValue=10 )
Line Coverage for Module self-instances :

SCORE	LINE
100.00	100.00

tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_pinmux_hw_debug_en

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
ALWAYS	84	0	0
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	106	1	1	100.00
CONT_ASSIGN	106	1	1	100.00
CONT_ASSIGN	106	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
84		unreachable
85		unreachable
87		unreachable
93	1	1
106	3	3

---

Line Coverage for Module : prim_lc_sync ( parameter NumCopies=4,AsyncOn=0,ResetValueIsOn=0,LcResetValue=10 )
Line Coverage for Module self-instances :

SCORE	LINE
100.00	100.00

tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_or_hardened.u_prim_lc_sync_a

SCORE	LINE
100.00	100.00

tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_or_hardened.u_prim_lc_sync_b

	Line No.	Total	Covered	Percent
TOTAL		5	5	100.00
ALWAYS	84	0	0
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	106	1	1	100.00
CONT_ASSIGN	106	1	1	100.00
CONT_ASSIGN	106	1	1	100.00
CONT_ASSIGN	106	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
84		unreachable
85		unreachable
87		unreachable
93	1	1
106	4	4

---

Line Coverage for Module : prim_lc_sync ( parameter NumCopies=2,AsyncOn=1,ResetValueIsOn=0,LcResetValue=10 )
Line Coverage for Module self-instances :

SCORE	LINE
100.00	100.00

tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_dft_en

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	68	1	1	100.00
CONT_ASSIGN	106	1	1	100.00
CONT_ASSIGN	106	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
68	1	1
106	2	2

---

Assert Coverage for Module : prim_lc_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	9054	9054	0	0
OutputsKnown_A	1911084947	1906147890	0	0
gen_flops.OutputDelay_A	1527933452	1524978300	0	17958
gen_no_flops.OutputDelay_A	383151495	381126690	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9054	9054	0	0
T4	9	9	0	0
T5	9	9	0	0
T6	9	9	0	0
T17	9	9	0	0
T18	9	9	0	0
T19	9	9	0	0
T31	9	9	0	0
T114	9	9	0	0
T142	9	9	0	0
T165	9	9	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1911084947	1906147890	0	0
T4	351545	347691	0	0
T5	2452060	2447770	0	0
T6	308660	305016	0	0
T17	1051901	1045327	0	0
T18	1971998	1969060	0	0
T19	1214778	1206313	0	0
T31	5585132	5581788	0	0
T114	1086921	1083336	0	0
T142	317092	310767	0	0
T165	248211	244805	0	0

gen_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1527933452	1524978300	0	17958
T4	281288	279018	0	18
T5	1500256	1497602	0	18
T6	246842	244692	0	18
T17	843398	839506	0	18
T18	1460816	1459060	0	18
T19	970668	965552	0	18
T31	3445862	3443928	0	18
T114	872268	870078	0	18
T142	253000	249318	0	18
T165	198276	196262	0	18

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	383151495	381126690	0	0
T4	70257	68649	0	0
T5	951804	950016	0	0
T6	61818	60300	0	0
T17	208503	205773	0	0
T18	511182	509976	0	0
T19	244110	240681	0	0
T31	2139270	2137842	0	0
T114	214653	213210	0	0
T142	64092	61425	0	0
T165	49935	48519	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_dft_en

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	68	1	1	100.00
CONT_ASSIGN	106	1	1	100.00
CONT_ASSIGN	106	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
68	1	1
106	2	2

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_dft_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	1006	1006	0	0
OutputsKnown_A	127717165	127042230	0	0
gen_flops.OutputDelay_A	127717165	127035286	0	2994

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1006	1006	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T31	1	1	0	0
T114	1	1	0	0
T142	1	1	0	0
T165	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	127717165	127042230	0	0
T4	23419	22883	0	0
T5	317268	316672	0	0
T6	20606	20100	0	0
T17	69501	68591	0	0
T18	170394	169992	0	0
T19	81370	80227	0	0
T31	713090	712614	0	0
T114	71551	71070	0	0
T142	21364	20475	0	0
T165	16645	16173	0	0

gen_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	127717165	127035286	0	2994
T4	23419	22879	0	3
T5	317268	316636	0	3
T6	20606	20096	0	3
T17	69501	68583	0	3
T18	170394	169988	0	3
T19	81370	80215	0	3
T31	713090	712610	0	3
T114	71551	71062	0	3
T142	21364	20471	0	3
T165	16645	16169	0	3

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_hw_debug_en

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	68	1	1	100.00
CONT_ASSIGN	106	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
68	1	1
106	1	1

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_hw_debug_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	1006	1006	0	0
OutputsKnown_A	127717165	127042230	0	0
gen_flops.OutputDelay_A	127717165	127035286	0	2994

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1006	1006	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T31	1	1	0	0
T114	1	1	0	0
T142	1	1	0	0
T165	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	127717165	127042230	0	0
T4	23419	22883	0	0
T5	317268	316672	0	0
T6	20606	20100	0	0
T17	69501	68591	0	0
T18	170394	169992	0	0
T19	81370	80227	0	0
T31	713090	712614	0	0
T114	71551	71070	0	0
T142	21364	20475	0	0
T165	16645	16173	0	0

gen_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	127717165	127035286	0	2994
T4	23419	22879	0	3
T5	317268	316636	0	3
T6	20606	20096	0	3
T17	69501	68583	0	3
T18	170394	169988	0	3
T19	81370	80215	0	3
T31	713090	712610	0	3
T114	71551	71062	0	3
T142	21364	20471	0	3
T165	16645	16169	0	3

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_check_byp_en

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	68	1	1	100.00
CONT_ASSIGN	106	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
68	1	1
106	1	1

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_check_byp_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	1006	1006	0	0
OutputsKnown_A	127717165	127042230	0	0
gen_flops.OutputDelay_A	127717165	127035286	0	2994

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1006	1006	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T31	1	1	0	0
T114	1	1	0	0
T142	1	1	0	0
T165	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	127717165	127042230	0	0
T4	23419	22883	0	0
T5	317268	316672	0	0
T6	20606	20100	0	0
T17	69501	68591	0	0
T18	170394	169992	0	0
T19	81370	80227	0	0
T31	713090	712614	0	0
T114	71551	71070	0	0
T142	21364	20475	0	0
T165	16645	16173	0	0

gen_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	127717165	127035286	0	2994
T4	23419	22879	0	3
T5	317268	316636	0	3
T6	20606	20096	0	3
T17	69501	68583	0	3
T18	170394	169988	0	3
T19	81370	80215	0	3
T31	713090	712610	0	3
T114	71551	71062	0	3
T142	21364	20471	0	3
T165	16645	16169	0	3

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_escalate_en

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	68	1	1	100.00
CONT_ASSIGN	106	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
68	1	1
106	1	1

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_lc_escalate_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	1006	1006	0	0
OutputsKnown_A	127717165	127042230	0	0
gen_flops.OutputDelay_A	127717165	127035286	0	2994

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1006	1006	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T31	1	1	0	0
T114	1	1	0	0
T142	1	1	0	0
T165	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	127717165	127042230	0	0
T4	23419	22883	0	0
T5	317268	316672	0	0
T6	20606	20100	0	0
T17	69501	68591	0	0
T18	170394	169992	0	0
T19	81370	80227	0	0
T31	713090	712614	0	0
T114	71551	71070	0	0
T142	21364	20475	0	0
T165	16645	16173	0	0

gen_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	127717165	127035286	0	2994
T4	23419	22879	0	3
T5	317268	316636	0	3
T6	20606	20096	0	3
T17	69501	68583	0	3
T18	170394	169988	0	3
T19	81370	80215	0	3
T31	713090	712610	0	3
T114	71551	71062	0	3
T142	21364	20471	0	3
T165	16645	16169	0	3

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_or_hardened.u_prim_lc_sync_a

	Line No.	Total	Covered	Percent
TOTAL		5	5	100.00
ALWAYS	84	0	0
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	106	1	1	100.00
CONT_ASSIGN	106	1	1	100.00
CONT_ASSIGN	106	1	1	100.00
CONT_ASSIGN	106	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
84		unreachable
85		unreachable
87		unreachable
93	1	1
106	4	4

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_or_hardened.u_prim_lc_sync_a

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	1006	1006	0	0
OutputsKnown_A	127717165	127042230	0	0
gen_no_flops.OutputDelay_A	127717165	127042230	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1006	1006	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T31	1	1	0	0
T114	1	1	0	0
T142	1	1	0	0
T165	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	127717165	127042230	0	0
T4	23419	22883	0	0
T5	317268	316672	0	0
T6	20606	20100	0	0
T17	69501	68591	0	0
T18	170394	169992	0	0
T19	81370	80227	0	0
T31	713090	712614	0	0
T114	71551	71070	0	0
T142	21364	20475	0	0
T165	16645	16173	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	127717165	127042230	0	0
T4	23419	22883	0	0
T5	317268	316672	0	0
T6	20606	20100	0	0
T17	69501	68591	0	0
T18	170394	169992	0	0
T19	81370	80227	0	0
T31	713090	712614	0	0
T114	71551	71070	0	0
T142	21364	20475	0	0
T165	16645	16173	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_or_hardened.u_prim_lc_sync_b

	Line No.	Total	Covered	Percent
TOTAL		5	5	100.00
ALWAYS	84	0	0
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	106	1	1	100.00
CONT_ASSIGN	106	1	1	100.00
CONT_ASSIGN	106	1	1	100.00
CONT_ASSIGN	106	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
84		unreachable
85		unreachable
87		unreachable
93	1	1
106	4	4

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_or_hardened.u_prim_lc_sync_b

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	1006	1006	0	0
OutputsKnown_A	127717165	127042230	0	0
gen_no_flops.OutputDelay_A	127717165	127042230	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1006	1006	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T31	1	1	0	0
T114	1	1	0	0
T142	1	1	0	0
T165	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	127717165	127042230	0	0
T4	23419	22883	0	0
T5	317268	316672	0	0
T6	20606	20100	0	0
T17	69501	68591	0	0
T18	170394	169992	0	0
T19	81370	80227	0	0
T31	713090	712614	0	0
T114	71551	71070	0	0
T142	21364	20475	0	0
T165	16645	16173	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	127717165	127042230	0	0
T4	23419	22883	0	0
T5	317268	316672	0	0
T6	20606	20100	0	0
T17	69501	68591	0	0
T18	170394	169992	0	0
T19	81370	80227	0	0
T31	713090	712614	0	0
T114	71551	71070	0	0
T142	21364	20475	0	0
T165	16645	16173	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_pinmux_hw_debug_en

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
ALWAYS	84	0	0
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	106	1	1	100.00
CONT_ASSIGN	106	1	1	100.00
CONT_ASSIGN	106	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
84		unreachable
85		unreachable
87		unreachable
93	1	1
106	3	3

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_prim_lc_sync_pinmux_hw_debug_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	1006	1006	0	0
OutputsKnown_A	127717165	127042230	0	0
gen_no_flops.OutputDelay_A	127717165	127042230	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1006	1006	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T31	1	1	0	0
T114	1	1	0	0
T142	1	1	0	0
T165	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	127717165	127042230	0	0
T4	23419	22883	0	0
T5	317268	316672	0	0
T6	20606	20100	0	0
T17	69501	68591	0	0
T18	170394	169992	0	0
T19	81370	80227	0	0
T31	713090	712614	0	0
T114	71551	71070	0	0
T142	21364	20475	0	0
T165	16645	16173	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	127717165	127042230	0	0
T4	23419	22883	0	0
T5	317268	316672	0	0
T6	20606	20100	0	0
T17	69501	68591	0	0
T18	170394	169992	0	0
T19	81370	80227	0	0
T31	713090	712614	0	0
T114	71551	71070	0	0
T142	21364	20475	0	0
T165	16645	16173	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_lc_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	68	1	1	100.00
CONT_ASSIGN	106	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
68	1	1
106	1	1

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_lc_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	1006	1006	0	0
OutputsKnown_A	508532396	508426140	0	0
gen_flops.OutputDelay_A	508532396	508418578	0	2991

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1006	1006	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T31	1	1	0	0
T114	1	1	0	0
T142	1	1	0	0
T165	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	508532396	508426140	0	0
T4	93806	93755	0	0
T5	115592	115533	0	0
T6	82209	82158	0	0
T17	282697	282595	0	0
T18	389620	389558	0	0
T19	322594	322362	0	0
T31	296751	296745	0	0
T114	293032	292923	0	0
T142	83772	83721	0	0
T165	65848	65797	0	0

gen_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	508532396	508418578	0	2991
T4	93806	93751	0	3
T5	115592	115529	0	3
T6	82209	82154	0	3
T17	282697	282587	0	3
T18	389620	389554	0	3
T19	322594	322346	0	3
T31	296751	296744	0	3
T114	293032	292915	0	3
T142	83772	83717	0	3
T165	65848	65793	0	3

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_pwrmgr_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	68	1	1	100.00
CONT_ASSIGN	106	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
68	1	1
106	1	1

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_pwrmgr_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	1006	1006	0	0
OutputsKnown_A	508532396	508426140	0	0
gen_flops.OutputDelay_A	508532396	508418578	0	2991

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1006	1006	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T31	1	1	0	0
T114	1	1	0	0
T142	1	1	0	0
T165	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	508532396	508426140	0	0
T4	93806	93755	0	0
T5	115592	115533	0	0
T6	82209	82158	0	0
T17	282697	282595	0	0
T18	389620	389558	0	0
T19	322594	322362	0	0
T31	296751	296745	0	0
T114	293032	292923	0	0
T142	83772	83721	0	0
T165	65848	65797	0	0

gen_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	508532396	508418578	0	2991
T4	93806	93751	0	3
T5	115592	115529	0	3
T6	82209	82154	0	3
T17	282697	282587	0	3
T18	389620	389554	0	3
T19	322594	322346	0	3
T31	296751	296744	0	3
T114	293032	292915	0	3
T142	83772	83717	0	3
T165	65848	65793	0	3