Unified Coverage Report :: Module :: pinmux_strap_sampling

Module : pinmux_strap_sampling

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.41	99.34	100.00			98.31	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_pinmux_component_0.1/rtl/pinmux_strap_sampling.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling	99.41	99.34	100.00			98.31	100.00

---

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.41	99.34	100.00			98.31	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.49	99.62	95.65			98.70	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.51	99.03	88.46	97.97		85.09	92.00	u_pinmux_aon

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_pinmux_jtag_buf_dft	100.00	100.00
u_pinmux_jtag_buf_lc	100.00	100.00
u_pinmux_jtag_buf_rv	100.00	100.00
u_por_scanmode_sync	100.00						100.00
u_prim_lc_or_hardened	100.00	100.00	100.00				100.00
u_prim_lc_sender_pinmux_hw_debug_en	100.00	100.00				100.00
u_prim_lc_sync_lc_check_byp_en	100.00	100.00				100.00	100.00
u_prim_lc_sync_lc_dft_en	100.00	100.00				100.00	100.00
u_prim_lc_sync_lc_escalate_en	100.00	100.00				100.00	100.00
u_prim_lc_sync_lc_hw_debug_en	100.00	100.00				100.00	100.00
u_prim_lc_sync_pinmux_hw_debug_en	100.00	100.00					100.00
u_rst_por_aon_n_mux	85.19	100.00	55.56				100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pinmux_strap_sampling

	Line No.	Total	Covered	Percent
TOTAL		303	301	99.34
CONT_ASSIGN	132	1	1	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	153	1	1	100.00
CONT_ASSIGN	157	1	1	100.00
CONT_ASSIGN	187	1	1	100.00
CONT_ASSIGN	230	1	1	100.00
CONT_ASSIGN	232	1	1	100.00
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	240	1	1	100.00
CONT_ASSIGN	241	1	1	100.00
CONT_ASSIGN	242	1	1	100.00
CONT_ASSIGN	259	1	1	100.00
ALWAYS	262	9	9	100.00
ALWAYS	283	9	9	100.00
CONT_ASSIGN	308	1	1	100.00
ALWAYS	312	17	17	100.00
CONT_ASSIGN	371	1	1	100.00
CONT_ASSIGN	372	1	1	100.00
CONT_ASSIGN	373	1	1	100.00
CONT_ASSIGN	396	1	1	100.00
CONT_ASSIGN	396	1	1	100.00
CONT_ASSIGN	396	1	1	100.00
CONT_ASSIGN	396	1	1	100.00
CONT_ASSIGN	396	1	1	100.00
CONT_ASSIGN	400	1	1	100.00
CONT_ASSIGN	401	1	1	100.00
CONT_ASSIGN	404	1	1	100.00
CONT_ASSIGN	404	1	1	100.00
CONT_ASSIGN	404	1	1	100.00
CONT_ASSIGN	404	1	1	100.00
CONT_ASSIGN	405	1	1	100.00
CONT_ASSIGN	405	1	1	100.00
CONT_ASSIGN	405	1	1	100.00
CONT_ASSIGN	405	1	1	100.00
CONT_ASSIGN	412	1	1	100.00
CONT_ASSIGN	412	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	417	1	1	100.00
CONT_ASSIGN	417	1	1	100.00
CONT_ASSIGN	417	1	1	100.00
CONT_ASSIGN	417	1	1	100.00
CONT_ASSIGN	417	1	1	100.00
CONT_ASSIGN	417	1	1	100.00
CONT_ASSIGN	417	1	1	100.00
CONT_ASSIGN	417	1	1	100.00
CONT_ASSIGN	417	1	1	100.00
CONT_ASSIGN	417	1	1	100.00
CONT_ASSIGN	417	1	1	100.00
CONT_ASSIGN	417	1	1	100.00
CONT_ASSIGN	417	1	1	100.00
CONT_ASSIGN	417	1	1	100.00
CONT_ASSIGN	417	1	1	100.00
CONT_ASSIGN	417	1	1	100.00
CONT_ASSIGN	417	1	1	100.00
CONT_ASSIGN	417	1	1	100.00
CONT_ASSIGN	417	1	1	100.00
CONT_ASSIGN	417	1	1	100.00
CONT_ASSIGN	417	1	1	100.00
CONT_ASSIGN	417	1	1	100.00
CONT_ASSIGN	417	1	1	100.00
CONT_ASSIGN	417	1	1	100.00
CONT_ASSIGN	417	1	1	100.00
CONT_ASSIGN	417	1	1	100.00
CONT_ASSIGN	417	1	1	100.00
CONT_ASSIGN	417	1	1	100.00
CONT_ASSIGN	417	1	1	100.00
CONT_ASSIGN	417	1	1	100.00
CONT_ASSIGN	417	1	1	100.00
CONT_ASSIGN	417	1	1	100.00
CONT_ASSIGN	417	1	1	100.00
CONT_ASSIGN	417	1	1	100.00
CONT_ASSIGN	417	1	1	100.00
CONT_ASSIGN	417	1	1	100.00
CONT_ASSIGN	417	1	1	100.00
CONT_ASSIGN	417	1	1	100.00
CONT_ASSIGN	417	1	1	100.00
CONT_ASSIGN	417	1	1	100.00
CONT_ASSIGN	417	1	1	100.00
CONT_ASSIGN	417	1	1	100.00
CONT_ASSIGN	417	1	1	100.00
CONT_ASSIGN	417	1	1	100.00
CONT_ASSIGN	417	1	1	100.00
CONT_ASSIGN	417	1	1	100.00
CONT_ASSIGN	417	1	1	100.00
CONT_ASSIGN	417	1	1	100.00
CONT_ASSIGN	417	1	1	100.00
CONT_ASSIGN	417	1	1	100.00
CONT_ASSIGN	417	1	1	100.00
CONT_ASSIGN	417	1	1	100.00
CONT_ASSIGN	417	1	1	100.00
CONT_ASSIGN	417	1	1	100.00
CONT_ASSIGN	417	1	1	100.00
CONT_ASSIGN	417	1	1	100.00
CONT_ASSIGN	417	1	1	100.00
CONT_ASSIGN	417	1	1	100.00
CONT_ASSIGN	418	1	1	100.00
CONT_ASSIGN	418	1	1	100.00
CONT_ASSIGN	418	1	1	100.00
CONT_ASSIGN	418	1	1	100.00
CONT_ASSIGN	418	1	1	100.00
CONT_ASSIGN	418	1	1	100.00
CONT_ASSIGN	418	1	1	100.00
CONT_ASSIGN	418	1	1	100.00
CONT_ASSIGN	418	1	1	100.00
CONT_ASSIGN	418	1	1	100.00
CONT_ASSIGN	418	1	1	100.00
CONT_ASSIGN	418	1	1	100.00
CONT_ASSIGN	418	1	1	100.00
CONT_ASSIGN	418	1	1	100.00
CONT_ASSIGN	418	1	1	100.00
CONT_ASSIGN	418	1	1	100.00
CONT_ASSIGN	418	1	1	100.00
CONT_ASSIGN	418	1	1	100.00
CONT_ASSIGN	418	1	1	100.00
CONT_ASSIGN	418	1	1	100.00
CONT_ASSIGN	418	1	1	100.00
CONT_ASSIGN	418	1	1	100.00
CONT_ASSIGN	418	1	1	100.00
CONT_ASSIGN	418	1	1	100.00
CONT_ASSIGN	418	1	1	100.00
CONT_ASSIGN	418	1	1	100.00
CONT_ASSIGN	418	1	1	100.00
CONT_ASSIGN	418	1	1	100.00
CONT_ASSIGN	418	1	1	100.00
CONT_ASSIGN	418	1	1	100.00
CONT_ASSIGN	418	1	1	100.00
CONT_ASSIGN	418	1	1	100.00
CONT_ASSIGN	418	1	1	100.00
CONT_ASSIGN	418	1	1	100.00
CONT_ASSIGN	418	1	1	100.00
CONT_ASSIGN	418	1	1	100.00
CONT_ASSIGN	418	1	1	100.00
CONT_ASSIGN	418	1	1	100.00
CONT_ASSIGN	418	1	1	100.00
CONT_ASSIGN	418	1	1	100.00
CONT_ASSIGN	418	1	1	100.00
CONT_ASSIGN	418	1	1	100.00
CONT_ASSIGN	418	1	1	100.00
CONT_ASSIGN	418	1	1	100.00
CONT_ASSIGN	418	1	1	100.00
CONT_ASSIGN	418	1	1	100.00
CONT_ASSIGN	418	1	1	100.00
CONT_ASSIGN	418	1	1	100.00
CONT_ASSIGN	418	1	1	100.00
CONT_ASSIGN	418	1	1	100.00
CONT_ASSIGN	418	1	1	100.00
CONT_ASSIGN	418	1	1	100.00
CONT_ASSIGN	418	1	1	100.00
CONT_ASSIGN	418	1	1	100.00
CONT_ASSIGN	418	1	1	100.00
CONT_ASSIGN	418	1	1	100.00
CONT_ASSIGN	418	1	1	100.00
CONT_ASSIGN	418	1	1	100.00
CONT_ASSIGN	419	1	1	100.00
CONT_ASSIGN	419	1	1	100.00
CONT_ASSIGN	419	1	1	100.00
CONT_ASSIGN	419	1	1	100.00
CONT_ASSIGN	419	1	1	100.00
CONT_ASSIGN	419	1	1	100.00
CONT_ASSIGN	419	1	1	100.00
CONT_ASSIGN	419	1	1	100.00
CONT_ASSIGN	419	1	1	100.00
CONT_ASSIGN	419	1	1	100.00
CONT_ASSIGN	419	1	1	100.00
CONT_ASSIGN	419	1	1	100.00
CONT_ASSIGN	419	1	1	100.00
CONT_ASSIGN	419	1	1	100.00
CONT_ASSIGN	419	1	1	100.00
CONT_ASSIGN	419	1	1	100.00
CONT_ASSIGN	419	1	1	100.00
CONT_ASSIGN	419	1	1	100.00
CONT_ASSIGN	419	1	1	100.00
CONT_ASSIGN	419	1	1	100.00
CONT_ASSIGN	419	1	1	100.00
CONT_ASSIGN	419	1	1	100.00
CONT_ASSIGN	419	1	1	100.00
CONT_ASSIGN	419	1	1	100.00
CONT_ASSIGN	419	1	1	100.00
CONT_ASSIGN	419	1	1	100.00
CONT_ASSIGN	419	1	1	100.00
CONT_ASSIGN	419	1	1	100.00
CONT_ASSIGN	419	1	1	100.00
CONT_ASSIGN	419	1	1	100.00
CONT_ASSIGN	419	1	1	100.00
CONT_ASSIGN	419	1	1	100.00
CONT_ASSIGN	419	1	1	100.00
CONT_ASSIGN	419	1	1	100.00
CONT_ASSIGN	419	1	1	100.00
CONT_ASSIGN	419	1	1	100.00
CONT_ASSIGN	419	1	1	100.00
CONT_ASSIGN	419	1	1	100.00
CONT_ASSIGN	419	1	1	100.00
CONT_ASSIGN	419	1	1	100.00
CONT_ASSIGN	419	1	1	100.00
CONT_ASSIGN	419	1	1	100.00
CONT_ASSIGN	419	1	1	100.00
CONT_ASSIGN	419	1	1	100.00
CONT_ASSIGN	419	1	1	100.00
CONT_ASSIGN	419	1	1	100.00
CONT_ASSIGN	419	1	1	100.00
CONT_ASSIGN	419	1	1	100.00
CONT_ASSIGN	419	1	1	100.00
CONT_ASSIGN	419	1	1	100.00
CONT_ASSIGN	419	1	1	100.00
CONT_ASSIGN	419	1	1	100.00
CONT_ASSIGN	419	1	1	100.00
CONT_ASSIGN	419	1	1	100.00
CONT_ASSIGN	419	1	0	0.00
CONT_ASSIGN	419	1	0	0.00
CONT_ASSIGN	419	1	1	100.00
CONT_ASSIGN	419	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	420	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_pinmux_component_0.1/rtl/pinmux_strap_sampling.sv' or '../src/lowrisc_ip_pinmux_component_0.1/rtl/pinmux_strap_sampling.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
132	1	1
133	1	1
153	1	1
157	1	1
187	1	1
230	1	1
232	1	1
236	1	1
240	1	1
241	1	1
242	1	1
259	1	1
262	1	1
263	1	1
264	1	1
268	1	1
269	1	1
			MISSING_ELSE
274	1	1
275	1	1
276	1	1
277	1	1
			MISSING_ELSE
			MISSING_ELSE
283	1	1
284	1	1
285	1	1
286	1	1
287	1	1
289	1	1
290	1	1
291	1	1
292	1	1
308	1	1
312	1	1
315	1	1
316	1	1
317	1	1
319	1	1
321	1	1
323	1	1
324	1	1
325	1	1
328	1	1
329	1	1
330	1	1
331	1	1
			MISSING_ELSE
335	1	1
336	1	1
337	1	1
338	1	1
			==> MISSING_ELSE
371	1	1
372	1	1
373	1	1
396	5	5
400	1	1
401	1	1
404	4	4
405	4	4
412	2	2
414	3	3
417	58	58
418	58	58
419	56	58
420	58	58

---

Cond Coverage for Module : pinmux_strap_sampling

	Total	Covered	Percent
Conditions	55	55	100.00
Logical	55	55	100.00
Non-Logical	0	0
Event	0	0

 LINE       230
 EXPRESSION (lc_strap_sample_en ? in_padring_i[30] : tap_strap_q[0])
             ---------1--------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       232
 EXPRESSION (rv_strap_sample_en ? in_padring_i[27] : tap_strap_q[1])
             ---------1--------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       236
 EXPRESSION (dft_strap_sample_en ? ({in_padring_i[42], in_padring_i[40]}) : dft_strap_q)
             ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       240
 EXPRESSION (dft_strap_sample_en | dft_strap_valid_q)
             ---------1---------   --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6

 LINE       268
 EXPRESSION (strap_en_q && tap_sampling_en)
             -----1----    -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T136,T20,T62
1	1	Covered	T4,T5,T6

 LINE       274
 EXPRESSION (strap_en_q || tap_sampling_en)
             -----1----    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T5,T17,T19
0	1	Covered	T4,T5,T6
1	0	Covered	T136,T20,T62

 LINE       396
 EXPRESSION (jtag_en ? 1'b0 : in_padring_i[35])
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T62,T59,T60

 LINE       396
 EXPRESSION (jtag_en ? 1'b0 : in_padring_i[36])
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T62,T59,T60

 LINE       396
 EXPRESSION (jtag_en ? 1'b0 : in_padring_i[37])
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T62,T59,T60

 LINE       396
 EXPRESSION (jtag_en ? 1'b0 : in_padring_i[38])
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T62,T59,T60

 LINE       396
 EXPRESSION (jtag_en ? 1'b0 : in_padring_i[39])
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T62,T59,T60

 LINE       400
 EXPRESSION (jtag_en ? jtag_rsp.tdo : out_core_i[36])
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T62,T59,T60

 LINE       401
 EXPRESSION (jtag_en ? jtag_rsp.tdo_oe : oe_core_i[36])
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T62,T59,T60

 LINE       404
 EXPRESSION (jtag_en ? 1'b0 : out_core_i[35])
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T62,T59,T60

 LINE       404
 EXPRESSION (jtag_en ? 1'b0 : out_core_i[37])
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T62,T59,T60

 LINE       404
 EXPRESSION (jtag_en ? 1'b0 : out_core_i[38])
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T62,T59,T60

 LINE       404
 EXPRESSION (jtag_en ? 1'b0 : out_core_i[39])
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T62,T59,T60

 LINE       405
 EXPRESSION (jtag_en ? 1'b0 : oe_core_i[35])
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T62,T59,T60

 LINE       405
 EXPRESSION (jtag_en ? 1'b0 : oe_core_i[37])
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T62,T59,T60

 LINE       405
 EXPRESSION (jtag_en ? 1'b0 : oe_core_i[38])
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T62,T59,T60

 LINE       405
 EXPRESSION (jtag_en ? 1'b0 : oe_core_i[39])
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T62,T59,T60

 LINE       412
 EXPRESSION 
 Number  Term
      1  jtag_en ? ('{schmitt_en:1'b1, (*adjust*)default:'0, (*adjust*)default:'0, (*adjust*)default:'0, (*adjust*)default:'0, (*adjust*)default:'0, (*adjust*)default:'0, (*adjust*)default:'0, (*adjust*)default:'0, (*adjust*)default:'0}) : attr_core_i[38])

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T62,T59,T60

 LINE       412
 EXPRESSION 
 Number  Term
      1  jtag_en ? ('{schmitt_en:1'b1, (*adjust*)default:'0, (*adjust*)default:'0, (*adjust*)default:'0, (*adjust*)default:'0, (*adjust*)default:'0, (*adjust*)default:'0, (*adjust*)default:'0, (*adjust*)default:'0, (*adjust*)default:'0}) : attr_core_i[39])

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T62,T59,T60

 LINE       414
 EXPRESSION (jtag_en ? '0 : attr_core_i[35])
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T62,T59,T60

 LINE       414
 EXPRESSION (jtag_en ? '0 : attr_core_i[36])
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T62,T59,T60

 LINE       414
 EXPRESSION (jtag_en ? '0 : attr_core_i[37])
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T62,T59,T60

---

Branch Coverage for Module : pinmux_strap_sampling

	Line No.	Total	Covered	Percent
Branches		59	58	98.31
TERNARY	230	2	2	100.00
TERNARY	232	2	2	100.00
TERNARY	236	2	2	100.00
TERNARY	396	2	2	100.00
TERNARY	404	2	2	100.00
TERNARY	405	2	2	100.00
TERNARY	414	2	2	100.00
TERNARY	396	2	2	100.00
TERNARY	400	2	2	100.00
TERNARY	401	2	2	100.00
TERNARY	414	2	2	100.00
TERNARY	396	2	2	100.00
TERNARY	404	2	2	100.00
TERNARY	405	2	2	100.00
TERNARY	414	2	2	100.00
TERNARY	396	2	2	100.00
TERNARY	404	2	2	100.00
TERNARY	405	2	2	100.00
TERNARY	412	2	2	100.00
TERNARY	396	2	2	100.00
TERNARY	404	2	2	100.00
TERNARY	405	2	2	100.00
TERNARY	412	2	2	100.00
IF	268	2	2	100.00
IF	274	3	3	100.00
IF	283	2	2	100.00
CASE	321	6	5	83.33

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_pinmux_component_0.1/rtl/pinmux_strap_sampling.sv' or '../src/lowrisc_ip_pinmux_component_0.1/rtl/pinmux_strap_sampling.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	230	(lc_strap_sample_en) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	232	(rv_strap_sample_en) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	236	(dft_strap_sample_en) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	396	(jtag_en) ? 

Branches:

-1-	Status	Tests
1	Covered	T62,T59,T60
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	404	(jtag_en) ? 

Branches:

-1-	Status	Tests
1	Covered	T62,T59,T60
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	405	(jtag_en) ? 

Branches:

-1-	Status	Tests
1	Covered	T62,T59,T60
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	414	(jtag_en) ? 

Branches:

-1-	Status	Tests
1	Covered	T62,T59,T60
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	396	(jtag_en) ? 

Branches:

-1-	Status	Tests
1	Covered	T62,T59,T60
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	400	(jtag_en) ? 

Branches:

-1-	Status	Tests
1	Covered	T62,T59,T60
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	401	(jtag_en) ? 

Branches:

-1-	Status	Tests
1	Covered	T62,T59,T60
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	414	(jtag_en) ? 

Branches:

-1-	Status	Tests
1	Covered	T62,T59,T60
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	396	(jtag_en) ? 

Branches:

-1-	Status	Tests
1	Covered	T62,T59,T60
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	404	(jtag_en) ? 

Branches:

-1-	Status	Tests
1	Covered	T62,T59,T60
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	405	(jtag_en) ? 

Branches:

-1-	Status	Tests
1	Covered	T62,T59,T60
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	414	(jtag_en) ? 

Branches:

-1-	Status	Tests
1	Covered	T62,T59,T60
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	396	(jtag_en) ? 

Branches:

-1-	Status	Tests
1	Covered	T62,T59,T60
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	404	(jtag_en) ? 

Branches:

-1-	Status	Tests
1	Covered	T62,T59,T60
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	405	(jtag_en) ? 

Branches:

-1-	Status	Tests
1	Covered	T62,T59,T60
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	412	(jtag_en) ? 

Branches:

-1-	Status	Tests
1	Covered	T62,T59,T60
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	396	(jtag_en) ? 

Branches:

-1-	Status	Tests
1	Covered	T62,T59,T60
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	404	(jtag_en) ? 

Branches:

-1-	Status	Tests
1	Covered	T62,T59,T60
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	405	(jtag_en) ? 

Branches:

-1-	Status	Tests
1	Covered	T62,T59,T60
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	412	(jtag_en) ? 

Branches:

-1-	Status	Tests
1	Covered	T62,T59,T60
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	268	if ((strap_en_q && tap_sampling_en))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	274	if ((strap_en_q || tap_sampling_en))
-2-:	276	if (lc_ctrl_pkg::lc_tx_test_true_strict(pinmux_hw_debug_en[HwDebugEnSample]))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
0	-	Covered	T5,T17,T19

	LineNo.	Expression
-1-:	283	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	321	case (tap_strap)
-2-:	328	if (lc_ctrl_pkg::lc_tx_test_true_strict(pinmux_hw_debug_en[HwDebugEnTapSel]))
-3-:	335	if (lc_ctrl_pkg::lc_tx_test_true_strict(lc_dft_en[DftEnTapSel]))

Branches:

-1-	-2-	-3-	Status	Tests
LcTapSel	-	-	Covered	T62,T59,T60
RvTapSel	1	-	Covered	T61,T117,T63
RvTapSel	0	-	Covered	T61,T424,T425
DftTapSel	-	1	Covered	T116,T97,T159
DftTapSel	-	0	Not Covered
default	-	-	Covered	T4,T5,T6

---

Assert Coverage for Module : pinmux_strap_sampling

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DftTapOff0_A	127717165	38410377	0	282
LcHwDebugEnClear_A	127717165	11975219	0	15
LcHwDebugEnSetRev0_A	127717165	1450	0	101
LcHwDebugEnSetRev1_A	127717165	1450	0	101
LcHwDebugEnSet_A	127717165	1450	0	0
RvTapOff0_A	127717165	254	0	202
RvTapOff1_A	127717165	35626483	0	0
TapStrapKnown_A	127717165	127042230	0	0
dft_strap0_idxRange_A	1006	1006	0	0
dft_strap1_idxRange_A	1006	1006	0	0
tap_strap0_idxRange_A	1006	1006	0	0
tap_strap1_idxRange_A	1006	1006	0	0
tck_idxRange_A	1006	1006	0	0
tdi_idxRange_A	1006	1006	0	0
tdo_idxRange_A	1006	1006	0	0
tms_idxRange_A	1006	1006	0	0
trst_idxRange_A	1006	1006	0	0

DftTapOff0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	127717165	38410377	0	282
T4	23419	2481	0	0
T5	317268	53140	0	0
T6	20606	2481	0	0
T17	69501	10067	0	0
T18	170394	2483	0	0
T19	81370	11257	0	0
T21	0	0	0	2
T31	713090	2483	0	0
T60	0	0	0	2
T62	0	0	0	2
T67	0	0	0	2
T68	0	0	0	2
T78	0	0	0	2
T114	71551	10069	0	0
T136	0	0	0	2
T137	0	0	0	2
T142	21364	2481	0	0
T165	16645	2481	0	0
T172	0	0	0	2
T174	0	0	0	2

LcHwDebugEnClear_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	127717165	11975219	0	15
T5	317268	24551	0	0
T6	20606	0	0	0
T17	69501	5103	0	0
T18	170394	0	0	0
T19	81370	0	0	0
T31	713090	0	0	0
T57	362476	0	0	0
T59	0	10333	0	0
T60	0	2296	0	0
T114	71551	5103	0	0
T115	0	5044	0	0
T127	0	4953	0	0
T128	0	4982	0	0
T142	21364	0	0	0
T158	0	0	0	1
T165	16645	0	0	0
T203	0	0	0	1
T214	0	0	0	1
T215	0	0	0	1
T238	0	12195	0	0
T300	0	0	0	1
T302	0	0	0	1
T361	0	5101	0	0
T426	0	0	0	1
T427	0	0	0	1
T428	0	0	0	1
T429	0	0	0	1

LcHwDebugEnSetRev0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	127717165	1450	0	101
T4	23419	1	0	0
T5	317268	9	0	0
T6	20606	1	0	0
T17	69501	2	0	0
T18	170394	1	0	0
T19	81370	3	0	0
T21	0	0	0	1
T31	713090	1	0	0
T55	0	0	0	1
T60	0	0	0	1
T62	0	0	0	1
T68	0	0	0	1
T78	0	0	0	1
T114	71551	2	0	0
T142	21364	1	0	0
T158	0	0	0	1
T165	16645	1	0	0
T172	0	0	0	1
T174	0	0	0	1
T284	0	0	0	1

LcHwDebugEnSetRev1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	127717165	1450	0	101
T4	23419	1	0	0
T5	317268	9	0	0
T6	20606	1	0	0
T17	69501	2	0	0
T18	170394	1	0	0
T19	81370	3	0	0
T21	0	0	0	1
T31	713090	1	0	0
T55	0	0	0	1
T60	0	0	0	1
T62	0	0	0	1
T68	0	0	0	1
T78	0	0	0	1
T114	71551	2	0	0
T142	21364	1	0	0
T158	0	0	0	1
T165	16645	1	0	0
T172	0	0	0	1
T174	0	0	0	1
T284	0	0	0	1

LcHwDebugEnSet_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	127717165	1450	0	0
T4	23419	1	0	0
T5	317268	9	0	0
T6	20606	1	0	0
T17	69501	2	0	0
T18	170394	1	0	0
T19	81370	3	0	0
T31	713090	1	0	0
T114	71551	2	0	0
T142	21364	1	0	0
T165	16645	1	0	0

RvTapOff0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	127717165	254	0	202
T1	43459	0	0	0
T20	510355	1	0	0
T21	0	2	0	2
T34	240662	0	0	0
T55	0	0	0	2
T59	49246	0	0	0
T60	0	3	0	2
T62	19830	1	0	2
T68	0	3	0	2
T78	0	3	0	2
T107	125291	0	0	0
T138	0	1	0	0
T158	0	1	0	2
T172	0	1	0	2
T174	0	1	0	2
T179	23090	0	0	0
T180	26753	0	0	0
T181	42132	0	0	0
T189	125831	0	0	0
T284	0	0	0	2

RvTapOff1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	127717165	35626483	0	0
T4	23419	2812	0	0
T5	317268	47838	0	0
T6	20606	2800	0	0
T17	69501	10808	0	0
T18	170394	2827	0	0
T19	81370	8605	0	0
T31	713090	2867	0	0
T114	71551	10462	0	0
T142	21364	3037	0	0
T165	16645	2790	0	0

TapStrapKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	127717165	127042230	0	0
T4	23419	22883	0	0
T5	317268	316672	0	0
T6	20606	20100	0	0
T17	69501	68591	0	0
T18	170394	169992	0	0
T19	81370	80227	0	0
T31	713090	712614	0	0
T114	71551	71070	0	0
T142	21364	20475	0	0
T165	16645	16173	0	0

dft_strap0_idxRange_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1006	1006	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T31	1	1	0	0
T114	1	1	0	0
T142	1	1	0	0
T165	1	1	0	0

dft_strap1_idxRange_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1006	1006	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T31	1	1	0	0
T114	1	1	0	0
T142	1	1	0	0
T165	1	1	0	0

tap_strap0_idxRange_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1006	1006	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T31	1	1	0	0
T114	1	1	0	0
T142	1	1	0	0
T165	1	1	0	0

tap_strap1_idxRange_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1006	1006	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T31	1	1	0	0
T114	1	1	0	0
T142	1	1	0	0
T165	1	1	0	0

tck_idxRange_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1006	1006	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T31	1	1	0	0
T114	1	1	0	0
T142	1	1	0	0
T165	1	1	0	0

tdi_idxRange_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1006	1006	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T31	1	1	0	0
T114	1	1	0	0
T142	1	1	0	0
T165	1	1	0	0

tdo_idxRange_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1006	1006	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T31	1	1	0	0
T114	1	1	0	0
T142	1	1	0	0
T165	1	1	0	0

tms_idxRange_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1006	1006	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T31	1	1	0	0
T114	1	1	0	0
T142	1	1	0	0
T165	1	1	0	0

trst_idxRange_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1006	1006	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T31	1	1	0	0
T114	1	1	0	0
T142	1	1	0	0
T165	1	1	0	0