Line Coverage for Module :
prim_edn_req
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 54 | 1 | 1 | 100.00 |
CONT_ASSIGN | 139 | 1 | 1 | 100.00 |
ALWAYS | 143 | 3 | 3 | 100.00 |
CONT_ASSIGN | 149 | 1 | 1 | 100.00 |
ALWAYS | 163 | 0 | 0 | |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_edn_req_0.1/rtl/prim_edn_req.sv' or '../src/lowrisc_prim_edn_req_0.1/rtl/prim_edn_req.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
54 |
1 |
1 |
139 |
1 |
1 |
143 |
1 |
1 |
144 |
1 |
1 |
146 |
1 |
1 |
149 |
1 |
1 |
163 |
|
unreachable |
164 |
|
unreachable |
165 |
|
unreachable |
166 |
|
unreachable |
167 |
|
unreachable |
168 |
|
unreachable |
|
|
|
==> MISSING_ELSE |
Cond Coverage for Module :
prim_edn_req
| Total | Covered | Percent |
Conditions | 13 | 11 | 84.62 |
Logical | 13 | 11 | 84.62 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 54
EXPRESSION (req_i & ((~ack_o)))
--1-- -----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T4,T5,T6 |
1 | 1 | Covered | T4,T5,T6 |
LINE 139
EXPRESSION ((req_i && ack_o) ? 1'b1 : (word_ack ? (fips_q & word_fips) : fips_q))
--------1-------
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T4,T5,T6 |
LINE 139
SUB-EXPRESSION (req_i && ack_o)
--1-- --2--
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T4,T5,T6 |
1 | 1 | Covered | T4,T5,T6 |
LINE 139
SUB-EXPRESSION (word_ack ? (fips_q & word_fips) : fips_q)
----1---
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T4,T5,T6 |
LINE 139
SUB-EXPRESSION (fips_q & word_fips)
---1-- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T4,T5,T6 |
1 | 1 | Covered | T82,T72,T143 |
Branch Coverage for Module :
prim_edn_req
| Line No. | Total | Covered | Percent |
Branches |
|
5 |
5 |
100.00 |
TERNARY |
139 |
3 |
3 |
100.00 |
IF |
143 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_edn_req_0.1/rtl/prim_edn_req.sv' or '../src/lowrisc_prim_edn_req_0.1/rtl/prim_edn_req.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 139 ((req_i && ack_o)) ?
-2-: 139 (word_ack) ?
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T4,T5,T6 |
0 |
1 |
Covered |
T4,T5,T6 |
0 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 143 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T6 |
0 |
Covered |
T4,T5,T6 |
Assert Coverage for Module :
prim_edn_req
Assertion Details
DataOutputDiffFromPrev_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
507881805 |
97434502 |
0 |
0 |
T1 |
128767 |
0 |
0 |
0 |
T20 |
212338 |
181439 |
0 |
0 |
T34 |
989389 |
0 |
0 |
0 |
T55 |
0 |
139270 |
0 |
0 |
T56 |
0 |
965109 |
0 |
0 |
T57 |
150680 |
123151 |
0 |
0 |
T58 |
0 |
100544 |
0 |
0 |
T59 |
200405 |
0 |
0 |
0 |
T62 |
79638 |
0 |
0 |
0 |
T82 |
0 |
74727 |
0 |
0 |
T107 |
517692 |
440684 |
0 |
0 |
T110 |
0 |
202387 |
0 |
0 |
T136 |
462483 |
0 |
0 |
0 |
T174 |
0 |
104074 |
0 |
0 |
T179 |
91787 |
0 |
0 |
0 |
T189 |
519259 |
0 |
0 |
0 |
T415 |
0 |
101448 |
0 |
0 |
DataOutputValid_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
508532396 |
4316 |
0 |
0 |
T4 |
93806 |
1 |
0 |
0 |
T5 |
115592 |
18 |
0 |
0 |
T6 |
82209 |
1 |
0 |
0 |
T17 |
282697 |
4 |
0 |
0 |
T18 |
389620 |
1 |
0 |
0 |
T19 |
322594 |
3 |
0 |
0 |
T31 |
296751 |
1 |
0 |
0 |
T114 |
293032 |
4 |
0 |
0 |
T142 |
83772 |
1 |
0 |
0 |
T165 |
65848 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_edn_if
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 54 | 1 | 1 | 100.00 |
CONT_ASSIGN | 139 | 1 | 1 | 100.00 |
ALWAYS | 143 | 3 | 3 | 100.00 |
CONT_ASSIGN | 149 | 1 | 1 | 100.00 |
ALWAYS | 163 | 0 | 0 | |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_edn_req_0.1/rtl/prim_edn_req.sv' or '../src/lowrisc_prim_edn_req_0.1/rtl/prim_edn_req.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
54 |
1 |
1 |
139 |
1 |
1 |
143 |
1 |
1 |
144 |
1 |
1 |
146 |
1 |
1 |
149 |
1 |
1 |
163 |
|
unreachable |
164 |
|
unreachable |
165 |
|
unreachable |
166 |
|
unreachable |
167 |
|
unreachable |
168 |
|
unreachable |
|
|
|
==> MISSING_ELSE |
Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_edn_if
| Total | Covered | Percent |
Conditions | 13 | 11 | 84.62 |
Logical | 13 | 11 | 84.62 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 54
EXPRESSION (req_i & ((~ack_o)))
--1-- -----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T4,T5,T6 |
1 | 1 | Covered | T4,T5,T6 |
LINE 139
EXPRESSION ((req_i && ack_o) ? 1'b1 : (word_ack ? (fips_q & word_fips) : fips_q))
--------1-------
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T4,T5,T6 |
LINE 139
SUB-EXPRESSION (req_i && ack_o)
--1-- --2--
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T4,T5,T6 |
1 | 1 | Covered | T4,T5,T6 |
LINE 139
SUB-EXPRESSION (word_ack ? (fips_q & word_fips) : fips_q)
----1---
-1- | Status | Tests |
0 | Covered | T4,T5,T6 |
1 | Covered | T4,T5,T6 |
LINE 139
SUB-EXPRESSION (fips_q & word_fips)
---1-- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T4,T5,T6 |
1 | 1 | Covered | T82,T72,T143 |
Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_edn_if
| Line No. | Total | Covered | Percent |
Branches |
|
5 |
5 |
100.00 |
TERNARY |
139 |
3 |
3 |
100.00 |
IF |
143 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_edn_req_0.1/rtl/prim_edn_req.sv' or '../src/lowrisc_prim_edn_req_0.1/rtl/prim_edn_req.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 139 ((req_i && ack_o)) ?
-2-: 139 (word_ack) ?
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T4,T5,T6 |
0 |
1 |
Covered |
T4,T5,T6 |
0 |
0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 143 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T6 |
0 |
Covered |
T4,T5,T6 |
Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_edn_if
Assertion Details
DataOutputDiffFromPrev_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
507881805 |
97434502 |
0 |
0 |
T1 |
128767 |
0 |
0 |
0 |
T20 |
212338 |
181439 |
0 |
0 |
T34 |
989389 |
0 |
0 |
0 |
T55 |
0 |
139270 |
0 |
0 |
T56 |
0 |
965109 |
0 |
0 |
T57 |
150680 |
123151 |
0 |
0 |
T58 |
0 |
100544 |
0 |
0 |
T59 |
200405 |
0 |
0 |
0 |
T62 |
79638 |
0 |
0 |
0 |
T82 |
0 |
74727 |
0 |
0 |
T107 |
517692 |
440684 |
0 |
0 |
T110 |
0 |
202387 |
0 |
0 |
T136 |
462483 |
0 |
0 |
0 |
T174 |
0 |
104074 |
0 |
0 |
T179 |
91787 |
0 |
0 |
0 |
T189 |
519259 |
0 |
0 |
0 |
T415 |
0 |
101448 |
0 |
0 |
DataOutputValid_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
508532396 |
4316 |
0 |
0 |
T4 |
93806 |
1 |
0 |
0 |
T5 |
115592 |
18 |
0 |
0 |
T6 |
82209 |
1 |
0 |
0 |
T17 |
282697 |
4 |
0 |
0 |
T18 |
389620 |
1 |
0 |
0 |
T19 |
322594 |
3 |
0 |
0 |
T31 |
296751 |
1 |
0 |
0 |
T114 |
293032 |
4 |
0 |
0 |
T142 |
83772 |
1 |
0 |
0 |
T165 |
65848 |
1 |
0 |
0 |