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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
90.71 92.91 83.55 90.13 95.03 97.53 85.09


Total test records in report: 1006
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T475 /workspace/coverage/default/70.chip_sw_all_escalation_resets.3814625739 Jul 01 07:44:10 PM PDT 24 Jul 01 07:55:54 PM PDT 24 5393324144 ps
T194 /workspace/coverage/default/2.chip_sw_otbn_smoketest.1640303243 Jul 01 07:35:26 PM PDT 24 Jul 01 07:52:00 PM PDT 24 4837397000 ps
T201 /workspace/coverage/default/0.chip_sw_otp_ctrl_vendor_test_csr_access.1987846938 Jul 01 07:11:27 PM PDT 24 Jul 01 07:13:20 PM PDT 24 2316250673 ps
T432 /workspace/coverage/default/54.chip_sw_alert_handler_lpg_sleep_mode_alerts.3729950190 Jul 01 07:45:29 PM PDT 24 Jul 01 07:52:58 PM PDT 24 3631975820 ps
T154 /workspace/coverage/default/0.chip_sw_sram_ctrl_execution_main.3320437383 Jul 01 07:11:27 PM PDT 24 Jul 01 07:25:30 PM PDT 24 6283707244 ps
T220 /workspace/coverage/default/2.chip_sw_i2c_host_tx_rx_idx1.598676577 Jul 01 07:34:11 PM PDT 24 Jul 01 07:48:38 PM PDT 24 5461134370 ps
T553 /workspace/coverage/default/1.chip_sw_entropy_src_smoketest.2651974311 Jul 01 07:28:22 PM PDT 24 Jul 01 07:36:32 PM PDT 24 2977809144 ps
T198 /workspace/coverage/default/11.chip_sw_alert_handler_lpg_sleep_mode_alerts.1317153011 Jul 01 07:41:38 PM PDT 24 Jul 01 07:47:36 PM PDT 24 3215860566 ps
T385 /workspace/coverage/default/67.chip_sw_all_escalation_resets.1175505294 Jul 01 07:44:30 PM PDT 24 Jul 01 07:54:28 PM PDT 24 4627252140 ps
T325 /workspace/coverage/default/19.chip_sw_alert_handler_lpg_sleep_mode_alerts.1154798645 Jul 01 07:44:45 PM PDT 24 Jul 01 07:53:02 PM PDT 24 4473212600 ps
T211 /workspace/coverage/default/2.chip_sw_lc_walkthrough_testunlocks.907177372 Jul 01 07:29:17 PM PDT 24 Jul 01 08:06:39 PM PDT 24 33707826633 ps
T103 /workspace/coverage/default/2.chip_sw_power_idle_load.5465159 Jul 01 07:34:42 PM PDT 24 Jul 01 07:47:49 PM PDT 24 4239378672 ps
T554 /workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq.620091259 Jul 01 07:27:25 PM PDT 24 Jul 01 08:11:19 PM PDT 24 13752471009 ps
T407 /workspace/coverage/default/0.chip_sw_edn_entropy_reqs_jitter.1991186871 Jul 01 07:11:11 PM PDT 24 Jul 01 07:37:27 PM PDT 24 6545455450 ps
T375 /workspace/coverage/default/1.chip_sw_pwrmgr_all_reset_reqs.4145538990 Jul 01 07:20:30 PM PDT 24 Jul 01 07:48:46 PM PDT 24 12089556765 ps
T122 /workspace/coverage/default/1.chip_sw_alert_test.4004293997 Jul 01 07:22:57 PM PDT 24 Jul 01 07:28:14 PM PDT 24 3556549380 ps
T417 /workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq.421403719 Jul 01 07:31:33 PM PDT 24 Jul 01 08:27:57 PM PDT 24 17296151272 ps
T301 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0.47383646 Jul 01 07:19:42 PM PDT 24 Jul 01 08:08:54 PM PDT 24 10634506945 ps
T555 /workspace/coverage/default/2.chip_sw_alert_handler_escalation.1101146454 Jul 01 07:31:10 PM PDT 24 Jul 01 07:42:21 PM PDT 24 5544422878 ps
T556 /workspace/coverage/default/1.chip_sw_otp_ctrl_ecc_error_vendor_test.2642236025 Jul 01 07:17:11 PM PDT 24 Jul 01 07:21:52 PM PDT 24 3172480550 ps
T557 /workspace/coverage/default/1.chip_sw_aes_idle.3587330115 Jul 01 07:22:09 PM PDT 24 Jul 01 07:27:00 PM PDT 24 2817102756 ps
T558 /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.600669833 Jul 01 07:25:00 PM PDT 24 Jul 01 07:39:09 PM PDT 24 5167234972 ps
T221 /workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx2.1574734945 Jul 01 07:10:48 PM PDT 24 Jul 01 07:24:59 PM PDT 24 4906121620 ps
T167 /workspace/coverage/default/65.chip_sw_all_escalation_resets.3530171731 Jul 01 07:44:02 PM PDT 24 Jul 01 07:55:17 PM PDT 24 5563113650 ps
T186 /workspace/coverage/default/0.chip_plic_all_irqs_0.435954772 Jul 01 07:10:50 PM PDT 24 Jul 01 07:24:26 PM PDT 24 6322536100 ps
T185 /workspace/coverage/default/2.chip_sw_alert_handler_reverse_ping_in_deep_sleep.4024222723 Jul 01 07:31:22 PM PDT 24 Jul 01 11:00:20 PM PDT 24 255484798456 ps
T559 /workspace/coverage/default/2.chip_sw_flash_rma_unlocked.2482429818 Jul 01 07:30:52 PM PDT 24 Jul 01 08:57:40 PM PDT 24 42261741696 ps
T433 /workspace/coverage/default/29.chip_sw_alert_handler_lpg_sleep_mode_alerts.3405693312 Jul 01 07:43:53 PM PDT 24 Jul 01 07:49:40 PM PDT 24 3902155060 ps
T560 /workspace/coverage/default/0.rom_keymgr_functest.915399835 Jul 01 07:13:22 PM PDT 24 Jul 01 07:22:41 PM PDT 24 5091635544 ps
T356 /workspace/coverage/default/0.chip_sw_uart_tx_rx_idx2.420133010 Jul 01 07:11:03 PM PDT 24 Jul 01 07:21:32 PM PDT 24 3890873048 ps
T561 /workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_alerts.1738951651 Jul 01 07:22:37 PM PDT 24 Jul 01 07:30:09 PM PDT 24 3790736536 ps
T463 /workspace/coverage/default/40.chip_sw_all_escalation_resets.42094233 Jul 01 07:43:24 PM PDT 24 Jul 01 07:52:44 PM PDT 24 5621399526 ps
T439 /workspace/coverage/default/12.chip_sw_all_escalation_resets.1704921768 Jul 01 07:40:21 PM PDT 24 Jul 01 07:49:22 PM PDT 24 4966928136 ps
T562 /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_prod.2783738204 Jul 01 07:11:07 PM PDT 24 Jul 01 07:35:16 PM PDT 24 9028787730 ps
T441 /workspace/coverage/default/85.chip_sw_alert_handler_lpg_sleep_mode_alerts.2293485940 Jul 01 07:47:08 PM PDT 24 Jul 01 07:52:29 PM PDT 24 3404160804 ps
T563 /workspace/coverage/default/2.chip_sw_uart_tx_rx_idx2.2567264043 Jul 01 07:26:22 PM PDT 24 Jul 01 07:39:00 PM PDT 24 3566788454 ps
T564 /workspace/coverage/default/4.chip_sw_uart_tx_rx_idx2.873152509 Jul 01 07:37:52 PM PDT 24 Jul 01 07:48:24 PM PDT 24 3934562348 ps
T565 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.3755363601 Jul 01 07:13:39 PM PDT 24 Jul 01 07:23:24 PM PDT 24 4617156534 ps
T362 /workspace/coverage/default/0.chip_sw_pwrmgr_all_reset_reqs.2264329730 Jul 01 07:11:40 PM PDT 24 Jul 01 07:40:33 PM PDT 24 11206322606 ps
T129 /workspace/coverage/default/2.chip_sw_rstmgr_sw_rst.111228785 Jul 01 07:28:14 PM PDT 24 Jul 01 07:31:56 PM PDT 24 2806153668 ps
T224 /workspace/coverage/default/0.chip_sw_i2c_device_tx_rx.802967184 Jul 01 07:12:26 PM PDT 24 Jul 01 07:22:01 PM PDT 24 4385401608 ps
T302 /workspace/coverage/default/1.rom_volatile_raw_unlock.2712578388 Jul 01 07:30:59 PM PDT 24 Jul 01 07:32:52 PM PDT 24 2261059750 ps
T566 /workspace/coverage/default/2.chip_sw_flash_ctrl_ops.951553937 Jul 01 07:35:23 PM PDT 24 Jul 01 07:45:03 PM PDT 24 3435504680 ps
T567 /workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq.3879614532 Jul 01 07:08:45 PM PDT 24 Jul 01 07:38:10 PM PDT 24 8877229693 ps
T568 /workspace/coverage/default/0.chip_sw_aon_timer_wdog_lc_escalate.445524339 Jul 01 07:09:49 PM PDT 24 Jul 01 07:18:19 PM PDT 24 4678910488 ps
T569 /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_prod.286517755 Jul 01 07:19:24 PM PDT 24 Jul 01 07:42:14 PM PDT 24 7853114760 ps
T84 /workspace/coverage/default/2.chip_sw_csrng_edn_concurrency_reduced_freq.3247226421 Jul 01 07:34:19 PM PDT 24 Jul 01 10:50:31 PM PDT 24 85901021271 ps
T570 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.801850507 Jul 01 07:18:17 PM PDT 24 Jul 01 08:27:26 PM PDT 24 15039009318 ps
T571 /workspace/coverage/default/1.chip_sw_sram_ctrl_smoketest.3987446050 Jul 01 07:27:34 PM PDT 24 Jul 01 07:32:00 PM PDT 24 2341576200 ps
T164 /workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_pings.1282433181 Jul 01 07:23:59 PM PDT 24 Jul 01 07:51:49 PM PDT 24 13131810484 ps
T572 /workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_no_meas.1363777648 Jul 01 07:17:03 PM PDT 24 Jul 01 08:13:54 PM PDT 24 15422399678 ps
T479 /workspace/coverage/default/70.chip_sw_alert_handler_lpg_sleep_mode_alerts.183573492 Jul 01 07:44:21 PM PDT 24 Jul 01 07:51:27 PM PDT 24 4071094602 ps
T274 /workspace/coverage/default/0.chip_sw_plic_sw_irq.2124075486 Jul 01 07:13:53 PM PDT 24 Jul 01 07:18:28 PM PDT 24 3214090170 ps
T573 /workspace/coverage/default/1.chip_sw_pwrmgr_wdog_reset.2430844081 Jul 01 07:23:50 PM PDT 24 Jul 01 07:35:28 PM PDT 24 3973990600 ps
T574 /workspace/coverage/default/2.chip_sw_hmac_multistream.286702883 Jul 01 07:32:09 PM PDT 24 Jul 01 08:04:12 PM PDT 24 7168549300 ps
T575 /workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_invalid_meas.555013189 Jul 01 07:21:30 PM PDT 24 Jul 01 08:22:50 PM PDT 24 15788492242 ps
T213 /workspace/coverage/default/1.chip_sw_lc_walkthrough_testunlocks.2720853602 Jul 01 07:20:42 PM PDT 24 Jul 01 07:54:27 PM PDT 24 27945686200 ps
T576 /workspace/coverage/default/0.chip_sw_flash_crash_alert.735865497 Jul 01 07:11:05 PM PDT 24 Jul 01 07:21:45 PM PDT 24 4716505314 ps
T70 /workspace/coverage/default/1.chip_sw_pwrmgr_full_aon_reset.828202387 Jul 01 07:22:20 PM PDT 24 Jul 01 07:32:36 PM PDT 24 7421156632 ps
T490 /workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_alerts.166841359 Jul 01 07:32:16 PM PDT 24 Jul 01 07:40:45 PM PDT 24 3718747320 ps
T374 /workspace/coverage/default/1.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.3602535162 Jul 01 07:22:41 PM PDT 24 Jul 01 07:36:31 PM PDT 24 20101859948 ps
T577 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.3988878806 Jul 01 07:20:17 PM PDT 24 Jul 01 08:14:54 PM PDT 24 15937743464 ps
T192 /workspace/coverage/default/2.chip_plic_all_irqs_20.2198372928 Jul 01 07:33:44 PM PDT 24 Jul 01 07:45:26 PM PDT 24 4901192200 ps
T578 /workspace/coverage/default/1.chip_sw_uart_tx_rx.4210478218 Jul 01 07:15:31 PM PDT 24 Jul 01 07:25:17 PM PDT 24 4662001440 ps
T89 /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.1247367138 Jul 01 07:29:19 PM PDT 24 Jul 01 07:36:26 PM PDT 24 5619257910 ps
T97 /workspace/coverage/default/1.chip_tap_straps_rma.1117202857 Jul 01 07:23:47 PM PDT 24 Jul 01 07:27:39 PM PDT 24 3866489837 ps
T357 /workspace/coverage/default/13.chip_sw_uart_rand_baudrate.2127405543 Jul 01 07:40:06 PM PDT 24 Jul 01 08:15:21 PM PDT 24 12824507584 ps
T200 /workspace/coverage/default/1.chip_sw_otp_ctrl_vendor_test_csr_access.1603705660 Jul 01 07:17:41 PM PDT 24 Jul 01 07:19:28 PM PDT 24 2449607491 ps
T470 /workspace/coverage/default/9.chip_sw_alert_handler_lpg_sleep_mode_alerts.2504586768 Jul 01 07:39:22 PM PDT 24 Jul 01 07:44:48 PM PDT 24 3075824790 ps
T579 /workspace/coverage/default/0.chip_sw_lc_ctrl_transition.1316383958 Jul 01 07:11:43 PM PDT 24 Jul 01 07:32:22 PM PDT 24 9331476780 ps
T453 /workspace/coverage/default/76.chip_sw_all_escalation_resets.3279116559 Jul 01 07:44:49 PM PDT 24 Jul 01 07:52:42 PM PDT 24 4965671560 ps
T580 /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_rma.4143785206 Jul 01 07:11:04 PM PDT 24 Jul 01 07:30:55 PM PDT 24 7473185340 ps
T581 /workspace/coverage/default/1.chip_sw_flash_ctrl_access.3683754089 Jul 01 07:15:11 PM PDT 24 Jul 01 07:30:17 PM PDT 24 5637045224 ps
T303 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.524854780 Jul 01 07:24:30 PM PDT 24 Jul 01 08:36:58 PM PDT 24 15138791036 ps
T582 /workspace/coverage/default/1.chip_sw_clkmgr_smoketest.4091604125 Jul 01 07:25:13 PM PDT 24 Jul 01 07:30:30 PM PDT 24 3037833416 ps
T251 /workspace/coverage/default/2.chip_sw_lc_walkthrough_rma.1522280232 Jul 01 07:29:38 PM PDT 24 Jul 01 08:53:13 PM PDT 24 47670157872 ps
T316 /workspace/coverage/default/2.chip_sw_otbn_mem_scramble.327609505 Jul 01 07:29:58 PM PDT 24 Jul 01 07:39:01 PM PDT 24 3400117528 ps
T583 /workspace/coverage/default/0.chip_sw_clkmgr_jitter.1410643536 Jul 01 07:12:21 PM PDT 24 Jul 01 07:15:25 PM PDT 24 3072544032 ps
T168 /workspace/coverage/default/83.chip_sw_alert_handler_lpg_sleep_mode_alerts.533430830 Jul 01 07:45:46 PM PDT 24 Jul 01 07:51:46 PM PDT 24 3105230100 ps
T584 /workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en.3195204115 Jul 01 07:30:48 PM PDT 24 Jul 01 08:33:15 PM PDT 24 18488430001 ps
T585 /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.2156031447 Jul 01 07:24:49 PM PDT 24 Jul 01 07:38:40 PM PDT 24 3736332540 ps
T225 /workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx1.1009945750 Jul 01 07:09:04 PM PDT 24 Jul 01 07:23:02 PM PDT 24 5233275040 ps
T214 /workspace/coverage/default/0.chip_sw_lc_ctrl_rand_to_scrap.2542302925 Jul 01 07:08:55 PM PDT 24 Jul 01 07:10:55 PM PDT 24 3465749874 ps
T586 /workspace/coverage/default/0.chip_sw_pwrmgr_b2b_sleep_reset_req.1239881447 Jul 01 07:11:04 PM PDT 24 Jul 01 07:56:43 PM PDT 24 32628765320 ps
T386 /workspace/coverage/default/8.chip_sw_all_escalation_resets.1006301718 Jul 01 07:38:26 PM PDT 24 Jul 01 07:49:53 PM PDT 24 5172062620 ps
T39 /workspace/coverage/default/1.chip_sw_gpio_smoketest.59272496 Jul 01 07:25:16 PM PDT 24 Jul 01 07:29:16 PM PDT 24 2357232630 ps
T377 /workspace/coverage/default/1.chip_sival_flash_info_access.1537614414 Jul 01 07:21:03 PM PDT 24 Jul 01 07:25:55 PM PDT 24 3434970136 ps
T587 /workspace/coverage/default/81.chip_sw_all_escalation_resets.3842888066 Jul 01 07:46:01 PM PDT 24 Jul 01 07:55:52 PM PDT 24 4212433650 ps
T588 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.738851755 Jul 01 07:34:32 PM PDT 24 Jul 01 07:45:56 PM PDT 24 4477059856 ps
T387 /workspace/coverage/default/1.chip_sw_all_escalation_resets.1645893882 Jul 01 07:16:11 PM PDT 24 Jul 01 07:24:47 PM PDT 24 4118252868 ps
T505 /workspace/coverage/default/78.chip_sw_alert_handler_lpg_sleep_mode_alerts.2818990133 Jul 01 07:46:34 PM PDT 24 Jul 01 07:51:42 PM PDT 24 3866076424 ps
T409 /workspace/coverage/default/2.chip_sw_csrng_edn_concurrency.1553025718 Jul 01 07:30:33 PM PDT 24 Jul 01 08:45:52 PM PDT 24 16395919200 ps
T408 /workspace/coverage/default/9.chip_sw_csrng_edn_concurrency.2142339583 Jul 01 07:40:25 PM PDT 24 Jul 01 09:07:06 PM PDT 24 25449103064 ps
T589 /workspace/coverage/default/0.chip_sw_clkmgr_off_peri.659804814 Jul 01 07:15:23 PM PDT 24 Jul 01 07:40:58 PM PDT 24 11263742302 ps
T590 /workspace/coverage/default/0.chip_sw_keymgr_sideload_kmac.4077179961 Jul 01 07:11:30 PM PDT 24 Jul 01 07:52:31 PM PDT 24 10994967210 ps
T591 /workspace/coverage/default/0.chip_sw_aes_enc_jitter_en_reduced_freq.3723983184 Jul 01 07:11:29 PM PDT 24 Jul 01 07:15:03 PM PDT 24 2452278058 ps
T291 /workspace/coverage/default/71.chip_sw_all_escalation_resets.2455813937 Jul 01 07:45:39 PM PDT 24 Jul 01 07:54:36 PM PDT 24 4910272880 ps
T46 /workspace/coverage/default/2.chip_sw_spi_host_tx_rx.2909359709 Jul 01 07:27:49 PM PDT 24 Jul 01 07:34:01 PM PDT 24 3349796760 ps
T592 /workspace/coverage/default/0.chip_sw_csrng_fuse_en_sw_app_read_test.1290903572 Jul 01 07:12:37 PM PDT 24 Jul 01 07:20:22 PM PDT 24 4797865002 ps
T276 /workspace/coverage/default/2.chip_sw_power_sleep_load.4282187828 Jul 01 07:37:04 PM PDT 24 Jul 01 07:44:58 PM PDT 24 3808250280 ps
T349 /workspace/coverage/default/0.chip_sw_pattgen_ios.2743149854 Jul 01 07:10:26 PM PDT 24 Jul 01 07:15:34 PM PDT 24 3044242894 ps
T593 /workspace/coverage/default/2.rom_e2e_asm_init_dev.738755621 Jul 01 07:39:04 PM PDT 24 Jul 01 08:38:16 PM PDT 24 16068721845 ps
T273 /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_disabled.1214680521 Jul 01 07:30:02 PM PDT 24 Jul 01 07:34:24 PM PDT 24 2636455000 ps
T594 /workspace/coverage/default/0.chip_sw_pwrmgr_wdog_reset.938303554 Jul 01 07:10:45 PM PDT 24 Jul 01 07:19:01 PM PDT 24 5188159240 ps
T364 /workspace/coverage/default/1.chip_sw_entropy_src_csrng.1953952911 Jul 01 07:23:04 PM PDT 24 Jul 01 07:40:43 PM PDT 24 6133848552 ps
T370 /workspace/coverage/default/14.chip_sw_all_escalation_resets.4280283967 Jul 01 07:43:26 PM PDT 24 Jul 01 07:52:15 PM PDT 24 5835683560 ps
T146 /workspace/coverage/default/1.chip_sw_clkmgr_off_otbn_trans.10249944 Jul 01 07:25:16 PM PDT 24 Jul 01 07:32:59 PM PDT 24 5317807632 ps
T430 /workspace/coverage/default/50.chip_sw_alert_handler_lpg_sleep_mode_alerts.3234121095 Jul 01 07:41:45 PM PDT 24 Jul 01 07:47:05 PM PDT 24 3539778092 ps
T595 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.3876119697 Jul 01 07:12:46 PM PDT 24 Jul 01 07:24:24 PM PDT 24 4794672000 ps
T596 /workspace/coverage/default/0.chip_sw_pwrmgr_smoketest.1147722132 Jul 01 07:16:47 PM PDT 24 Jul 01 07:24:53 PM PDT 24 5372225064 ps
T304 /workspace/coverage/default/2.chip_sw_rom_ctrl_integrity_check.4075922525 Jul 01 07:31:50 PM PDT 24 Jul 01 07:41:00 PM PDT 24 9871561054 ps
T597 /workspace/coverage/default/0.chip_sw_alert_handler_ping_ok.1453672057 Jul 01 07:13:07 PM PDT 24 Jul 01 07:36:54 PM PDT 24 8338143508 ps
T499 /workspace/coverage/default/4.chip_sw_all_escalation_resets.838571779 Jul 01 07:39:59 PM PDT 24 Jul 01 07:50:17 PM PDT 24 4858778296 ps
T317 /workspace/coverage/default/0.chip_sw_data_integrity_escalation.153788011 Jul 01 07:11:18 PM PDT 24 Jul 01 07:25:05 PM PDT 24 5540483768 ps
T148 /workspace/coverage/default/0.chip_sw_csrng_lc_hw_debug_en_test.4031382057 Jul 01 07:10:11 PM PDT 24 Jul 01 07:22:20 PM PDT 24 7677577860 ps
T245 /workspace/coverage/default/0.chip_sw_sysrst_ctrl_in_irq.3488921782 Jul 01 07:12:54 PM PDT 24 Jul 01 07:24:49 PM PDT 24 5403034159 ps
T509 /workspace/coverage/default/7.chip_sw_alert_handler_lpg_sleep_mode_alerts.1498256683 Jul 01 07:38:46 PM PDT 24 Jul 01 07:46:23 PM PDT 24 3831346100 ps
T598 /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.3610113459 Jul 01 07:26:20 PM PDT 24 Jul 01 07:38:22 PM PDT 24 3795396360 ps
T118 /workspace/coverage/default/0.rom_e2e_jtag_inject_dev.2902528514 Jul 01 07:13:57 PM PDT 24 Jul 01 08:03:00 PM PDT 24 29659902227 ps
T599 /workspace/coverage/default/2.chip_sw_uart_rand_baudrate.1264135056 Jul 01 07:27:55 PM PDT 24 Jul 01 08:09:07 PM PDT 24 12479491120 ps
T40 /workspace/coverage/default/0.chip_sw_gpio.4077679244 Jul 01 07:09:51 PM PDT 24 Jul 01 07:15:54 PM PDT 24 3543135891 ps
T378 /workspace/coverage/default/0.chip_sw_hmac_enc_jitter_en.1879494195 Jul 01 07:14:19 PM PDT 24 Jul 01 07:20:21 PM PDT 24 3534296790 ps
T600 /workspace/coverage/default/2.chip_sw_aon_timer_sleep_wdog_sleep_pause.2083572043 Jul 01 07:29:24 PM PDT 24 Jul 01 07:36:55 PM PDT 24 7042295096 ps
T388 /workspace/coverage/default/72.chip_sw_alert_handler_lpg_sleep_mode_alerts.4118199138 Jul 01 07:43:36 PM PDT 24 Jul 01 07:50:44 PM PDT 24 3821718150 ps
T601 /workspace/coverage/default/1.rom_e2e_asm_init_test_unlocked0.2790739484 Jul 01 07:37:13 PM PDT 24 Jul 01 08:28:46 PM PDT 24 11358068317 ps
T602 /workspace/coverage/default/1.chip_sw_rstmgr_sw_req.2943728404 Jul 01 07:19:50 PM PDT 24 Jul 01 07:26:14 PM PDT 24 3317698708 ps
T119 /workspace/coverage/default/2.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.3978259805 Jul 01 07:34:46 PM PDT 24 Jul 01 07:46:09 PM PDT 24 4505543368 ps
T603 /workspace/coverage/default/0.chip_sw_kmac_mode_kmac.1506534635 Jul 01 07:14:39 PM PDT 24 Jul 01 07:21:30 PM PDT 24 2930603444 ps
T604 /workspace/coverage/default/1.chip_sw_rstmgr_smoketest.1189755512 Jul 01 07:26:46 PM PDT 24 Jul 01 07:31:18 PM PDT 24 3032246136 ps
T206 /workspace/coverage/default/0.chip_sw_lc_ctrl_program_error.968223605 Jul 01 07:11:55 PM PDT 24 Jul 01 07:20:51 PM PDT 24 5620291096 ps
T169 /workspace/coverage/default/84.chip_sw_all_escalation_resets.2236434923 Jul 01 07:44:58 PM PDT 24 Jul 01 07:55:52 PM PDT 24 5279609520 ps
T605 /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.2410856884 Jul 01 07:25:15 PM PDT 24 Jul 01 07:37:23 PM PDT 24 4863808050 ps
T258 /workspace/coverage/default/0.chip_sw_flash_init.3844896609 Jul 01 07:09:44 PM PDT 24 Jul 01 07:45:29 PM PDT 24 21474894247 ps
T473 /workspace/coverage/default/96.chip_sw_all_escalation_resets.2350468803 Jul 01 07:46:03 PM PDT 24 Jul 01 07:55:06 PM PDT 24 5471285480 ps
T606 /workspace/coverage/default/4.chip_sw_csrng_edn_concurrency.1062500712 Jul 01 07:38:42 PM PDT 24 Jul 01 08:31:54 PM PDT 24 16022190088 ps
T607 /workspace/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.516771081 Jul 01 07:33:34 PM PDT 24 Jul 01 07:38:33 PM PDT 24 2811330749 ps
T216 /workspace/coverage/default/1.chip_sw_sleep_sram_ret_contents_scramble.3816746379 Jul 01 07:25:33 PM PDT 24 Jul 01 07:35:28 PM PDT 24 8450202790 ps
T438 /workspace/coverage/default/55.chip_sw_alert_handler_lpg_sleep_mode_alerts.4102526069 Jul 01 07:45:57 PM PDT 24 Jul 01 07:54:01 PM PDT 24 4028262640 ps
T22 /workspace/coverage/default/0.chip_sw_sleep_pin_mio_dio_val.3327721058 Jul 01 07:09:52 PM PDT 24 Jul 01 07:16:01 PM PDT 24 3980784662 ps
T608 /workspace/coverage/default/0.chip_sw_otp_ctrl_dai_lock.3962069822 Jul 01 07:11:21 PM PDT 24 Jul 01 08:52:09 PM PDT 24 27664652236 ps
T507 /workspace/coverage/default/12.chip_sw_alert_handler_lpg_sleep_mode_alerts.1606491399 Jul 01 07:40:09 PM PDT 24 Jul 01 07:46:51 PM PDT 24 3218941660 ps
T609 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.4186193381 Jul 01 07:16:00 PM PDT 24 Jul 01 08:09:05 PM PDT 24 11295298600 ps
T292 /workspace/coverage/default/1.chip_sw_rstmgr_cpu_info.3400626211 Jul 01 07:19:32 PM PDT 24 Jul 01 07:29:58 PM PDT 24 5909453584 ps
T285 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.2932647737 Jul 01 07:19:07 PM PDT 24 Jul 01 08:44:10 PM PDT 24 18233965344 ps
T400 /workspace/coverage/default/1.chip_sw_rv_core_ibex_lockstep_glitch.2313133027 Jul 01 07:25:16 PM PDT 24 Jul 01 07:29:26 PM PDT 24 2782236810 ps
T16 /workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_wake_ups.109926022 Jul 01 07:13:40 PM PDT 24 Jul 01 07:32:13 PM PDT 24 20476264304 ps
T9 /workspace/coverage/default/0.chip_rv_dm_ndm_reset_req.3890318999 Jul 01 07:11:56 PM PDT 24 Jul 01 07:18:29 PM PDT 24 3373947000 ps
T610 /workspace/coverage/default/0.chip_sw_edn_sw_mode.2848380543 Jul 01 07:10:47 PM PDT 24 Jul 01 07:56:58 PM PDT 24 10922322482 ps
T611 /workspace/coverage/default/1.chip_sw_entropy_src_kat_test.4122466935 Jul 01 07:26:00 PM PDT 24 Jul 01 07:29:23 PM PDT 24 2851489044 ps
T612 /workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.2926485069 Jul 01 07:10:33 PM PDT 24 Jul 01 07:32:17 PM PDT 24 11130463978 ps
T471 /workspace/coverage/default/6.chip_sw_all_escalation_resets.3961796291 Jul 01 07:37:58 PM PDT 24 Jul 01 07:50:05 PM PDT 24 5160486372 ps
T613 /workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en.3001225054 Jul 01 07:16:11 PM PDT 24 Jul 01 07:28:18 PM PDT 24 4751879943 ps
T10 /workspace/coverage/default/2.chip_rv_dm_ndm_reset_req.3332959735 Jul 01 07:34:35 PM PDT 24 Jul 01 07:41:21 PM PDT 24 4371130984 ps
T215 /workspace/coverage/default/0.chip_sw_lc_ctrl_raw_to_scrap.3928552199 Jul 01 07:09:59 PM PDT 24 Jul 01 07:12:32 PM PDT 24 3294585360 ps
T376 /workspace/coverage/default/2.chip_sw_aon_timer_irq.3427171519 Jul 01 07:29:21 PM PDT 24 Jul 01 07:36:08 PM PDT 24 3756957916 ps
T614 /workspace/coverage/default/2.chip_sw_example_rom.1049587050 Jul 01 07:24:51 PM PDT 24 Jul 01 07:27:06 PM PDT 24 2533783846 ps
T187 /workspace/coverage/default/1.chip_plic_all_irqs_0.3609941709 Jul 01 07:25:07 PM PDT 24 Jul 01 07:47:51 PM PDT 24 6081547140 ps
T615 /workspace/coverage/default/15.chip_sw_uart_rand_baudrate.3422958323 Jul 01 07:40:04 PM PDT 24 Jul 01 08:06:59 PM PDT 24 8363594836 ps
T616 /workspace/coverage/default/16.chip_sw_uart_rand_baudrate.127920834 Jul 01 07:39:48 PM PDT 24 Jul 01 07:46:33 PM PDT 24 3747449746 ps
T467 /workspace/coverage/default/86.chip_sw_alert_handler_lpg_sleep_mode_alerts.3919046921 Jul 01 07:45:40 PM PDT 24 Jul 01 07:50:31 PM PDT 24 4028820614 ps
T519 /workspace/coverage/default/53.chip_sw_all_escalation_resets.2137658545 Jul 01 07:42:58 PM PDT 24 Jul 01 07:53:23 PM PDT 24 5311017300 ps
T25 /workspace/coverage/default/0.chip_sw_spi_device_pass_through_collision.3108962072 Jul 01 07:09:27 PM PDT 24 Jul 01 07:18:31 PM PDT 24 5011368930 ps
T500 /workspace/coverage/default/39.chip_sw_alert_handler_lpg_sleep_mode_alerts.810249061 Jul 01 07:42:23 PM PDT 24 Jul 01 07:50:22 PM PDT 24 4051849080 ps
T246 /workspace/coverage/default/0.chip_sw_sysrst_ctrl_inputs.3262280212 Jul 01 07:09:13 PM PDT 24 Jul 01 07:13:32 PM PDT 24 2773563560 ps
T617 /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_power_glitch_reset.4136093920 Jul 01 07:11:06 PM PDT 24 Jul 01 07:18:13 PM PDT 24 4410057958 ps
T618 /workspace/coverage/default/0.rom_e2e_asm_init_test_unlocked0.2773991474 Jul 01 07:18:06 PM PDT 24 Jul 01 08:13:22 PM PDT 24 11476328400 ps
T426 /workspace/coverage/default/2.chip_sw_lc_ctrl_rand_to_scrap.3133529637 Jul 01 07:29:47 PM PDT 24 Jul 01 07:32:19 PM PDT 24 3299691570 ps
T619 /workspace/coverage/default/1.chip_sw_aes_entropy.630180691 Jul 01 07:22:17 PM PDT 24 Jul 01 07:26:54 PM PDT 24 2602065420 ps
T620 /workspace/coverage/default/0.chip_sw_aes_enc_jitter_en.2012468346 Jul 01 07:10:22 PM PDT 24 Jul 01 07:16:31 PM PDT 24 3095153031 ps
T621 /workspace/coverage/default/1.chip_sw_entropy_src_ast_rng_req.974076657 Jul 01 07:24:41 PM PDT 24 Jul 01 07:28:23 PM PDT 24 2970262920 ps
T389 /workspace/coverage/default/7.chip_sw_all_escalation_resets.2326941992 Jul 01 07:43:03 PM PDT 24 Jul 01 07:52:50 PM PDT 24 4672909286 ps
T622 /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_power_glitch_reset.2657180622 Jul 01 07:30:55 PM PDT 24 Jul 01 07:39:24 PM PDT 24 5213285560 ps
T449 /workspace/coverage/default/62.chip_sw_alert_handler_lpg_sleep_mode_alerts.295070579 Jul 01 07:44:18 PM PDT 24 Jul 01 07:51:59 PM PDT 24 4637359460 ps
T265 /workspace/coverage/default/44.chip_sw_alert_handler_lpg_sleep_mode_alerts.2174857865 Jul 01 07:41:42 PM PDT 24 Jul 01 07:48:28 PM PDT 24 4202848990 ps
T623 /workspace/coverage/default/1.chip_sw_uart_rand_baudrate.611745437 Jul 01 07:15:42 PM PDT 24 Jul 01 07:25:05 PM PDT 24 4317017770 ps
T38 /workspace/coverage/default/0.chip_sw_usbdev_config_host.2514436671 Jul 01 07:12:04 PM PDT 24 Jul 01 07:47:13 PM PDT 24 7769435028 ps
T71 /workspace/coverage/default/2.chip_sw_sensor_ctrl_status.283248829 Jul 01 07:33:11 PM PDT 24 Jul 01 07:37:42 PM PDT 24 2888771542 ps
T624 /workspace/coverage/default/0.chip_sw_hmac_oneshot.1731920050 Jul 01 07:12:15 PM PDT 24 Jul 01 07:19:32 PM PDT 24 3037504200 ps
T625 /workspace/coverage/default/2.chip_sw_kmac_mode_kmac.1513557263 Jul 01 07:32:20 PM PDT 24 Jul 01 07:37:15 PM PDT 24 2872585610 ps
T626 /workspace/coverage/default/1.chip_sw_aes_enc.2143960765 Jul 01 07:23:58 PM PDT 24 Jul 01 07:29:24 PM PDT 24 3105644392 ps
T627 /workspace/coverage/default/2.chip_sw_pwrmgr_usb_clk_disabled_when_active.521771476 Jul 01 07:28:47 PM PDT 24 Jul 01 07:35:13 PM PDT 24 4185060580 ps
T628 /workspace/coverage/default/0.chip_sw_ast_clk_outputs.711912574 Jul 01 07:14:47 PM PDT 24 Jul 01 07:34:01 PM PDT 24 7228054264 ps
T508 /workspace/coverage/default/21.chip_sw_all_escalation_resets.3972803846 Jul 01 07:40:22 PM PDT 24 Jul 01 07:49:16 PM PDT 24 4956076180 ps
T436 /workspace/coverage/default/98.chip_sw_all_escalation_resets.1884623813 Jul 01 07:46:29 PM PDT 24 Jul 01 07:53:52 PM PDT 24 5438293060 ps
T629 /workspace/coverage/default/2.chip_sw_csrng_smoketest.4109074184 Jul 01 07:35:19 PM PDT 24 Jul 01 07:38:27 PM PDT 24 2224075824 ps
T495 /workspace/coverage/default/80.chip_sw_alert_handler_lpg_sleep_mode_alerts.1317729585 Jul 01 07:46:21 PM PDT 24 Jul 01 07:51:09 PM PDT 24 3269069472 ps
T630 /workspace/coverage/default/0.chip_sw_pwrmgr_main_power_glitch_reset.3883638533 Jul 01 07:09:02 PM PDT 24 Jul 01 07:13:03 PM PDT 24 4335927203 ps
T631 /workspace/coverage/default/2.chip_sw_keymgr_key_derivation_prod.3438780712 Jul 01 07:32:00 PM PDT 24 Jul 01 08:06:12 PM PDT 24 8970808152 ps
T632 /workspace/coverage/default/2.chip_sw_flash_ctrl_access.2269131949 Jul 01 07:28:37 PM PDT 24 Jul 01 07:47:25 PM PDT 24 6254685322 ps
T633 /workspace/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.3306819179 Jul 01 07:26:51 PM PDT 24 Jul 01 07:49:27 PM PDT 24 7210588285 ps
T634 /workspace/coverage/default/2.chip_sw_edn_entropy_reqs.1255383453 Jul 01 07:31:37 PM PDT 24 Jul 01 07:48:53 PM PDT 24 6229575462 ps
T635 /workspace/coverage/default/17.chip_sw_uart_rand_baudrate.3554725285 Jul 01 07:40:29 PM PDT 24 Jul 01 07:47:58 PM PDT 24 4655851072 ps
T636 /workspace/coverage/default/1.chip_sw_edn_auto_mode.3979350464 Jul 01 07:22:19 PM PDT 24 Jul 01 07:36:22 PM PDT 24 4328291368 ps
T637 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_lc.801877384 Jul 01 07:34:20 PM PDT 24 Jul 01 07:51:39 PM PDT 24 8563528603 ps
T638 /workspace/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en.1922121424 Jul 01 07:29:22 PM PDT 24 Jul 01 07:34:13 PM PDT 24 3413990117 ps
T639 /workspace/coverage/default/0.chip_sw_alert_handler_reverse_ping_in_deep_sleep.469232055 Jul 01 07:09:53 PM PDT 24 Jul 01 10:52:54 PM PDT 24 255779920028 ps
T640 /workspace/coverage/default/1.chip_sw_keymgr_key_derivation_prod.2733984888 Jul 01 07:25:03 PM PDT 24 Jul 01 07:56:17 PM PDT 24 9250339596 ps
T26 /workspace/coverage/default/2.chip_sw_spi_device_pass_through_collision.626906089 Jul 01 07:28:06 PM PDT 24 Jul 01 07:38:56 PM PDT 24 5275853443 ps
T641 /workspace/coverage/default/8.chip_sw_csrng_edn_concurrency.1597556980 Jul 01 07:43:42 PM PDT 24 Jul 01 08:46:28 PM PDT 24 18909074640 ps
T207 /workspace/coverage/default/1.chip_sw_lc_ctrl_program_error.289438280 Jul 01 07:28:24 PM PDT 24 Jul 01 07:39:47 PM PDT 24 5554866464 ps
T642 /workspace/coverage/default/2.chip_sw_clkmgr_sleep_frequency.3057962823 Jul 01 07:35:50 PM PDT 24 Jul 01 07:45:08 PM PDT 24 3993893584 ps
T457 /workspace/coverage/default/48.chip_sw_alert_handler_lpg_sleep_mode_alerts.1801693303 Jul 01 07:42:44 PM PDT 24 Jul 01 07:49:43 PM PDT 24 4302274772 ps
T91 /workspace/coverage/default/3.chip_sw_sensor_ctrl_alert.1238162031 Jul 01 07:39:05 PM PDT 24 Jul 01 07:54:50 PM PDT 24 8565132316 ps
T170 /workspace/coverage/default/3.chip_sw_alert_handler_lpg_sleep_mode_alerts.144716226 Jul 01 07:37:23 PM PDT 24 Jul 01 07:45:38 PM PDT 24 3532378000 ps
T643 /workspace/coverage/default/0.rom_e2e_asm_init_prod_end.4036325253 Jul 01 07:17:12 PM PDT 24 Jul 01 08:25:31 PM PDT 24 15817411633 ps
T644 /workspace/coverage/default/0.chip_sw_aon_timer_wdog_bite_reset.2450274438 Jul 01 07:11:54 PM PDT 24 Jul 01 07:27:50 PM PDT 24 7075449422 ps
T645 /workspace/coverage/default/2.rom_keymgr_functest.1833653314 Jul 01 07:37:01 PM PDT 24 Jul 01 07:46:38 PM PDT 24 4712393502 ps
T335 /workspace/coverage/default/2.chip_sw_sysrst_ctrl_ec_rst_l.367587609 Jul 01 07:31:16 PM PDT 24 Jul 01 08:25:41 PM PDT 24 20236539818 ps
T646 /workspace/coverage/default/0.chip_sw_aes_idle.1257720047 Jul 01 07:11:19 PM PDT 24 Jul 01 07:15:37 PM PDT 24 2386233254 ps
T222 /workspace/coverage/default/2.chip_sw_i2c_host_tx_rx.763470893 Jul 01 07:27:43 PM PDT 24 Jul 01 07:46:23 PM PDT 24 5259479588 ps
T647 /workspace/coverage/default/2.chip_sw_clkmgr_smoketest.3279952399 Jul 01 07:35:09 PM PDT 24 Jul 01 07:39:05 PM PDT 24 3053126492 ps
T648 /workspace/coverage/default/1.rom_keymgr_functest.49821085 Jul 01 07:27:45 PM PDT 24 Jul 01 07:39:19 PM PDT 24 5276742584 ps
T195 /workspace/coverage/default/0.chip_sw_exit_test_unlocked_bootstrap.371958480 Jul 01 07:11:39 PM PDT 24 Jul 01 10:19:47 PM PDT 24 58718044667 ps
T318 /workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.1795180279 Jul 01 07:35:41 PM PDT 24 Jul 01 07:45:03 PM PDT 24 4945717695 ps
T649 /workspace/coverage/default/1.chip_sw_edn_kat.3209948084 Jul 01 07:23:02 PM PDT 24 Jul 01 07:33:03 PM PDT 24 3045472976 ps
T458 /workspace/coverage/default/23.chip_sw_all_escalation_resets.3985005102 Jul 01 07:41:40 PM PDT 24 Jul 01 07:54:25 PM PDT 24 5861110230 ps
T650 /workspace/coverage/default/0.chip_sw_entropy_src_smoketest.2943716288 Jul 01 07:15:19 PM PDT 24 Jul 01 07:23:04 PM PDT 24 3607483778 ps
T651 /workspace/coverage/default/2.chip_sw_keymgr_sideload_kmac.2043220975 Jul 01 07:31:49 PM PDT 24 Jul 01 08:07:56 PM PDT 24 11787542652 ps
T652 /workspace/coverage/default/2.chip_sw_entropy_src_smoketest.518062530 Jul 01 07:35:04 PM PDT 24 Jul 01 07:42:54 PM PDT 24 3186447384 ps
T427 /workspace/coverage/default/1.chip_sw_lc_ctrl_rand_to_scrap.1593052119 Jul 01 07:20:56 PM PDT 24 Jul 01 07:23:12 PM PDT 24 2843764568 ps
T653 /workspace/coverage/default/2.chip_sw_entropy_src_ast_rng_req.2266331038 Jul 01 07:31:08 PM PDT 24 Jul 01 07:34:27 PM PDT 24 3145149344 ps
T425 /workspace/coverage/default/0.chip_sw_rv_dm_access_after_escalation_reset.3188865226 Jul 01 07:17:05 PM PDT 24 Jul 01 07:27:21 PM PDT 24 5516757101 ps
T480 /workspace/coverage/default/26.chip_sw_alert_handler_lpg_sleep_mode_alerts.4145871757 Jul 01 07:42:52 PM PDT 24 Jul 01 07:49:30 PM PDT 24 3427163356 ps
T654 /workspace/coverage/default/2.rom_e2e_smoke.2484625461 Jul 01 07:42:20 PM PDT 24 Jul 01 08:52:25 PM PDT 24 14805925000 ps
T476 /workspace/coverage/default/75.chip_sw_all_escalation_resets.3388866119 Jul 01 07:44:54 PM PDT 24 Jul 01 07:53:04 PM PDT 24 5211869614 ps
T90 /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.842469439 Jul 01 07:14:17 PM PDT 24 Jul 01 07:21:12 PM PDT 24 5509176328 ps
T488 /workspace/coverage/default/8.chip_sw_alert_handler_lpg_sleep_mode_alerts.3923030182 Jul 01 07:37:46 PM PDT 24 Jul 01 07:44:09 PM PDT 24 3387467970 ps
T655 /workspace/coverage/default/0.chip_sw_aon_timer_smoketest.688024356 Jul 01 07:16:45 PM PDT 24 Jul 01 07:21:39 PM PDT 24 3344953414 ps
T656 /workspace/coverage/default/1.chip_sw_alert_handler_lpg_clkoff.1169386767 Jul 01 07:23:38 PM PDT 24 Jul 01 07:53:01 PM PDT 24 8148950480 ps
T657 /workspace/coverage/default/0.chip_sw_rv_plic_smoketest.3681871466 Jul 01 07:13:10 PM PDT 24 Jul 01 07:16:39 PM PDT 24 2492024208 ps
T658 /workspace/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.987102519 Jul 01 07:34:52 PM PDT 24 Jul 01 07:40:16 PM PDT 24 3913982620 ps
T659 /workspace/coverage/default/2.chip_sw_aes_enc_jitter_en.181178128 Jul 01 07:30:02 PM PDT 24 Jul 01 07:34:27 PM PDT 24 2740365421 ps
T660 /workspace/coverage/default/0.chip_sw_kmac_mode_cshake.3126919182 Jul 01 07:10:59 PM PDT 24 Jul 01 07:15:58 PM PDT 24 3241327188 ps
T277 /workspace/coverage/default/0.chip_sw_power_sleep_load.2992689973 Jul 01 07:20:50 PM PDT 24 Jul 01 07:27:53 PM PDT 24 5012031624 ps
T477 /workspace/coverage/default/35.chip_sw_alert_handler_lpg_sleep_mode_alerts.3898861249 Jul 01 07:41:45 PM PDT 24 Jul 01 07:48:37 PM PDT 24 4122486450 ps
T661 /workspace/coverage/default/1.chip_sw_edn_entropy_reqs_jitter.1313812063 Jul 01 07:23:38 PM PDT 24 Jul 01 07:44:43 PM PDT 24 6109209170 ps
T208 /workspace/coverage/default/2.chip_sw_lc_ctrl_program_error.1549376316 Jul 01 07:34:20 PM PDT 24 Jul 01 07:42:44 PM PDT 24 4934274408 ps
T329 /workspace/coverage/default/1.chip_sw_rv_core_ibex_icache_invalidate.1835190935 Jul 01 07:30:01 PM PDT 24 Jul 01 07:33:36 PM PDT 24 2965245744 ps
T662 /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_prod.3980506672 Jul 01 07:28:36 PM PDT 24 Jul 01 07:48:28 PM PDT 24 8013115896 ps
T663 /workspace/coverage/default/1.chip_sw_flash_ctrl_ops.1418969773 Jul 01 07:18:46 PM PDT 24 Jul 01 07:29:09 PM PDT 24 4292064632 ps
T664 /workspace/coverage/default/0.chip_sw_flash_ctrl_write_clear.2698759058 Jul 01 07:14:31 PM PDT 24 Jul 01 07:20:55 PM PDT 24 3434695080 ps
T319 /workspace/coverage/default/0.chip_sw_otbn_mem_scramble.818236125 Jul 01 07:10:04 PM PDT 24 Jul 01 07:18:44 PM PDT 24 3739023180 ps
T665 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.3994025945 Jul 01 07:11:44 PM PDT 24 Jul 01 07:22:34 PM PDT 24 4225318904 ps
T666 /workspace/coverage/default/0.chip_sw_alert_handler_lpg_clkoff.1864612364 Jul 01 07:11:19 PM PDT 24 Jul 01 07:37:23 PM PDT 24 6390964684 ps
T667 /workspace/coverage/default/0.chip_sw_uart_tx_rx_idx1.13916305 Jul 01 07:08:58 PM PDT 24 Jul 01 07:19:43 PM PDT 24 3789913900 ps
T668 /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.2919196960 Jul 01 07:19:42 PM PDT 24 Jul 01 07:43:51 PM PDT 24 18194593751 ps
T669 /workspace/coverage/default/2.chip_sw_clkmgr_off_otbn_trans.2143009616 Jul 01 07:32:41 PM PDT 24 Jul 01 07:43:21 PM PDT 24 4975417400 ps
T371 /workspace/coverage/default/0.chip_sw_sensor_ctrl_status.3816811266 Jul 01 07:11:33 PM PDT 24 Jul 01 07:16:23 PM PDT 24 3495334252 ps
T65 /workspace/coverage/default/1.chip_jtag_mem_access.3614629310 Jul 01 07:16:52 PM PDT 24 Jul 01 07:37:33 PM PDT 24 13425308864 ps
T670 /workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en.1076376901 Jul 01 07:10:10 PM PDT 24 Jul 01 08:19:03 PM PDT 24 19050140689 ps
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