Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
90.71 92.91 83.55 90.13 95.03 97.53 85.09


Total test records in report: 1006
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html

T474 /workspace/coverage/default/57.chip_sw_all_escalation_resets.129434087 Jul 01 07:46:44 PM PDT 24 Jul 01 07:56:46 PM PDT 24 5594931806 ps
T671 /workspace/coverage/default/2.chip_sw_flash_ctrl_write_clear.930701107 Jul 01 07:34:59 PM PDT 24 Jul 01 07:41:15 PM PDT 24 2844402800 ps
T672 /workspace/coverage/default/2.chip_sw_pwrmgr_sysrst_ctrl_reset.2800157300 Jul 01 07:30:02 PM PDT 24 Jul 01 07:51:45 PM PDT 24 7308271128 ps
T464 /workspace/coverage/default/30.chip_sw_all_escalation_resets.1259993738 Jul 01 07:41:38 PM PDT 24 Jul 01 07:50:55 PM PDT 24 4331851280 ps
T673 /workspace/coverage/default/1.rom_e2e_asm_init_prod_end.1782213868 Jul 01 07:36:11 PM PDT 24 Jul 01 08:37:32 PM PDT 24 15787187256 ps
T674 /workspace/coverage/default/14.chip_sw_lc_ctrl_transition.4246958438 Jul 01 07:39:53 PM PDT 24 Jul 01 07:55:16 PM PDT 24 8996214755 ps
T675 /workspace/coverage/default/2.chip_sw_otp_ctrl_ecc_error_vendor_test.2152800989 Jul 01 07:29:16 PM PDT 24 Jul 01 07:33:56 PM PDT 24 2292425326 ps
T676 /workspace/coverage/default/2.chip_sw_clkmgr_jitter.1371097115 Jul 01 07:34:59 PM PDT 24 Jul 01 07:39:19 PM PDT 24 2431655962 ps
T478 /workspace/coverage/default/71.chip_sw_alert_handler_lpg_sleep_mode_alerts.1079513944 Jul 01 07:47:50 PM PDT 24 Jul 01 07:53:25 PM PDT 24 3682810216 ps
T677 /workspace/coverage/default/0.chip_sw_keymgr_key_derivation.2129059291 Jul 01 07:12:34 PM PDT 24 Jul 01 07:32:33 PM PDT 24 7015663738 ps
T160 /workspace/coverage/default/4.chip_tap_straps_dev.3074118664 Jul 01 07:37:03 PM PDT 24 Jul 01 07:52:49 PM PDT 24 10097012356 ps
T678 /workspace/coverage/default/2.chip_sw_kmac_idle.829835286 Jul 01 07:31:59 PM PDT 24 Jul 01 07:36:29 PM PDT 24 2977115000 ps
T517 /workspace/coverage/default/43.chip_sw_all_escalation_resets.1021598628 Jul 01 07:42:19 PM PDT 24 Jul 01 07:51:40 PM PDT 24 4512634380 ps
T679 /workspace/coverage/default/13.chip_sw_lc_ctrl_transition.1410208926 Jul 01 07:41:37 PM PDT 24 Jul 01 07:52:38 PM PDT 24 6873482539 ps
T680 /workspace/coverage/default/1.chip_sw_alert_handler_entropy.3469343047 Jul 01 07:22:24 PM PDT 24 Jul 01 07:28:51 PM PDT 24 3870267214 ps
T681 /workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_power_glitch_reset.4162313979 Jul 01 07:09:35 PM PDT 24 Jul 01 08:00:14 PM PDT 24 44218563058 ps
T506 /workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_alerts.2482284067 Jul 01 07:11:00 PM PDT 24 Jul 01 07:17:14 PM PDT 24 4140505850 ps
T493 /workspace/coverage/default/83.chip_sw_all_escalation_resets.1272416524 Jul 01 07:45:25 PM PDT 24 Jul 01 07:54:00 PM PDT 24 5294209400 ps
T682 /workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.4116182657 Jul 01 07:20:01 PM PDT 24 Jul 01 07:32:48 PM PDT 24 5595613040 ps
T367 /workspace/coverage/default/0.chip_sw_pwrmgr_lowpower_cancel.4155896958 Jul 01 07:13:39 PM PDT 24 Jul 01 07:19:45 PM PDT 24 3551198580 ps
T683 /workspace/coverage/default/1.chip_sw_hmac_smoketest.1958319335 Jul 01 07:25:35 PM PDT 24 Jul 01 07:31:31 PM PDT 24 3220233184 ps
T205 /workspace/coverage/default/0.chip_sw_otp_ctrl_escalation.1714953367 Jul 01 07:09:58 PM PDT 24 Jul 01 07:22:11 PM PDT 24 5411723602 ps
T684 /workspace/coverage/default/2.rom_e2e_asm_init_rma.2566669604 Jul 01 07:40:49 PM PDT 24 Jul 01 08:37:28 PM PDT 24 15327104172 ps
T685 /workspace/coverage/default/2.chip_sw_pwrmgr_smoketest.2847941787 Jul 01 07:35:41 PM PDT 24 Jul 01 07:43:59 PM PDT 24 5981429362 ps
T252 /workspace/coverage/default/0.chip_sw_lc_walkthrough_prod.1785033003 Jul 01 07:09:05 PM PDT 24 Jul 01 08:37:22 PM PDT 24 48204002050 ps
T85 /workspace/coverage/default/1.chip_sw_csrng_edn_concurrency_reduced_freq.3532264333 Jul 01 07:33:14 PM PDT 24 Jul 01 08:53:13 PM PDT 24 30499102682 ps
T353 /workspace/coverage/default/1.chip_sw_pattgen_ios.1444022120 Jul 01 07:19:53 PM PDT 24 Jul 01 07:25:25 PM PDT 24 2944072534 ps
T247 /workspace/coverage/default/1.chip_sw_sysrst_ctrl_outputs.3867014959 Jul 01 07:21:39 PM PDT 24 Jul 01 07:28:55 PM PDT 24 3280282276 ps
T23 /workspace/coverage/default/2.chip_sw_sleep_pin_mio_dio_val.3684825549 Jul 01 07:27:49 PM PDT 24 Jul 01 07:32:29 PM PDT 24 3628151674 ps
T686 /workspace/coverage/default/2.chip_sw_aes_enc.694796438 Jul 01 07:29:58 PM PDT 24 Jul 01 07:35:50 PM PDT 24 2548432674 ps
T687 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod_end.1449661928 Jul 01 07:24:21 PM PDT 24 Jul 01 08:41:45 PM PDT 24 14915449328 ps
T93 /workspace/coverage/default/4.chip_sw_sensor_ctrl_alert.3198659615 Jul 01 07:39:08 PM PDT 24 Jul 01 07:52:16 PM PDT 24 5785675660 ps
T688 /workspace/coverage/default/1.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.1087617078 Jul 01 07:26:20 PM PDT 24 Jul 01 07:44:35 PM PDT 24 7706426887 ps
T459 /workspace/coverage/default/11.chip_sw_all_escalation_resets.3956764074 Jul 01 07:40:30 PM PDT 24 Jul 01 07:49:00 PM PDT 24 5842559404 ps
T689 /workspace/coverage/default/1.chip_sw_example_concurrency.3174712560 Jul 01 07:15:22 PM PDT 24 Jul 01 07:19:25 PM PDT 24 2557142032 ps
T690 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_rma.2280631248 Jul 01 07:14:57 PM PDT 24 Jul 01 08:27:13 PM PDT 24 14284013459 ps
T248 /workspace/coverage/default/2.chip_sw_sysrst_ctrl_inputs.1889018179 Jul 01 07:38:43 PM PDT 24 Jul 01 07:43:56 PM PDT 24 2873218845 ps
T691 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_rma.2536195392 Jul 01 07:16:28 PM PDT 24 Jul 01 08:19:18 PM PDT 24 14686173948 ps
T692 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_dev.998482864 Jul 01 07:17:38 PM PDT 24 Jul 01 08:21:19 PM PDT 24 14998572602 ps
T393 /workspace/coverage/default/1.chip_sw_rv_core_ibex_nmi_irq.1640890186 Jul 01 07:24:10 PM PDT 24 Jul 01 07:42:55 PM PDT 24 4807360584 ps
T188 /workspace/coverage/default/2.chip_plic_all_irqs_0.2427429636 Jul 01 07:33:22 PM PDT 24 Jul 01 07:50:24 PM PDT 24 6333052440 ps
T693 /workspace/coverage/default/2.chip_tap_straps_dev.2687205514 Jul 01 07:33:24 PM PDT 24 Jul 01 07:39:26 PM PDT 24 4645338543 ps
T694 /workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq.3418351406 Jul 01 07:36:18 PM PDT 24 Jul 01 07:50:05 PM PDT 24 4132619256 ps
T695 /workspace/coverage/default/1.chip_sw_clkmgr_reset_frequency.220523491 Jul 01 07:27:56 PM PDT 24 Jul 01 07:33:55 PM PDT 24 3152795628 ps
T696 /workspace/coverage/default/11.chip_sw_uart_rand_baudrate.167747895 Jul 01 07:39:09 PM PDT 24 Jul 01 08:05:13 PM PDT 24 8370218158 ps
T416 /workspace/coverage/default/0.chip_sw_usbdev_stream.2732254909 Jul 01 07:12:51 PM PDT 24 Jul 01 08:37:34 PM PDT 24 18920309406 ps
T697 /workspace/coverage/default/2.chip_sw_clkmgr_reset_frequency.1172305656 Jul 01 07:34:15 PM PDT 24 Jul 01 07:40:50 PM PDT 24 3167062092 ps
T698 /workspace/coverage/default/8.chip_sw_uart_rand_baudrate.4260665187 Jul 01 07:40:13 PM PDT 24 Jul 01 08:05:51 PM PDT 24 8669427576 ps
T244 /workspace/coverage/default/1.chip_sw_uart_tx_rx_bootstrap.4160116448 Jul 01 07:17:31 PM PDT 24 Jul 01 11:14:36 PM PDT 24 78162068426 ps
T513 /workspace/coverage/default/58.chip_sw_alert_handler_lpg_sleep_mode_alerts.2214655358 Jul 01 07:44:48 PM PDT 24 Jul 01 07:50:20 PM PDT 24 3493129664 ps
T699 /workspace/coverage/default/12.chip_sw_lc_ctrl_transition.4057066189 Jul 01 07:40:16 PM PDT 24 Jul 01 07:49:18 PM PDT 24 5878159464 ps
T700 /workspace/coverage/default/1.chip_sw_csrng_kat_test.887340075 Jul 01 07:23:37 PM PDT 24 Jul 01 07:27:59 PM PDT 24 3172002052 ps
T701 /workspace/coverage/default/1.chip_sw_kmac_entropy.2756836991 Jul 01 07:17:27 PM PDT 24 Jul 01 07:21:25 PM PDT 24 2926881384 ps
T702 /workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_meas.971673936 Jul 01 07:37:41 PM PDT 24 Jul 01 08:57:42 PM PDT 24 15397522048 ps
T703 /workspace/coverage/default/0.chip_sw_aes_smoketest.2675675480 Jul 01 07:14:12 PM PDT 24 Jul 01 07:21:00 PM PDT 24 2726604808 ps
T704 /workspace/coverage/default/2.chip_sw_kmac_mode_cshake.877373507 Jul 01 07:33:26 PM PDT 24 Jul 01 07:39:48 PM PDT 24 3287015304 ps
T705 /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_lc.1099839675 Jul 01 07:25:30 PM PDT 24 Jul 01 07:38:27 PM PDT 24 12358971548 ps
T254 /workspace/coverage/default/1.chip_sw_lc_walkthrough_rma.1699430567 Jul 01 07:19:32 PM PDT 24 Jul 01 08:46:08 PM PDT 24 46493717662 ps
T706 /workspace/coverage/default/0.chip_sw_uart_smoketest.1535080640 Jul 01 07:13:30 PM PDT 24 Jul 01 07:17:58 PM PDT 24 2662579648 ps
T707 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_dev.4071010962 Jul 01 07:18:55 PM PDT 24 Jul 01 08:53:45 PM PDT 24 23859964550 ps
T120 /workspace/coverage/default/1.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.4233837675 Jul 01 07:24:25 PM PDT 24 Jul 01 07:32:30 PM PDT 24 4451760828 ps
T708 /workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.502156067 Jul 01 07:14:11 PM PDT 24 Jul 01 08:22:11 PM PDT 24 25561862564 ps
T709 /workspace/coverage/default/0.chip_sw_clkmgr_jitter_frequency.868412384 Jul 01 07:12:27 PM PDT 24 Jul 01 07:20:16 PM PDT 24 3119765142 ps
T465 /workspace/coverage/default/24.chip_sw_alert_handler_lpg_sleep_mode_alerts.1233721824 Jul 01 07:45:08 PM PDT 24 Jul 01 07:51:41 PM PDT 24 4273499900 ps
T710 /workspace/coverage/default/0.chip_sw_lc_walkthrough_testunlocks.716728434 Jul 01 07:10:52 PM PDT 24 Jul 01 07:51:33 PM PDT 24 22756838220 ps
T711 /workspace/coverage/default/0.chip_sw_kmac_app_rom.1110629005 Jul 01 07:14:17 PM PDT 24 Jul 01 07:18:54 PM PDT 24 3466976224 ps
T712 /workspace/coverage/default/0.chip_tap_straps_prod.2302721120 Jul 01 07:19:50 PM PDT 24 Jul 01 07:22:03 PM PDT 24 2233456449 ps
T343 /workspace/coverage/default/88.chip_sw_all_escalation_resets.3120246877 Jul 01 07:46:26 PM PDT 24 Jul 01 07:55:31 PM PDT 24 6069816332 ps
T713 /workspace/coverage/default/8.chip_sw_lc_ctrl_transition.2800776392 Jul 01 07:37:31 PM PDT 24 Jul 01 07:55:24 PM PDT 24 9987955804 ps
T714 /workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en.3697137801 Jul 01 07:22:36 PM PDT 24 Jul 01 08:24:19 PM PDT 24 18589403484 ps
T348 /workspace/coverage/default/2.chip_sw_rstmgr_alert_info.3188224909 Jul 01 07:28:19 PM PDT 24 Jul 01 07:51:35 PM PDT 24 12853724822 ps
T715 /workspace/coverage/default/1.chip_sw_edn_entropy_reqs.1328832041 Jul 01 07:23:57 PM PDT 24 Jul 01 07:46:50 PM PDT 24 6533205274 ps
T716 /workspace/coverage/default/7.chip_sw_csrng_edn_concurrency.85906886 Jul 01 07:38:11 PM PDT 24 Jul 01 08:32:07 PM PDT 24 16168087780 ps
T330 /workspace/coverage/default/0.chip_sw_rv_core_ibex_icache_invalidate.4233100400 Jul 01 07:13:37 PM PDT 24 Jul 01 07:17:31 PM PDT 24 2881206431 ps
T717 /workspace/coverage/default/0.chip_sw_pwrmgr_usb_clk_disabled_when_active.552530318 Jul 01 07:10:46 PM PDT 24 Jul 01 07:16:36 PM PDT 24 4130529880 ps
T718 /workspace/coverage/default/0.chip_sw_pwrmgr_sysrst_ctrl_reset.4151013308 Jul 01 07:13:45 PM PDT 24 Jul 01 07:34:25 PM PDT 24 8040115592 ps
T719 /workspace/coverage/default/1.chip_sw_alert_handler_ping_timeout.3454800496 Jul 01 07:22:48 PM PDT 24 Jul 01 07:29:18 PM PDT 24 4082432756 ps
T320 /workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access.3359673702 Jul 01 07:13:26 PM PDT 24 Jul 01 07:26:50 PM PDT 24 4892200700 ps
T720 /workspace/coverage/default/1.chip_sw_ast_clk_outputs.35235417 Jul 01 07:28:05 PM PDT 24 Jul 01 07:46:14 PM PDT 24 6884553528 ps
T27 /workspace/coverage/default/1.chip_sw_spi_device_pass_through_collision.2062644661 Jul 01 07:18:39 PM PDT 24 Jul 01 07:27:10 PM PDT 24 4803461169 ps
T721 /workspace/coverage/default/0.rom_e2e_asm_init_prod.3813881185 Jul 01 07:16:54 PM PDT 24 Jul 01 08:24:50 PM PDT 24 14903248036 ps
T504 /workspace/coverage/default/85.chip_sw_all_escalation_resets.2264058152 Jul 01 07:48:20 PM PDT 24 Jul 01 07:57:47 PM PDT 24 5153844036 ps
T722 /workspace/coverage/default/1.chip_sw_aes_enc_jitter_en.3041485122 Jul 01 07:22:08 PM PDT 24 Jul 01 07:27:28 PM PDT 24 3514117046 ps
T723 /workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_reset_reqs.776238637 Jul 01 07:19:49 PM PDT 24 Jul 01 08:02:26 PM PDT 24 23327583971 ps
T724 /workspace/coverage/default/2.chip_sw_lc_ctrl_transition.1418828043 Jul 01 07:28:29 PM PDT 24 Jul 01 07:39:07 PM PDT 24 6150240942 ps
T725 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_rma.1763465842 Jul 01 07:19:01 PM PDT 24 Jul 01 08:15:37 PM PDT 24 13810707722 ps
T326 /workspace/coverage/default/42.chip_sw_alert_handler_lpg_sleep_mode_alerts.2454564737 Jul 01 07:43:03 PM PDT 24 Jul 01 07:48:29 PM PDT 24 4200239300 ps
T249 /workspace/coverage/default/1.chip_sw_sysrst_ctrl_inputs.3573733753 Jul 01 07:19:38 PM PDT 24 Jul 01 07:25:40 PM PDT 24 2911270223 ps
T149 /workspace/coverage/default/1.chip_sw_csrng_lc_hw_debug_en_test.4134758996 Jul 01 07:23:06 PM PDT 24 Jul 01 07:37:44 PM PDT 24 6696097864 ps
T726 /workspace/coverage/default/2.chip_sw_pwrmgr_usbdev_smoketest.687362737 Jul 01 07:36:12 PM PDT 24 Jul 01 07:42:21 PM PDT 24 6100243670 ps
T727 /workspace/coverage/default/2.chip_sw_otp_ctrl_smoketest.3499977267 Jul 01 07:35:21 PM PDT 24 Jul 01 07:40:25 PM PDT 24 3177159800 ps
T486 /workspace/coverage/default/26.chip_sw_all_escalation_resets.3806132193 Jul 01 07:40:19 PM PDT 24 Jul 01 07:53:08 PM PDT 24 5677519600 ps
T728 /workspace/coverage/default/64.chip_sw_all_escalation_resets.2388167235 Jul 01 07:44:12 PM PDT 24 Jul 01 07:55:38 PM PDT 24 5759614580 ps
T286 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.3564854219 Jul 01 07:24:37 PM PDT 24 Jul 01 09:19:02 PM PDT 24 24289349368 ps
T729 /workspace/coverage/default/1.chip_sw_sysrst_ctrl_in_irq.53974984 Jul 01 07:22:12 PM PDT 24 Jul 01 07:32:47 PM PDT 24 4152013759 ps
T66 /workspace/coverage/default/2.chip_jtag_mem_access.3472334609 Jul 01 07:26:14 PM PDT 24 Jul 01 07:50:13 PM PDT 24 13669377601 ps
T730 /workspace/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.1536444626 Jul 01 07:34:01 PM PDT 24 Jul 01 08:07:32 PM PDT 24 11152762637 ps
T731 /workspace/coverage/default/35.chip_sw_all_escalation_resets.1688690656 Jul 01 07:45:33 PM PDT 24 Jul 01 07:55:29 PM PDT 24 5457625716 ps
T732 /workspace/coverage/default/0.chip_sw_pwrmgr_usbdev_smoketest.2013159485 Jul 01 07:12:37 PM PDT 24 Jul 01 07:20:10 PM PDT 24 5818303650 ps
T733 /workspace/coverage/default/1.chip_sw_clkmgr_jitter_frequency.3077269731 Jul 01 07:28:18 PM PDT 24 Jul 01 07:38:12 PM PDT 24 3212418132 ps
T734 /workspace/coverage/default/1.chip_sw_otbn_randomness.2478332974 Jul 01 07:22:23 PM PDT 24 Jul 01 07:41:48 PM PDT 24 5632103196 ps
T445 /workspace/coverage/default/64.chip_sw_alert_handler_lpg_sleep_mode_alerts.4165590765 Jul 01 07:44:19 PM PDT 24 Jul 01 07:51:57 PM PDT 24 4478121840 ps
T446 /workspace/coverage/default/4.chip_sw_alert_handler_lpg_sleep_mode_alerts.1959145379 Jul 01 07:38:33 PM PDT 24 Jul 01 07:45:30 PM PDT 24 3488468780 ps
T735 /workspace/coverage/default/2.chip_sw_alert_handler_ping_ok.508526183 Jul 01 07:30:48 PM PDT 24 Jul 01 07:52:16 PM PDT 24 7929401730 ps
T736 /workspace/coverage/default/1.chip_sw_csrng_smoketest.2161922773 Jul 01 07:32:41 PM PDT 24 Jul 01 07:37:24 PM PDT 24 2758443616 ps
T737 /workspace/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.2270594376 Jul 01 07:33:55 PM PDT 24 Jul 01 07:43:50 PM PDT 24 5670893471 ps
T738 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.801757027 Jul 01 07:35:03 PM PDT 24 Jul 01 07:46:29 PM PDT 24 4443667946 ps
T739 /workspace/coverage/default/2.chip_sw_edn_kat.512114597 Jul 01 07:31:11 PM PDT 24 Jul 01 07:41:40 PM PDT 24 2949109064 ps
T740 /workspace/coverage/default/1.rom_e2e_smoke.2403555333 Jul 01 07:28:25 PM PDT 24 Jul 01 08:26:42 PM PDT 24 14564798240 ps
T442 /workspace/coverage/default/45.chip_sw_alert_handler_lpg_sleep_mode_alerts.1551380775 Jul 01 07:42:31 PM PDT 24 Jul 01 07:47:44 PM PDT 24 3245113976 ps
T741 /workspace/coverage/default/0.chip_sw_rstmgr_sw_req.3989345206 Jul 01 07:10:51 PM PDT 24 Jul 01 07:16:08 PM PDT 24 3966651990 ps
T742 /workspace/coverage/default/40.chip_sw_alert_handler_lpg_sleep_mode_alerts.2015197128 Jul 01 07:42:12 PM PDT 24 Jul 01 07:49:56 PM PDT 24 4041318200 ps
T496 /workspace/coverage/default/79.chip_sw_alert_handler_lpg_sleep_mode_alerts.2300242852 Jul 01 07:48:10 PM PDT 24 Jul 01 07:54:11 PM PDT 24 4027231280 ps
T743 /workspace/coverage/default/1.chip_sw_clkmgr_jitter_reduced_freq.3552141497 Jul 01 07:24:25 PM PDT 24 Jul 01 07:28:38 PM PDT 24 2837066979 ps
T744 /workspace/coverage/default/2.chip_sw_hmac_oneshot.2704119304 Jul 01 07:31:35 PM PDT 24 Jul 01 07:38:06 PM PDT 24 2523449860 ps
T745 /workspace/coverage/default/10.chip_sw_lc_ctrl_transition.3054724707 Jul 01 07:40:06 PM PDT 24 Jul 01 07:58:37 PM PDT 24 12141051160 ps
T256 /workspace/coverage/default/2.chip_sw_flash_init_reduced_freq.2310884897 Jul 01 07:33:16 PM PDT 24 Jul 01 08:10:31 PM PDT 24 24573747281 ps
T746 /workspace/coverage/default/0.chip_sw_lc_walkthrough_prodend.1028393196 Jul 01 07:09:58 PM PDT 24 Jul 01 07:22:05 PM PDT 24 8185288250 ps
T747 /workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_invalid_meas.2972259429 Jul 01 07:43:37 PM PDT 24 Jul 01 08:52:04 PM PDT 24 14932116300 ps
T456 /workspace/coverage/default/62.chip_sw_all_escalation_resets.1791130947 Jul 01 07:44:59 PM PDT 24 Jul 01 07:54:10 PM PDT 24 5985523880 ps
T748 /workspace/coverage/default/2.chip_sw_csrng_fuse_en_sw_app_read_test.1266305972 Jul 01 07:36:06 PM PDT 24 Jul 01 07:44:02 PM PDT 24 4588005564 ps
T428 /workspace/coverage/default/0.rom_volatile_raw_unlock.4116341669 Jul 01 07:14:48 PM PDT 24 Jul 01 07:16:53 PM PDT 24 2793366039 ps
T749 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.2795322436 Jul 01 07:12:27 PM PDT 24 Jul 01 07:22:13 PM PDT 24 3881137992 ps
T750 /workspace/coverage/default/2.chip_sw_kmac_entropy.3723644830 Jul 01 07:28:42 PM PDT 24 Jul 01 07:32:35 PM PDT 24 2533542860 ps
T751 /workspace/coverage/default/1.chip_sw_sleep_pwm_pulses.1390100065 Jul 01 07:16:29 PM PDT 24 Jul 01 07:42:33 PM PDT 24 10187787896 ps
T752 /workspace/coverage/default/2.chip_sw_gpio_smoketest.44233692 Jul 01 07:35:55 PM PDT 24 Jul 01 07:40:08 PM PDT 24 2705326065 ps
T753 /workspace/coverage/default/1.chip_sw_keymgr_key_derivation.1068349794 Jul 01 07:23:21 PM PDT 24 Jul 01 07:50:55 PM PDT 24 9691871052 ps
T754 /workspace/coverage/default/0.chip_sw_rstmgr_rst_cnsty_escalation.3382755607 Jul 01 07:09:27 PM PDT 24 Jul 01 07:22:31 PM PDT 24 5093003160 ps
T511 /workspace/coverage/default/87.chip_sw_all_escalation_resets.3084522268 Jul 01 07:45:17 PM PDT 24 Jul 01 07:53:59 PM PDT 24 5688981888 ps
T755 /workspace/coverage/default/0.chip_sw_flash_ctrl_clock_freqs.3874743309 Jul 01 07:10:21 PM PDT 24 Jul 01 07:26:17 PM PDT 24 5456248167 ps
T756 /workspace/coverage/default/0.chip_sw_lc_walkthrough_dev.3242070554 Jul 01 07:12:24 PM PDT 24 Jul 01 08:46:42 PM PDT 24 49639436418 ps
T293 /workspace/coverage/default/18.chip_sw_all_escalation_resets.701259337 Jul 01 07:40:16 PM PDT 24 Jul 01 07:49:17 PM PDT 24 4391061300 ps
T95 /workspace/coverage/default/0.chip_sw_sensor_ctrl_alert.14975343 Jul 01 07:12:04 PM PDT 24 Jul 01 07:27:24 PM PDT 24 7897069756 ps
T757 /workspace/coverage/default/1.chip_sw_sleep_sram_ret_contents_no_scramble.2338136827 Jul 01 07:25:37 PM PDT 24 Jul 01 07:38:06 PM PDT 24 7773255556 ps
T218 /workspace/coverage/default/0.chip_sw_flash_rma_unlocked.3394413767 Jul 01 07:10:25 PM PDT 24 Jul 01 08:42:10 PM PDT 24 43022042769 ps
T758 /workspace/coverage/default/1.chip_sw_flash_ctrl_idle_low_power.876207907 Jul 01 07:18:17 PM PDT 24 Jul 01 07:24:33 PM PDT 24 2771387516 ps
T379 /workspace/coverage/default/1.chip_sw_hmac_enc_jitter_en.1906830681 Jul 01 07:25:38 PM PDT 24 Jul 01 07:30:28 PM PDT 24 3608948507 ps
T437 /workspace/coverage/default/32.chip_sw_all_escalation_resets.3792886256 Jul 01 07:41:47 PM PDT 24 Jul 01 07:56:26 PM PDT 24 6491315794 ps
T759 /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.1375765272 Jul 01 07:10:56 PM PDT 24 Jul 01 07:36:36 PM PDT 24 18228476060 ps
T760 /workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq.827936544 Jul 01 07:12:51 PM PDT 24 Jul 01 08:14:00 PM PDT 24 17183482520 ps
T294 /workspace/coverage/default/42.chip_sw_all_escalation_resets.2099096739 Jul 01 07:42:51 PM PDT 24 Jul 01 07:52:13 PM PDT 24 5247367480 ps
T761 /workspace/coverage/default/0.rom_e2e_asm_init_rma.828058900 Jul 01 07:22:32 PM PDT 24 Jul 01 08:21:37 PM PDT 24 14724544976 ps
T762 /workspace/coverage/default/0.chip_sw_usb_ast_clk_calib.637183118 Jul 01 07:11:48 PM PDT 24 Jul 01 07:16:17 PM PDT 24 2739000413 ps
T763 /workspace/coverage/default/5.chip_sw_uart_rand_baudrate.3708594589 Jul 01 07:39:12 PM PDT 24 Jul 01 07:48:06 PM PDT 24 4116176084 ps
T764 /workspace/coverage/default/1.chip_sw_pwrmgr_sysrst_ctrl_reset.2871151730 Jul 01 07:20:17 PM PDT 24 Jul 01 07:38:34 PM PDT 24 8115188568 ps
T429 /workspace/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock.3770176207 Jul 01 07:12:33 PM PDT 24 Jul 01 07:14:36 PM PDT 24 2401840353 ps
T765 /workspace/coverage/default/2.rom_volatile_raw_unlock.1834690443 Jul 01 07:35:17 PM PDT 24 Jul 01 07:37:24 PM PDT 24 2570991868 ps
T766 /workspace/coverage/default/0.chip_sw_hmac_multistream.1670388481 Jul 01 07:14:14 PM PDT 24 Jul 01 07:51:26 PM PDT 24 8762408744 ps
T767 /workspace/coverage/default/2.chip_sw_edn_sw_mode.1788463660 Jul 01 07:31:07 PM PDT 24 Jul 01 08:08:35 PM PDT 24 10664538192 ps
T768 /workspace/coverage/default/1.chip_sw_sensor_ctrl_status.1468388015 Jul 01 07:29:34 PM PDT 24 Jul 01 07:35:03 PM PDT 24 3450285729 ps
T769 /workspace/coverage/default/1.chip_sw_hmac_enc_idle.2343705954 Jul 01 07:23:02 PM PDT 24 Jul 01 07:26:43 PM PDT 24 3357811504 ps
T770 /workspace/coverage/default/0.chip_sw_aes_masking_off.3087170052 Jul 01 07:11:49 PM PDT 24 Jul 01 07:16:37 PM PDT 24 3292194005 ps
T305 /workspace/coverage/default/2.chip_sw_data_integrity_escalation.1407795817 Jul 01 07:27:07 PM PDT 24 Jul 01 07:41:49 PM PDT 24 4532222750 ps
T307 /workspace/coverage/default/89.chip_sw_all_escalation_resets.2743871631 Jul 01 07:46:46 PM PDT 24 Jul 01 07:57:09 PM PDT 24 5884730120 ps
T308 /workspace/coverage/default/1.chip_sw_clkmgr_off_kmac_trans.3452766217 Jul 01 07:26:55 PM PDT 24 Jul 01 07:33:52 PM PDT 24 3718985852 ps
T309 /workspace/coverage/default/0.chip_sw_aon_timer_irq.1069474976 Jul 01 07:10:24 PM PDT 24 Jul 01 07:17:07 PM PDT 24 3621516856 ps
T310 /workspace/coverage/default/2.chip_sw_sysrst_ctrl_reset.1568611945 Jul 01 07:31:19 PM PDT 24 Jul 01 08:01:46 PM PDT 24 24151450498 ps
T311 /workspace/coverage/default/0.chip_sw_hmac_enc_jitter_en_reduced_freq.2552855997 Jul 01 07:14:10 PM PDT 24 Jul 01 07:19:21 PM PDT 24 3607913330 ps
T150 /workspace/coverage/default/0.chip_jtag_mem_access.378102765 Jul 01 07:04:10 PM PDT 24 Jul 01 07:26:23 PM PDT 24 14164250200 ps
T312 /workspace/coverage/default/74.chip_sw_all_escalation_resets.3487783478 Jul 01 07:45:25 PM PDT 24 Jul 01 07:54:41 PM PDT 24 5954284340 ps
T313 /workspace/coverage/default/18.chip_sw_alert_handler_lpg_sleep_mode_alerts.2664547929 Jul 01 07:39:38 PM PDT 24 Jul 01 07:46:38 PM PDT 24 3841264834 ps
T314 /workspace/coverage/default/2.chip_tap_straps_prod.4064085067 Jul 01 07:35:54 PM PDT 24 Jul 01 07:53:42 PM PDT 24 10511007069 ps
T771 /workspace/coverage/default/0.chip_sw_power_idle_load.3322573858 Jul 01 07:13:40 PM PDT 24 Jul 01 07:25:39 PM PDT 24 4329167200 ps
T772 /workspace/coverage/default/2.chip_sw_flash_init.2586176438 Jul 01 07:27:36 PM PDT 24 Jul 01 07:59:17 PM PDT 24 22375483565 ps
T773 /workspace/coverage/default/1.chip_sw_aes_smoketest.165718596 Jul 01 07:28:13 PM PDT 24 Jul 01 07:34:29 PM PDT 24 2773591908 ps
T774 /workspace/coverage/default/1.rom_e2e_asm_init_dev.195572552 Jul 01 07:37:03 PM PDT 24 Jul 01 08:36:45 PM PDT 24 15018721710 ps
T447 /workspace/coverage/default/60.chip_sw_alert_handler_lpg_sleep_mode_alerts.2572142114 Jul 01 07:43:59 PM PDT 24 Jul 01 07:49:07 PM PDT 24 3646846984 ps
T775 /workspace/coverage/default/1.chip_sw_power_idle_load.807923945 Jul 01 07:27:27 PM PDT 24 Jul 01 07:37:35 PM PDT 24 4641584912 ps
T776 /workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_invalid_meas.2842383946 Jul 01 07:30:07 PM PDT 24 Jul 01 08:29:44 PM PDT 24 14427496772 ps
T777 /workspace/coverage/default/56.chip_sw_all_escalation_resets.3306843159 Jul 01 07:43:37 PM PDT 24 Jul 01 07:54:21 PM PDT 24 5164090608 ps
T778 /workspace/coverage/default/1.chip_sw_kmac_idle.2135406494 Jul 01 07:27:15 PM PDT 24 Jul 01 07:30:22 PM PDT 24 3341299888 ps
T779 /workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_power_glitch_reset.995913743 Jul 01 07:28:40 PM PDT 24 Jul 01 08:14:28 PM PDT 24 39527369848 ps
T340 /workspace/coverage/default/2.chip_sw_keymgr_sideload_otbn.4209237198 Jul 01 07:31:34 PM PDT 24 Jul 01 08:21:11 PM PDT 24 13800552982 ps
T780 /workspace/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.326347921 Jul 01 07:16:18 PM PDT 24 Jul 01 07:38:19 PM PDT 24 7614133029 ps
T96 /workspace/coverage/default/2.chip_sw_ast_clk_rst_inputs.3081837734 Jul 01 07:34:47 PM PDT 24 Jul 01 08:04:08 PM PDT 24 17053280892 ps
T781 /workspace/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock.231811497 Jul 01 07:19:51 PM PDT 24 Jul 01 07:21:47 PM PDT 24 2419838583 ps
T782 /workspace/coverage/default/6.chip_sw_csrng_edn_concurrency.2097404524 Jul 01 07:39:46 PM PDT 24 Jul 01 09:21:59 PM PDT 24 26898427464 ps
T783 /workspace/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.3923782055 Jul 01 07:34:52 PM PDT 24 Jul 01 07:54:21 PM PDT 24 6595075445 ps
T784 /workspace/coverage/default/0.chip_sw_clkmgr_sleep_frequency.467405238 Jul 01 07:16:04 PM PDT 24 Jul 01 07:29:02 PM PDT 24 4545767044 ps
T785 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_prod_end.3510206007 Jul 01 07:16:46 PM PDT 24 Jul 01 08:42:04 PM PDT 24 23450367299 ps
T444 /workspace/coverage/default/37.chip_sw_alert_handler_lpg_sleep_mode_alerts.4057638282 Jul 01 07:41:12 PM PDT 24 Jul 01 07:48:07 PM PDT 24 3723322318 ps
T786 /workspace/coverage/default/60.chip_sw_all_escalation_resets.13326877 Jul 01 07:44:38 PM PDT 24 Jul 01 07:52:26 PM PDT 24 4259648200 ps
T787 /workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_meas.1907156052 Jul 01 07:20:26 PM PDT 24 Jul 01 08:23:54 PM PDT 24 15243831800 ps
T494 /workspace/coverage/default/68.chip_sw_all_escalation_resets.1058110307 Jul 01 07:44:30 PM PDT 24 Jul 01 07:54:34 PM PDT 24 4858595672 ps
T788 /workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.4123030126 Jul 01 07:09:17 PM PDT 24 Jul 01 07:25:38 PM PDT 24 8752493933 ps
T789 /workspace/coverage/default/1.chip_sw_otbn_smoketest.4047927099 Jul 01 07:26:59 PM PDT 24 Jul 01 07:56:04 PM PDT 24 8604051090 ps
T790 /workspace/coverage/default/2.chip_sw_uart_tx_rx_idx1.181110621 Jul 01 07:26:46 PM PDT 24 Jul 01 07:39:13 PM PDT 24 3369996240 ps
T791 /workspace/coverage/default/78.chip_sw_all_escalation_resets.707111463 Jul 01 07:44:54 PM PDT 24 Jul 01 07:54:46 PM PDT 24 5311822312 ps
T792 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod.4142838270 Jul 01 07:18:23 PM PDT 24 Jul 01 08:32:15 PM PDT 24 14229150925 ps
T793 /workspace/coverage/default/9.chip_sw_uart_rand_baudrate.3208942688 Jul 01 07:39:17 PM PDT 24 Jul 01 08:01:35 PM PDT 24 8249290288 ps
T794 /workspace/coverage/default/4.chip_sw_uart_tx_rx.2983772571 Jul 01 07:38:10 PM PDT 24 Jul 01 07:46:50 PM PDT 24 4145472500 ps
T795 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_rma.946472583 Jul 01 07:18:01 PM PDT 24 Jul 01 08:52:12 PM PDT 24 22821185482 ps
T796 /workspace/coverage/default/0.chip_sw_alert_handler_entropy.1900750518 Jul 01 07:13:16 PM PDT 24 Jul 01 07:17:28 PM PDT 24 3437897378 ps
T797 /workspace/coverage/default/0.chip_sw_flash_scrambling_smoketest.3558939452 Jul 01 07:17:08 PM PDT 24 Jul 01 07:21:09 PM PDT 24 3126619608 ps
T798 /workspace/coverage/default/0.chip_sw_sysrst_ctrl_ec_rst_l.1328885512 Jul 01 07:08:50 PM PDT 24 Jul 01 08:00:06 PM PDT 24 21253460390 ps
T468 /workspace/coverage/default/74.chip_sw_alert_handler_lpg_sleep_mode_alerts.2534846634 Jul 01 07:44:35 PM PDT 24 Jul 01 07:51:16 PM PDT 24 3829404478 ps
T799 /workspace/coverage/default/1.chip_sw_example_flash.2173676409 Jul 01 07:16:21 PM PDT 24 Jul 01 07:19:50 PM PDT 24 3391373422 ps
T161 /workspace/coverage/default/0.chip_sw_usbdev_aon_pullup.696795438 Jul 01 07:09:29 PM PDT 24 Jul 01 07:19:22 PM PDT 24 3644722864 ps
T241 /workspace/coverage/default/2.chip_sw_spi_device_pass_through.79016076 Jul 01 07:26:58 PM PDT 24 Jul 01 07:39:42 PM PDT 24 7019352737 ps
T800 /workspace/coverage/default/2.chip_sw_rv_plic_smoketest.739228368 Jul 01 07:34:33 PM PDT 24 Jul 01 07:37:35 PM PDT 24 2461307960 ps
T801 /workspace/coverage/default/0.chip_tap_straps_dev.242432694 Jul 01 07:11:56 PM PDT 24 Jul 01 07:15:50 PM PDT 24 3049717273 ps
T802 /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_test_unlocked0.1970373293 Jul 01 07:28:15 PM PDT 24 Jul 01 07:38:58 PM PDT 24 4999876674 ps
T481 /workspace/coverage/default/17.chip_sw_all_escalation_resets.1046934779 Jul 01 07:42:59 PM PDT 24 Jul 01 07:55:18 PM PDT 24 5552478504 ps
T803 /workspace/coverage/default/1.chip_sw_flash_crash_alert.3937249921 Jul 01 07:25:04 PM PDT 24 Jul 01 07:35:05 PM PDT 24 5738125720 ps
T159 /workspace/coverage/default/2.chip_tap_straps_testunlock0.4168047451 Jul 01 07:33:24 PM PDT 24 Jul 01 07:43:51 PM PDT 24 5981774562 ps
T804 /workspace/coverage/default/0.chip_sw_otp_ctrl_ecc_error_vendor_test.3435642979 Jul 01 07:11:53 PM PDT 24 Jul 01 07:16:14 PM PDT 24 3065046923 ps
T805 /workspace/coverage/default/2.rom_e2e_asm_init_test_unlocked0.3913646440 Jul 01 07:43:11 PM PDT 24 Jul 01 08:39:35 PM PDT 24 11489998200 ps
T806 /workspace/coverage/default/2.chip_sw_entropy_src_kat_test.3131303618 Jul 01 07:30:42 PM PDT 24 Jul 01 07:35:24 PM PDT 24 2881365816 ps
T807 /workspace/coverage/default/2.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.4080941886 Jul 01 07:30:10 PM PDT 24 Jul 01 07:39:05 PM PDT 24 19306681054 ps
T808 /workspace/coverage/default/2.chip_sw_flash_ctrl_mem_protection.1770242047 Jul 01 07:35:31 PM PDT 24 Jul 01 07:53:42 PM PDT 24 5482938938 ps
T809 /workspace/coverage/default/2.chip_sw_uart_tx_rx_bootstrap.700080123 Jul 01 07:27:33 PM PDT 24 Jul 01 11:27:11 PM PDT 24 78836526096 ps
T810 /workspace/coverage/default/2.chip_sw_clkmgr_off_aes_trans.3008575907 Jul 01 07:32:15 PM PDT 24 Jul 01 07:42:35 PM PDT 24 5936791216 ps
T811 /workspace/coverage/default/0.chip_sw_example_flash.1393985852 Jul 01 07:09:43 PM PDT 24 Jul 01 07:13:50 PM PDT 24 3463900278 ps
T54 /workspace/coverage/default/0.chip_sw_spi_device_tpm.18779288 Jul 01 07:09:18 PM PDT 24 Jul 01 07:17:13 PM PDT 24 3643401512 ps
T223 /workspace/coverage/default/1.chip_sw_i2c_host_tx_rx.821137426 Jul 01 07:17:40 PM PDT 24 Jul 01 07:33:22 PM PDT 24 5534570400 ps
T92 /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.4248708142 Jul 01 07:35:24 PM PDT 24 Jul 01 07:44:55 PM PDT 24 5903702046 ps
T812 /workspace/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en.1218309588 Jul 01 07:33:09 PM PDT 24 Jul 01 07:38:40 PM PDT 24 2799706290 ps
T176 /workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_wake_ups.321338349 Jul 01 07:35:22 PM PDT 24 Jul 01 07:44:59 PM PDT 24 6949571704 ps
T813 /workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_no_scramble.73240570 Jul 01 07:32:13 PM PDT 24 Jul 01 07:45:19 PM PDT 24 8199632696 ps
T814 /workspace/coverage/default/0.chip_sw_example_manufacturer.2668868113 Jul 01 07:10:29 PM PDT 24 Jul 01 07:14:39 PM PDT 24 2071754900 ps
T815 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.791029883 Jul 01 07:18:46 PM PDT 24 Jul 01 07:31:31 PM PDT 24 4154848840 ps
T816 /workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_pings.2569429907 Jul 01 07:32:08 PM PDT 24 Jul 01 08:00:20 PM PDT 24 12962233112 ps
T817 /workspace/coverage/default/0.chip_sw_flash_ctrl_idle_low_power.902282285 Jul 01 07:10:58 PM PDT 24 Jul 01 07:16:39 PM PDT 24 3722265554 ps
T818 /workspace/coverage/default/1.chip_sw_flash_ctrl_write_clear.2866924119 Jul 01 07:25:17 PM PDT 24 Jul 01 07:31:22 PM PDT 24 3055604368 ps
T819 /workspace/coverage/default/1.chip_sw_keymgr_key_derivation_jitter_en.1048506168 Jul 01 07:25:15 PM PDT 24 Jul 01 07:49:09 PM PDT 24 6971978434 ps
T321 /workspace/coverage/default/1.chip_sw_otbn_mem_scramble.2689897390 Jul 01 07:23:03 PM PDT 24 Jul 01 07:31:19 PM PDT 24 3584679008 ps
T401 /workspace/coverage/default/2.chip_sw_rv_core_ibex_lockstep_glitch.2514272162 Jul 01 07:33:36 PM PDT 24 Jul 01 07:39:15 PM PDT 24 3689245720 ps
T820 /workspace/coverage/default/1.chip_sw_csrng_fuse_en_sw_app_read_test.3911808395 Jul 01 07:25:56 PM PDT 24 Jul 01 07:35:50 PM PDT 24 4883980720 ps
T821 /workspace/coverage/default/1.chip_sw_clkmgr_off_aes_trans.1470214390 Jul 01 07:28:04 PM PDT 24 Jul 01 07:37:07 PM PDT 24 4367304078 ps
T822 /workspace/coverage/default/94.chip_sw_all_escalation_resets.427118512 Jul 01 07:46:33 PM PDT 24 Jul 01 07:57:30 PM PDT 24 5748566408 ps
T823 /workspace/coverage/default/1.chip_sw_uart_tx_rx_idx2.1996500553 Jul 01 07:16:03 PM PDT 24 Jul 01 07:27:10 PM PDT 24 4017623050 ps
T450 /workspace/coverage/default/20.chip_sw_all_escalation_resets.4044738432 Jul 01 07:41:22 PM PDT 24 Jul 01 07:52:08 PM PDT 24 4688737080 ps
T13 /workspace/coverage/default/2.chip_sw_sleep_pin_retention.1132099134 Jul 01 07:27:01 PM PDT 24 Jul 01 07:32:35 PM PDT 24 4518755050 ps
T295 /workspace/coverage/default/92.chip_sw_all_escalation_resets.1756066644 Jul 01 07:47:36 PM PDT 24 Jul 01 07:56:59 PM PDT 24 5554641302 ps
T344 /workspace/coverage/default/69.chip_sw_alert_handler_lpg_sleep_mode_alerts.3319442427 Jul 01 07:43:32 PM PDT 24 Jul 01 07:50:08 PM PDT 24 3691097680 ps
T824 /workspace/coverage/default/1.chip_sw_rom_ctrl_integrity_check.2939150845 Jul 01 07:24:59 PM PDT 24 Jul 01 07:32:01 PM PDT 24 9784518049 ps
T434 /workspace/coverage/default/88.chip_sw_alert_handler_lpg_sleep_mode_alerts.2986781391 Jul 01 07:46:08 PM PDT 24 Jul 01 07:52:35 PM PDT 24 4242571650 ps
T825 /workspace/coverage/default/2.chip_sw_alert_handler_ping_timeout.1223450594 Jul 01 07:32:12 PM PDT 24 Jul 01 07:40:17 PM PDT 24 5159910852 ps
T466 /workspace/coverage/default/25.chip_sw_all_escalation_resets.1940355491 Jul 01 07:41:57 PM PDT 24 Jul 01 07:54:06 PM PDT 24 5334873812 ps
T826 /workspace/coverage/default/1.chip_sw_hmac_enc_jitter_en_reduced_freq.2321131742 Jul 01 07:25:56 PM PDT 24 Jul 01 07:30:18 PM PDT 24 3168237770 ps
T827 /workspace/coverage/default/79.chip_sw_all_escalation_resets.2314136276 Jul 01 07:44:21 PM PDT 24 Jul 01 07:53:59 PM PDT 24 5826739576 ps
T472 /workspace/coverage/default/66.chip_sw_all_escalation_resets.415121980 Jul 01 07:44:38 PM PDT 24 Jul 01 07:51:55 PM PDT 24 5123774000 ps
T828 /workspace/coverage/default/1.chip_sw_pwrmgr_usb_clk_disabled_when_active.2505908258 Jul 01 07:21:08 PM PDT 24 Jul 01 07:29:25 PM PDT 24 5596653000 ps
T829 /workspace/coverage/default/0.chip_sw_clkmgr_off_kmac_trans.3479599338 Jul 01 07:11:46 PM PDT 24 Jul 01 07:17:27 PM PDT 24 4841880420 ps
T830 /workspace/coverage/default/2.chip_sw_pwrmgr_full_aon_reset.2128616116 Jul 01 07:29:25 PM PDT 24 Jul 01 07:37:36 PM PDT 24 8343966434 ps
T510 /workspace/coverage/default/51.chip_sw_alert_handler_lpg_sleep_mode_alerts.1972395545 Jul 01 07:44:15 PM PDT 24 Jul 01 07:49:53 PM PDT 24 3976225500 ps
T352 /workspace/coverage/default/1.chip_rv_dm_ndm_reset_req.2766768772 Jul 01 07:25:18 PM PDT 24 Jul 01 07:32:52 PM PDT 24 5188544358 ps
T831 /workspace/coverage/default/63.chip_sw_alert_handler_lpg_sleep_mode_alerts.2098727524 Jul 01 07:44:28 PM PDT 24 Jul 01 07:50:55 PM PDT 24 4068360800 ps
T832 /workspace/coverage/default/2.chip_sw_pwrmgr_main_power_glitch_reset.1172863713 Jul 01 07:30:31 PM PDT 24 Jul 01 07:36:41 PM PDT 24 5003002904 ps
T833 /workspace/coverage/default/1.chip_sw_flash_init_reduced_freq.2342268784 Jul 01 07:24:40 PM PDT 24 Jul 01 08:00:59 PM PDT 24 20376146482 ps
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%