| T350 |
/workspace/coverage/default/0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.2685607488 |
|
|
Jul 01 07:13:43 PM PDT 24 |
Jul 01 07:23:31 PM PDT 24 |
5009885704 ps |
| T394 |
/workspace/coverage/default/2.chip_sw_rv_core_ibex_nmi_irq.950908164 |
|
|
Jul 01 07:31:35 PM PDT 24 |
Jul 01 07:44:10 PM PDT 24 |
4709279310 ps |
| T414 |
/workspace/coverage/default/0.chip_sw_rv_core_ibex_nmi_irq.3197203609 |
|
|
Jul 01 07:10:48 PM PDT 24 |
Jul 01 07:24:13 PM PDT 24 |
4562521048 ps |
| T834 |
/workspace/coverage/default/0.chip_sw_usbdev_setuprx.3620835261 |
|
|
Jul 01 07:12:43 PM PDT 24 |
Jul 01 07:23:07 PM PDT 24 |
3717089432 ps |
| T462 |
/workspace/coverage/default/49.chip_sw_all_escalation_resets.967560430 |
|
|
Jul 01 07:42:39 PM PDT 24 |
Jul 01 07:51:46 PM PDT 24 |
5725986014 ps |
| T363 |
/workspace/coverage/default/1.chip_sw_rstmgr_alert_info.3976929150 |
|
|
Jul 01 07:19:34 PM PDT 24 |
Jul 01 07:49:07 PM PDT 24 |
14913787708 ps |
| T835 |
/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.3968714507 |
|
|
Jul 01 07:32:59 PM PDT 24 |
Jul 01 07:43:25 PM PDT 24 |
5176149126 ps |
| T836 |
/workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.4261816327 |
|
|
Jul 01 07:23:55 PM PDT 24 |
Jul 01 08:31:30 PM PDT 24 |
24685378562 ps |
| T837 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_prod.1528780654 |
|
|
Jul 01 07:21:59 PM PDT 24 |
Jul 01 08:21:02 PM PDT 24 |
15506990176 ps |
| T368 |
/workspace/coverage/default/2.chip_sw_pwrmgr_lowpower_cancel.2896805674 |
|
|
Jul 01 07:33:02 PM PDT 24 |
Jul 01 07:40:31 PM PDT 24 |
3982782400 ps |
| T838 |
/workspace/coverage/default/0.chip_sw_csrng_kat_test.3338232220 |
|
|
Jul 01 07:12:32 PM PDT 24 |
Jul 01 07:18:59 PM PDT 24 |
2843566582 ps |
| T41 |
/workspace/coverage/default/2.chip_sw_gpio.230129698 |
|
|
Jul 01 07:34:58 PM PDT 24 |
Jul 01 07:42:22 PM PDT 24 |
4038815751 ps |
| T839 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_idle_low_power.2353643634 |
|
|
Jul 01 07:27:43 PM PDT 24 |
Jul 01 07:32:36 PM PDT 24 |
2760627428 ps |
| T840 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_prod_end.1862917786 |
|
|
Jul 01 07:23:56 PM PDT 24 |
Jul 01 08:44:07 PM PDT 24 |
15572606188 ps |
| T841 |
/workspace/coverage/default/2.chip_sival_flash_info_access.469732904 |
|
|
Jul 01 07:26:30 PM PDT 24 |
Jul 01 07:32:30 PM PDT 24 |
3196047522 ps |
| T842 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.3259376794 |
|
|
Jul 01 07:16:38 PM PDT 24 |
Jul 01 09:05:28 PM PDT 24 |
24117342984 ps |
| T843 |
/workspace/coverage/default/0.chip_sw_keymgr_key_derivation_prod.988156454 |
|
|
Jul 01 07:12:11 PM PDT 24 |
Jul 01 07:43:10 PM PDT 24 |
8365651288 ps |
| T844 |
/workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.275119679 |
|
|
Jul 01 07:35:50 PM PDT 24 |
Jul 01 07:59:12 PM PDT 24 |
13511021195 ps |
| T845 |
/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.3669630449 |
|
|
Jul 01 07:33:49 PM PDT 24 |
Jul 01 07:44:54 PM PDT 24 |
3851245724 ps |
| T514 |
/workspace/coverage/default/15.chip_sw_alert_handler_lpg_sleep_mode_alerts.3504707688 |
|
|
Jul 01 07:43:01 PM PDT 24 |
Jul 01 07:49:12 PM PDT 24 |
3463115432 ps |
| T482 |
/workspace/coverage/default/20.chip_sw_alert_handler_lpg_sleep_mode_alerts.3158376095 |
|
|
Jul 01 07:40:26 PM PDT 24 |
Jul 01 07:48:12 PM PDT 24 |
4358332430 ps |
| T846 |
/workspace/coverage/default/1.chip_sw_lc_ctrl_otp_hw_cfg0.3142368167 |
|
|
Jul 01 07:18:44 PM PDT 24 |
Jul 01 07:24:17 PM PDT 24 |
3362872232 ps |
| T512 |
/workspace/coverage/default/59.chip_sw_all_escalation_resets.900395684 |
|
|
Jul 01 07:44:58 PM PDT 24 |
Jul 01 07:57:00 PM PDT 24 |
5706775192 ps |
| T171 |
/workspace/coverage/default/63.chip_sw_all_escalation_resets.1704543789 |
|
|
Jul 01 07:46:49 PM PDT 24 |
Jul 01 07:57:55 PM PDT 24 |
5121516556 ps |
| T847 |
/workspace/coverage/default/4.chip_sw_aon_timer_sleep_wdog_sleep_pause.265624756 |
|
|
Jul 01 07:40:15 PM PDT 24 |
Jul 01 07:49:30 PM PDT 24 |
7120694124 ps |
| T848 |
/workspace/coverage/default/1.chip_sw_aes_enc_jitter_en_reduced_freq.1811226749 |
|
|
Jul 01 07:27:32 PM PDT 24 |
Jul 01 07:32:37 PM PDT 24 |
3043719961 ps |
| T157 |
/workspace/coverage/default/0.chip_sw_sleep_pin_wake.3441995414 |
|
|
Jul 01 07:09:26 PM PDT 24 |
Jul 01 07:19:15 PM PDT 24 |
6748614920 ps |
| T402 |
/workspace/coverage/default/0.chip_sw_rv_core_ibex_lockstep_glitch.251234138 |
|
|
Jul 01 07:15:16 PM PDT 24 |
Jul 01 07:19:50 PM PDT 24 |
2707801120 ps |
| T849 |
/workspace/coverage/default/3.chip_sw_csrng_edn_concurrency.3163826801 |
|
|
Jul 01 07:36:45 PM PDT 24 |
Jul 01 08:45:29 PM PDT 24 |
20119426188 ps |
| T850 |
/workspace/coverage/default/1.chip_sw_sysrst_ctrl_ec_rst_l.4134274436 |
|
|
Jul 01 07:23:38 PM PDT 24 |
Jul 01 08:15:43 PM PDT 24 |
21078447415 ps |
| T851 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_dev.521699107 |
|
|
Jul 01 07:17:36 PM PDT 24 |
Jul 01 08:18:35 PM PDT 24 |
14400703192 ps |
| T852 |
/workspace/coverage/default/0.chip_sw_edn_kat.425640707 |
|
|
Jul 01 07:10:43 PM PDT 24 |
Jul 01 07:23:04 PM PDT 24 |
3885761756 ps |
| T853 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.32609885 |
|
|
Jul 01 07:21:44 PM PDT 24 |
Jul 01 08:16:36 PM PDT 24 |
15260639357 ps |
| T177 |
/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_wake_ups.2325977004 |
|
|
Jul 01 07:11:33 PM PDT 24 |
Jul 01 07:38:25 PM PDT 24 |
22227990444 ps |
| T454 |
/workspace/coverage/default/93.chip_sw_all_escalation_resets.3910843615 |
|
|
Jul 01 07:47:11 PM PDT 24 |
Jul 01 07:56:27 PM PDT 24 |
4863514880 ps |
| T854 |
/workspace/coverage/default/0.chip_sw_clkmgr_off_otbn_trans.2597274676 |
|
|
Jul 01 07:12:23 PM PDT 24 |
Jul 01 07:20:39 PM PDT 24 |
5403666034 ps |
| T515 |
/workspace/coverage/default/3.chip_sw_all_escalation_resets.4064409244 |
|
|
Jul 01 07:36:48 PM PDT 24 |
Jul 01 07:46:20 PM PDT 24 |
4406432740 ps |
| T855 |
/workspace/coverage/default/0.rom_e2e_asm_init_dev.711391204 |
|
|
Jul 01 07:18:50 PM PDT 24 |
Jul 01 08:32:14 PM PDT 24 |
15769310587 ps |
| T856 |
/workspace/coverage/default/5.chip_sw_data_integrity_escalation.3434544984 |
|
|
Jul 01 07:41:41 PM PDT 24 |
Jul 01 07:53:16 PM PDT 24 |
6749789152 ps |
| T857 |
/workspace/coverage/default/1.chip_sw_clkmgr_jitter.3147609912 |
|
|
Jul 01 07:26:59 PM PDT 24 |
Jul 01 07:32:34 PM PDT 24 |
2744362049 ps |
| T858 |
/workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.3625666564 |
|
|
Jul 01 07:35:27 PM PDT 24 |
Jul 01 08:03:35 PM PDT 24 |
18862710384 ps |
| T859 |
/workspace/coverage/default/2.chip_sw_rv_timer_smoketest.3711677562 |
|
|
Jul 01 07:36:48 PM PDT 24 |
Jul 01 07:40:55 PM PDT 24 |
2775007064 ps |
| T860 |
/workspace/coverage/default/0.chip_sw_alert_handler_ping_timeout.1720787083 |
|
|
Jul 01 07:11:37 PM PDT 24 |
Jul 01 07:19:48 PM PDT 24 |
5295666512 ps |
| T861 |
/workspace/coverage/default/1.chip_sw_clkmgr_off_peri.216173793 |
|
|
Jul 01 07:28:44 PM PDT 24 |
Jul 01 07:47:21 PM PDT 24 |
10546353608 ps |
| T862 |
/workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_scramble.2645187676 |
|
|
Jul 01 07:15:05 PM PDT 24 |
Jul 01 07:30:55 PM PDT 24 |
9050050732 ps |
| T863 |
/workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_no_scramble.1895040050 |
|
|
Jul 01 07:12:42 PM PDT 24 |
Jul 01 07:24:50 PM PDT 24 |
8755602066 ps |
| T864 |
/workspace/coverage/default/0.chip_sw_kmac_entropy.402384591 |
|
|
Jul 01 07:10:26 PM PDT 24 |
Jul 01 07:15:43 PM PDT 24 |
2527324514 ps |
| T865 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_lc_rw_en.756932184 |
|
|
Jul 01 07:10:13 PM PDT 24 |
Jul 01 07:19:53 PM PDT 24 |
4101299313 ps |
| T866 |
/workspace/coverage/default/0.chip_sw_uart_tx_rx_bootstrap.498451935 |
|
|
Jul 01 07:09:14 PM PDT 24 |
Jul 01 10:57:08 PM PDT 24 |
78336488345 ps |
| T867 |
/workspace/coverage/default/0.chip_sw_csrng_smoketest.3098615760 |
|
|
Jul 01 07:16:15 PM PDT 24 |
Jul 01 07:20:46 PM PDT 24 |
2758767072 ps |
| T484 |
/workspace/coverage/default/54.chip_sw_all_escalation_resets.982449172 |
|
|
Jul 01 07:44:56 PM PDT 24 |
Jul 01 07:54:23 PM PDT 24 |
6346145956 ps |
| T868 |
/workspace/coverage/default/1.chip_sw_aon_timer_sleep_wdog_sleep_pause.2338665903 |
|
|
Jul 01 07:22:54 PM PDT 24 |
Jul 01 07:33:42 PM PDT 24 |
6914734656 ps |
| T869 |
/workspace/coverage/default/2.chip_sw_sysrst_ctrl_outputs.1760394914 |
|
|
Jul 01 07:29:55 PM PDT 24 |
Jul 01 07:37:07 PM PDT 24 |
3887613800 ps |
| T242 |
/workspace/coverage/default/0.chip_sw_spi_device_pass_through.1780422253 |
|
|
Jul 01 07:11:48 PM PDT 24 |
Jul 01 07:23:30 PM PDT 24 |
6624489786 ps |
| T870 |
/workspace/coverage/default/2.chip_sw_aes_masking_off.3306158343 |
|
|
Jul 01 07:31:47 PM PDT 24 |
Jul 01 07:36:48 PM PDT 24 |
2874890026 ps |
| T178 |
/workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_wake_ups.3609298161 |
|
|
Jul 01 07:34:22 PM PDT 24 |
Jul 01 08:01:49 PM PDT 24 |
23818030024 ps |
| T871 |
/workspace/coverage/default/1.rom_e2e_static_critical.2805798703 |
|
|
Jul 01 07:38:14 PM PDT 24 |
Jul 01 08:55:27 PM PDT 24 |
17587248342 ps |
| T872 |
/workspace/coverage/default/0.chip_sw_hmac_enc_idle.3887051018 |
|
|
Jul 01 07:11:49 PM PDT 24 |
Jul 01 07:16:15 PM PDT 24 |
2490767766 ps |
| T873 |
/workspace/coverage/default/1.chip_sw_rv_plic_smoketest.1865400138 |
|
|
Jul 01 07:26:50 PM PDT 24 |
Jul 01 07:30:13 PM PDT 24 |
2926099772 ps |
| T483 |
/workspace/coverage/default/67.chip_sw_alert_handler_lpg_sleep_mode_alerts.4270398904 |
|
|
Jul 01 07:44:37 PM PDT 24 |
Jul 01 07:51:34 PM PDT 24 |
3903199966 ps |
| T874 |
/workspace/coverage/default/39.chip_sw_all_escalation_resets.3584721344 |
|
|
Jul 01 07:41:59 PM PDT 24 |
Jul 01 07:52:37 PM PDT 24 |
5524885780 ps |
| T516 |
/workspace/coverage/default/90.chip_sw_all_escalation_resets.2350969149 |
|
|
Jul 01 07:46:21 PM PDT 24 |
Jul 01 07:55:37 PM PDT 24 |
6042027764 ps |
| T875 |
/workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq.3149826791 |
|
|
Jul 01 07:38:08 PM PDT 24 |
Jul 01 08:01:16 PM PDT 24 |
8322203762 ps |
| T451 |
/workspace/coverage/default/95.chip_sw_all_escalation_resets.2165843734 |
|
|
Jul 01 07:46:13 PM PDT 24 |
Jul 01 07:55:35 PM PDT 24 |
5729575688 ps |
| T14 |
/workspace/coverage/default/1.chip_sw_sleep_pin_retention.2810262023 |
|
|
Jul 01 07:19:14 PM PDT 24 |
Jul 01 07:24:53 PM PDT 24 |
3213267688 ps |
| T876 |
/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_wake_5_bug.455484005 |
|
|
Jul 01 07:13:35 PM PDT 24 |
Jul 01 07:22:43 PM PDT 24 |
6795294324 ps |
| T877 |
/workspace/coverage/default/3.chip_sw_uart_tx_rx_idx3.966013129 |
|
|
Jul 01 07:38:20 PM PDT 24 |
Jul 01 07:49:09 PM PDT 24 |
3825880934 ps |
| T878 |
/workspace/coverage/default/2.chip_sw_pwrmgr_sleep_wake_5_bug.1820768527 |
|
|
Jul 01 07:33:24 PM PDT 24 |
Jul 01 07:40:29 PM PDT 24 |
6497163290 ps |
| T460 |
/workspace/coverage/default/66.chip_sw_alert_handler_lpg_sleep_mode_alerts.3541613321 |
|
|
Jul 01 07:45:29 PM PDT 24 |
Jul 01 07:51:32 PM PDT 24 |
3253124470 ps |
| T879 |
/workspace/coverage/default/5.chip_sw_csrng_edn_concurrency.3819045110 |
|
|
Jul 01 07:38:21 PM PDT 24 |
Jul 01 08:33:29 PM PDT 24 |
17067040090 ps |
| T880 |
/workspace/coverage/default/2.chip_sw_lc_ctrl_otp_hw_cfg0.85894740 |
|
|
Jul 01 07:27:27 PM PDT 24 |
Jul 01 07:33:45 PM PDT 24 |
3156880400 ps |
| T881 |
/workspace/coverage/default/38.chip_sw_all_escalation_resets.1212435861 |
|
|
Jul 01 07:41:43 PM PDT 24 |
Jul 01 07:52:25 PM PDT 24 |
5024187922 ps |
| T882 |
/workspace/coverage/default/2.chip_sw_uart_smoketest.2978307900 |
|
|
Jul 01 07:39:07 PM PDT 24 |
Jul 01 07:44:19 PM PDT 24 |
2766047064 ps |
| T883 |
/workspace/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.3217919304 |
|
|
Jul 01 07:15:49 PM PDT 24 |
Jul 01 07:20:09 PM PDT 24 |
2934255505 ps |
| T487 |
/workspace/coverage/default/17.chip_sw_alert_handler_lpg_sleep_mode_alerts.2885851172 |
|
|
Jul 01 07:43:01 PM PDT 24 |
Jul 01 07:49:48 PM PDT 24 |
3606799600 ps |
| T884 |
/workspace/coverage/default/0.chip_sw_otbn_smoketest.3300490426 |
|
|
Jul 01 07:19:35 PM PDT 24 |
Jul 01 07:58:00 PM PDT 24 |
10449180020 ps |
| T461 |
/workspace/coverage/default/29.chip_sw_all_escalation_resets.1561179782 |
|
|
Jul 01 07:43:18 PM PDT 24 |
Jul 01 07:53:11 PM PDT 24 |
5600489908 ps |
| T885 |
/workspace/coverage/default/2.chip_sw_hmac_enc_jitter_en.1218491051 |
|
|
Jul 01 07:33:29 PM PDT 24 |
Jul 01 07:37:41 PM PDT 24 |
3390817697 ps |
| T382 |
/workspace/coverage/default/2.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.2748404947 |
|
|
Jul 01 07:34:31 PM PDT 24 |
Jul 01 07:39:55 PM PDT 24 |
6289373100 ps |
| T886 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en.2375349817 |
|
|
Jul 01 07:11:37 PM PDT 24 |
Jul 01 07:24:10 PM PDT 24 |
3551900888 ps |
| T887 |
/workspace/coverage/default/1.chip_sw_rstmgr_sw_rst.3287182877 |
|
|
Jul 01 07:20:33 PM PDT 24 |
Jul 01 07:24:10 PM PDT 24 |
2568543528 ps |
| T888 |
/workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en.350836254 |
|
|
Jul 01 07:10:14 PM PDT 24 |
Jul 01 07:23:01 PM PDT 24 |
5573665154 ps |
| T24 |
/workspace/coverage/default/1.chip_sw_sleep_pin_mio_dio_val.4284405972 |
|
|
Jul 01 07:16:53 PM PDT 24 |
Jul 01 07:22:36 PM PDT 24 |
3503331712 ps |
| T501 |
/workspace/coverage/default/82.chip_sw_all_escalation_resets.1573513146 |
|
|
Jul 01 07:44:11 PM PDT 24 |
Jul 01 07:51:24 PM PDT 24 |
5649270888 ps |
| T306 |
/workspace/coverage/default/1.chip_sw_data_integrity_escalation.2108571944 |
|
|
Jul 01 07:17:41 PM PDT 24 |
Jul 01 07:29:28 PM PDT 24 |
5657534504 ps |
| T889 |
/workspace/coverage/default/3.chip_tap_straps_prod.3942902933 |
|
|
Jul 01 07:36:17 PM PDT 24 |
Jul 01 07:44:56 PM PDT 24 |
6872734436 ps |
| T48 |
/workspace/coverage/default/0.chip_sw_spi_host_tx_rx.3683777178 |
|
|
Jul 01 07:09:32 PM PDT 24 |
Jul 01 07:14:07 PM PDT 24 |
2811062072 ps |
| T890 |
/workspace/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.492034456 |
|
|
Jul 01 07:21:52 PM PDT 24 |
Jul 01 07:23:45 PM PDT 24 |
2483189723 ps |
| T112 |
/workspace/coverage/default/1.chip_plic_all_irqs_10.3760915694 |
|
|
Jul 01 07:29:10 PM PDT 24 |
Jul 01 07:39:05 PM PDT 24 |
4221396200 ps |
| T156 |
/workspace/coverage/default/2.chip_sw_alert_test.410007132 |
|
|
Jul 01 07:30:30 PM PDT 24 |
Jul 01 07:36:40 PM PDT 24 |
3108872752 ps |
| T891 |
/workspace/coverage/default/11.chip_sw_lc_ctrl_transition.3427223864 |
|
|
Jul 01 07:39:15 PM PDT 24 |
Jul 01 08:00:32 PM PDT 24 |
10341014935 ps |
| T892 |
/workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_dev.1116245664 |
|
|
Jul 01 07:29:58 PM PDT 24 |
Jul 01 07:53:40 PM PDT 24 |
8800669012 ps |
| T893 |
/workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_por_reset.269040993 |
|
|
Jul 01 07:10:23 PM PDT 24 |
Jul 01 07:16:49 PM PDT 24 |
5138111722 ps |
| T894 |
/workspace/coverage/default/3.chip_sw_uart_tx_rx.1201211031 |
|
|
Jul 01 07:36:09 PM PDT 24 |
Jul 01 07:49:23 PM PDT 24 |
4689345096 ps |
| T895 |
/workspace/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.3019890922 |
|
|
Jul 01 07:28:55 PM PDT 24 |
Jul 01 07:30:43 PM PDT 24 |
2009142740 ps |
| T896 |
/workspace/coverage/default/2.chip_sw_pwrmgr_all_reset_reqs.1672689610 |
|
|
Jul 01 07:30:16 PM PDT 24 |
Jul 01 07:57:20 PM PDT 24 |
11567741167 ps |
| T897 |
/workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.2398866996 |
|
|
Jul 01 07:16:19 PM PDT 24 |
Jul 01 07:24:12 PM PDT 24 |
4837040496 ps |
| T15 |
/workspace/coverage/default/0.chip_sw_sleep_pin_retention.3048060187 |
|
|
Jul 01 07:09:55 PM PDT 24 |
Jul 01 07:16:09 PM PDT 24 |
3794276840 ps |
| T139 |
/workspace/coverage/default/2.chip_jtag_csr_rw.2684939953 |
|
|
Jul 01 07:26:06 PM PDT 24 |
Jul 01 07:40:29 PM PDT 24 |
8950699735 ps |
| T898 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.4042433546 |
|
|
Jul 01 07:17:08 PM PDT 24 |
Jul 01 08:06:56 PM PDT 24 |
10853866400 ps |
| T398 |
/workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.3943847204 |
|
|
Jul 01 07:12:38 PM PDT 24 |
Jul 01 07:21:54 PM PDT 24 |
5012222472 ps |
| T899 |
/workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_rma.195317121 |
|
|
Jul 01 07:28:15 PM PDT 24 |
Jul 01 07:50:47 PM PDT 24 |
6828826968 ps |
| T900 |
/workspace/coverage/default/3.chip_tap_straps_dev.2014501358 |
|
|
Jul 01 07:38:08 PM PDT 24 |
Jul 01 07:40:44 PM PDT 24 |
3285931155 ps |
| T901 |
/workspace/coverage/default/0.chip_sw_csrng_edn_concurrency.3377624760 |
|
|
Jul 01 07:09:51 PM PDT 24 |
Jul 01 08:50:55 PM PDT 24 |
20832633244 ps |
| T497 |
/workspace/coverage/default/55.chip_sw_all_escalation_resets.1306221516 |
|
|
Jul 01 07:42:34 PM PDT 24 |
Jul 01 07:53:08 PM PDT 24 |
5274861588 ps |
| T902 |
/workspace/coverage/default/2.chip_sw_aon_timer_smoketest.3471093510 |
|
|
Jul 01 07:39:15 PM PDT 24 |
Jul 01 07:46:04 PM PDT 24 |
2622570944 ps |
| T431 |
/workspace/coverage/default/52.chip_sw_alert_handler_lpg_sleep_mode_alerts.1151849861 |
|
|
Jul 01 07:45:05 PM PDT 24 |
Jul 01 07:51:38 PM PDT 24 |
3582680222 ps |
| T903 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en.2835616013 |
|
|
Jul 01 07:11:33 PM PDT 24 |
Jul 01 07:31:34 PM PDT 24 |
5978404915 ps |
| T904 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_clock_freqs.2045460226 |
|
|
Jul 01 07:27:19 PM PDT 24 |
Jul 01 07:49:29 PM PDT 24 |
5531734068 ps |
| T905 |
/workspace/coverage/default/14.chip_sw_alert_handler_lpg_sleep_mode_alerts.436469144 |
|
|
Jul 01 07:41:56 PM PDT 24 |
Jul 01 07:49:43 PM PDT 24 |
3835632992 ps |
| T906 |
/workspace/coverage/default/2.chip_sw_clkmgr_off_peri.1792606527 |
|
|
Jul 01 07:33:38 PM PDT 24 |
Jul 01 07:55:46 PM PDT 24 |
12469759194 ps |
| T907 |
/workspace/coverage/default/0.chip_sw_csrng_edn_concurrency_reduced_freq.384836347 |
|
|
Jul 01 07:12:51 PM PDT 24 |
Jul 01 08:19:51 PM PDT 24 |
22836854235 ps |
| T908 |
/workspace/coverage/default/2.chip_sw_hmac_enc_jitter_en_reduced_freq.222883785 |
|
|
Jul 01 07:35:20 PM PDT 24 |
Jul 01 07:40:09 PM PDT 24 |
2738979221 ps |
| T909 |
/workspace/coverage/default/1.chip_sw_hmac_enc.2995418290 |
|
|
Jul 01 07:23:11 PM PDT 24 |
Jul 01 07:27:40 PM PDT 24 |
3135072470 ps |
| T910 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.4278296419 |
|
|
Jul 01 07:19:19 PM PDT 24 |
Jul 01 08:30:10 PM PDT 24 |
15677823500 ps |
| T911 |
/workspace/coverage/default/7.chip_sw_lc_ctrl_transition.1453199414 |
|
|
Jul 01 07:40:10 PM PDT 24 |
Jul 01 07:55:18 PM PDT 24 |
9324675354 ps |
| T365 |
/workspace/coverage/default/0.chip_sw_entropy_src_csrng.3337218761 |
|
|
Jul 01 07:13:07 PM PDT 24 |
Jul 01 07:32:41 PM PDT 24 |
6018089360 ps |
| T912 |
/workspace/coverage/default/2.chip_sw_edn_auto_mode.1397970709 |
|
|
Jul 01 07:32:16 PM PDT 24 |
Jul 01 07:53:37 PM PDT 24 |
3934127134 ps |
| T913 |
/workspace/coverage/default/1.chip_sw_uart_smoketest.3511972145 |
|
|
Jul 01 07:25:58 PM PDT 24 |
Jul 01 07:29:02 PM PDT 24 |
2724520734 ps |
| T227 |
/workspace/coverage/default/2.chip_sw_i2c_host_tx_rx_idx2.1896082802 |
|
|
Jul 01 07:28:21 PM PDT 24 |
Jul 01 07:41:04 PM PDT 24 |
4575828430 ps |
| T914 |
/workspace/coverage/default/2.chip_sw_rstmgr_smoketest.1095778196 |
|
|
Jul 01 07:36:06 PM PDT 24 |
Jul 01 07:39:23 PM PDT 24 |
2376659420 ps |
| T455 |
/workspace/coverage/default/5.chip_sw_alert_handler_lpg_sleep_mode_alerts.1512985943 |
|
|
Jul 01 07:42:14 PM PDT 24 |
Jul 01 07:48:10 PM PDT 24 |
3505679248 ps |
| T412 |
/workspace/coverage/default/1.chip_sw_edn_boot_mode.642766478 |
|
|
Jul 01 07:23:05 PM PDT 24 |
Jul 01 07:36:26 PM PDT 24 |
3382161802 ps |
| T915 |
/workspace/coverage/default/84.chip_sw_alert_handler_lpg_sleep_mode_alerts.42231970 |
|
|
Jul 01 07:45:18 PM PDT 24 |
Jul 01 07:51:25 PM PDT 24 |
4150380400 ps |
| T448 |
/workspace/coverage/default/31.chip_sw_alert_handler_lpg_sleep_mode_alerts.2753054620 |
|
|
Jul 01 07:42:40 PM PDT 24 |
Jul 01 07:47:58 PM PDT 24 |
3449806932 ps |
| T331 |
/workspace/coverage/default/2.chip_sw_rv_core_ibex_icache_invalidate.1946658470 |
|
|
Jul 01 07:38:09 PM PDT 24 |
Jul 01 07:42:16 PM PDT 24 |
2765741404 ps |
| T916 |
/workspace/coverage/default/0.chip_sw_lc_ctrl_test_locked0_to_scrap.1544009291 |
|
|
Jul 01 07:09:11 PM PDT 24 |
Jul 01 07:11:48 PM PDT 24 |
3363813699 ps |
| T489 |
/workspace/coverage/default/44.chip_sw_all_escalation_resets.2872910719 |
|
|
Jul 01 07:42:56 PM PDT 24 |
Jul 01 07:50:11 PM PDT 24 |
4439432912 ps |
| T243 |
/workspace/coverage/default/1.chip_sw_spi_device_pass_through.3591905013 |
|
|
Jul 01 07:18:11 PM PDT 24 |
Jul 01 07:31:34 PM PDT 24 |
7303751874 ps |
| T917 |
/workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_no_meas.2469476073 |
|
|
Jul 01 07:44:04 PM PDT 24 |
Jul 01 08:45:32 PM PDT 24 |
14698809460 ps |
| T918 |
/workspace/coverage/default/1.chip_sw_exit_test_unlocked_bootstrap.2250525959 |
|
|
Jul 01 07:18:57 PM PDT 24 |
Jul 01 10:15:12 PM PDT 24 |
58755261744 ps |
| T919 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_mem_protection.2083430813 |
|
|
Jul 01 07:27:24 PM PDT 24 |
Jul 01 07:51:25 PM PDT 24 |
6237747118 ps |
| T491 |
/workspace/coverage/default/10.chip_sw_all_escalation_resets.1552767456 |
|
|
Jul 01 07:39:52 PM PDT 24 |
Jul 01 07:47:41 PM PDT 24 |
4393315670 ps |
| T253 |
/workspace/coverage/default/1.chip_sw_lc_walkthrough_prod.2824436830 |
|
|
Jul 01 07:14:54 PM PDT 24 |
Jul 01 08:41:31 PM PDT 24 |
48546130571 ps |
| T920 |
/workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.3638541241 |
|
|
Jul 01 07:22:38 PM PDT 24 |
Jul 01 07:48:58 PM PDT 24 |
13486947038 ps |
| T921 |
/workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_scramble.1462398913 |
|
|
Jul 01 07:33:31 PM PDT 24 |
Jul 01 07:43:58 PM PDT 24 |
7691827164 ps |
| T922 |
/workspace/coverage/default/2.chip_sw_aes_enc_jitter_en_reduced_freq.1383048040 |
|
|
Jul 01 07:38:37 PM PDT 24 |
Jul 01 07:44:06 PM PDT 24 |
3084930871 ps |
| T923 |
/workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access.4082239231 |
|
|
Jul 01 07:27:27 PM PDT 24 |
Jul 01 07:38:32 PM PDT 24 |
5326532616 ps |
| T520 |
/workspace/coverage/default/75.chip_sw_alert_handler_lpg_sleep_mode_alerts.2188975323 |
|
|
Jul 01 07:45:31 PM PDT 24 |
Jul 01 07:52:01 PM PDT 24 |
3545039742 ps |
| T924 |
/workspace/coverage/default/89.chip_sw_alert_handler_lpg_sleep_mode_alerts.727205693 |
|
|
Jul 01 07:46:20 PM PDT 24 |
Jul 01 07:51:52 PM PDT 24 |
3791324368 ps |
| T452 |
/workspace/coverage/default/82.chip_sw_alert_handler_lpg_sleep_mode_alerts.757379170 |
|
|
Jul 01 07:45:03 PM PDT 24 |
Jul 01 07:50:49 PM PDT 24 |
3865941660 ps |
| T98 |
/workspace/coverage/default/0.chip_tap_straps_rma.40093658 |
|
|
Jul 01 07:13:37 PM PDT 24 |
Jul 01 07:19:50 PM PDT 24 |
3747297881 ps |
| T925 |
/workspace/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en.75697247 |
|
|
Jul 01 07:31:54 PM PDT 24 |
Jul 01 08:01:23 PM PDT 24 |
12105766582 ps |
| T926 |
/workspace/coverage/default/3.chip_sw_uart_tx_rx_idx2.3871088814 |
|
|
Jul 01 07:36:52 PM PDT 24 |
Jul 01 07:48:39 PM PDT 24 |
4222496440 ps |
| T927 |
/workspace/coverage/default/3.chip_sw_aon_timer_sleep_wdog_sleep_pause.2429981567 |
|
|
Jul 01 07:37:03 PM PDT 24 |
Jul 01 07:43:32 PM PDT 24 |
6604511580 ps |
| T928 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en.3510025894 |
|
|
Jul 01 07:28:17 PM PDT 24 |
Jul 01 07:45:49 PM PDT 24 |
5870926997 ps |
| T929 |
/workspace/coverage/default/16.chip_sw_all_escalation_resets.175837343 |
|
|
Jul 01 07:42:48 PM PDT 24 |
Jul 01 07:52:59 PM PDT 24 |
6031887700 ps |
| T469 |
/workspace/coverage/default/36.chip_sw_all_escalation_resets.3759781906 |
|
|
Jul 01 07:42:28 PM PDT 24 |
Jul 01 07:56:06 PM PDT 24 |
5012188968 ps |
| T930 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.119170339 |
|
|
Jul 01 07:19:30 PM PDT 24 |
Jul 01 08:48:28 PM PDT 24 |
22853863366 ps |
| T931 |
/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_por_reset.2767196885 |
|
|
Jul 01 07:13:38 PM PDT 24 |
Jul 01 07:24:05 PM PDT 24 |
7353530200 ps |
| T932 |
/workspace/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.2628984905 |
|
|
Jul 01 07:14:05 PM PDT 24 |
Jul 01 07:38:30 PM PDT 24 |
10072453911 ps |
| T99 |
/workspace/coverage/default/4.chip_tap_straps_testunlock0.1657224088 |
|
|
Jul 01 07:40:22 PM PDT 24 |
Jul 01 07:48:49 PM PDT 24 |
4674654489 ps |
| T933 |
/workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.1461021281 |
|
|
Jul 01 07:30:34 PM PDT 24 |
Jul 01 07:39:23 PM PDT 24 |
5450427056 ps |
| T934 |
/workspace/coverage/default/1.chip_sw_example_rom.2416652611 |
|
|
Jul 01 07:15:41 PM PDT 24 |
Jul 01 07:17:33 PM PDT 24 |
2408279712 ps |
| T275 |
/workspace/coverage/default/2.chip_sw_plic_sw_irq.87427173 |
|
|
Jul 01 07:35:18 PM PDT 24 |
Jul 01 07:39:12 PM PDT 24 |
2950734950 ps |
| T935 |
/workspace/coverage/default/0.chip_sw_hmac_smoketest.203783647 |
|
|
Jul 01 07:13:33 PM PDT 24 |
Jul 01 07:19:32 PM PDT 24 |
3749887572 ps |
| T936 |
/workspace/coverage/default/27.chip_sw_alert_handler_lpg_sleep_mode_alerts.2910280664 |
|
|
Jul 01 07:41:56 PM PDT 24 |
Jul 01 07:48:10 PM PDT 24 |
3526542180 ps |
| T937 |
/workspace/coverage/default/1.chip_sw_uart_tx_rx_idx3.3598333455 |
|
|
Jul 01 07:19:01 PM PDT 24 |
Jul 01 07:30:18 PM PDT 24 |
4563233800 ps |
| T345 |
/workspace/coverage/default/38.chip_sw_alert_handler_lpg_sleep_mode_alerts.1544604255 |
|
|
Jul 01 07:42:44 PM PDT 24 |
Jul 01 07:48:53 PM PDT 24 |
3370508740 ps |
| T938 |
/workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.1657844133 |
|
|
Jul 01 07:34:54 PM PDT 24 |
Jul 01 08:49:31 PM PDT 24 |
24492206928 ps |
| T939 |
/workspace/coverage/default/2.chip_sw_clkmgr_off_hmac_trans.3708309712 |
|
|
Jul 01 07:33:30 PM PDT 24 |
Jul 01 07:41:52 PM PDT 24 |
5080872440 ps |
| T940 |
/workspace/coverage/default/33.chip_sw_alert_handler_lpg_sleep_mode_alerts.3291213377 |
|
|
Jul 01 07:41:41 PM PDT 24 |
Jul 01 07:49:24 PM PDT 24 |
3874148280 ps |
| T941 |
/workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_test_unlocked0.921846265 |
|
|
Jul 01 07:18:34 PM PDT 24 |
Jul 01 07:31:45 PM PDT 24 |
4349749692 ps |
| T942 |
/workspace/coverage/default/4.chip_tap_straps_rma.2122719836 |
|
|
Jul 01 07:37:46 PM PDT 24 |
Jul 01 07:42:37 PM PDT 24 |
3765792216 ps |
| T943 |
/workspace/coverage/default/2.chip_sw_hmac_enc_idle.1122006718 |
|
|
Jul 01 07:32:02 PM PDT 24 |
Jul 01 07:36:57 PM PDT 24 |
3227849156 ps |
| T498 |
/workspace/coverage/default/58.chip_sw_all_escalation_resets.956320535 |
|
|
Jul 01 07:43:10 PM PDT 24 |
Jul 01 07:54:10 PM PDT 24 |
5743895702 ps |
| T944 |
/workspace/coverage/default/2.chip_sw_pwrmgr_b2b_sleep_reset_req.2019978773 |
|
|
Jul 01 07:35:24 PM PDT 24 |
Jul 01 08:15:47 PM PDT 24 |
30674505586 ps |
| T945 |
/workspace/coverage/default/1.chip_sw_uart_tx_rx_idx1.2653990074 |
|
|
Jul 01 07:17:25 PM PDT 24 |
Jul 01 07:29:48 PM PDT 24 |
3856989620 ps |
| T946 |
/workspace/coverage/default/2.chip_sw_aes_smoketest.1429639939 |
|
|
Jul 01 07:37:11 PM PDT 24 |
Jul 01 07:41:13 PM PDT 24 |
2273334520 ps |
| T947 |
/workspace/coverage/default/0.chip_sw_lc_walkthrough_rma.32532972 |
|
|
Jul 01 07:13:22 PM PDT 24 |
Jul 01 08:45:27 PM PDT 24 |
45327633900 ps |
| T948 |
/workspace/coverage/default/34.chip_sw_alert_handler_lpg_sleep_mode_alerts.2782833230 |
|
|
Jul 01 07:41:10 PM PDT 24 |
Jul 01 07:47:24 PM PDT 24 |
3763861352 ps |
| T949 |
/workspace/coverage/default/0.chip_sw_rv_timer_irq.3179973220 |
|
|
Jul 01 07:13:12 PM PDT 24 |
Jul 01 07:16:42 PM PDT 24 |
2653859128 ps |
| T383 |
/workspace/coverage/default/1.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.1269601973 |
|
|
Jul 01 07:28:50 PM PDT 24 |
Jul 01 07:36:44 PM PDT 24 |
6042361368 ps |
| T950 |
/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx1.1478291057 |
|
|
Jul 01 07:37:22 PM PDT 24 |
Jul 01 07:50:01 PM PDT 24 |
5152034268 ps |
| T226 |
/workspace/coverage/default/1.chip_sw_i2c_host_tx_rx_idx1.1749406991 |
|
|
Jul 01 07:19:18 PM PDT 24 |
Jul 01 07:35:05 PM PDT 24 |
4871356140 ps |
| T951 |
/workspace/coverage/default/1.chip_sw_rv_timer_smoketest.1614674131 |
|
|
Jul 01 07:26:36 PM PDT 24 |
Jul 01 07:30:37 PM PDT 24 |
2935040888 ps |
| T952 |
/workspace/coverage/default/2.chip_sw_lc_walkthrough_prod.3618340613 |
|
|
Jul 01 07:29:27 PM PDT 24 |
Jul 01 09:07:10 PM PDT 24 |
49806066948 ps |
| T953 |
/workspace/coverage/default/0.chip_sw_uart_rand_baudrate.1486405846 |
|
|
Jul 01 07:10:33 PM PDT 24 |
Jul 01 07:18:37 PM PDT 24 |
4131925056 ps |
| T954 |
/workspace/coverage/default/1.chip_tap_straps_dev.2242319174 |
|
|
Jul 01 07:23:20 PM PDT 24 |
Jul 01 07:35:12 PM PDT 24 |
5761137073 ps |
| T955 |
/workspace/coverage/default/2.chip_sw_rstmgr_sw_req.1733412014 |
|
|
Jul 01 07:29:26 PM PDT 24 |
Jul 01 07:38:28 PM PDT 24 |
3929697840 ps |
| T956 |
/workspace/coverage/default/1.chip_sw_kmac_mode_cshake.4005657610 |
|
|
Jul 01 07:23:10 PM PDT 24 |
Jul 01 07:27:28 PM PDT 24 |
3011806962 ps |
| T957 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.3822321954 |
|
|
Jul 01 07:18:20 PM PDT 24 |
Jul 01 08:24:08 PM PDT 24 |
15782092440 ps |
| T958 |
/workspace/coverage/default/1.chip_sw_pwrmgr_sleep_power_glitch_reset.1474340903 |
|
|
Jul 01 07:19:38 PM PDT 24 |
Jul 01 07:26:41 PM PDT 24 |
6704980182 ps |
| T959 |
/workspace/coverage/default/0.chip_sw_entropy_src_ast_rng_req.1238260467 |
|
|
Jul 01 07:12:59 PM PDT 24 |
Jul 01 07:17:56 PM PDT 24 |
3237386144 ps |
| T960 |
/workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en.1735694501 |
|
|
Jul 01 07:33:16 PM PDT 24 |
Jul 01 07:43:32 PM PDT 24 |
5639972492 ps |
| T961 |
/workspace/coverage/default/2.chip_sw_alert_handler_lpg_reset_toggle.2604986035 |
|
|
Jul 01 07:30:11 PM PDT 24 |
Jul 01 07:58:19 PM PDT 24 |
8220336820 ps |
| T962 |
/workspace/coverage/default/1.chip_sw_flash_scrambling_smoketest.1517081692 |
|
|
Jul 01 07:30:42 PM PDT 24 |
Jul 01 07:34:11 PM PDT 24 |
2942790152 ps |
| T963 |
/workspace/coverage/default/2.chip_sw_sysrst_ctrl_in_irq.346453200 |
|
|
Jul 01 07:28:39 PM PDT 24 |
Jul 01 07:40:00 PM PDT 24 |
5294673176 ps |
| T964 |
/workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en.1819947216 |
|
|
Jul 01 07:29:01 PM PDT 24 |
Jul 01 07:41:58 PM PDT 24 |
4510176087 ps |
| T965 |
/workspace/coverage/default/1.chip_sw_aon_timer_wdog_lc_escalate.3673143381 |
|
|
Jul 01 07:23:05 PM PDT 24 |
Jul 01 07:38:13 PM PDT 24 |
5882848520 ps |
| T228 |
/workspace/coverage/default/1.chip_sw_i2c_device_tx_rx.3371740345 |
|
|
Jul 01 07:15:41 PM PDT 24 |
Jul 01 07:24:54 PM PDT 24 |
4109953640 ps |
| T966 |
/workspace/coverage/default/61.chip_sw_alert_handler_lpg_sleep_mode_alerts.1631505497 |
|
|
Jul 01 07:43:14 PM PDT 24 |
Jul 01 07:48:50 PM PDT 24 |
3117017260 ps |
| T967 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0.2390881918 |
|
|
Jul 01 07:16:05 PM PDT 24 |
Jul 01 08:03:58 PM PDT 24 |
11282871884 ps |
| T968 |
/workspace/coverage/default/73.chip_sw_alert_handler_lpg_sleep_mode_alerts.2456833305 |
|
|
Jul 01 07:45:22 PM PDT 24 |
Jul 01 07:51:03 PM PDT 24 |
3844210306 ps |
| T969 |
/workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.2485684029 |
|
|
Jul 01 07:19:41 PM PDT 24 |
Jul 01 07:27:30 PM PDT 24 |
7492533600 ps |
| T970 |
/workspace/coverage/default/1.chip_sw_kmac_smoketest.2036331708 |
|
|
Jul 01 07:26:25 PM PDT 24 |
Jul 01 07:31:03 PM PDT 24 |
3100624640 ps |
| T971 |
/workspace/coverage/default/10.chip_sw_uart_rand_baudrate.3512130350 |
|
|
Jul 01 07:38:18 PM PDT 24 |
Jul 01 07:49:10 PM PDT 24 |
4415827864 ps |
| T972 |
/workspace/coverage/default/1.chip_sw_lc_ctrl_transition.109141630 |
|
|
Jul 01 07:19:07 PM PDT 24 |
Jul 01 07:27:05 PM PDT 24 |
5022724031 ps |
| T113 |
/workspace/coverage/default/2.chip_plic_all_irqs_10.495370928 |
|
|
Jul 01 07:32:21 PM PDT 24 |
Jul 01 07:41:23 PM PDT 24 |
4178157368 ps |
| T973 |
/workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.2447185901 |
|
|
Jul 01 07:29:10 PM PDT 24 |
Jul 01 07:59:40 PM PDT 24 |
13154090420 ps |
| T974 |
/workspace/coverage/default/2.chip_sw_kmac_smoketest.180411935 |
|
|
Jul 01 07:36:24 PM PDT 24 |
Jul 01 07:43:30 PM PDT 24 |
3566111984 ps |
| T366 |
/workspace/coverage/default/2.chip_sw_entropy_src_csrng.3758001421 |
|
|
Jul 01 07:31:36 PM PDT 24 |
Jul 01 07:53:41 PM PDT 24 |
5987303392 ps |
| T975 |
/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx3.3340758018 |
|
|
Jul 01 07:40:14 PM PDT 24 |
Jul 01 07:52:24 PM PDT 24 |
4253997130 ps |
| T976 |
/workspace/coverage/default/4.chip_sw_lc_ctrl_transition.4088008408 |
|
|
Jul 01 07:37:58 PM PDT 24 |
Jul 01 07:49:46 PM PDT 24 |
11298877848 ps |
| T977 |
/workspace/coverage/default/0.chip_sw_aon_timer_sleep_wdog_sleep_pause.2329887674 |
|
|
Jul 01 07:12:21 PM PDT 24 |
Jul 01 07:23:00 PM PDT 24 |
8019915564 ps |
| T978 |
/workspace/coverage/default/0.chip_sw_kmac_idle.2094997065 |
|
|
Jul 01 07:12:43 PM PDT 24 |
Jul 01 07:16:49 PM PDT 24 |
3207557290 ps |
| T979 |
/workspace/coverage/default/2.chip_sw_i2c_device_tx_rx.3855732517 |
|
|
Jul 01 07:28:38 PM PDT 24 |
Jul 01 07:41:27 PM PDT 24 |
4303848264 ps |
| T518 |
/workspace/coverage/default/24.chip_sw_all_escalation_resets.2989379142 |
|
|
Jul 01 07:44:07 PM PDT 24 |
Jul 01 07:56:15 PM PDT 24 |
5708719100 ps |
| T980 |
/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.3423283143 |
|
|
Jul 01 07:12:28 PM PDT 24 |
Jul 01 07:22:31 PM PDT 24 |
3593517386 ps |
| T981 |
/workspace/coverage/default/0.chip_sw_flash_init_reduced_freq.1671403714 |
|
|
Jul 01 07:10:34 PM PDT 24 |
Jul 01 07:42:21 PM PDT 24 |
22363154733 ps |
| T982 |
/workspace/coverage/default/1.chip_sw_rstmgr_rst_cnsty_escalation.3878578957 |
|
|
Jul 01 07:15:53 PM PDT 24 |
Jul 01 07:24:10 PM PDT 24 |
5042727494 ps |
| T983 |
/workspace/coverage/default/0.chip_sival_flash_info_access.1077120143 |
|
|
Jul 01 07:11:18 PM PDT 24 |
Jul 01 07:19:34 PM PDT 24 |
3766522984 ps |
| T229 |
/workspace/coverage/default/1.chip_sw_i2c_host_tx_rx_idx2.4093247135 |
|
|
Jul 01 07:18:37 PM PDT 24 |
Jul 01 07:32:16 PM PDT 24 |
4678100600 ps |
| T984 |
/workspace/coverage/default/14.chip_sw_uart_rand_baudrate.3983517306 |
|
|
Jul 01 07:39:59 PM PDT 24 |
Jul 01 08:19:59 PM PDT 24 |
13039815442 ps |
| T503 |
/workspace/coverage/default/9.chip_sw_all_escalation_resets.3610958375 |
|
|
Jul 01 07:38:36 PM PDT 24 |
Jul 01 07:48:55 PM PDT 24 |
5983663400 ps |
| T985 |
/workspace/coverage/default/2.chip_sw_hmac_smoketest.1810493493 |
|
|
Jul 01 07:36:06 PM PDT 24 |
Jul 01 07:44:19 PM PDT 24 |
3904650520 ps |
| T986 |
/workspace/coverage/default/0.rom_e2e_static_critical.3331853612 |
|
|
Jul 01 07:20:47 PM PDT 24 |
Jul 01 08:23:52 PM PDT 24 |
17506640172 ps |
| T987 |
/workspace/coverage/default/1.chip_sw_inject_scramble_seed.2240276139 |
|
|
Jul 01 07:16:49 PM PDT 24 |
Jul 01 10:33:22 PM PDT 24 |
64455147294 ps |
| T418 |
/workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_wake_ups.601586788 |
|
|
Jul 01 07:35:39 PM PDT 24 |
Jul 01 08:01:11 PM PDT 24 |
21596024128 ps |
| T327 |
/workspace/coverage/default/13.chip_sw_all_escalation_resets.2700936666 |
|
|
Jul 01 07:41:08 PM PDT 24 |
Jul 01 07:50:51 PM PDT 24 |
5675778440 ps |
| T11 |
/workspace/coverage/default/0.chip_jtag_csr_rw.1534097013 |
|
|
Jul 01 07:04:15 PM PDT 24 |
Jul 01 07:43:11 PM PDT 24 |
22265892631 ps |
| T369 |
/workspace/coverage/default/1.chip_sw_pwrmgr_lowpower_cancel.1078129802 |
|
|
Jul 01 07:25:32 PM PDT 24 |
Jul 01 07:33:24 PM PDT 24 |
4017129660 ps |
| T988 |
/workspace/coverage/default/0.chip_sw_inject_scramble_seed.3524898090 |
|
|
Jul 01 07:09:30 PM PDT 24 |
Jul 01 10:36:38 PM PDT 24 |
65062621438 ps |
| T989 |
/workspace/coverage/default/2.chip_sw_csrng_lc_hw_debug_en_test.501959451 |
|
|
Jul 01 07:31:24 PM PDT 24 |
Jul 01 07:45:41 PM PDT 24 |
5888949192 ps |
| T990 |
/workspace/coverage/default/0.chip_sw_example_concurrency.3714603604 |
|
|
Jul 01 07:10:42 PM PDT 24 |
Jul 01 07:15:36 PM PDT 24 |
3089952950 ps |
| T991 |
/workspace/coverage/default/0.chip_sw_sleep_pwm_pulses.890870279 |
|
|
Jul 01 07:09:36 PM PDT 24 |
Jul 01 07:31:57 PM PDT 24 |
8284718808 ps |
| T992 |
/workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.2621740641 |
|
|
Jul 01 07:30:29 PM PDT 24 |
Jul 01 07:53:12 PM PDT 24 |
13260901162 ps |
| T492 |
/workspace/coverage/default/15.chip_sw_all_escalation_resets.2071649586 |
|
|
Jul 01 07:39:54 PM PDT 24 |
Jul 01 07:49:55 PM PDT 24 |
6204302368 ps |
| T993 |
/workspace/coverage/default/1.chip_sw_clkmgr_off_hmac_trans.734162550 |
|
|
Jul 01 07:25:28 PM PDT 24 |
Jul 01 07:33:41 PM PDT 24 |
5497183952 ps |
| T994 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.762253976 |
|
|
Jul 01 07:16:17 PM PDT 24 |
Jul 01 08:09:41 PM PDT 24 |
14457823888 ps |
| T94 |
/workspace/coverage/default/1.chip_sw_sensor_ctrl_alert.3491878981 |
|
|
Jul 01 07:27:09 PM PDT 24 |
Jul 01 07:37:33 PM PDT 24 |
5913301572 ps |
| T995 |
/workspace/coverage/default/0.chip_sw_all_escalation_resets.1215307592 |
|
|
Jul 01 07:09:11 PM PDT 24 |
Jul 01 07:21:08 PM PDT 24 |
5506165768 ps |
| T12 |
/workspace/coverage/default/2.chip_sw_sleep_pin_wake.1822408016 |
|
|
Jul 01 07:27:07 PM PDT 24 |
Jul 01 07:35:08 PM PDT 24 |
6747073160 ps |
| T996 |
/workspace/coverage/default/0.chip_sw_kmac_smoketest.3550383122 |
|
|
Jul 01 07:12:05 PM PDT 24 |
Jul 01 07:15:59 PM PDT 24 |
3603627964 ps |
| T997 |
/workspace/coverage/default/0.chip_sw_clkmgr_off_hmac_trans.239945420 |
|
|
Jul 01 07:11:25 PM PDT 24 |
Jul 01 07:18:15 PM PDT 24 |
3993837096 ps |
| T998 |
/workspace/coverage/default/19.chip_sw_uart_rand_baudrate.1281762051 |
|
|
Jul 01 07:40:33 PM PDT 24 |
Jul 01 08:15:42 PM PDT 24 |
12942998436 ps |
| T999 |
/workspace/coverage/default/1.chip_sw_csrng_edn_concurrency.284134190 |
|
|
Jul 01 07:23:06 PM PDT 24 |
Jul 01 09:08:29 PM PDT 24 |
26459144260 ps |
| T1000 |
/workspace/coverage/default/0.chip_sw_gpio_smoketest.1856203982 |
|
|
Jul 01 07:14:33 PM PDT 24 |
Jul 01 07:18:59 PM PDT 24 |
2601780844 ps |
| T1001 |
/workspace/coverage/default/91.chip_sw_all_escalation_resets.2677946522 |
|
|
Jul 01 07:46:49 PM PDT 24 |
Jul 01 07:55:32 PM PDT 24 |
4880795042 ps |
| T1002 |
/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.1494894621 |
|
|
Jul 01 07:35:04 PM PDT 24 |
Jul 01 07:47:33 PM PDT 24 |
4304665160 ps |
| T336 |
/workspace/coverage/default/2.chip_sw_keymgr_sideload_aes.3461867760 |
|
|
Jul 01 07:31:09 PM PDT 24 |
Jul 01 08:02:25 PM PDT 24 |
11258194760 ps |
| T1003 |
/workspace/coverage/default/86.chip_sw_all_escalation_resets.4028088932 |
|
|
Jul 01 07:45:16 PM PDT 24 |
Jul 01 07:54:30 PM PDT 24 |
5796849740 ps |
| T1004 |
/workspace/coverage/default/2.rom_e2e_shutdown_exception_c.309521025 |
|
|
Jul 01 07:41:09 PM PDT 24 |
Jul 01 08:38:20 PM PDT 24 |
15118835002 ps |
| T1005 |
/workspace/coverage/default/77.chip_sw_all_escalation_resets.1003142903 |
|
|
Jul 01 07:45:30 PM PDT 24 |
Jul 01 07:56:21 PM PDT 24 |
4874697828 ps |
| T1006 |
/workspace/coverage/default/2.chip_sw_clkmgr_jitter_frequency.44659984 |
|
|
Jul 01 07:33:06 PM PDT 24 |
Jul 01 07:42:15 PM PDT 24 |
3382935150 ps |
| T337 |
/workspace/coverage/default/0.chip_sw_keymgr_sideload_aes.3786989391 |
|
|
Jul 01 07:17:17 PM PDT 24 |
Jul 01 07:42:05 PM PDT 24 |
7745892512 ps |
| T42 |
/workspace/coverage/pad_ctrl_test_mode/2.chip_padctrl_attributes.4066699694 |
|
|
Jul 01 07:02:01 PM PDT 24 |
Jul 01 07:06:12 PM PDT 24 |
5632063673 ps |
| T43 |
/workspace/coverage/pad_ctrl_test_mode/3.chip_padctrl_attributes.3000455513 |
|
|
Jul 01 07:02:01 PM PDT 24 |
Jul 01 07:06:47 PM PDT 24 |
4892281112 ps |
| T44 |
/workspace/coverage/pad_ctrl_test_mode/7.chip_padctrl_attributes.1346772604 |
|
|
Jul 01 07:02:09 PM PDT 24 |
Jul 01 07:07:54 PM PDT 24 |
4687356600 ps |
| T47 |
/workspace/coverage/pad_ctrl_test_mode/4.chip_padctrl_attributes.818009604 |
|
|
Jul 01 07:02:02 PM PDT 24 |
Jul 01 07:06:05 PM PDT 24 |
4245575041 ps |