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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.10 95.45 93.86 95.43 94.82 97.53 99.55


Total test records in report: 2900
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T371 /workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.2515831512 Jul 02 11:26:47 AM PDT 24 Jul 02 12:01:58 PM PDT 24 13425092728 ps
T372 /workspace/coverage/default/84.chip_sw_all_escalation_resets.3706617465 Jul 02 11:37:13 AM PDT 24 Jul 02 11:47:52 AM PDT 24 5880208960 ps
T249 /workspace/coverage/default/0.chip_sw_plic_sw_irq.815744195 Jul 02 11:00:02 AM PDT 24 Jul 02 11:04:22 AM PDT 24 2745218494 ps
T954 /workspace/coverage/default/0.chip_sw_clkmgr_jitter_reduced_freq.4144833877 Jul 02 11:02:11 AM PDT 24 Jul 02 11:04:56 AM PDT 24 2697361488 ps
T346 /workspace/coverage/default/0.chip_sw_pattgen_ios.616743225 Jul 02 10:59:55 AM PDT 24 Jul 02 11:04:07 AM PDT 24 2915874652 ps
T86 /workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_pings.4090180772 Jul 02 10:59:20 AM PDT 24 Jul 02 11:19:19 AM PDT 24 11004063360 ps
T955 /workspace/coverage/default/0.rom_e2e_smoke.4035501882 Jul 02 11:10:01 AM PDT 24 Jul 02 12:15:08 PM PDT 24 15821996968 ps
T309 /workspace/coverage/default/62.chip_sw_all_escalation_resets.2613136232 Jul 02 11:32:59 AM PDT 24 Jul 02 11:41:26 AM PDT 24 4496261856 ps
T205 /workspace/coverage/default/0.chip_sw_sysrst_ctrl_in_irq.176723019 Jul 02 11:00:15 AM PDT 24 Jul 02 11:11:40 AM PDT 24 4361323039 ps
T956 /workspace/coverage/default/1.chip_sw_clkmgr_sleep_frequency.1524223647 Jul 02 11:11:45 AM PDT 24 Jul 02 11:25:36 AM PDT 24 4672881844 ps
T957 /workspace/coverage/default/1.chip_sw_rv_timer_irq.1717844028 Jul 02 11:06:07 AM PDT 24 Jul 02 11:09:47 AM PDT 24 3140235270 ps
T327 /workspace/coverage/default/2.chip_sw_i2c_host_tx_rx_idx2.1170338625 Jul 02 11:15:21 AM PDT 24 Jul 02 11:26:52 AM PDT 24 4095345434 ps
T958 /workspace/coverage/default/1.chip_sw_aes_masking_off.1952793726 Jul 02 11:08:27 AM PDT 24 Jul 02 11:14:34 AM PDT 24 3233171127 ps
T218 /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_prod.2912543884 Jul 02 10:58:08 AM PDT 24 Jul 02 11:19:35 AM PDT 24 8763887744 ps
T840 /workspace/coverage/default/34.chip_sw_all_escalation_resets.46615461 Jul 02 11:31:06 AM PDT 24 Jul 02 11:40:19 AM PDT 24 6173206126 ps
T3 /workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_wake_ups.3282369115 Jul 02 11:14:36 AM PDT 24 Jul 02 11:45:02 AM PDT 24 23307915460 ps
T959 /workspace/coverage/default/6.chip_sw_csrng_edn_concurrency.928373696 Jul 02 11:28:19 AM PDT 24 Jul 02 12:19:30 PM PDT 24 14951803228 ps
T725 /workspace/coverage/default/0.chip_sw_sleep_pwm_pulses.81576871 Jul 02 11:02:42 AM PDT 24 Jul 02 11:29:51 AM PDT 24 9215932936 ps
T222 /workspace/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en.1683251933 Jul 02 11:01:14 AM PDT 24 Jul 02 11:22:57 AM PDT 24 6752668547 ps
T161 /workspace/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.2937059555 Jul 02 10:57:36 AM PDT 24 Jul 02 10:59:25 AM PDT 24 2101071171 ps
T960 /workspace/coverage/default/0.chip_sw_flash_ctrl_clock_freqs.685962215 Jul 02 10:59:08 AM PDT 24 Jul 02 11:21:44 AM PDT 24 6101730662 ps
T447 /workspace/coverage/default/1.chip_sw_alert_handler_ping_timeout.1834093580 Jul 02 11:07:04 AM PDT 24 Jul 02 11:16:36 AM PDT 24 4620755310 ps
T961 /workspace/coverage/default/1.chip_sw_hmac_enc_jitter_en.795027848 Jul 02 11:09:12 AM PDT 24 Jul 02 11:13:22 AM PDT 24 3388691835 ps
T962 /workspace/coverage/default/0.chip_sw_entropy_src_kat_test.933270598 Jul 02 10:59:08 AM PDT 24 Jul 02 11:02:59 AM PDT 24 2828831032 ps
T963 /workspace/coverage/default/1.chip_sw_aon_timer_wdog_bite_reset.430774186 Jul 02 11:08:15 AM PDT 24 Jul 02 11:24:26 AM PDT 24 8868487900 ps
T964 /workspace/coverage/default/1.chip_sw_aes_enc_jitter_en_reduced_freq.1258572833 Jul 02 11:14:25 AM PDT 24 Jul 02 11:19:13 AM PDT 24 2828121509 ps
T270 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_dev.4178298542 Jul 02 11:07:41 AM PDT 24 Jul 02 12:13:07 PM PDT 24 13981977888 ps
T833 /workspace/coverage/default/87.chip_sw_alert_handler_lpg_sleep_mode_alerts.1334351947 Jul 02 11:37:13 AM PDT 24 Jul 02 11:44:27 AM PDT 24 4458544264 ps
T965 /workspace/coverage/default/1.chip_sw_csrng_smoketest.2403604060 Jul 02 11:13:51 AM PDT 24 Jul 02 11:19:42 AM PDT 24 2863789912 ps
T326 /workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq.705254903 Jul 02 11:16:48 AM PDT 24 Jul 02 11:27:51 AM PDT 24 4739541736 ps
T33 /workspace/coverage/default/0.chip_sw_sysrst_ctrl_reset.1691574066 Jul 02 11:00:09 AM PDT 24 Jul 02 11:36:50 AM PDT 24 24155893914 ps
T966 /workspace/coverage/default/15.chip_sw_alert_handler_lpg_sleep_mode_alerts.2042308079 Jul 02 11:30:05 AM PDT 24 Jul 02 11:37:32 AM PDT 24 4545933892 ps
T967 /workspace/coverage/default/9.chip_sw_uart_rand_baudrate.1006128054 Jul 02 11:28:17 AM PDT 24 Jul 02 11:36:49 AM PDT 24 4406892700 ps
T968 /workspace/coverage/default/0.chip_sw_uart_smoketest.2625133177 Jul 02 11:04:53 AM PDT 24 Jul 02 11:09:06 AM PDT 24 2701167440 ps
T87 /workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_pings.3121884808 Jul 02 11:09:11 AM PDT 24 Jul 02 11:29:16 AM PDT 24 12314564012 ps
T255 /workspace/coverage/default/0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.4198158485 Jul 02 11:01:21 AM PDT 24 Jul 02 11:08:14 AM PDT 24 4142336148 ps
T969 /workspace/coverage/default/0.chip_sw_clkmgr_off_hmac_trans.2234442459 Jul 02 11:02:49 AM PDT 24 Jul 02 11:10:07 AM PDT 24 4782138840 ps
T970 /workspace/coverage/default/0.chip_sw_hmac_enc.618212025 Jul 02 10:59:49 AM PDT 24 Jul 02 11:04:56 AM PDT 24 2407702784 ps
T971 /workspace/coverage/default/0.chip_sw_alert_handler_escalation.291201129 Jul 02 11:01:30 AM PDT 24 Jul 02 11:09:02 AM PDT 24 5178883032 ps
T250 /workspace/coverage/default/2.chip_sw_plic_sw_irq.708385417 Jul 02 11:20:01 AM PDT 24 Jul 02 11:24:48 AM PDT 24 2706346968 ps
T281 /workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en.3344577025 Jul 02 11:20:54 AM PDT 24 Jul 02 11:32:41 AM PDT 24 5112983102 ps
T66 /workspace/coverage/default/2.chip_tap_straps_testunlock0.3352212382 Jul 02 11:22:21 AM PDT 24 Jul 02 11:26:16 AM PDT 24 3538127524 ps
T122 /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.968897475 Jul 02 11:00:45 AM PDT 24 Jul 02 11:07:55 AM PDT 24 5701710340 ps
T972 /workspace/coverage/default/0.chip_sw_kmac_mode_cshake.50529799 Jul 02 11:02:23 AM PDT 24 Jul 02 11:07:06 AM PDT 24 3289515522 ps
T740 /workspace/coverage/default/10.chip_sw_alert_handler_lpg_sleep_mode_alerts.2317455675 Jul 02 11:29:38 AM PDT 24 Jul 02 11:35:36 AM PDT 24 4270809160 ps
T973 /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_por_reset.2968956012 Jul 02 10:58:56 AM PDT 24 Jul 02 11:11:01 AM PDT 24 9630986242 ps
T282 /workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access.3011468106 Jul 02 11:20:15 AM PDT 24 Jul 02 11:30:20 AM PDT 24 4001744044 ps
T774 /workspace/coverage/default/66.chip_sw_alert_handler_lpg_sleep_mode_alerts.342204015 Jul 02 11:36:50 AM PDT 24 Jul 02 11:44:00 AM PDT 24 4230479392 ps
T974 /workspace/coverage/default/1.rom_e2e_asm_init_prod.3882949843 Jul 02 11:17:47 AM PDT 24 Jul 02 12:21:49 PM PDT 24 15517362025 ps
T975 /workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_meas.3673033675 Jul 02 11:18:45 AM PDT 24 Jul 02 12:10:58 PM PDT 24 15048111992 ps
T976 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_prod.3473424129 Jul 02 11:11:03 AM PDT 24 Jul 02 12:20:19 PM PDT 24 14901788024 ps
T762 /workspace/coverage/default/14.chip_sw_alert_handler_lpg_sleep_mode_alerts.2871842132 Jul 02 11:29:24 AM PDT 24 Jul 02 11:36:27 AM PDT 24 3813277200 ps
T340 /workspace/coverage/default/1.chip_sw_pwrmgr_lowpower_cancel.3050473931 Jul 02 11:12:42 AM PDT 24 Jul 02 11:20:56 AM PDT 24 4052467710 ps
T788 /workspace/coverage/default/80.chip_sw_alert_handler_lpg_sleep_mode_alerts.1382744739 Jul 02 11:35:09 AM PDT 24 Jul 02 11:40:59 AM PDT 24 3915391932 ps
T321 /workspace/coverage/default/1.chip_sw_i2c_host_tx_rx_idx2.3165001554 Jul 02 11:04:11 AM PDT 24 Jul 02 11:18:28 AM PDT 24 4174706212 ps
T977 /workspace/coverage/default/0.chip_sw_pwrmgr_usb_clk_disabled_when_active.1175157739 Jul 02 10:59:30 AM PDT 24 Jul 02 11:08:20 AM PDT 24 4142370792 ps
T978 /workspace/coverage/default/2.chip_sw_uart_rand_baudrate.368561614 Jul 02 11:16:25 AM PDT 24 Jul 02 12:00:31 PM PDT 24 13244739474 ps
T979 /workspace/coverage/default/1.rom_e2e_static_critical.499814848 Jul 02 11:18:29 AM PDT 24 Jul 02 12:23:02 PM PDT 24 17613460832 ps
T449 /workspace/coverage/default/1.chip_sw_edn_entropy_reqs_jitter.870279786 Jul 02 11:08:32 AM PDT 24 Jul 02 11:23:22 AM PDT 24 5633214855 ps
T980 /workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_power_glitch_reset.3575828972 Jul 02 11:08:02 AM PDT 24 Jul 02 12:05:18 PM PDT 24 36082911527 ps
T981 /workspace/coverage/default/0.rom_e2e_shutdown_exception_c.1963497874 Jul 02 11:08:36 AM PDT 24 Jul 02 12:07:57 PM PDT 24 14440485440 ps
T982 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.1737766192 Jul 02 11:25:08 AM PDT 24 Jul 02 11:36:16 AM PDT 24 5027538712 ps
T838 /workspace/coverage/default/64.chip_sw_all_escalation_resets.252654121 Jul 02 11:33:38 AM PDT 24 Jul 02 11:44:12 AM PDT 24 4512290326 ps
T983 /workspace/coverage/default/2.chip_sw_example_manufacturer.776803678 Jul 02 11:15:17 AM PDT 24 Jul 02 11:19:53 AM PDT 24 2623480078 ps
T984 /workspace/coverage/default/2.chip_sw_entropy_src_kat_test.2889777700 Jul 02 11:19:31 AM PDT 24 Jul 02 11:23:12 AM PDT 24 2245185192 ps
T791 /workspace/coverage/default/77.chip_sw_alert_handler_lpg_sleep_mode_alerts.1352639104 Jul 02 11:34:09 AM PDT 24 Jul 02 11:42:04 AM PDT 24 3239120160 ps
T256 /workspace/coverage/default/2.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.264954353 Jul 02 11:22:22 AM PDT 24 Jul 02 11:31:24 AM PDT 24 4798427928 ps
T985 /workspace/coverage/default/2.chip_sw_power_sleep_load.306673065 Jul 02 11:23:27 AM PDT 24 Jul 02 11:31:46 AM PDT 24 10133906850 ps
T986 /workspace/coverage/default/1.chip_sw_hmac_multistream.2876681593 Jul 02 11:11:30 AM PDT 24 Jul 02 11:43:51 AM PDT 24 7469756228 ps
T750 /workspace/coverage/default/29.chip_sw_all_escalation_resets.2603133278 Jul 02 11:31:03 AM PDT 24 Jul 02 11:41:41 AM PDT 24 5781318752 ps
T987 /workspace/coverage/default/1.chip_sw_otp_ctrl_smoketest.983524901 Jul 02 11:14:43 AM PDT 24 Jul 02 11:20:01 AM PDT 24 2587003152 ps
T743 /workspace/coverage/default/24.chip_sw_alert_handler_lpg_sleep_mode_alerts.1774111559 Jul 02 11:30:23 AM PDT 24 Jul 02 11:35:55 AM PDT 24 4225134658 ps
T162 /workspace/coverage/default/1.chip_sw_lc_walkthrough_testunlocks.1679090876 Jul 02 11:06:13 AM PDT 24 Jul 02 11:44:24 AM PDT 24 25189619723 ps
T988 /workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access.328157036 Jul 02 11:10:41 AM PDT 24 Jul 02 11:22:49 AM PDT 24 5417431940 ps
T989 /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.1855182111 Jul 02 11:11:18 AM PDT 24 Jul 02 11:23:20 AM PDT 24 4717715208 ps
T990 /workspace/coverage/default/2.chip_sw_alert_handler_ping_timeout.2202269453 Jul 02 11:19:10 AM PDT 24 Jul 02 11:27:38 AM PDT 24 4359217760 ps
T738 /workspace/coverage/default/25.chip_sw_all_escalation_resets.1074713342 Jul 02 11:31:00 AM PDT 24 Jul 02 11:42:06 AM PDT 24 5337153650 ps
T221 /workspace/coverage/default/2.chip_sw_keymgr_sideload_kmac.1284084404 Jul 02 11:20:45 AM PDT 24 Jul 02 12:00:09 PM PDT 24 11115550200 ps
T166 /workspace/coverage/default/0.chip_sw_lc_walkthrough_testunlocks.3120678465 Jul 02 11:00:57 AM PDT 24 Jul 02 11:35:42 AM PDT 24 26038592952 ps
T61 /workspace/coverage/default/0.chip_sw_alert_test.1811914973 Jul 02 11:01:19 AM PDT 24 Jul 02 11:07:42 AM PDT 24 2706368206 ps
T991 /workspace/coverage/default/3.chip_sw_lc_ctrl_transition.1635515022 Jul 02 11:25:21 AM PDT 24 Jul 02 11:34:43 AM PDT 24 6514083259 ps
T206 /workspace/coverage/default/1.chip_sw_sysrst_ctrl_outputs.722726595 Jul 02 11:06:01 AM PDT 24 Jul 02 11:12:39 AM PDT 24 3886465762 ps
T342 /workspace/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en.3740932557 Jul 02 11:15:44 AM PDT 24 Jul 02 11:26:34 AM PDT 24 3698411258 ps
T357 /workspace/coverage/default/2.chip_sw_flash_ctrl_idle_low_power.703223282 Jul 02 11:16:37 AM PDT 24 Jul 02 11:23:15 AM PDT 24 2870553614 ps
T320 /workspace/coverage/default/2.chip_sw_i2c_host_tx_rx_idx1.3426236679 Jul 02 11:15:48 AM PDT 24 Jul 02 11:27:51 AM PDT 24 5093007418 ps
T362 /workspace/coverage/default/1.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.3433652161 Jul 02 11:11:01 AM PDT 24 Jul 02 11:20:47 AM PDT 24 5814532944 ps
T992 /workspace/coverage/default/2.rom_e2e_static_critical.2550487033 Jul 02 11:30:24 AM PDT 24 Jul 02 12:46:51 PM PDT 24 16984480360 ps
T993 /workspace/coverage/default/1.chip_sw_aes_smoketest.1271481427 Jul 02 11:15:02 AM PDT 24 Jul 02 11:20:23 AM PDT 24 2425226810 ps
T994 /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_prod.1890142122 Jul 02 11:05:46 AM PDT 24 Jul 02 11:26:54 AM PDT 24 8017271800 ps
T995 /workspace/coverage/default/7.chip_sw_csrng_edn_concurrency.1704173434 Jul 02 11:27:14 AM PDT 24 Jul 02 12:24:17 PM PDT 24 16447176716 ps
T996 /workspace/coverage/default/0.chip_sw_flash_ctrl_write_clear.3513302519 Jul 02 11:00:26 AM PDT 24 Jul 02 11:05:49 AM PDT 24 3144731384 ps
T997 /workspace/coverage/default/0.chip_sw_clkmgr_sleep_frequency.935761726 Jul 02 11:02:00 AM PDT 24 Jul 02 11:13:21 AM PDT 24 5351214500 ps
T998 /workspace/coverage/default/0.chip_sw_clkmgr_reset_frequency.1320531976 Jul 02 11:00:58 AM PDT 24 Jul 02 11:09:33 AM PDT 24 3612005070 ps
T355 /workspace/coverage/default/75.chip_sw_all_escalation_resets.4114459315 Jul 02 11:36:25 AM PDT 24 Jul 02 11:45:35 AM PDT 24 4336975460 ps
T999 /workspace/coverage/default/0.chip_sw_csrng_kat_test.4035682910 Jul 02 11:00:59 AM PDT 24 Jul 02 11:04:48 AM PDT 24 2209806340 ps
T841 /workspace/coverage/default/11.chip_sw_all_escalation_resets.3723981503 Jul 02 11:28:26 AM PDT 24 Jul 02 11:36:48 AM PDT 24 4470587144 ps
T1000 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.1130999801 Jul 02 10:59:26 AM PDT 24 Jul 02 11:09:36 AM PDT 24 4165632270 ps
T804 /workspace/coverage/default/37.chip_sw_all_escalation_resets.3270207307 Jul 02 11:31:59 AM PDT 24 Jul 02 11:41:47 AM PDT 24 6406233740 ps
T828 /workspace/coverage/default/69.chip_sw_all_escalation_resets.3039451531 Jul 02 11:34:06 AM PDT 24 Jul 02 11:43:34 AM PDT 24 5427266216 ps
T1001 /workspace/coverage/default/2.chip_sw_clkmgr_off_kmac_trans.2107288302 Jul 02 11:25:26 AM PDT 24 Jul 02 11:33:44 AM PDT 24 4718135344 ps
T1002 /workspace/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en.2022894198 Jul 02 11:02:21 AM PDT 24 Jul 02 11:21:57 AM PDT 24 6074117718 ps
T313 /workspace/coverage/default/2.chip_plic_all_irqs_20.3977578846 Jul 02 11:20:21 AM PDT 24 Jul 02 11:31:31 AM PDT 24 4079575456 ps
T1003 /workspace/coverage/default/0.chip_sw_csrng_fuse_en_sw_app_read_test.810846828 Jul 02 10:59:08 AM PDT 24 Jul 02 11:07:54 AM PDT 24 5125729300 ps
T1004 /workspace/coverage/default/0.chip_sw_pwrmgr_wdog_reset.4237654127 Jul 02 11:00:53 AM PDT 24 Jul 02 11:10:40 AM PDT 24 5190212124 ps
T1005 /workspace/coverage/default/1.chip_sw_csrng_fuse_en_sw_app_read_test.2044065395 Jul 02 11:09:37 AM PDT 24 Jul 02 11:19:56 AM PDT 24 4493938000 ps
T825 /workspace/coverage/default/15.chip_sw_all_escalation_resets.4008204433 Jul 02 11:28:53 AM PDT 24 Jul 02 11:41:12 AM PDT 24 4207586580 ps
T1006 /workspace/coverage/default/1.chip_sw_rstmgr_sw_req.3742658724 Jul 02 11:06:25 AM PDT 24 Jul 02 11:13:17 AM PDT 24 3416077850 ps
T358 /workspace/coverage/default/1.chip_sw_flash_ctrl_idle_low_power.3866604648 Jul 02 11:04:52 AM PDT 24 Jul 02 11:12:07 AM PDT 24 3721396010 ps
T1007 /workspace/coverage/default/1.chip_sw_kmac_mode_cshake.3072844568 Jul 02 11:10:33 AM PDT 24 Jul 02 11:15:51 AM PDT 24 3159986054 ps
T1008 /workspace/coverage/default/1.chip_sw_hmac_oneshot.3592064269 Jul 02 11:10:09 AM PDT 24 Jul 02 11:15:56 AM PDT 24 3301581308 ps
T352 /workspace/coverage/default/0.chip_sival_flash_info_access.1393789854 Jul 02 10:59:33 AM PDT 24 Jul 02 11:03:52 AM PDT 24 3156184204 ps
T842 /workspace/coverage/default/83.chip_sw_all_escalation_resets.1857281120 Jul 02 11:34:34 AM PDT 24 Jul 02 11:46:51 AM PDT 24 5670216844 ps
T403 /workspace/coverage/default/1.chip_sw_kmac_app_rom.282651095 Jul 02 11:10:17 AM PDT 24 Jul 02 11:14:24 AM PDT 24 2500631304 ps
T812 /workspace/coverage/default/23.chip_sw_alert_handler_lpg_sleep_mode_alerts.1348079314 Jul 02 11:30:36 AM PDT 24 Jul 02 11:36:12 AM PDT 24 3233301576 ps
T824 /workspace/coverage/default/68.chip_sw_alert_handler_lpg_sleep_mode_alerts.1363014910 Jul 02 11:36:55 AM PDT 24 Jul 02 11:42:54 AM PDT 24 3223633808 ps
T1009 /workspace/coverage/default/2.chip_sw_rv_core_ibex_rnd.330796783 Jul 02 11:17:58 AM PDT 24 Jul 02 11:35:07 AM PDT 24 5868549920 ps
T359 /workspace/coverage/default/1.chip_sw_aon_timer_irq.3778996081 Jul 02 11:06:59 AM PDT 24 Jul 02 11:13:51 AM PDT 24 3929155430 ps
T332 /workspace/coverage/default/0.chip_sw_i2c_device_tx_rx.2348186433 Jul 02 11:03:09 AM PDT 24 Jul 02 11:13:17 AM PDT 24 4235955280 ps
T343 /workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en.1877426680 Jul 02 11:04:06 AM PDT 24 Jul 02 11:15:51 AM PDT 24 4341315726 ps
T1010 /workspace/coverage/default/0.chip_sw_pwrmgr_main_power_glitch_reset.3325622477 Jul 02 11:00:41 AM PDT 24 Jul 02 11:06:55 AM PDT 24 3671091950 ps
T157 /workspace/coverage/default/2.chip_sw_otp_ctrl_vendor_test_csr_access.3339441253 Jul 02 11:15:55 AM PDT 24 Jul 02 11:18:30 AM PDT 24 1867649755 ps
T1011 /workspace/coverage/default/0.chip_sw_otp_ctrl_ecc_error_vendor_test.4203526517 Jul 02 10:58:53 AM PDT 24 Jul 02 11:03:53 AM PDT 24 2568701522 ps
T775 /workspace/coverage/default/11.chip_sw_alert_handler_lpg_sleep_mode_alerts.2255511649 Jul 02 11:28:39 AM PDT 24 Jul 02 11:34:46 AM PDT 24 3708934266 ps
T763 /workspace/coverage/default/76.chip_sw_all_escalation_resets.4072276050 Jul 02 11:35:31 AM PDT 24 Jul 02 11:44:31 AM PDT 24 5279608624 ps
T1012 /workspace/coverage/default/12.chip_sw_uart_rand_baudrate.2825134286 Jul 02 11:28:51 AM PDT 24 Jul 02 11:38:22 AM PDT 24 4322077448 ps
T334 /workspace/coverage/default/2.chip_sw_i2c_device_tx_rx.3563809205 Jul 02 11:15:25 AM PDT 24 Jul 02 11:26:03 AM PDT 24 3630043416 ps
T335 /workspace/coverage/default/1.chip_sw_i2c_device_tx_rx.1691318143 Jul 02 11:07:07 AM PDT 24 Jul 02 11:15:37 AM PDT 24 3740084316 ps
T1013 /workspace/coverage/default/0.rom_keymgr_functest.780241206 Jul 02 11:06:06 AM PDT 24 Jul 02 11:15:23 AM PDT 24 4155446140 ps
T1014 /workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_invalid_meas.567640770 Jul 02 11:18:30 AM PDT 24 Jul 02 12:25:25 PM PDT 24 14818598104 ps
T1015 /workspace/coverage/default/17.chip_sw_all_escalation_resets.812799678 Jul 02 11:29:42 AM PDT 24 Jul 02 11:39:24 AM PDT 24 5749495936 ps
T1016 /workspace/coverage/default/0.chip_sw_alert_handler_lpg_clkoff.2627567608 Jul 02 11:01:32 AM PDT 24 Jul 02 11:39:18 AM PDT 24 9165627528 ps
T1017 /workspace/coverage/default/0.chip_sw_pwrmgr_sysrst_ctrl_reset.2671357864 Jul 02 10:59:54 AM PDT 24 Jul 02 11:18:03 AM PDT 24 7868153436 ps
T1018 /workspace/coverage/default/1.chip_sw_edn_entropy_reqs.3044825789 Jul 02 11:09:21 AM PDT 24 Jul 02 11:29:30 AM PDT 24 5546221400 ps
T124 /workspace/coverage/default/2.chip_sw_sensor_ctrl_alert.2130254953 Jul 02 11:19:48 AM PDT 24 Jul 02 11:32:42 AM PDT 24 5487174804 ps
T167 /workspace/coverage/default/0.rom_e2e_shutdown_output.4280120523 Jul 02 11:06:38 AM PDT 24 Jul 02 12:00:16 PM PDT 24 22304045971 ps
T13 /workspace/coverage/default/1.chip_sw_sleep_pin_wake.1108282347 Jul 02 11:06:38 AM PDT 24 Jul 02 11:12:19 AM PDT 24 5087944356 ps
T1019 /workspace/coverage/default/0.chip_sw_clkmgr_off_peri.1992791362 Jul 02 11:03:47 AM PDT 24 Jul 02 11:30:43 AM PDT 24 11577031032 ps
T706 /workspace/coverage/default/1.chip_sw_rv_core_ibex_nmi_irq.2544605244 Jul 02 11:07:22 AM PDT 24 Jul 02 11:23:32 AM PDT 24 4904885976 ps
T1020 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0.2695052952 Jul 02 11:09:46 AM PDT 24 Jul 02 12:41:47 PM PDT 24 17989578998 ps
T1021 /workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_scramble.3779734488 Jul 02 11:23:11 AM PDT 24 Jul 02 11:33:23 AM PDT 24 7899554318 ps
T116 /workspace/coverage/default/2.chip_sw_edn_auto_mode.2280944505 Jul 02 11:21:26 AM PDT 24 Jul 02 11:45:23 AM PDT 24 5388083480 ps
T172 /workspace/coverage/default/2.chip_sw_lc_ctrl_program_error.1351796788 Jul 02 11:22:40 AM PDT 24 Jul 02 11:34:56 AM PDT 24 5440310608 ps
T1022 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_rma.3570967517 Jul 02 11:10:30 AM PDT 24 Jul 02 01:00:55 PM PDT 24 22279157356 ps
T363 /workspace/coverage/default/2.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.2946176004 Jul 02 11:22:31 AM PDT 24 Jul 02 11:29:57 AM PDT 24 5995346208 ps
T134 /workspace/coverage/default/1.chip_sw_pwrmgr_full_aon_reset.2024107640 Jul 02 11:05:56 AM PDT 24 Jul 02 11:15:36 AM PDT 24 7493627610 ps
T1023 /workspace/coverage/default/1.chip_sw_otp_ctrl_ecc_error_vendor_test.2380769438 Jul 02 11:05:38 AM PDT 24 Jul 02 11:09:41 AM PDT 24 2496997701 ps
T1024 /workspace/coverage/default/0.chip_sw_aes_entropy.2380534107 Jul 02 11:00:14 AM PDT 24 Jul 02 11:03:43 AM PDT 24 2406258976 ps
T797 /workspace/coverage/default/8.chip_sw_alert_handler_lpg_sleep_mode_alerts.1452681107 Jul 02 11:29:00 AM PDT 24 Jul 02 11:36:11 AM PDT 24 3142663328 ps
T180 /workspace/coverage/default/0.chip_sw_lc_ctrl_rma_to_scrap.4159837684 Jul 02 10:58:20 AM PDT 24 Jul 02 11:00:57 AM PDT 24 2244943740 ps
T1025 /workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_no_meas.3753165361 Jul 02 11:30:29 AM PDT 24 Jul 02 12:43:25 PM PDT 24 14723427216 ps
T1026 /workspace/coverage/default/2.chip_sw_alert_handler_ping_ok.4050259688 Jul 02 11:17:55 AM PDT 24 Jul 02 11:41:05 AM PDT 24 7510652440 ps
T345 /workspace/coverage/default/0.chip_sw_flash_ctrl_ops.787048448 Jul 02 10:59:26 AM PDT 24 Jul 02 11:10:46 AM PDT 24 3812075970 ps
T1027 /workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.3327751361 Jul 02 11:13:50 AM PDT 24 Jul 02 12:32:48 PM PDT 24 24337238734 ps
T261 /workspace/coverage/default/1.chip_sw_alert_handler_reverse_ping_in_deep_sleep.1815098694 Jul 02 11:09:53 AM PDT 24 Jul 02 02:43:53 PM PDT 24 254303398590 ps
T1028 /workspace/coverage/default/0.chip_sw_otp_ctrl_smoketest.2506215185 Jul 02 11:02:52 AM PDT 24 Jul 02 11:08:45 AM PDT 24 2902926952 ps
T223 /workspace/coverage/default/0.chip_sw_keymgr_sideload_otbn.3810756633 Jul 02 11:00:19 AM PDT 24 Jul 02 12:20:42 PM PDT 24 18628901360 ps
T1029 /workspace/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.555167166 Jul 02 11:01:33 AM PDT 24 Jul 02 11:07:38 AM PDT 24 3722542963 ps
T227 /workspace/coverage/default/1.chip_sw_flash_init.1028759182 Jul 02 11:04:25 AM PDT 24 Jul 02 11:35:12 AM PDT 24 23186360000 ps
T1030 /workspace/coverage/default/0.chip_sw_alert_handler_reverse_ping_in_deep_sleep.3231021695 Jul 02 11:00:13 AM PDT 24 Jul 02 02:45:04 PM PDT 24 254643107328 ps
T1031 /workspace/coverage/default/14.chip_sw_lc_ctrl_transition.3762699541 Jul 02 11:29:34 AM PDT 24 Jul 02 11:42:30 AM PDT 24 10289453385 ps
T770 /workspace/coverage/default/50.chip_sw_alert_handler_lpg_sleep_mode_alerts.3797847011 Jul 02 11:34:13 AM PDT 24 Jul 02 11:40:47 AM PDT 24 4012247136 ps
T140 /workspace/coverage/default/2.chip_sw_uart_tx_rx_idx2.1795756234 Jul 02 11:16:11 AM PDT 24 Jul 02 11:29:47 AM PDT 24 4862134424 ps
T1032 /workspace/coverage/default/2.chip_sw_power_idle_load.3303154680 Jul 02 11:23:32 AM PDT 24 Jul 02 11:35:39 AM PDT 24 4548511730 ps
T1033 /workspace/coverage/default/2.chip_sw_otp_ctrl_smoketest.817996765 Jul 02 11:27:09 AM PDT 24 Jul 02 11:32:29 AM PDT 24 2730751204 ps
T1034 /workspace/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en.1535355270 Jul 02 11:09:57 AM PDT 24 Jul 02 11:15:28 AM PDT 24 3365332244 ps
T1035 /workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en.2151469688 Jul 02 11:02:38 AM PDT 24 Jul 02 11:10:16 AM PDT 24 4118124991 ps
T1036 /workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_power_glitch_reset.2899675140 Jul 02 10:59:29 AM PDT 24 Jul 02 11:54:16 AM PDT 24 42918815940 ps
T48 /workspace/coverage/default/1.chip_sw_sysrst_ctrl_ulp_z3_wakeup.672494266 Jul 02 11:06:33 AM PDT 24 Jul 02 11:18:09 AM PDT 24 7049068592 ps
T314 /workspace/coverage/default/0.chip_plic_all_irqs_20.319601589 Jul 02 11:01:35 AM PDT 24 Jul 02 11:16:24 AM PDT 24 4980825170 ps
T1037 /workspace/coverage/default/2.chip_sw_uart_tx_rx_idx1.2696915447 Jul 02 11:15:16 AM PDT 24 Jul 02 11:26:38 AM PDT 24 4715464300 ps
T1038 /workspace/coverage/default/1.chip_sw_aon_timer_smoketest.1931307240 Jul 02 11:14:31 AM PDT 24 Jul 02 11:19:35 AM PDT 24 3223772902 ps
T1039 /workspace/coverage/default/2.chip_sw_edn_entropy_reqs.3212828410 Jul 02 11:20:14 AM PDT 24 Jul 02 11:44:02 AM PDT 24 6432066592 ps
T1040 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_dev.2683396390 Jul 02 11:08:38 AM PDT 24 Jul 02 12:52:44 PM PDT 24 23446412219 ps
T1041 /workspace/coverage/default/2.chip_sw_hmac_oneshot.4163600132 Jul 02 11:20:16 AM PDT 24 Jul 02 11:25:21 AM PDT 24 2912283930 ps
T219 /workspace/coverage/default/1.chip_sw_keymgr_sideload_aes.1086285705 Jul 02 11:10:00 AM PDT 24 Jul 02 11:39:20 AM PDT 24 9777857872 ps
T1042 /workspace/coverage/default/8.chip_sw_lc_ctrl_transition.383949591 Jul 02 11:27:15 AM PDT 24 Jul 02 11:41:38 AM PDT 24 8572870348 ps
T798 /workspace/coverage/default/60.chip_sw_all_escalation_resets.2761385799 Jul 02 11:33:19 AM PDT 24 Jul 02 11:43:47 AM PDT 24 4411553752 ps
T1043 /workspace/coverage/default/2.chip_sw_aes_idle.1739049427 Jul 02 11:20:54 AM PDT 24 Jul 02 11:24:29 AM PDT 24 3445118536 ps
T1044 /workspace/coverage/default/2.chip_sw_clkmgr_off_aes_trans.3893616611 Jul 02 11:21:21 AM PDT 24 Jul 02 11:31:00 AM PDT 24 4600343638 ps
T186 /workspace/coverage/default/0.chip_sw_rv_core_ibex_icache_invalidate.2354662762 Jul 02 11:00:16 AM PDT 24 Jul 02 11:03:42 AM PDT 24 2483862573 ps
T401 /workspace/coverage/default/1.chip_sw_pwrmgr_usbdev_smoketest.747290473 Jul 02 11:14:05 AM PDT 24 Jul 02 11:24:18 AM PDT 24 5109830958 ps
T1045 /workspace/coverage/default/0.chip_sw_uart_tx_rx_idx1.2371909589 Jul 02 10:57:31 AM PDT 24 Jul 02 11:07:58 AM PDT 24 4695220878 ps
T1046 /workspace/coverage/default/2.chip_sw_kmac_mode_kmac.851886235 Jul 02 11:20:25 AM PDT 24 Jul 02 11:25:31 AM PDT 24 3131166880 ps
T1047 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_prod_end.1865528585 Jul 02 11:09:46 AM PDT 24 Jul 02 01:08:15 PM PDT 24 23976329856 ps
T1048 /workspace/coverage/default/2.chip_sw_kmac_idle.165455886 Jul 02 11:21:06 AM PDT 24 Jul 02 11:25:02 AM PDT 24 2888973216 ps
T91 /workspace/coverage/default/41.chip_sw_alert_handler_lpg_sleep_mode_alerts.3828982612 Jul 02 11:33:34 AM PDT 24 Jul 02 11:39:33 AM PDT 24 3971938292 ps
T829 /workspace/coverage/default/79.chip_sw_all_escalation_resets.2938113844 Jul 02 11:35:45 AM PDT 24 Jul 02 11:49:19 AM PDT 24 5982928576 ps
T1049 /workspace/coverage/default/2.chip_sw_flash_crash_alert.1169049448 Jul 02 11:23:18 AM PDT 24 Jul 02 11:36:26 AM PDT 24 6288822424 ps
T1050 /workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.4108905676 Jul 02 11:06:03 AM PDT 24 Jul 02 11:31:35 AM PDT 24 13598657009 ps
T1051 /workspace/coverage/default/0.chip_sw_hmac_oneshot.669748052 Jul 02 11:01:01 AM PDT 24 Jul 02 11:06:40 AM PDT 24 3107182740 ps
T1052 /workspace/coverage/default/18.chip_sw_uart_rand_baudrate.2150502497 Jul 02 11:31:48 AM PDT 24 Jul 02 11:53:17 AM PDT 24 8766763610 ps
T1053 /workspace/coverage/default/2.chip_sw_example_concurrency.131435964 Jul 02 11:16:24 AM PDT 24 Jul 02 11:22:18 AM PDT 24 2903386232 ps
T1054 /workspace/coverage/default/0.chip_sw_kmac_mode_kmac.1770805042 Jul 02 11:01:30 AM PDT 24 Jul 02 11:07:58 AM PDT 24 3064866060 ps
T37 /workspace/coverage/default/0.chip_sw_gpio_smoketest.676357323 Jul 02 11:02:35 AM PDT 24 Jul 02 11:07:20 AM PDT 24 2685951024 ps
T1055 /workspace/coverage/default/1.chip_sw_example_flash.1142500390 Jul 02 11:06:38 AM PDT 24 Jul 02 11:12:06 AM PDT 24 2533794200 ps
T1056 /workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.118165593 Jul 02 10:59:16 AM PDT 24 Jul 02 11:25:09 AM PDT 24 11576189607 ps
T1057 /workspace/coverage/default/2.rom_e2e_asm_init_test_unlocked0.1526432417 Jul 02 11:32:09 AM PDT 24 Jul 02 12:14:19 PM PDT 24 11375949636 ps
T330 /workspace/coverage/default/14.chip_sw_uart_rand_baudrate.2667786957 Jul 02 11:28:49 AM PDT 24 Jul 02 12:04:21 PM PDT 24 13340666132 ps
T14 /workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_wake_ups.3151995310 Jul 02 11:01:12 AM PDT 24 Jul 02 11:30:04 AM PDT 24 21576060806 ps
T1058 /workspace/coverage/default/3.chip_sw_all_escalation_resets.1608945952 Jul 02 11:24:00 AM PDT 24 Jul 02 11:30:28 AM PDT 24 4427218272 ps
T1059 /workspace/coverage/default/0.chip_sw_rv_plic_smoketest.3289818850 Jul 02 11:03:57 AM PDT 24 Jul 02 11:08:59 AM PDT 24 2739216904 ps
T1060 /workspace/coverage/default/2.chip_sw_lc_ctrl_otp_hw_cfg0.287471967 Jul 02 11:16:08 AM PDT 24 Jul 02 11:21:31 AM PDT 24 2598095186 ps
T1061 /workspace/coverage/default/0.chip_sw_entropy_src_smoketest.1158655553 Jul 02 11:05:27 AM PDT 24 Jul 02 11:17:53 AM PDT 24 4372612620 ps
T207 /workspace/coverage/default/2.chip_sw_sysrst_ctrl_reset.595253364 Jul 02 11:18:04 AM PDT 24 Jul 02 11:50:55 AM PDT 24 23823409748 ps
T1062 /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.2637220591 Jul 02 10:58:30 AM PDT 24 Jul 02 11:04:11 AM PDT 24 6419114236 ps
T1063 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.2839404534 Jul 02 11:07:14 AM PDT 24 Jul 02 12:14:42 PM PDT 24 15721064526 ps
T156 /workspace/coverage/default/1.chip_sw_otp_ctrl_vendor_test_csr_access.4249535403 Jul 02 11:05:08 AM PDT 24 Jul 02 11:08:45 AM PDT 24 2895397703 ps
T1064 /workspace/coverage/default/12.chip_sw_lc_ctrl_transition.1999262055 Jul 02 11:28:19 AM PDT 24 Jul 02 11:36:38 AM PDT 24 4911787357 ps
T819 /workspace/coverage/default/56.chip_sw_alert_handler_lpg_sleep_mode_alerts.4123388994 Jul 02 11:35:27 AM PDT 24 Jul 02 11:42:00 AM PDT 24 3292454312 ps
T16 /workspace/coverage/default/0.chip_sw_sleep_pin_wake.1770332054 Jul 02 10:59:06 AM PDT 24 Jul 02 11:03:04 AM PDT 24 3376282510 ps
T428 /workspace/coverage/default/0.rom_e2e_jtag_inject_test_unlocked0.4102790063 Jul 02 11:05:50 AM PDT 24 Jul 02 11:46:17 AM PDT 24 25476714557 ps
T429 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.3408874533 Jul 02 10:59:37 AM PDT 24 Jul 02 11:10:40 AM PDT 24 5138739416 ps
T430 /workspace/coverage/default/0.chip_sw_csrng_smoketest.4160632301 Jul 02 11:02:45 AM PDT 24 Jul 02 11:07:39 AM PDT 24 2620831720 ps
T431 /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_power_glitch_reset.3497867204 Jul 02 11:06:36 AM PDT 24 Jul 02 11:14:59 AM PDT 24 6025058784 ps
T432 /workspace/coverage/default/84.chip_sw_alert_handler_lpg_sleep_mode_alerts.1128654810 Jul 02 11:35:13 AM PDT 24 Jul 02 11:42:50 AM PDT 24 3787380884 ps
T271 /workspace/coverage/default/0.chip_sw_data_integrity_escalation.439774011 Jul 02 10:58:47 AM PDT 24 Jul 02 11:10:27 AM PDT 24 5107382200 ps
T105 /workspace/coverage/default/1.chip_sw_csrng_edn_concurrency_reduced_freq.352707636 Jul 02 11:13:19 AM PDT 24 Jul 02 12:13:35 PM PDT 24 21937205167 ps
T272 /workspace/coverage/default/2.chip_sw_flash_ctrl_ops.3141818845 Jul 02 11:15:45 AM PDT 24 Jul 02 11:28:37 AM PDT 24 3815472500 ps
T273 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_dev.291922481 Jul 02 11:11:06 AM PDT 24 Jul 02 12:11:06 PM PDT 24 15702369376 ps
T208 /workspace/coverage/default/1.chip_sw_sysrst_ctrl_in_irq.681094921 Jul 02 11:06:42 AM PDT 24 Jul 02 11:16:14 AM PDT 24 5305599333 ps
T177 /workspace/coverage/default/2.chip_sw_lc_walkthrough_dev.4232717683 Jul 02 11:17:37 AM PDT 24 Jul 02 01:04:50 PM PDT 24 49982629760 ps
T274 /workspace/coverage/default/32.chip_sw_all_escalation_resets.1300831744 Jul 02 11:31:14 AM PDT 24 Jul 02 11:43:33 AM PDT 24 6432234096 ps
T275 /workspace/coverage/default/0.chip_sw_pwrmgr_b2b_sleep_reset_req.1731657532 Jul 02 10:59:25 AM PDT 24 Jul 02 11:35:31 AM PDT 24 26783230046 ps
T276 /workspace/coverage/default/0.chip_sw_aes_enc_jitter_en_reduced_freq.184793458 Jul 02 11:01:30 AM PDT 24 Jul 02 11:06:22 AM PDT 24 2963975025 ps
T277 /workspace/coverage/default/2.rom_keymgr_functest.3268207381 Jul 02 11:26:51 AM PDT 24 Jul 02 11:33:36 AM PDT 24 3784046900 ps
T1065 /workspace/coverage/default/2.chip_sw_keymgr_key_derivation.1816404767 Jul 02 11:21:10 AM PDT 24 Jul 02 12:05:10 PM PDT 24 12096696990 ps
T1066 /workspace/coverage/default/2.chip_sw_edn_sw_mode.2144456522 Jul 02 11:18:20 AM PDT 24 Jul 02 11:49:29 AM PDT 24 8304538020 ps
T34 /workspace/coverage/default/0.chip_sw_usbdev_dpi.2811999562 Jul 02 10:58:18 AM PDT 24 Jul 02 11:47:12 AM PDT 24 11772759352 ps
T1067 /workspace/coverage/default/2.chip_sw_otbn_smoketest.677717473 Jul 02 11:24:49 AM PDT 24 Jul 02 11:42:42 AM PDT 24 5559496824 ps
T1068 /workspace/coverage/default/1.chip_sw_alert_handler_lpg_clkoff.2557222021 Jul 02 11:08:56 AM PDT 24 Jul 02 11:28:17 AM PDT 24 5890363092 ps
T1069 /workspace/coverage/default/1.chip_sw_flash_scrambling_smoketest.1499610177 Jul 02 11:16:49 AM PDT 24 Jul 02 11:20:39 AM PDT 24 2471778752 ps
T1070 /workspace/coverage/default/2.chip_sw_csrng_kat_test.108259276 Jul 02 11:19:09 AM PDT 24 Jul 02 11:23:03 AM PDT 24 2262795000 ps
T1071 /workspace/coverage/default/2.chip_sw_aon_timer_smoketest.3697513413 Jul 02 11:24:02 AM PDT 24 Jul 02 11:28:59 AM PDT 24 2555517636 ps
T1072 /workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_no_meas.2396606473 Jul 02 11:17:49 AM PDT 24 Jul 02 12:14:29 PM PDT 24 14433686216 ps
T1073 /workspace/coverage/default/1.chip_sw_sleep_sram_ret_contents_scramble.1544922421 Jul 02 11:10:35 AM PDT 24 Jul 02 11:22:35 AM PDT 24 9101434934 ps
T323 /workspace/coverage/default/1.chip_sw_rstmgr_alert_info.826430579 Jul 02 11:06:12 AM PDT 24 Jul 02 11:31:25 AM PDT 24 12416335656 ps
T1074 /workspace/coverage/default/2.chip_sw_otp_ctrl_ecc_error_vendor_test.2312653515 Jul 02 11:16:51 AM PDT 24 Jul 02 11:22:21 AM PDT 24 2864585216 ps
T38 /workspace/coverage/default/1.chip_sw_gpio_smoketest.3835236932 Jul 02 11:13:15 AM PDT 24 Jul 02 11:17:52 AM PDT 24 2870857803 ps
T1075 /workspace/coverage/default/4.chip_sw_csrng_edn_concurrency.4140824247 Jul 02 11:27:28 AM PDT 24 Jul 02 12:34:20 PM PDT 24 16293115064 ps
T1076 /workspace/coverage/default/0.chip_sw_flash_ctrl_mem_protection.3303021243 Jul 02 11:02:28 AM PDT 24 Jul 02 11:25:46 AM PDT 24 5948535274 ps
T123 /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_wake_5_bug.1426366022 Jul 02 11:13:23 AM PDT 24 Jul 02 11:24:18 AM PDT 24 7051061892 ps
T808 /workspace/coverage/default/7.chip_sw_all_escalation_resets.2952445103 Jul 02 11:31:09 AM PDT 24 Jul 02 11:41:07 AM PDT 24 5122896352 ps
T1077 /workspace/coverage/default/3.chip_sw_csrng_edn_concurrency.2378648577 Jul 02 11:26:28 AM PDT 24 Jul 02 12:56:13 PM PDT 24 26527262000 ps
T1078 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_prod.619372580 Jul 02 11:10:25 AM PDT 24 Jul 02 01:10:01 PM PDT 24 23426462296 ps
T117 /workspace/coverage/default/1.chip_sw_edn_auto_mode.2440103227 Jul 02 11:07:52 AM PDT 24 Jul 02 11:30:11 AM PDT 24 4594009408 ps
T364 /workspace/coverage/default/0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.4200420473 Jul 02 11:03:12 AM PDT 24 Jul 02 11:11:44 AM PDT 24 6349434252 ps
T830 /workspace/coverage/default/61.chip_sw_alert_handler_lpg_sleep_mode_alerts.3910528473 Jul 02 11:34:09 AM PDT 24 Jul 02 11:39:59 AM PDT 24 3470113320 ps
T1079 /workspace/coverage/default/0.chip_sw_otp_ctrl_dai_lock.1886599696 Jul 02 10:58:20 AM PDT 24 Jul 02 12:36:27 PM PDT 24 27872036920 ps
T1080 /workspace/coverage/default/0.chip_sw_uart_tx_rx_idx2.1519938231 Jul 02 10:58:28 AM PDT 24 Jul 02 11:09:42 AM PDT 24 3996484120 ps
T741 /workspace/coverage/default/91.chip_sw_all_escalation_resets.2740070052 Jul 02 11:35:18 AM PDT 24 Jul 02 11:45:07 AM PDT 24 5519796982 ps
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