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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.10 95.45 93.86 95.43 94.82 97.53 99.55


Total test records in report: 2900
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T145 /workspace/coverage/default/0.chip_sw_exit_test_unlocked_bootstrap.3287748997 Jul 02 10:59:47 AM PDT 24 Jul 02 02:20:55 PM PDT 24 60539788446 ps
T336 /workspace/coverage/default/2.chip_sw_pwrmgr_lowpower_cancel.27931283 Jul 02 11:21:34 AM PDT 24 Jul 02 11:30:57 AM PDT 24 4684272650 ps
T1081 /workspace/coverage/default/0.chip_sw_ast_clk_outputs.622455756 Jul 02 11:01:59 AM PDT 24 Jul 02 11:20:05 AM PDT 24 7639241900 ps
T1082 /workspace/coverage/default/2.chip_sw_clkmgr_jitter.3339844741 Jul 02 11:21:39 AM PDT 24 Jul 02 11:25:24 AM PDT 24 2855427364 ps
T764 /workspace/coverage/default/3.chip_sw_alert_handler_lpg_sleep_mode_alerts.3861937805 Jul 02 11:27:24 AM PDT 24 Jul 02 11:33:51 AM PDT 24 3501102280 ps
T1083 /workspace/coverage/default/0.chip_sw_aon_timer_smoketest.992725534 Jul 02 11:01:56 AM PDT 24 Jul 02 11:06:10 AM PDT 24 2652093892 ps
T76 /workspace/coverage/default/0.chip_sw_usbdev_pullup.2957720642 Jul 02 10:59:11 AM PDT 24 Jul 02 11:04:09 AM PDT 24 2372998266 ps
T821 /workspace/coverage/default/63.chip_sw_all_escalation_resets.424053552 Jul 02 11:32:56 AM PDT 24 Jul 02 11:41:45 AM PDT 24 5863532554 ps
T1084 /workspace/coverage/default/1.chip_sw_clkmgr_jitter_reduced_freq.866433281 Jul 02 11:11:30 AM PDT 24 Jul 02 11:15:09 AM PDT 24 3209971177 ps
T1085 /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_test_unlocked0.341656964 Jul 02 10:58:45 AM PDT 24 Jul 02 11:09:36 AM PDT 24 4629789640 ps
T101 /workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_wake_ups.2032278115 Jul 02 11:22:30 AM PDT 24 Jul 02 11:31:08 AM PDT 24 7521420140 ps
T224 /workspace/coverage/default/1.chip_sw_keymgr_sideload_otbn.1078909426 Jul 02 11:08:14 AM PDT 24 Jul 02 12:05:45 PM PDT 24 13829870816 ps
T1086 /workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.4166725357 Jul 02 11:25:49 AM PDT 24 Jul 02 11:44:05 AM PDT 24 8667986361 ps
T1087 /workspace/coverage/default/2.chip_sw_uart_smoketest.2390830565 Jul 02 11:25:48 AM PDT 24 Jul 02 11:30:16 AM PDT 24 2945953462 ps
T150 /workspace/coverage/default/0.chip_plic_all_irqs_10.3750316922 Jul 02 10:59:45 AM PDT 24 Jul 02 11:08:06 AM PDT 24 3319010800 ps
T1088 /workspace/coverage/default/2.chip_sw_flash_ctrl_clock_freqs.626619075 Jul 02 11:16:48 AM PDT 24 Jul 02 11:37:19 AM PDT 24 5172798120 ps
T1089 /workspace/coverage/default/4.chip_tap_straps_prod.548354299 Jul 02 11:27:01 AM PDT 24 Jul 02 11:54:24 AM PDT 24 16247219649 ps
T1090 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.857369230 Jul 02 11:04:36 AM PDT 24 Jul 02 12:04:25 PM PDT 24 15432329878 ps
T1091 /workspace/coverage/default/57.chip_sw_all_escalation_resets.1480913430 Jul 02 11:33:39 AM PDT 24 Jul 02 11:45:23 AM PDT 24 6254834136 ps
T771 /workspace/coverage/default/38.chip_sw_all_escalation_resets.3970754473 Jul 02 11:31:14 AM PDT 24 Jul 02 11:45:28 AM PDT 24 5695959150 ps
T351 /workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.1677782736 Jul 02 11:13:35 AM PDT 24 Jul 02 11:26:43 AM PDT 24 5548585275 ps
T1092 /workspace/coverage/default/2.chip_sw_csrng_fuse_en_sw_app_read_test.4156862033 Jul 02 11:19:48 AM PDT 24 Jul 02 11:28:30 AM PDT 24 3912361240 ps
T220 /workspace/coverage/default/2.chip_sw_keymgr_sideload_aes.2004170944 Jul 02 11:22:36 AM PDT 24 Jul 02 12:05:35 PM PDT 24 13002687794 ps
T1093 /workspace/coverage/default/1.chip_sw_ast_clk_outputs.807885967 Jul 02 11:11:48 AM PDT 24 Jul 02 11:30:07 AM PDT 24 8989913626 ps
T10 /workspace/coverage/default/1.chip_sw_sleep_pin_retention.1942269037 Jul 02 11:04:11 AM PDT 24 Jul 02 11:08:39 AM PDT 24 3358771780 ps
T228 /workspace/coverage/default/0.chip_sw_lc_walkthrough_prod.1915765979 Jul 02 10:58:59 AM PDT 24 Jul 02 12:34:39 PM PDT 24 46045436768 ps
T315 /workspace/coverage/default/1.chip_plic_all_irqs_0.803130096 Jul 02 11:11:55 AM PDT 24 Jul 02 11:33:51 AM PDT 24 6112547372 ps
T407 /workspace/coverage/default/2.chip_sw_lc_ctrl_transition.1595142446 Jul 02 11:15:37 AM PDT 24 Jul 02 11:28:05 AM PDT 24 5414944748 ps
T408 /workspace/coverage/default/0.chip_sw_uart_tx_rx_idx3.217307028 Jul 02 10:57:56 AM PDT 24 Jul 02 11:10:36 AM PDT 24 4886052728 ps
T409 /workspace/coverage/default/0.rom_e2e_asm_init_test_unlocked0.4160763245 Jul 02 11:08:11 AM PDT 24 Jul 02 12:02:31 PM PDT 24 11352837308 ps
T135 /workspace/coverage/default/2.chip_sw_sensor_ctrl_status.2567921308 Jul 02 11:20:50 AM PDT 24 Jul 02 11:24:02 AM PDT 24 2107939708 ps
T410 /workspace/coverage/default/2.chip_sw_example_rom.295457190 Jul 02 11:13:32 AM PDT 24 Jul 02 11:16:05 AM PDT 24 2736032316 ps
T35 /workspace/coverage/default/0.chip_sw_usbdev_config_host.4101183065 Jul 02 10:58:29 AM PDT 24 Jul 02 11:27:10 AM PDT 24 8425924760 ps
T411 /workspace/coverage/default/47.chip_sw_alert_handler_lpg_sleep_mode_alerts.4137585766 Jul 02 11:31:58 AM PDT 24 Jul 02 11:39:31 AM PDT 24 3234343464 ps
T1094 /workspace/coverage/default/0.chip_sw_lc_ctrl_transition.1342510004 Jul 02 10:57:40 AM PDT 24 Jul 02 11:14:19 AM PDT 24 10911819271 ps
T1095 /workspace/coverage/default/2.chip_sw_kmac_smoketest.360956519 Jul 02 11:24:42 AM PDT 24 Jul 02 11:30:25 AM PDT 24 3663599700 ps
T209 /workspace/coverage/default/1.chip_sw_sysrst_ctrl_inputs.3304225651 Jul 02 11:05:55 AM PDT 24 Jul 02 11:11:58 AM PDT 24 3514481244 ps
T790 /workspace/coverage/default/63.chip_sw_alert_handler_lpg_sleep_mode_alerts.3251415707 Jul 02 11:33:35 AM PDT 24 Jul 02 11:39:07 AM PDT 24 3028016666 ps
T1096 /workspace/coverage/default/2.chip_sw_alert_handler_lpg_reset_toggle.4161125687 Jul 02 11:18:51 AM PDT 24 Jul 02 11:52:38 AM PDT 24 8598671076 ps
T1097 /workspace/coverage/default/1.rom_e2e_asm_init_dev.756417700 Jul 02 11:17:50 AM PDT 24 Jul 02 12:28:54 PM PDT 24 15373205529 ps
T704 /workspace/coverage/default/87.chip_sw_all_escalation_resets.2792254258 Jul 02 11:35:15 AM PDT 24 Jul 02 11:43:21 AM PDT 24 5892683760 ps
T1098 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0.1686818647 Jul 02 11:07:21 AM PDT 24 Jul 02 11:56:07 AM PDT 24 11043303406 ps
T1099 /workspace/coverage/default/9.chip_sw_csrng_edn_concurrency.680645520 Jul 02 11:28:52 AM PDT 24 Jul 02 01:04:47 PM PDT 24 27232301068 ps
T1100 /workspace/coverage/default/1.chip_sw_rv_core_ibex_rnd.1679913919 Jul 02 11:08:17 AM PDT 24 Jul 02 11:27:33 AM PDT 24 5335696944 ps
T1101 /workspace/coverage/default/2.chip_sw_flash_ctrl_mem_protection.4034328504 Jul 02 11:24:51 AM PDT 24 Jul 02 11:44:16 AM PDT 24 5677750804 ps
T1102 /workspace/coverage/default/2.chip_sw_entropy_src_smoketest.2673576718 Jul 02 11:24:16 AM PDT 24 Jul 02 11:31:22 AM PDT 24 3239824116 ps
T1103 /workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.3340605227 Jul 02 11:17:06 AM PDT 24 Jul 02 11:38:52 AM PDT 24 12830731372 ps
T1104 /workspace/coverage/default/2.chip_sw_aon_timer_wdog_bite_reset.2564934663 Jul 02 11:19:24 AM PDT 24 Jul 02 11:35:29 AM PDT 24 9522984750 ps
T1105 /workspace/coverage/default/7.chip_sw_lc_ctrl_transition.3833760950 Jul 02 11:28:07 AM PDT 24 Jul 02 11:35:16 AM PDT 24 6054978219 ps
T294 /workspace/coverage/default/0.chip_sw_sram_ctrl_execution_main.2164598590 Jul 02 11:00:18 AM PDT 24 Jul 02 11:18:39 AM PDT 24 10021310760 ps
T1106 /workspace/coverage/default/13.chip_sw_lc_ctrl_transition.1734753534 Jul 02 11:29:50 AM PDT 24 Jul 02 11:42:45 AM PDT 24 8424498117 ps
T1107 /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_rma.493953573 Jul 02 10:58:21 AM PDT 24 Jul 02 11:22:17 AM PDT 24 7576912600 ps
T1108 /workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_no_scramble.1626181719 Jul 02 11:21:00 AM PDT 24 Jul 02 11:35:50 AM PDT 24 8874949576 ps
T286 /workspace/coverage/default/1.chip_sw_rv_core_ibex_address_translation.2039716123 Jul 02 11:12:26 AM PDT 24 Jul 02 11:19:10 AM PDT 24 3202713404 ps
T1109 /workspace/coverage/default/0.chip_sw_flash_ctrl_access.832227466 Jul 02 10:58:59 AM PDT 24 Jul 02 11:18:59 AM PDT 24 5199071500 ps
T318 /workspace/coverage/default/2.chip_plic_all_irqs_0.2376054259 Jul 02 11:21:02 AM PDT 24 Jul 02 11:45:01 AM PDT 24 6056235816 ps
T1110 /workspace/coverage/default/0.chip_sw_rv_timer_irq.2559328717 Jul 02 11:01:28 AM PDT 24 Jul 02 11:05:43 AM PDT 24 2608977078 ps
T319 /workspace/coverage/default/0.chip_plic_all_irqs_0.572812725 Jul 02 11:01:20 AM PDT 24 Jul 02 11:24:13 AM PDT 24 6602273640 ps
T77 /workspace/coverage/default/0.chip_sw_usbdev_aon_pullup.2128024260 Jul 02 10:57:29 AM PDT 24 Jul 02 11:04:33 AM PDT 24 4071897192 ps
T229 /workspace/coverage/default/1.chip_sw_flash_init_reduced_freq.3621111032 Jul 02 11:11:51 AM PDT 24 Jul 02 11:46:57 AM PDT 24 27799019342 ps
T1111 /workspace/coverage/default/4.chip_sw_uart_tx_rx.2218363391 Jul 02 11:26:46 AM PDT 24 Jul 02 11:39:10 AM PDT 24 4790414700 ps
T758 /workspace/coverage/default/74.chip_sw_all_escalation_resets.2455379474 Jul 02 11:35:05 AM PDT 24 Jul 02 11:44:05 AM PDT 24 4623471348 ps
T1112 /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.4193209929 Jul 02 11:03:32 AM PDT 24 Jul 02 11:28:17 AM PDT 24 15420413654 ps
T1113 /workspace/coverage/default/2.chip_sw_clkmgr_smoketest.1139367517 Jul 02 11:26:08 AM PDT 24 Jul 02 11:29:50 AM PDT 24 3351809358 ps
T1114 /workspace/coverage/default/1.chip_sw_flash_crash_alert.1159348110 Jul 02 11:13:22 AM PDT 24 Jul 02 11:23:58 AM PDT 24 6104906968 ps
T353 /workspace/coverage/default/1.chip_sw_i2c_host_tx_rx_idx1.257484945 Jul 02 11:05:34 AM PDT 24 Jul 02 11:20:24 AM PDT 24 4996765750 ps
T1115 /workspace/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en.1269722015 Jul 02 11:01:46 AM PDT 24 Jul 02 11:05:56 AM PDT 24 2941393574 ps
T1116 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.608866723 Jul 02 11:21:46 AM PDT 24 Jul 02 11:33:05 AM PDT 24 4448148644 ps
T1117 /workspace/coverage/default/2.chip_sw_csrng_smoketest.3646904410 Jul 02 11:23:59 AM PDT 24 Jul 02 11:29:22 AM PDT 24 2232643208 ps
T739 /workspace/coverage/default/71.chip_sw_alert_handler_lpg_sleep_mode_alerts.258839209 Jul 02 11:37:26 AM PDT 24 Jul 02 11:44:06 AM PDT 24 4149000596 ps
T1118 /workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_por_reset.3384424908 Jul 02 10:59:53 AM PDT 24 Jul 02 11:12:30 AM PDT 24 5971116699 ps
T404 /workspace/coverage/default/0.chip_sw_rom_ctrl_integrity_check.1814260531 Jul 02 11:00:47 AM PDT 24 Jul 02 11:08:51 AM PDT 24 8797137219 ps
T1119 /workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en.1164596470 Jul 02 11:18:26 AM PDT 24 Jul 02 12:16:31 PM PDT 24 18989377655 ps
T1120 /workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq.2631374876 Jul 02 11:26:40 AM PDT 24 Jul 02 11:56:18 AM PDT 24 8274104434 ps
T827 /workspace/coverage/default/76.chip_sw_alert_handler_lpg_sleep_mode_alerts.2461135776 Jul 02 11:34:41 AM PDT 24 Jul 02 11:40:23 AM PDT 24 3412436216 ps
T1121 /workspace/coverage/default/2.chip_sw_pwrmgr_sysrst_ctrl_reset.2593320105 Jul 02 11:16:57 AM PDT 24 Jul 02 11:37:47 AM PDT 24 7100774300 ps
T1122 /workspace/coverage/default/1.chip_sw_flash_ctrl_clock_freqs.2587872222 Jul 02 11:07:40 AM PDT 24 Jul 02 11:26:59 AM PDT 24 5495842937 ps
T1123 /workspace/coverage/default/2.chip_sival_flash_info_access.168409688 Jul 02 11:16:35 AM PDT 24 Jul 02 11:22:08 AM PDT 24 2758032344 ps
T347 /workspace/coverage/default/2.chip_sw_pattgen_ios.2126120724 Jul 02 11:16:08 AM PDT 24 Jul 02 11:21:45 AM PDT 24 2960884240 ps
T1124 /workspace/coverage/default/2.chip_sw_aes_enc_jitter_en_reduced_freq.2393833954 Jul 02 11:25:27 AM PDT 24 Jul 02 11:30:18 AM PDT 24 3392198755 ps
T772 /workspace/coverage/default/65.chip_sw_alert_handler_lpg_sleep_mode_alerts.3813012585 Jul 02 11:34:01 AM PDT 24 Jul 02 11:40:24 AM PDT 24 3513982052 ps
T1125 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.3682411335 Jul 02 11:21:31 AM PDT 24 Jul 02 11:34:12 AM PDT 24 3541025560 ps
T1126 /workspace/coverage/default/1.chip_tap_straps_rma.1690092853 Jul 02 11:11:06 AM PDT 24 Jul 02 11:19:37 AM PDT 24 5063106173 ps
T826 /workspace/coverage/default/36.chip_sw_all_escalation_resets.3793121172 Jul 02 11:32:46 AM PDT 24 Jul 02 11:47:25 AM PDT 24 5890658928 ps
T836 /workspace/coverage/default/94.chip_sw_all_escalation_resets.171402804 Jul 02 11:35:38 AM PDT 24 Jul 02 11:43:19 AM PDT 24 4098236688 ps
T337 /workspace/coverage/default/0.chip_sw_pwrmgr_lowpower_cancel.4204692148 Jul 02 11:00:33 AM PDT 24 Jul 02 11:06:44 AM PDT 24 3467703618 ps
T711 /workspace/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock.2556321894 Jul 02 11:17:35 AM PDT 24 Jul 02 11:19:42 AM PDT 24 1943826770 ps
T817 /workspace/coverage/default/51.chip_sw_alert_handler_lpg_sleep_mode_alerts.4097744355 Jul 02 11:33:45 AM PDT 24 Jul 02 11:42:07 AM PDT 24 3706433212 ps
T1127 /workspace/coverage/default/0.rom_e2e_static_critical.3296051556 Jul 02 11:06:26 AM PDT 24 Jul 02 12:14:18 PM PDT 24 16859683148 ps
T1128 /workspace/coverage/default/0.chip_sw_rstmgr_smoketest.1564040381 Jul 02 11:02:47 AM PDT 24 Jul 02 11:05:55 AM PDT 24 3329653290 ps
T1129 /workspace/coverage/default/0.chip_sw_sysrst_ctrl_inputs.1480795943 Jul 02 10:58:20 AM PDT 24 Jul 02 11:03:46 AM PDT 24 3749450752 ps
T822 /workspace/coverage/default/69.chip_sw_alert_handler_lpg_sleep_mode_alerts.3925843844 Jul 02 11:33:47 AM PDT 24 Jul 02 11:38:55 AM PDT 24 3801337680 ps
T1130 /workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.4101693184 Jul 02 11:02:01 AM PDT 24 Jul 02 11:14:02 AM PDT 24 5053349272 ps
T757 /workspace/coverage/default/9.chip_sw_alert_handler_lpg_sleep_mode_alerts.517633853 Jul 02 11:30:43 AM PDT 24 Jul 02 11:38:09 AM PDT 24 3618552666 ps
T1131 /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_dev.2088331677 Jul 02 10:58:58 AM PDT 24 Jul 02 11:20:54 AM PDT 24 7211736440 ps
T759 /workspace/coverage/default/13.chip_sw_all_escalation_resets.3454546385 Jul 02 11:29:03 AM PDT 24 Jul 02 11:37:39 AM PDT 24 5212865352 ps
T387 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.3138879331 Jul 02 11:06:32 AM PDT 24 Jul 02 12:45:49 PM PDT 24 24077408584 ps
T1132 /workspace/coverage/default/2.chip_sw_aes_smoketest.913843967 Jul 02 11:25:08 AM PDT 24 Jul 02 11:31:27 AM PDT 24 3152529480 ps
T1133 /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.3456513628 Jul 02 11:11:16 AM PDT 24 Jul 02 11:20:32 AM PDT 24 4279041560 ps
T1134 /workspace/coverage/default/2.chip_sw_rom_ctrl_integrity_check.3722867524 Jul 02 11:20:11 AM PDT 24 Jul 02 11:30:19 AM PDT 24 9589731711 ps
T173 /workspace/coverage/default/0.chip_sw_lc_ctrl_program_error.1604901925 Jul 02 11:02:56 AM PDT 24 Jul 02 11:11:31 AM PDT 24 5209709356 ps
T235 /workspace/coverage/default/0.chip_sw_flash_ctrl_lc_rw_en.1774899944 Jul 02 11:02:02 AM PDT 24 Jul 02 11:11:56 AM PDT 24 4814894414 ps
T1135 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod.2564833505 Jul 02 11:07:28 AM PDT 24 Jul 02 12:10:49 PM PDT 24 14662404980 ps
T1136 /workspace/coverage/default/1.chip_sw_otbn_randomness.212335313 Jul 02 11:07:50 AM PDT 24 Jul 02 11:26:10 AM PDT 24 5288754684 ps
T1137 /workspace/coverage/default/2.chip_sw_edn_entropy_reqs_jitter.3543384433 Jul 02 11:19:39 AM PDT 24 Jul 02 11:35:36 AM PDT 24 5863537949 ps
T1138 /workspace/coverage/default/1.chip_sw_otbn_mem_scramble.3704080676 Jul 02 11:07:13 AM PDT 24 Jul 02 11:15:18 AM PDT 24 3223050024 ps
T1139 /workspace/coverage/default/1.chip_sw_alert_handler_escalation.1792601831 Jul 02 11:08:08 AM PDT 24 Jul 02 11:16:40 AM PDT 24 4638064210 ps
T350 /workspace/coverage/default/1.chip_sw_sensor_ctrl_status.588533468 Jul 02 11:09:44 AM PDT 24 Jul 02 11:13:30 AM PDT 24 2980285034 ps
T1140 /workspace/coverage/default/9.chip_sw_lc_ctrl_transition.71875662 Jul 02 11:28:43 AM PDT 24 Jul 02 11:45:07 AM PDT 24 11637781655 ps
T1141 /workspace/coverage/default/1.chip_sw_uart_tx_rx.4158642328 Jul 02 11:04:44 AM PDT 24 Jul 02 11:16:23 AM PDT 24 4153953940 ps
T1142 /workspace/coverage/default/0.chip_sw_example_concurrency.130172387 Jul 02 10:58:07 AM PDT 24 Jul 02 11:02:26 AM PDT 24 2671855820 ps
T1143 /workspace/coverage/default/0.chip_sw_keymgr_key_derivation.2146387015 Jul 02 11:00:01 AM PDT 24 Jul 02 11:29:46 AM PDT 24 8604515924 ps
T322 /workspace/coverage/default/2.chip_sw_rstmgr_alert_info.482462345 Jul 02 11:18:01 AM PDT 24 Jul 02 11:48:00 AM PDT 24 10958047512 ps
T1144 /workspace/coverage/default/1.chip_sw_uart_rand_baudrate.1740368120 Jul 02 11:02:29 AM PDT 24 Jul 02 11:32:43 AM PDT 24 8827915840 ps
T1145 /workspace/coverage/default/0.chip_sw_aes_idle.889480943 Jul 02 10:59:10 AM PDT 24 Jul 02 11:03:41 AM PDT 24 2497245948 ps
T331 /workspace/coverage/default/1.chip_sw_i2c_host_tx_rx.4051156818 Jul 02 11:07:13 AM PDT 24 Jul 02 11:19:42 AM PDT 24 5390425958 ps
T1146 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.2254687991 Jul 02 11:08:51 AM PDT 24 Jul 02 12:25:00 PM PDT 24 15188677012 ps
T1147 /workspace/coverage/default/0.chip_sw_usbdev_stream.2353117432 Jul 02 10:59:58 AM PDT 24 Jul 02 12:32:37 PM PDT 24 18656285440 ps
T818 /workspace/coverage/default/57.chip_sw_alert_handler_lpg_sleep_mode_alerts.1943596678 Jul 02 11:34:31 AM PDT 24 Jul 02 11:40:56 AM PDT 24 3906689672 ps
T39 /workspace/coverage/default/1.chip_sw_gpio.16297799 Jul 02 11:05:29 AM PDT 24 Jul 02 11:13:51 AM PDT 24 3454333264 ps
T1148 /workspace/coverage/default/42.chip_sw_all_escalation_resets.2910854612 Jul 02 11:33:48 AM PDT 24 Jul 02 11:43:58 AM PDT 24 4270208904 ps
T1149 /workspace/coverage/default/0.chip_sw_aes_masking_off.445872023 Jul 02 10:59:59 AM PDT 24 Jul 02 11:06:10 AM PDT 24 3413435470 ps
T1150 /workspace/coverage/default/2.chip_tap_straps_prod.1123141606 Jul 02 11:22:03 AM PDT 24 Jul 02 11:50:43 AM PDT 24 14400052725 ps
T712 /workspace/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock.1853677862 Jul 02 11:05:53 AM PDT 24 Jul 02 11:07:45 AM PDT 24 2282409729 ps
T1151 /workspace/coverage/default/11.chip_sw_uart_rand_baudrate.603611818 Jul 02 11:29:27 AM PDT 24 Jul 02 12:05:40 PM PDT 24 13405165212 ps
T1152 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.1676573438 Jul 02 11:03:28 AM PDT 24 Jul 02 11:15:47 AM PDT 24 5270178804 ps
T230 /workspace/coverage/default/1.chip_sw_lc_walkthrough_rma.2296519641 Jul 02 11:08:21 AM PDT 24 Jul 02 12:54:20 PM PDT 24 46443038880 ps
T1153 /workspace/coverage/default/1.chip_sw_pwrmgr_wdog_reset.2619066730 Jul 02 11:07:30 AM PDT 24 Jul 02 11:15:36 AM PDT 24 4793737024 ps
T1154 /workspace/coverage/default/2.chip_sw_rstmgr_smoketest.834889828 Jul 02 11:26:53 AM PDT 24 Jul 02 11:31:29 AM PDT 24 2939369720 ps
T1155 /workspace/coverage/default/1.chip_sw_clkmgr_off_aes_trans.2626018739 Jul 02 11:10:59 AM PDT 24 Jul 02 11:19:15 AM PDT 24 4689644504 ps
T102 /workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_wake_ups.3320449452 Jul 02 11:11:43 AM PDT 24 Jul 02 11:19:38 AM PDT 24 7283475194 ps
T1156 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.3908304910 Jul 02 11:09:43 AM PDT 24 Jul 02 11:57:01 AM PDT 24 11908586910 ps
T1157 /workspace/coverage/default/1.chip_sw_edn_sw_mode.217600753 Jul 02 11:09:49 AM PDT 24 Jul 02 11:31:07 AM PDT 24 6717334376 ps
T234 /workspace/coverage/default/0.chip_sw_flash_init.2624080226 Jul 02 10:57:54 AM PDT 24 Jul 02 11:45:28 AM PDT 24 26795045626 ps
T1158 /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_dev.1564831975 Jul 02 11:17:09 AM PDT 24 Jul 02 11:41:34 AM PDT 24 7534996600 ps
T1159 /workspace/coverage/default/2.chip_sw_entropy_src_ast_rng_req.3930785692 Jul 02 11:19:07 AM PDT 24 Jul 02 11:22:25 AM PDT 24 2586821284 ps
T361 /workspace/coverage/default/0.chip_sw_hmac_enc_jitter_en_reduced_freq.4235494922 Jul 02 11:05:02 AM PDT 24 Jul 02 11:09:15 AM PDT 24 2949669875 ps
T1160 /workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_meas.824258529 Jul 02 11:07:37 AM PDT 24 Jul 02 12:00:53 PM PDT 24 15240293808 ps
T1161 /workspace/coverage/default/0.chip_tap_straps_dev.1016880926 Jul 02 11:00:20 AM PDT 24 Jul 02 11:02:36 AM PDT 24 2869091275 ps
T785 /workspace/coverage/default/78.chip_sw_alert_handler_lpg_sleep_mode_alerts.1331482434 Jul 02 11:34:38 AM PDT 24 Jul 02 11:40:35 AM PDT 24 4053041912 ps
T747 /workspace/coverage/default/35.chip_sw_all_escalation_resets.38345291 Jul 02 11:30:57 AM PDT 24 Jul 02 11:39:50 AM PDT 24 5350984432 ps
T1162 /workspace/coverage/default/0.chip_sw_pwrmgr_full_aon_reset.3405308711 Jul 02 10:58:40 AM PDT 24 Jul 02 11:07:57 AM PDT 24 10034595560 ps
T1163 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_rma.2915300170 Jul 02 11:11:24 AM PDT 24 Jul 02 12:17:03 PM PDT 24 14819009500 ps
T1164 /workspace/coverage/default/0.chip_sw_aon_timer_irq.1718171267 Jul 02 10:59:21 AM PDT 24 Jul 02 11:05:24 AM PDT 24 3246125526 ps
T1165 /workspace/coverage/default/0.rom_e2e_jtag_inject_dev.167522723 Jul 02 11:07:15 AM PDT 24 Jul 02 11:58:32 AM PDT 24 31775167949 ps
T749 /workspace/coverage/default/28.chip_sw_alert_handler_lpg_sleep_mode_alerts.1158563270 Jul 02 11:31:07 AM PDT 24 Jul 02 11:37:04 AM PDT 24 3442347286 ps
T1166 /workspace/coverage/default/0.chip_sw_edn_auto_mode.162436439 Jul 02 10:59:59 AM PDT 24 Jul 02 11:18:28 AM PDT 24 4319599794 ps
T15 /workspace/coverage/default/2.chip_sw_sleep_pin_wake.3110563667 Jul 02 11:14:56 AM PDT 24 Jul 02 11:24:13 AM PDT 24 5496226134 ps
T81 /workspace/coverage/default/2.chip_jtag_csr_rw.4053562002 Jul 02 11:14:34 AM PDT 24 Jul 02 11:21:00 AM PDT 24 5011818380 ps
T421 /workspace/coverage/default/0.rom_e2e_asm_init_rma.84218362 Jul 02 11:06:02 AM PDT 24 Jul 02 12:12:34 PM PDT 24 14666282700 ps
T422 /workspace/coverage/default/30.chip_sw_all_escalation_resets.1657385850 Jul 02 11:31:46 AM PDT 24 Jul 02 11:43:00 AM PDT 24 6692328630 ps
T423 /workspace/coverage/default/1.chip_sw_uart_tx_rx_idx3.1941864083 Jul 02 11:03:51 AM PDT 24 Jul 02 11:15:48 AM PDT 24 4729939840 ps
T424 /workspace/coverage/default/1.chip_sw_clkmgr_off_otbn_trans.200685678 Jul 02 11:11:36 AM PDT 24 Jul 02 11:18:33 AM PDT 24 3994442204 ps
T425 /workspace/coverage/default/2.chip_sw_alert_handler_lpg_clkoff.795655214 Jul 02 11:19:40 AM PDT 24 Jul 02 11:48:21 AM PDT 24 6263566060 ps
T426 /workspace/coverage/default/0.chip_sw_rstmgr_rst_cnsty_escalation.2487731934 Jul 02 10:57:47 AM PDT 24 Jul 02 11:08:31 AM PDT 24 5533108188 ps
T310 /workspace/coverage/default/81.chip_sw_alert_handler_lpg_sleep_mode_alerts.2730889766 Jul 02 11:36:55 AM PDT 24 Jul 02 11:42:30 AM PDT 24 3725684784 ps
T427 /workspace/coverage/default/93.chip_sw_all_escalation_resets.4263090108 Jul 02 11:36:51 AM PDT 24 Jul 02 11:45:45 AM PDT 24 5053474052 ps
T1167 /workspace/coverage/default/2.chip_sw_aes_entropy.4163257449 Jul 02 11:18:25 AM PDT 24 Jul 02 11:23:32 AM PDT 24 3061965890 ps
T1168 /workspace/coverage/default/1.chip_sw_pwrmgr_smoketest.3477946402 Jul 02 11:13:57 AM PDT 24 Jul 02 11:25:26 AM PDT 24 6607225888 ps
T1169 /workspace/coverage/default/2.chip_sw_lc_walkthrough_prodend.218973200 Jul 02 11:17:10 AM PDT 24 Jul 02 11:37:27 AM PDT 24 8776678900 ps
T1170 /workspace/coverage/default/2.chip_sw_uart_tx_rx_idx3.1166155412 Jul 02 11:14:30 AM PDT 24 Jul 02 11:26:02 AM PDT 24 4663514590 ps
T754 /workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_pings.4010621576 Jul 02 11:18:30 AM PDT 24 Jul 02 11:42:37 AM PDT 24 12314762800 ps
T384 /workspace/coverage/default/2.chip_sw_edn_boot_mode.1220704971 Jul 02 11:19:33 AM PDT 24 Jul 02 11:30:25 AM PDT 24 2943050178 ps
T776 /workspace/coverage/default/92.chip_sw_all_escalation_resets.3248547379 Jul 02 11:37:19 AM PDT 24 Jul 02 11:48:26 AM PDT 24 5257771284 ps
T1171 /workspace/coverage/default/0.chip_sw_pwrmgr_usbdev_smoketest.1083147312 Jul 02 11:05:45 AM PDT 24 Jul 02 11:14:01 AM PDT 24 5210583240 ps
T1172 /workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_scramble.3055424005 Jul 02 11:01:06 AM PDT 24 Jul 02 11:10:16 AM PDT 24 8225575436 ps
T406 /workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_wake_ups.380733722 Jul 02 11:23:06 AM PDT 24 Jul 02 11:49:45 AM PDT 24 21016095968 ps
T1173 /workspace/coverage/default/0.chip_sw_lc_ctrl_otp_hw_cfg0.4262948573 Jul 02 10:59:30 AM PDT 24 Jul 02 11:04:36 AM PDT 24 2938796862 ps
T251 /workspace/coverage/default/1.chip_sw_plic_sw_irq.3319965008 Jul 02 11:11:20 AM PDT 24 Jul 02 11:15:22 AM PDT 24 2942839444 ps
T1174 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.4091578159 Jul 02 11:11:26 AM PDT 24 Jul 02 01:08:53 PM PDT 24 23943156144 ps
T1175 /workspace/coverage/default/1.chip_sw_example_manufacturer.553118935 Jul 02 11:05:46 AM PDT 24 Jul 02 11:09:12 AM PDT 24 2672258960 ps
T796 /workspace/coverage/default/88.chip_sw_all_escalation_resets.4183195207 Jul 02 11:36:21 AM PDT 24 Jul 02 11:45:24 AM PDT 24 5302235920 ps
T773 /workspace/coverage/default/65.chip_sw_all_escalation_resets.64439982 Jul 02 11:34:51 AM PDT 24 Jul 02 11:43:09 AM PDT 24 4766239180 ps
T1176 /workspace/coverage/default/0.chip_tap_straps_prod.114326858 Jul 02 10:59:55 AM PDT 24 Jul 02 11:23:03 AM PDT 24 12539179510 ps
T1177 /workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_invalid_meas.183547313 Jul 02 11:08:20 AM PDT 24 Jul 02 12:15:33 PM PDT 24 14873228740 ps
T1178 /workspace/coverage/default/1.chip_sw_sleep_pwm_pulses.1144666971 Jul 02 11:04:06 AM PDT 24 Jul 02 11:23:08 AM PDT 24 9384738966 ps
T1179 /workspace/coverage/default/21.chip_sw_alert_handler_lpg_sleep_mode_alerts.3402625513 Jul 02 11:30:10 AM PDT 24 Jul 02 11:37:33 AM PDT 24 4150270024 ps
T1180 /workspace/coverage/default/12.chip_sw_all_escalation_resets.1707055191 Jul 02 11:28:53 AM PDT 24 Jul 02 11:41:00 AM PDT 24 4950583418 ps
T1181 /workspace/coverage/default/0.chip_sw_usbdev_vbus.2034202382 Jul 02 10:58:06 AM PDT 24 Jul 02 11:01:34 AM PDT 24 2848780106 ps
T1182 /workspace/coverage/default/0.chip_sw_usbdev_setuprx.2827015732 Jul 02 10:58:05 AM PDT 24 Jul 02 11:06:33 AM PDT 24 3964360352 ps
T1183 /workspace/coverage/default/2.chip_sw_kmac_entropy.745932117 Jul 02 11:16:21 AM PDT 24 Jul 02 11:21:30 AM PDT 24 3178986532 ps
T820 /workspace/coverage/default/48.chip_sw_alert_handler_lpg_sleep_mode_alerts.2720233528 Jul 02 11:33:32 AM PDT 24 Jul 02 11:42:09 AM PDT 24 3676047488 ps
T1184 /workspace/coverage/default/19.chip_sw_uart_rand_baudrate.323750495 Jul 02 11:29:56 AM PDT 24 Jul 02 12:10:12 PM PDT 24 13409280752 ps
T778 /workspace/coverage/default/72.chip_sw_all_escalation_resets.2161078009 Jul 02 11:35:19 AM PDT 24 Jul 02 11:43:35 AM PDT 24 3980508000 ps
T1185 /workspace/coverage/default/1.chip_sw_aon_timer_sleep_wdog_sleep_pause.2637168168 Jul 02 11:06:21 AM PDT 24 Jul 02 11:14:43 AM PDT 24 7027807828 ps
T1186 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.1319292524 Jul 02 11:00:29 AM PDT 24 Jul 02 11:10:47 AM PDT 24 4333067856 ps
T1187 /workspace/coverage/default/2.chip_sw_flash_ctrl_write_clear.1818052023 Jul 02 11:22:49 AM PDT 24 Jul 02 11:29:41 AM PDT 24 3450975794 ps
T814 /workspace/coverage/default/10.chip_sw_all_escalation_resets.197985989 Jul 02 11:28:11 AM PDT 24 Jul 02 11:38:43 AM PDT 24 4585265506 ps
T383 /workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx1.4191677564 Jul 02 11:02:32 AM PDT 24 Jul 02 11:17:12 AM PDT 24 4733770236 ps
T200 /workspace/coverage/default/2.chip_jtag_mem_access.1525581382 Jul 02 11:14:19 AM PDT 24 Jul 02 11:40:04 AM PDT 24 13605718080 ps
T385 /workspace/coverage/default/0.chip_sw_edn_boot_mode.2277478409 Jul 02 11:00:56 AM PDT 24 Jul 02 11:11:56 AM PDT 24 3198284196 ps
T1188 /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_lc.1957134204 Jul 02 11:10:52 AM PDT 24 Jul 02 11:21:44 AM PDT 24 6912702296 ps
T1189 /workspace/coverage/default/8.chip_sw_csrng_edn_concurrency.945624009 Jul 02 11:28:58 AM PDT 24 Jul 02 12:56:09 PM PDT 24 24175227088 ps
T1190 /workspace/coverage/default/0.rom_e2e_asm_init_prod.3240260085 Jul 02 11:07:57 AM PDT 24 Jul 02 12:21:35 PM PDT 24 15477010900 ps
T125 /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.76858961 Jul 02 11:12:24 AM PDT 24 Jul 02 11:21:04 AM PDT 24 5492401504 ps
T1191 /workspace/coverage/default/0.chip_sw_pwrmgr_smoketest.762209489 Jul 02 11:03:25 AM PDT 24 Jul 02 11:10:26 AM PDT 24 5685791600 ps
T1192 /workspace/coverage/default/1.chip_sw_edn_kat.2933750667 Jul 02 11:08:27 AM PDT 24 Jul 02 11:18:31 AM PDT 24 3274813472 ps
T806 /workspace/coverage/default/68.chip_sw_all_escalation_resets.2935823762 Jul 02 11:33:59 AM PDT 24 Jul 02 11:45:51 AM PDT 24 4893876088 ps
T1193 /workspace/coverage/default/0.chip_sw_kmac_app_rom.1149300727 Jul 02 11:00:57 AM PDT 24 Jul 02 11:05:12 AM PDT 24 2335059256 ps
T196 /workspace/coverage/default/1.chip_sw_spi_device_pass_through_collision.2311172242 Jul 02 11:04:26 AM PDT 24 Jul 02 11:15:41 AM PDT 24 4626726212 ps
T1194 /workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.1699879600 Jul 02 11:04:05 AM PDT 24 Jul 02 11:12:41 AM PDT 24 3683158395 ps
T213 /workspace/coverage/default/2.chip_sw_sysrst_ctrl_ec_rst_l.859962354 Jul 02 11:18:57 AM PDT 24 Jul 02 12:16:40 PM PDT 24 21066780463 ps
T1195 /workspace/coverage/default/4.chip_tap_straps_testunlock0.72578156 Jul 02 11:26:39 AM PDT 24 Jul 02 11:30:07 AM PDT 24 3263428483 ps
T1196 /workspace/coverage/default/3.chip_sw_uart_tx_rx.1243283864 Jul 02 11:25:47 AM PDT 24 Jul 02 11:36:11 AM PDT 24 4464700040 ps
T1197 /workspace/coverage/default/1.chip_sw_power_idle_load.740236031 Jul 02 11:12:08 AM PDT 24 Jul 02 11:23:43 AM PDT 24 4352111000 ps
T1198 /workspace/coverage/default/0.chip_sw_uart_rand_baudrate.3786835511 Jul 02 10:58:31 AM PDT 24 Jul 02 11:11:10 AM PDT 24 4681042396 ps
T1199 /workspace/coverage/default/2.chip_sw_pwrmgr_usbdev_smoketest.1335186378 Jul 02 11:27:12 AM PDT 24 Jul 02 11:33:32 AM PDT 24 5115211132 ps
T1200 /workspace/coverage/default/26.chip_sw_all_escalation_resets.1992039778 Jul 02 11:31:55 AM PDT 24 Jul 02 11:47:05 AM PDT 24 6141323688 ps
T1201 /workspace/coverage/default/2.rom_e2e_asm_init_prod.2802720480 Jul 02 11:29:21 AM PDT 24 Jul 02 12:24:01 PM PDT 24 15598166924 ps
T1202 /workspace/coverage/default/2.rom_e2e_shutdown_output.485122587 Jul 02 11:32:25 AM PDT 24 Jul 02 12:26:04 PM PDT 24 29840632010 ps
T1203 /workspace/coverage/default/89.chip_sw_all_escalation_resets.1163860566 Jul 02 11:35:28 AM PDT 24 Jul 02 11:43:47 AM PDT 24 4812272104 ps
T23 /workspace/coverage/default/0.chip_sw_sleep_pin_mio_dio_val.914687602 Jul 02 10:59:26 AM PDT 24 Jul 02 11:05:06 AM PDT 24 3261932909 ps
T1204 /workspace/coverage/default/2.chip_sw_alert_handler_entropy.209661337 Jul 02 11:20:17 AM PDT 24 Jul 02 11:25:59 AM PDT 24 3717113792 ps
T146 /workspace/coverage/default/2.chip_sw_exit_test_unlocked_bootstrap.3350389890 Jul 02 11:14:50 AM PDT 24 Jul 02 02:15:48 PM PDT 24 57652175960 ps
T1205 /workspace/coverage/default/1.rom_e2e_smoke.3135587234 Jul 02 11:17:45 AM PDT 24 Jul 02 12:15:56 PM PDT 24 15480286120 ps
T1206 /workspace/coverage/default/0.chip_sw_flash_ctrl_idle_low_power.1171191840 Jul 02 11:03:00 AM PDT 24 Jul 02 11:09:55 AM PDT 24 3525204772 ps
T1207 /workspace/coverage/default/2.chip_sw_sysrst_ctrl_outputs.2989104132 Jul 02 11:19:18 AM PDT 24 Jul 02 11:26:25 AM PDT 24 3859791966 ps
T1208 /workspace/coverage/default/1.chip_sw_example_concurrency.3719893742 Jul 02 11:04:33 AM PDT 24 Jul 02 11:08:39 AM PDT 24 2592876904 ps
T1209 /workspace/coverage/default/1.chip_sw_uart_smoketest.643460525 Jul 02 11:17:29 AM PDT 24 Jul 02 11:21:19 AM PDT 24 3292886210 ps
T225 /workspace/coverage/default/2.chip_sw_keymgr_sideload_otbn.1698338076 Jul 02 11:20:58 AM PDT 24 Jul 02 12:19:37 PM PDT 24 16924049440 ps
T731 /workspace/coverage/default/1.chip_sw_pattgen_ios.3285887505 Jul 02 11:04:15 AM PDT 24 Jul 02 11:08:38 AM PDT 24 2972337974 ps
T1210 /workspace/coverage/default/2.chip_sw_keymgr_key_derivation_prod.2778417458 Jul 02 11:20:24 AM PDT 24 Jul 02 11:55:13 AM PDT 24 11202319626 ps
T1211 /workspace/coverage/default/0.chip_sw_lc_walkthrough_dev.2879714150 Jul 02 10:59:20 AM PDT 24 Jul 02 12:37:02 PM PDT 24 50700792700 ps
T49 /workspace/coverage/default/0.chip_sw_sysrst_ctrl_ulp_z3_wakeup.71804748 Jul 02 11:03:23 AM PDT 24 Jul 02 11:14:21 AM PDT 24 5830357678 ps
T807 /workspace/coverage/default/41.chip_sw_all_escalation_resets.4150123832 Jul 02 11:34:34 AM PDT 24 Jul 02 11:44:25 AM PDT 24 5416301956 ps
T1212 /workspace/coverage/default/7.chip_sw_uart_rand_baudrate.735798324 Jul 02 11:30:49 AM PDT 24 Jul 02 12:06:52 PM PDT 24 13434650456 ps
T737 /workspace/coverage/default/52.chip_sw_alert_handler_lpg_sleep_mode_alerts.922021100 Jul 02 11:37:08 AM PDT 24 Jul 02 11:45:30 AM PDT 24 4407102266 ps
T1213 /workspace/coverage/default/16.chip_sw_all_escalation_resets.1192588505 Jul 02 11:30:12 AM PDT 24 Jul 02 11:41:38 AM PDT 24 4663645502 ps
T1214 /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_rma.2552017717 Jul 02 11:04:19 AM PDT 24 Jul 02 11:26:17 AM PDT 24 9171551330 ps
T767 /workspace/coverage/default/59.chip_sw_all_escalation_resets.1619662581 Jul 02 11:33:44 AM PDT 24 Jul 02 11:42:42 AM PDT 24 5103144916 ps
T231 /workspace/coverage/default/2.chip_sw_lc_walkthrough_rma.2677926538 Jul 02 11:16:42 AM PDT 24 Jul 02 12:31:34 PM PDT 24 47007416190 ps
T1215 /workspace/coverage/default/0.chip_sw_rv_core_ibex_rnd.1470570461 Jul 02 11:00:13 AM PDT 24 Jul 02 11:16:50 AM PDT 24 4913384324 ps
T386 /workspace/coverage/default/1.chip_sw_edn_boot_mode.2256504933 Jul 02 11:08:45 AM PDT 24 Jul 02 11:17:42 AM PDT 24 2979343668 ps
T1216 /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.2824892587 Jul 02 11:14:03 AM PDT 24 Jul 02 11:24:22 AM PDT 24 3956885642 ps
T1217 /workspace/coverage/default/2.chip_sw_aon_timer_irq.3411596773 Jul 02 11:18:07 AM PDT 24 Jul 02 11:24:32 AM PDT 24 3668048700 ps
T1218 /workspace/coverage/default/0.chip_sw_rv_timer_smoketest.3256908288 Jul 02 11:07:27 AM PDT 24 Jul 02 11:13:48 AM PDT 24 3512182960 ps
T1219 /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_por_reset.625327658 Jul 02 11:06:01 AM PDT 24 Jul 02 11:17:13 AM PDT 24 7441899686 ps
T245 /workspace/coverage/default/85.chip_sw_alert_handler_lpg_sleep_mode_alerts.698776593 Jul 02 11:34:44 AM PDT 24 Jul 02 11:40:56 AM PDT 24 3693329804 ps
T1220 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.989692532 Jul 02 11:25:10 AM PDT 24 Jul 02 11:37:10 AM PDT 24 4518823138 ps
T441 /workspace/coverage/default/0.rom_e2e_jtag_inject_rma.1352102594 Jul 02 11:05:46 AM PDT 24 Jul 02 11:43:53 AM PDT 24 26425060701 ps
T72 /workspace/coverage/default/2.chip_tap_straps_rma.3328992089 Jul 02 11:22:31 AM PDT 24 Jul 02 11:29:02 AM PDT 24 4754978271 ps
T1221 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.1302954461 Jul 02 11:07:08 AM PDT 24 Jul 02 12:12:25 PM PDT 24 15011575863 ps
T128 /workspace/coverage/default/0.chip_sw_sensor_ctrl_alert.558495423 Jul 02 11:00:43 AM PDT 24 Jul 02 11:10:03 AM PDT 24 4933740038 ps
T1222 /workspace/coverage/default/2.chip_sw_rstmgr_sw_req.1779469860 Jul 02 11:17:47 AM PDT 24 Jul 02 11:26:53 AM PDT 24 4808612712 ps
T236 /workspace/coverage/default/0.chip_sw_lc_walkthrough_rma.64968378 Jul 02 11:00:26 AM PDT 24 Jul 02 12:33:41 PM PDT 24 45999653206 ps
T1223 /workspace/coverage/default/1.chip_sw_aes_idle.2485702126 Jul 02 11:07:55 AM PDT 24 Jul 02 11:11:48 AM PDT 24 2193666946 ps
T1224 /workspace/coverage/default/17.chip_sw_uart_rand_baudrate.3670820013 Jul 02 11:31:03 AM PDT 24 Jul 02 11:40:29 AM PDT 24 4297936096 ps
T834 /workspace/coverage/default/30.chip_sw_alert_handler_lpg_sleep_mode_alerts.760977211 Jul 02 11:30:40 AM PDT 24 Jul 02 11:37:01 AM PDT 24 3309752080 ps
T1225 /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.2177174843 Jul 02 11:12:31 AM PDT 24 Jul 02 11:21:58 AM PDT 24 4606300992 ps
T174 /workspace/coverage/default/1.chip_sw_lc_ctrl_program_error.1343317248 Jul 02 11:10:48 AM PDT 24 Jul 02 11:20:54 AM PDT 24 5372180992 ps
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