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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.04 95.43 93.74 95.53 94.46 97.53 99.53


Total test records in report: 2892
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T498 /workspace/coverage/default/1.chip_sw_rv_core_ibex_nmi_irq.4289200722 Jul 03 07:55:45 PM PDT 24 Jul 03 08:09:28 PM PDT 24 4763274318 ps
T254 /workspace/coverage/default/1.chip_sw_rv_timer_smoketest.2654024879 Jul 03 08:03:26 PM PDT 24 Jul 03 08:07:41 PM PDT 24 3214070280 ps
T879 /workspace/coverage/default/0.chip_sw_csrng_kat_test.2955538121 Jul 03 07:48:40 PM PDT 24 Jul 03 07:52:34 PM PDT 24 2815242696 ps
T880 /workspace/coverage/default/0.chip_sw_keymgr_key_derivation_prod.3623319573 Jul 03 07:48:49 PM PDT 24 Jul 03 08:12:59 PM PDT 24 6701097728 ps
T318 /workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.3857690168 Jul 03 07:51:00 PM PDT 24 Jul 03 08:58:04 PM PDT 24 24633614358 ps
T310 /workspace/coverage/default/1.chip_plic_all_irqs_20.4249834997 Jul 03 07:59:53 PM PDT 24 Jul 03 08:13:13 PM PDT 24 5187181100 ps
T133 /workspace/coverage/default/1.chip_sw_entropy_src_csrng.2026217572 Jul 03 07:57:28 PM PDT 24 Jul 03 08:21:24 PM PDT 24 5587229768 ps
T342 /workspace/coverage/default/93.chip_sw_all_escalation_resets.744150566 Jul 03 08:21:35 PM PDT 24 Jul 03 08:29:56 PM PDT 24 6423615276 ps
T306 /workspace/coverage/default/0.chip_plic_all_irqs_0.2605233833 Jul 03 07:49:37 PM PDT 24 Jul 03 08:12:51 PM PDT 24 6540908690 ps
T191 /workspace/coverage/default/37.chip_sw_all_escalation_resets.4152294353 Jul 03 08:18:18 PM PDT 24 Jul 03 08:29:28 PM PDT 24 4861208280 ps
T881 /workspace/coverage/default/1.chip_sw_aes_smoketest.5366323 Jul 03 08:03:43 PM PDT 24 Jul 03 08:09:16 PM PDT 24 3278208680 ps
T882 /workspace/coverage/default/0.chip_sw_lc_ctrl_otp_hw_cfg0.3076260198 Jul 03 07:47:49 PM PDT 24 Jul 03 07:52:32 PM PDT 24 2873775880 ps
T883 /workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.1421779167 Jul 03 07:55:13 PM PDT 24 Jul 03 08:21:45 PM PDT 24 14771191019 ps
T884 /workspace/coverage/default/2.rom_e2e_smoke.3223326977 Jul 03 08:17:33 PM PDT 24 Jul 03 09:13:02 PM PDT 24 14853929740 ps
T346 /workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en.915698995 Jul 03 07:47:01 PM PDT 24 Jul 03 07:56:58 PM PDT 24 4247850609 ps
T233 /workspace/coverage/default/2.chip_sw_flash_init_reduced_freq.2559110996 Jul 03 08:11:43 PM PDT 24 Jul 03 08:36:38 PM PDT 24 21655373831 ps
T681 /workspace/coverage/default/87.chip_sw_all_escalation_resets.4015758621 Jul 03 08:22:47 PM PDT 24 Jul 03 08:31:37 PM PDT 24 5369096200 ps
T885 /workspace/coverage/default/1.chip_sw_keymgr_key_derivation_jitter_en.535641482 Jul 03 07:59:10 PM PDT 24 Jul 03 08:46:19 PM PDT 24 11802571269 ps
T231 /workspace/coverage/default/2.chip_sw_lc_walkthrough_rma.3380360742 Jul 03 08:05:36 PM PDT 24 Jul 03 09:36:37 PM PDT 24 49584841700 ps
T886 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.362081463 Jul 03 08:10:35 PM PDT 24 Jul 03 08:20:59 PM PDT 24 5158555240 ps
T198 /workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en.4237344873 Jul 03 07:50:06 PM PDT 24 Jul 03 07:59:58 PM PDT 24 5495982344 ps
T887 /workspace/coverage/default/2.chip_sw_example_rom.3586409801 Jul 03 08:04:26 PM PDT 24 Jul 03 08:06:36 PM PDT 24 2001191856 ps
T69 /workspace/coverage/default/0.chip_sw_usbdev_aon_pullup.2184065907 Jul 03 07:49:25 PM PDT 24 Jul 03 07:57:22 PM PDT 24 3537388686 ps
T48 /workspace/coverage/default/1.chip_sw_spi_host_tx_rx.3494347835 Jul 03 07:53:52 PM PDT 24 Jul 03 07:59:18 PM PDT 24 3599343420 ps
T888 /workspace/coverage/default/1.chip_sw_kmac_mode_cshake.4225723452 Jul 03 07:58:15 PM PDT 24 Jul 03 08:03:37 PM PDT 24 3423180952 ps
T138 /workspace/coverage/default/0.chip_sw_sensor_ctrl_alert.4242040667 Jul 03 07:49:19 PM PDT 24 Jul 03 08:06:19 PM PDT 24 7437971384 ps
T889 /workspace/coverage/default/1.chip_sw_aon_timer_irq.2078706697 Jul 03 07:57:38 PM PDT 24 Jul 03 08:03:20 PM PDT 24 3956322704 ps
T676 /workspace/coverage/default/59.chip_sw_alert_handler_lpg_sleep_mode_alerts.1509951566 Jul 03 08:20:40 PM PDT 24 Jul 03 08:28:30 PM PDT 24 3861665960 ps
T890 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_rma.545449541 Jul 03 08:02:10 PM PDT 24 Jul 03 08:59:56 PM PDT 24 13431233548 ps
T891 /workspace/coverage/default/2.chip_sw_example_manufacturer.1373881110 Jul 03 08:05:37 PM PDT 24 Jul 03 08:08:37 PM PDT 24 1883898840 ps
T677 /workspace/coverage/default/44.chip_sw_all_escalation_resets.2232218037 Jul 03 08:20:11 PM PDT 24 Jul 03 08:31:53 PM PDT 24 4685741712 ps
T892 /workspace/coverage/default/0.chip_sw_keymgr_sideload_kmac.2332532739 Jul 03 07:49:43 PM PDT 24 Jul 03 08:31:54 PM PDT 24 13010802264 ps
T893 /workspace/coverage/default/1.chip_sw_flash_ctrl_idle_low_power.1260434001 Jul 03 07:54:42 PM PDT 24 Jul 03 08:02:30 PM PDT 24 3433006696 ps
T35 /workspace/coverage/default/0.chip_sw_sysrst_ctrl_ec_rst_l.4167992149 Jul 03 07:47:50 PM PDT 24 Jul 03 08:48:53 PM PDT 24 21257182252 ps
T139 /workspace/coverage/default/1.chip_sw_sensor_ctrl_alert.1069753423 Jul 03 07:59:08 PM PDT 24 Jul 03 08:09:23 PM PDT 24 6647048488 ps
T894 /workspace/coverage/default/1.chip_sw_aon_timer_sleep_wdog_sleep_pause.4047393027 Jul 03 07:59:33 PM PDT 24 Jul 03 08:09:01 PM PDT 24 7526255528 ps
T192 /workspace/coverage/default/84.chip_sw_all_escalation_resets.3359069263 Jul 03 08:20:59 PM PDT 24 Jul 03 08:31:34 PM PDT 24 5166292306 ps
T895 /workspace/coverage/default/1.rom_e2e_asm_init_prod_end.316470909 Jul 03 08:06:47 PM PDT 24 Jul 03 09:11:47 PM PDT 24 14970322100 ps
T896 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod_end.837146871 Jul 03 07:56:39 PM PDT 24 Jul 03 08:55:07 PM PDT 24 14679732525 ps
T682 /workspace/coverage/default/2.chip_sw_all_escalation_resets.1680887206 Jul 03 08:05:37 PM PDT 24 Jul 03 08:15:13 PM PDT 24 4820676484 ps
T725 /workspace/coverage/default/48.chip_sw_alert_handler_lpg_sleep_mode_alerts.2458737867 Jul 03 08:19:55 PM PDT 24 Jul 03 08:25:02 PM PDT 24 3852917580 ps
T897 /workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_invalid_meas.904294760 Jul 03 07:58:34 PM PDT 24 Jul 03 08:59:42 PM PDT 24 14795240500 ps
T898 /workspace/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.1905353101 Jul 03 08:11:20 PM PDT 24 Jul 03 08:34:05 PM PDT 24 8028817230 ps
T899 /workspace/coverage/default/1.chip_sw_kmac_smoketest.3617673361 Jul 03 08:04:06 PM PDT 24 Jul 03 08:08:54 PM PDT 24 3216905352 ps
T240 /workspace/coverage/default/80.chip_sw_alert_handler_lpg_sleep_mode_alerts.1786304767 Jul 03 08:19:59 PM PDT 24 Jul 03 08:24:19 PM PDT 24 3750350536 ps
T900 /workspace/coverage/default/0.chip_sw_flash_ctrl_clock_freqs.114224014 Jul 03 07:48:04 PM PDT 24 Jul 03 08:08:17 PM PDT 24 5585298312 ps
T901 /workspace/coverage/default/12.chip_sw_lc_ctrl_transition.3646248295 Jul 03 08:16:16 PM PDT 24 Jul 03 08:23:15 PM PDT 24 5756953928 ps
T902 /workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq.3504605791 Jul 03 07:49:07 PM PDT 24 Jul 03 08:42:29 PM PDT 24 17134748908 ps
T185 /workspace/coverage/default/46.chip_sw_all_escalation_resets.325638321 Jul 03 08:18:36 PM PDT 24 Jul 03 08:30:22 PM PDT 24 5223597524 ps
T56 /workspace/coverage/default/1.chip_sw_spi_device_tpm.4265509650 Jul 03 07:52:47 PM PDT 24 Jul 03 07:58:56 PM PDT 24 3418251520 ps
T903 /workspace/coverage/default/8.chip_sw_csrng_edn_concurrency.4238093103 Jul 03 08:16:07 PM PDT 24 Jul 03 09:16:44 PM PDT 24 19565945376 ps
T904 /workspace/coverage/default/2.chip_sw_rstmgr_smoketest.2820466906 Jul 03 08:13:19 PM PDT 24 Jul 03 08:18:55 PM PDT 24 3085038062 ps
T905 /workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_no_meas.281878958 Jul 03 08:17:02 PM PDT 24 Jul 03 09:17:07 PM PDT 24 14452333560 ps
T12 /workspace/coverage/default/2.chip_sw_sleep_pin_wake.3016754265 Jul 03 08:05:36 PM PDT 24 Jul 03 08:11:40 PM PDT 24 4555123838 ps
T402 /workspace/coverage/default/1.chip_sw_kmac_entropy.1824028370 Jul 03 07:52:20 PM PDT 24 Jul 03 07:56:41 PM PDT 24 2616552570 ps
T403 /workspace/coverage/default/71.chip_sw_all_escalation_resets.1524196641 Jul 03 08:23:05 PM PDT 24 Jul 03 08:32:21 PM PDT 24 5544104648 ps
T404 /workspace/coverage/default/11.chip_sw_uart_rand_baudrate.662128251 Jul 03 08:15:31 PM PDT 24 Jul 03 08:22:42 PM PDT 24 3979905024 ps
T405 /workspace/coverage/default/1.chip_sw_csrng_edn_concurrency.2322108519 Jul 03 07:58:35 PM PDT 24 Jul 03 09:58:53 PM PDT 24 26914387312 ps
T406 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_prod_end.609628151 Jul 03 07:59:14 PM PDT 24 Jul 03 09:47:00 PM PDT 24 23628341294 ps
T36 /workspace/coverage/default/0.chip_sw_usbdev_setuprx.147103353 Jul 03 07:47:26 PM PDT 24 Jul 03 07:57:14 PM PDT 24 3891648600 ps
T85 /workspace/coverage/default/4.chip_tap_straps_prod.3390532978 Jul 03 08:14:00 PM PDT 24 Jul 03 08:25:07 PM PDT 24 7455352278 ps
T149 /workspace/coverage/default/2.chip_sw_pwrmgr_full_aon_reset.1690493757 Jul 03 08:06:15 PM PDT 24 Jul 03 08:13:26 PM PDT 24 9023320280 ps
T407 /workspace/coverage/default/2.chip_sw_aon_timer_smoketest.3472172917 Jul 03 08:12:02 PM PDT 24 Jul 03 08:16:20 PM PDT 24 2770985592 ps
T9 /workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_wake_ups.678844652 Jul 03 08:01:10 PM PDT 24 Jul 03 08:32:58 PM PDT 24 24995264656 ps
T636 /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_disabled.610078289 Jul 03 07:48:14 PM PDT 24 Jul 03 07:52:50 PM PDT 24 3633103690 ps
T718 /workspace/coverage/default/84.chip_sw_alert_handler_lpg_sleep_mode_alerts.2282719994 Jul 03 08:21:26 PM PDT 24 Jul 03 08:27:08 PM PDT 24 3501731848 ps
T906 /workspace/coverage/default/1.chip_sw_hmac_multistream.2784926527 Jul 03 07:59:03 PM PDT 24 Jul 03 08:28:13 PM PDT 24 7539066608 ps
T907 /workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_reset_reqs.3224740273 Jul 03 07:47:55 PM PDT 24 Jul 03 08:39:28 PM PDT 24 24326508710 ps
T908 /workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.2347986020 Jul 03 08:00:59 PM PDT 24 Jul 03 08:58:53 PM PDT 24 24884973539 ps
T184 /workspace/coverage/default/2.chip_sw_rstmgr_alert_info.215663190 Jul 03 08:08:31 PM PDT 24 Jul 03 08:42:36 PM PDT 24 14727620110 ps
T909 /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.3002408803 Jul 03 08:00:10 PM PDT 24 Jul 03 08:10:29 PM PDT 24 3576824036 ps
T80 /workspace/coverage/default/1.chip_jtag_csr_rw.621470333 Jul 03 07:53:31 PM PDT 24 Jul 03 08:35:24 PM PDT 24 18972154420 ps
T910 /workspace/coverage/default/0.rom_e2e_smoke.1143061668 Jul 03 07:54:43 PM PDT 24 Jul 03 08:54:59 PM PDT 24 15083641612 ps
T911 /workspace/coverage/default/1.chip_sw_pwrmgr_smoketest.669883533 Jul 03 08:04:17 PM PDT 24 Jul 03 08:13:03 PM PDT 24 6418183392 ps
T204 /workspace/coverage/default/0.chip_sw_csrng_fuse_en_sw_app_read_test.220810365 Jul 03 07:53:56 PM PDT 24 Jul 03 08:04:14 PM PDT 24 4858363900 ps
T337 /workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en.182676926 Jul 03 07:54:28 PM PDT 24 Jul 03 08:06:20 PM PDT 24 4396847273 ps
T621 /workspace/coverage/default/1.chip_sw_rv_dm_access_after_escalation_reset.2358844421 Jul 03 08:01:09 PM PDT 24 Jul 03 08:10:42 PM PDT 24 4917118909 ps
T912 /workspace/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en.1684456980 Jul 03 08:10:26 PM PDT 24 Jul 03 08:52:03 PM PDT 24 11940099644 ps
T913 /workspace/coverage/default/2.chip_sw_kmac_app_rom.4093404872 Jul 03 08:12:24 PM PDT 24 Jul 03 08:15:15 PM PDT 24 2409546904 ps
T49 /workspace/coverage/default/2.chip_sw_spi_host_tx_rx.4288540441 Jul 03 08:05:31 PM PDT 24 Jul 03 08:10:04 PM PDT 24 2650782024 ps
T756 /workspace/coverage/default/81.chip_sw_all_escalation_resets.4246134771 Jul 03 08:20:31 PM PDT 24 Jul 03 08:29:19 PM PDT 24 6209631800 ps
T255 /workspace/coverage/default/0.chip_sw_rv_timer_irq.1122642436 Jul 03 07:48:31 PM PDT 24 Jul 03 07:53:10 PM PDT 24 2636475470 ps
T657 /workspace/coverage/default/4.chip_sw_all_escalation_resets.2967519236 Jul 03 08:13:50 PM PDT 24 Jul 03 08:26:42 PM PDT 24 4696094678 ps
T680 /workspace/coverage/default/36.chip_sw_alert_handler_lpg_sleep_mode_alerts.1188728025 Jul 03 08:18:14 PM PDT 24 Jul 03 08:25:08 PM PDT 24 3344938914 ps
T914 /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_test_unlocked0.3619730107 Jul 03 08:06:34 PM PDT 24 Jul 03 08:20:16 PM PDT 24 4535132972 ps
T274 /workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access.2018147398 Jul 03 08:00:42 PM PDT 24 Jul 03 08:11:07 PM PDT 24 4751476594 ps
T94 /workspace/coverage/default/0.chip_sw_alert_handler_entropy.1593237783 Jul 03 07:51:25 PM PDT 24 Jul 03 07:57:46 PM PDT 24 3549966615 ps
T134 /workspace/coverage/default/1.chip_sw_csrng_lc_hw_debug_en_test.1818067554 Jul 03 07:56:59 PM PDT 24 Jul 03 08:09:38 PM PDT 24 6883236086 ps
T333 /workspace/coverage/default/12.chip_sw_uart_rand_baudrate.2124249929 Jul 03 08:16:15 PM PDT 24 Jul 03 08:39:22 PM PDT 24 8278847960 ps
T915 /workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.2031280512 Jul 03 08:14:14 PM PDT 24 Jul 03 08:38:08 PM PDT 24 13403399346 ps
T916 /workspace/coverage/default/2.chip_sw_pwrmgr_all_reset_reqs.2738828204 Jul 03 08:06:23 PM PDT 24 Jul 03 08:30:53 PM PDT 24 12011743436 ps
T675 /workspace/coverage/default/22.chip_sw_all_escalation_resets.2172865739 Jul 03 08:17:36 PM PDT 24 Jul 03 08:29:25 PM PDT 24 6118398616 ps
T150 /workspace/coverage/default/2.chip_sw_sensor_ctrl_status.3601654800 Jul 03 08:09:47 PM PDT 24 Jul 03 08:14:38 PM PDT 24 3173277481 ps
T95 /workspace/coverage/default/2.chip_sw_alert_handler_entropy.306624793 Jul 03 08:07:29 PM PDT 24 Jul 03 08:11:48 PM PDT 24 3281097446 ps
T917 /workspace/coverage/default/2.chip_sw_aon_timer_wdog_bite_reset.3698614497 Jul 03 08:07:39 PM PDT 24 Jul 03 08:20:12 PM PDT 24 7198115160 ps
T918 /workspace/coverage/default/0.chip_sw_rv_core_ibex_rnd.4205650941 Jul 03 07:49:21 PM PDT 24 Jul 03 08:06:13 PM PDT 24 6118310174 ps
T919 /workspace/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.1753761774 Jul 03 08:11:25 PM PDT 24 Jul 03 08:27:22 PM PDT 24 7376342487 ps
T920 /workspace/coverage/default/2.chip_sw_flash_ctrl_mem_protection.4179247667 Jul 03 08:18:20 PM PDT 24 Jul 03 08:39:40 PM PDT 24 5532695324 ps
T356 /workspace/coverage/default/77.chip_sw_alert_handler_lpg_sleep_mode_alerts.3694167897 Jul 03 08:21:07 PM PDT 24 Jul 03 08:27:49 PM PDT 24 4149497698 ps
T359 /workspace/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.3405241814 Jul 03 07:56:44 PM PDT 24 Jul 03 08:15:44 PM PDT 24 7172220371 ps
T360 /workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_por_reset.463979766 Jul 03 08:05:27 PM PDT 24 Jul 03 08:14:33 PM PDT 24 7360500644 ps
T353 /workspace/coverage/default/2.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.3059904244 Jul 03 08:10:22 PM PDT 24 Jul 03 08:16:00 PM PDT 24 4806733296 ps
T361 /workspace/coverage/default/26.chip_sw_alert_handler_lpg_sleep_mode_alerts.2536919505 Jul 03 08:17:21 PM PDT 24 Jul 03 08:24:10 PM PDT 24 3988678600 ps
T362 /workspace/coverage/default/1.chip_sw_keymgr_sideload_kmac.1360097530 Jul 03 07:58:37 PM PDT 24 Jul 03 08:28:17 PM PDT 24 8056936104 ps
T11 /workspace/coverage/default/0.chip_sw_sleep_pin_retention.356552255 Jul 03 07:50:00 PM PDT 24 Jul 03 07:56:11 PM PDT 24 4682452456 ps
T363 /workspace/coverage/default/85.chip_sw_alert_handler_lpg_sleep_mode_alerts.1011257239 Jul 03 08:21:38 PM PDT 24 Jul 03 08:27:13 PM PDT 24 3585960376 ps
T364 /workspace/coverage/default/41.chip_sw_all_escalation_resets.1982697387 Jul 03 08:19:02 PM PDT 24 Jul 03 08:30:42 PM PDT 24 5036186392 ps
T297 /workspace/coverage/default/94.chip_sw_all_escalation_resets.2270059844 Jul 03 08:23:06 PM PDT 24 Jul 03 08:33:28 PM PDT 24 4944220404 ps
T921 /workspace/coverage/default/1.chip_sw_hmac_enc_jitter_en_reduced_freq.3194010516 Jul 03 08:01:29 PM PDT 24 Jul 03 08:05:58 PM PDT 24 3014747953 ps
T922 /workspace/coverage/default/8.chip_sw_lc_ctrl_transition.1518676308 Jul 03 08:16:43 PM PDT 24 Jul 03 08:34:09 PM PDT 24 10530177019 ps
T168 /workspace/coverage/default/1.chip_sw_spi_device_pass_through_collision.1678064791 Jul 03 07:56:16 PM PDT 24 Jul 03 08:04:32 PM PDT 24 3341395106 ps
T709 /workspace/coverage/default/30.chip_sw_all_escalation_resets.3167351116 Jul 03 08:19:45 PM PDT 24 Jul 03 08:29:25 PM PDT 24 5964437928 ps
T37 /workspace/coverage/default/0.chip_sw_usbdev_pincfg.3149001347 Jul 03 07:47:22 PM PDT 24 Jul 03 09:37:33 PM PDT 24 31988505994 ps
T923 /workspace/coverage/default/0.chip_sw_entropy_src_smoketest.2824137442 Jul 03 07:53:31 PM PDT 24 Jul 03 07:59:54 PM PDT 24 3727380200 ps
T924 /workspace/coverage/default/14.chip_sw_uart_rand_baudrate.932123269 Jul 03 08:17:31 PM PDT 24 Jul 03 08:42:59 PM PDT 24 8297453176 ps
T727 /workspace/coverage/default/3.chip_sw_all_escalation_resets.4287690871 Jul 03 08:13:59 PM PDT 24 Jul 03 08:27:43 PM PDT 24 5327592280 ps
T925 /workspace/coverage/default/0.chip_sw_otbn_randomness.2674393555 Jul 03 07:47:59 PM PDT 24 Jul 03 08:04:36 PM PDT 24 6678144000 ps
T684 /workspace/coverage/default/56.chip_sw_alert_handler_lpg_sleep_mode_alerts.572641918 Jul 03 08:23:53 PM PDT 24 Jul 03 08:29:38 PM PDT 24 3494264312 ps
T926 /workspace/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.3535177014 Jul 03 08:05:33 PM PDT 24 Jul 03 08:31:02 PM PDT 24 7359800546 ps
T927 /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_por_reset.1798738677 Jul 03 07:58:45 PM PDT 24 Jul 03 08:10:22 PM PDT 24 8601324812 ps
T928 /workspace/coverage/default/1.chip_sw_aes_enc.3468610264 Jul 03 08:03:20 PM PDT 24 Jul 03 08:07:17 PM PDT 24 3434343630 ps
T749 /workspace/coverage/default/72.chip_sw_all_escalation_resets.1858334640 Jul 03 08:20:57 PM PDT 24 Jul 03 08:31:16 PM PDT 24 5808816942 ps
T929 /workspace/coverage/default/0.chip_sw_clkmgr_smoketest.3137073877 Jul 03 07:55:17 PM PDT 24 Jul 03 07:59:31 PM PDT 24 3439283182 ps
T930 /workspace/coverage/default/10.chip_sw_uart_rand_baudrate.453409164 Jul 03 08:16:56 PM PDT 24 Jul 03 08:48:15 PM PDT 24 7793022582 ps
T757 /workspace/coverage/default/85.chip_sw_all_escalation_resets.3089512249 Jul 03 08:22:18 PM PDT 24 Jul 03 08:33:23 PM PDT 24 5940145700 ps
T81 /workspace/coverage/default/0.chip_tap_straps_testunlock0.2648577772 Jul 03 07:50:21 PM PDT 24 Jul 03 07:56:58 PM PDT 24 4783504114 ps
T38 /workspace/coverage/default/0.chip_sw_usbdev_config_host.4240065041 Jul 03 07:49:35 PM PDT 24 Jul 03 08:25:34 PM PDT 24 8066915424 ps
T931 /workspace/coverage/default/2.chip_sw_lc_ctrl_transition.520955328 Jul 03 08:06:30 PM PDT 24 Jul 03 08:18:25 PM PDT 24 6467807368 ps
T710 /workspace/coverage/default/34.chip_sw_alert_handler_lpg_sleep_mode_alerts.3507979650 Jul 03 08:17:53 PM PDT 24 Jul 03 08:27:02 PM PDT 24 4342255394 ps
T932 /workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.3017800053 Jul 03 07:47:31 PM PDT 24 Jul 03 07:58:07 PM PDT 24 4999375455 ps
T327 /workspace/coverage/default/0.chip_sw_flash_ctrl_ops.3923337098 Jul 03 07:47:54 PM PDT 24 Jul 03 07:57:36 PM PDT 24 4431265860 ps
T39 /workspace/coverage/default/1.chip_sw_gpio.2474619986 Jul 03 07:56:05 PM PDT 24 Jul 03 08:04:10 PM PDT 24 3583501044 ps
T933 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_dev.4017588752 Jul 03 07:59:39 PM PDT 24 Jul 03 09:36:19 PM PDT 24 23357964050 ps
T687 /workspace/coverage/default/23.chip_sw_alert_handler_lpg_sleep_mode_alerts.2132399819 Jul 03 08:17:34 PM PDT 24 Jul 03 08:24:45 PM PDT 24 3451321588 ps
T349 /workspace/coverage/default/2.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.2254214187 Jul 03 08:10:43 PM PDT 24 Jul 03 08:20:11 PM PDT 24 5661440524 ps
T717 /workspace/coverage/default/7.chip_sw_all_escalation_resets.2145884050 Jul 03 08:16:45 PM PDT 24 Jul 03 08:25:41 PM PDT 24 5728689562 ps
T758 /workspace/coverage/default/82.chip_sw_all_escalation_resets.4189500396 Jul 03 08:21:51 PM PDT 24 Jul 03 08:32:41 PM PDT 24 5088988812 ps
T934 /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_wake_5_bug.2218692491 Jul 03 07:52:06 PM PDT 24 Jul 03 08:02:06 PM PDT 24 5587123712 ps
T317 /workspace/coverage/default/1.chip_sw_i2c_host_tx_rx_idx2.3191653249 Jul 03 07:56:03 PM PDT 24 Jul 03 08:13:30 PM PDT 24 5330644856 ps
T226 /workspace/coverage/default/1.chip_sw_keymgr_sideload_otbn.3462050924 Jul 03 07:58:56 PM PDT 24 Jul 03 08:51:43 PM PDT 24 12747605356 ps
T187 /workspace/coverage/default/2.chip_sw_otp_ctrl_vendor_test_csr_access.2575613728 Jul 03 08:05:55 PM PDT 24 Jul 03 08:10:32 PM PDT 24 2995676041 ps
T180 /workspace/coverage/default/1.chip_plic_all_irqs_10.2552397123 Jul 03 08:01:18 PM PDT 24 Jul 03 08:09:40 PM PDT 24 4122031976 ps
T935 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0.3299237523 Jul 03 07:56:07 PM PDT 24 Jul 03 08:47:03 PM PDT 24 11313309043 ps
T936 /workspace/coverage/default/0.chip_sw_otp_ctrl_ecc_error_vendor_test.3424831406 Jul 03 07:51:00 PM PDT 24 Jul 03 07:55:50 PM PDT 24 2790395962 ps
T67 /workspace/coverage/default/2.chip_sw_alert_test.577211726 Jul 03 08:06:42 PM PDT 24 Jul 03 08:12:03 PM PDT 24 2747412472 ps
T937 /workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq.4112611788 Jul 03 08:14:39 PM PDT 24 Jul 03 08:44:35 PM PDT 24 9163728741 ps
T174 /workspace/coverage/default/2.chip_sw_sysrst_ctrl_reset.211983497 Jul 03 08:07:30 PM PDT 24 Jul 03 08:36:31 PM PDT 24 24796860408 ps
T8 /workspace/coverage/default/1.chip_rv_dm_ndm_reset_req.3719752883 Jul 03 08:01:14 PM PDT 24 Jul 03 08:11:42 PM PDT 24 4513445200 ps
T938 /workspace/coverage/default/6.chip_sw_lc_ctrl_transition.2817015112 Jul 03 08:14:45 PM PDT 24 Jul 03 08:39:01 PM PDT 24 12222908514 ps
T387 /workspace/coverage/default/77.chip_sw_all_escalation_resets.667735068 Jul 03 08:22:06 PM PDT 24 Jul 03 08:32:40 PM PDT 24 5926610990 ps
T721 /workspace/coverage/default/60.chip_sw_all_escalation_resets.2920371570 Jul 03 08:19:46 PM PDT 24 Jul 03 08:30:09 PM PDT 24 5365843760 ps
T939 /workspace/coverage/default/1.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.2565667767 Jul 03 08:02:26 PM PDT 24 Jul 03 08:24:57 PM PDT 24 9153905537 ps
T383 /workspace/coverage/default/0.chip_sw_usbdev_stream.3306160042 Jul 03 07:49:15 PM PDT 24 Jul 03 09:07:36 PM PDT 24 19114320684 ps
T940 /workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.1820672663 Jul 03 08:11:50 PM PDT 24 Jul 03 09:31:44 PM PDT 24 25362119765 ps
T683 /workspace/coverage/default/67.chip_sw_all_escalation_resets.2002974718 Jul 03 08:20:12 PM PDT 24 Jul 03 08:30:44 PM PDT 24 4819090552 ps
T307 /workspace/coverage/default/0.chip_plic_all_irqs_20.1587440122 Jul 03 07:50:42 PM PDT 24 Jul 03 08:03:00 PM PDT 24 4488644682 ps
T941 /workspace/coverage/default/1.chip_sw_alert_handler_escalation.1615059912 Jul 03 07:58:47 PM PDT 24 Jul 03 08:08:53 PM PDT 24 5303806408 ps
T243 /workspace/coverage/default/0.chip_sw_rstmgr_cpu_info.2833814174 Jul 03 07:50:03 PM PDT 24 Jul 03 07:59:17 PM PDT 24 4725347856 ps
T24 /workspace/coverage/default/2.chip_sw_sleep_pin_mio_dio_val.952059584 Jul 03 08:04:20 PM PDT 24 Jul 03 08:08:22 PM PDT 24 3017631825 ps
T263 /workspace/coverage/default/0.chip_sw_alert_handler_ping_timeout.1481271136 Jul 03 07:50:49 PM PDT 24 Jul 03 08:01:43 PM PDT 24 6268653184 ps
T98 /workspace/coverage/default/25.chip_sw_alert_handler_lpg_sleep_mode_alerts.2971026837 Jul 03 08:17:56 PM PDT 24 Jul 03 08:26:04 PM PDT 24 3412147392 ps
T99 /workspace/coverage/default/86.chip_sw_alert_handler_lpg_sleep_mode_alerts.3963182751 Jul 03 08:22:15 PM PDT 24 Jul 03 08:27:54 PM PDT 24 3019469752 ps
T140 /workspace/coverage/default/3.chip_sw_sensor_ctrl_alert.4136534374 Jul 03 08:14:14 PM PDT 24 Jul 03 08:27:22 PM PDT 24 5816797392 ps
T121 /workspace/coverage/default/2.chip_sw_csrng_edn_concurrency_reduced_freq.3470875341 Jul 03 08:17:12 PM PDT 24 Jul 03 09:18:22 PM PDT 24 19509743067 ps
T264 /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.3757557214 Jul 03 07:55:21 PM PDT 24 Jul 03 08:24:32 PM PDT 24 18077512821 ps
T265 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0.230782417 Jul 03 07:56:12 PM PDT 24 Jul 03 08:44:20 PM PDT 24 11515907620 ps
T266 /workspace/coverage/default/37.chip_sw_alert_handler_lpg_sleep_mode_alerts.1783769869 Jul 03 08:18:57 PM PDT 24 Jul 03 08:25:09 PM PDT 24 3851214988 ps
T942 /workspace/coverage/default/9.chip_sw_lc_ctrl_transition.582877454 Jul 03 08:16:19 PM PDT 24 Jul 03 08:31:53 PM PDT 24 9937550445 ps
T668 /workspace/coverage/default/50.chip_sw_alert_handler_lpg_sleep_mode_alerts.1799815439 Jul 03 08:21:08 PM PDT 24 Jul 03 08:29:07 PM PDT 24 3498474490 ps
T666 /workspace/coverage/default/19.chip_sw_all_escalation_resets.2722900073 Jul 03 08:19:21 PM PDT 24 Jul 03 08:33:07 PM PDT 24 4981344620 ps
T743 /workspace/coverage/default/8.chip_sw_alert_handler_lpg_sleep_mode_alerts.2495886770 Jul 03 08:16:03 PM PDT 24 Jul 03 08:23:20 PM PDT 24 3879079144 ps
T943 /workspace/coverage/default/1.chip_sw_aes_masking_off.3986267719 Jul 03 07:57:14 PM PDT 24 Jul 03 08:04:03 PM PDT 24 2660770878 ps
T667 /workspace/coverage/default/63.chip_sw_all_escalation_resets.2952200167 Jul 03 08:20:13 PM PDT 24 Jul 03 08:31:21 PM PDT 24 4443547280 ps
T247 /workspace/coverage/default/28.chip_sw_alert_handler_lpg_sleep_mode_alerts.2704286855 Jul 03 08:18:11 PM PDT 24 Jul 03 08:23:50 PM PDT 24 4003831540 ps
T347 /workspace/coverage/default/2.chip_sw_hmac_enc_jitter_en_reduced_freq.1870320405 Jul 03 08:11:52 PM PDT 24 Jul 03 08:17:28 PM PDT 24 3070042022 ps
T332 /workspace/coverage/default/1.chip_sival_flash_info_access.994217210 Jul 03 07:52:07 PM PDT 24 Jul 03 07:57:42 PM PDT 24 3571525932 ps
T944 /workspace/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en.279145782 Jul 03 07:48:52 PM PDT 24 Jul 03 08:09:17 PM PDT 24 6575690554 ps
T945 /workspace/coverage/default/2.chip_sw_lc_walkthrough_testunlocks.2325137930 Jul 03 08:05:35 PM PDT 24 Jul 03 08:44:58 PM PDT 24 25935398391 ps
T946 /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.3592981007 Jul 03 08:00:47 PM PDT 24 Jul 03 08:11:24 PM PDT 24 3781674520 ps
T111 /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_wake_ups.3556945614 Jul 03 08:01:17 PM PDT 24 Jul 03 08:30:25 PM PDT 24 26056201742 ps
T760 /workspace/coverage/default/29.chip_sw_alert_handler_lpg_sleep_mode_alerts.2100322509 Jul 03 08:17:52 PM PDT 24 Jul 03 08:24:15 PM PDT 24 3704362696 ps
T947 /workspace/coverage/default/2.chip_sw_aon_timer_irq.1264411298 Jul 03 08:06:22 PM PDT 24 Jul 03 08:13:45 PM PDT 24 3402679032 ps
T308 /workspace/coverage/default/2.chip_plic_all_irqs_0.3277766369 Jul 03 08:08:34 PM PDT 24 Jul 03 08:28:03 PM PDT 24 6222495420 ps
T948 /workspace/coverage/default/2.chip_sw_clkmgr_off_kmac_trans.315678176 Jul 03 08:08:31 PM PDT 24 Jul 03 08:15:44 PM PDT 24 4477725616 ps
T949 /workspace/coverage/default/0.chip_sw_aon_timer_wdog_lc_escalate.301274102 Jul 03 07:50:35 PM PDT 24 Jul 03 07:58:59 PM PDT 24 4060245528 ps
T738 /workspace/coverage/default/12.chip_sw_alert_handler_lpg_sleep_mode_alerts.18060673 Jul 03 08:18:17 PM PDT 24 Jul 03 08:25:11 PM PDT 24 4145594136 ps
T950 /workspace/coverage/default/0.chip_sw_aes_enc_jitter_en_reduced_freq.3991017452 Jul 03 07:50:29 PM PDT 24 Jul 03 07:56:16 PM PDT 24 2951803842 ps
T10 /workspace/coverage/default/1.chip_sw_sleep_pin_wake.1877211665 Jul 03 07:58:03 PM PDT 24 Jul 03 08:03:29 PM PDT 24 3488005000 ps
T408 /workspace/coverage/default/2.chip_sw_edn_sw_mode.1413009191 Jul 03 08:08:43 PM PDT 24 Jul 03 08:40:38 PM PDT 24 8948852352 ps
T409 /workspace/coverage/default/14.chip_sw_all_escalation_resets.1703967428 Jul 03 08:16:21 PM PDT 24 Jul 03 08:27:04 PM PDT 24 5288514770 ps
T259 /workspace/coverage/default/0.chip_sw_rv_core_ibex_lockstep_glitch.1028799190 Jul 03 07:53:55 PM PDT 24 Jul 03 07:56:45 PM PDT 24 2587364720 ps
T410 /workspace/coverage/default/0.chip_sw_usbdev_dpi.2045136005 Jul 03 07:46:55 PM PDT 24 Jul 03 08:38:47 PM PDT 24 12816229760 ps
T411 /workspace/coverage/default/2.chip_tap_straps_dev.2325619659 Jul 03 08:09:15 PM PDT 24 Jul 03 08:11:40 PM PDT 24 2940901603 ps
T53 /workspace/coverage/default/1.chip_sw_sysrst_ctrl_ulp_z3_wakeup.2333736586 Jul 03 07:55:18 PM PDT 24 Jul 03 08:02:20 PM PDT 24 5567727880 ps
T412 /workspace/coverage/default/25.chip_sw_all_escalation_resets.1879092954 Jul 03 08:17:51 PM PDT 24 Jul 03 08:26:54 PM PDT 24 4557113024 ps
T413 /workspace/coverage/default/2.chip_sw_power_sleep_load.4097655903 Jul 03 08:11:07 PM PDT 24 Jul 03 08:22:17 PM PDT 24 10172914590 ps
T414 /workspace/coverage/default/51.chip_sw_alert_handler_lpg_sleep_mode_alerts.147589972 Jul 03 08:20:30 PM PDT 24 Jul 03 08:26:55 PM PDT 24 3431117434 ps
T701 /workspace/coverage/default/41.chip_sw_alert_handler_lpg_sleep_mode_alerts.3217905531 Jul 03 08:22:04 PM PDT 24 Jul 03 08:30:00 PM PDT 24 3962589420 ps
T624 /workspace/coverage/default/0.chip_sw_lc_ctrl_rma_to_scrap.1003728809 Jul 03 07:50:58 PM PDT 24 Jul 03 07:53:08 PM PDT 24 2556603513 ps
T951 /workspace/coverage/default/2.chip_sw_hmac_enc_idle.3275429321 Jul 03 08:07:41 PM PDT 24 Jul 03 08:13:02 PM PDT 24 2939492528 ps
T952 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.425452936 Jul 03 07:55:56 PM PDT 24 Jul 03 08:54:04 PM PDT 24 14457899691 ps
T953 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.72465416 Jul 03 07:50:11 PM PDT 24 Jul 03 08:02:03 PM PDT 24 4493818674 ps
T236 /workspace/coverage/default/1.chip_sw_flash_ctrl_lc_rw_en.3860755893 Jul 03 07:52:49 PM PDT 24 Jul 03 07:59:54 PM PDT 24 5915187788 ps
T954 /workspace/coverage/default/0.chip_sw_clkmgr_jitter.1718701365 Jul 03 07:50:15 PM PDT 24 Jul 03 07:53:49 PM PDT 24 2686119138 ps
T424 /workspace/coverage/default/0.chip_sw_edn_entropy_reqs.1985429469 Jul 03 07:48:34 PM PDT 24 Jul 03 08:09:12 PM PDT 24 7083159832 ps
T25 /workspace/coverage/default/0.chip_sw_sleep_pin_mio_dio_val.1207945439 Jul 03 07:47:03 PM PDT 24 Jul 03 07:51:47 PM PDT 24 3226685015 ps
T248 /workspace/coverage/default/74.chip_sw_alert_handler_lpg_sleep_mode_alerts.3428136760 Jul 03 08:21:44 PM PDT 24 Jul 03 08:28:50 PM PDT 24 3614002584 ps
T955 /workspace/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en.1780100777 Jul 03 07:48:00 PM PDT 24 Jul 03 08:10:17 PM PDT 24 5963011082 ps
T956 /workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.1058865680 Jul 03 08:06:07 PM PDT 24 Jul 03 08:28:07 PM PDT 24 11919839141 ps
T957 /workspace/coverage/default/0.chip_sw_usb_ast_clk_calib.4143287417 Jul 03 07:49:24 PM PDT 24 Jul 03 07:54:45 PM PDT 24 3904613795 ps
T388 /workspace/coverage/default/2.chip_sw_rom_ctrl_integrity_check.3402673316 Jul 03 08:07:42 PM PDT 24 Jul 03 08:16:16 PM PDT 24 9722585784 ps
T739 /workspace/coverage/default/17.chip_sw_all_escalation_resets.1688260882 Jul 03 08:16:44 PM PDT 24 Jul 03 08:25:53 PM PDT 24 5494359980 ps
T237 /workspace/coverage/default/2.chip_sw_flash_init.3563254598 Jul 03 08:04:44 PM PDT 24 Jul 03 08:40:25 PM PDT 24 20890391448 ps
T350 /workspace/coverage/default/1.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.3044838482 Jul 03 08:02:08 PM PDT 24 Jul 03 08:13:49 PM PDT 24 5074677500 ps
T747 /workspace/coverage/default/53.chip_sw_alert_handler_lpg_sleep_mode_alerts.3823627738 Jul 03 08:20:15 PM PDT 24 Jul 03 08:26:21 PM PDT 24 3701579330 ps
T151 /workspace/coverage/default/0.chip_sw_sensor_ctrl_status.1317676977 Jul 03 07:50:57 PM PDT 24 Jul 03 07:55:54 PM PDT 24 2710066105 ps
T371 /workspace/coverage/default/0.chip_sw_edn_boot_mode.2730967746 Jul 03 07:49:04 PM PDT 24 Jul 03 08:00:52 PM PDT 24 2624614880 ps
T720 /workspace/coverage/default/62.chip_sw_alert_handler_lpg_sleep_mode_alerts.1994490518 Jul 03 08:20:34 PM PDT 24 Jul 03 08:29:15 PM PDT 24 3326289892 ps
T958 /workspace/coverage/default/0.chip_sw_clkmgr_off_otbn_trans.2886662710 Jul 03 07:50:32 PM PDT 24 Jul 03 07:59:48 PM PDT 24 5243549376 ps
T232 /workspace/coverage/default/1.chip_sw_flash_init.1820072205 Jul 03 07:56:00 PM PDT 24 Jul 03 08:32:36 PM PDT 24 17320371076 ps
T678 /workspace/coverage/default/15.chip_sw_alert_handler_lpg_sleep_mode_alerts.3680312988 Jul 03 08:16:49 PM PDT 24 Jul 03 08:24:23 PM PDT 24 3862728120 ps
T740 /workspace/coverage/default/95.chip_sw_all_escalation_resets.840540658 Jul 03 08:23:39 PM PDT 24 Jul 03 08:31:21 PM PDT 24 5335810154 ps
T959 /workspace/coverage/default/1.chip_sw_sleep_sram_ret_contents_scramble.864553659 Jul 03 08:00:34 PM PDT 24 Jul 03 08:15:26 PM PDT 24 8634146760 ps
T960 /workspace/coverage/default/1.chip_sw_sysrst_ctrl_ec_rst_l.3496177442 Jul 03 07:56:26 PM PDT 24 Jul 03 08:55:33 PM PDT 24 20207522313 ps
T275 /workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.469691521 Jul 03 08:11:45 PM PDT 24 Jul 03 08:22:49 PM PDT 24 5662601654 ps
T201 /workspace/coverage/default/2.chip_sw_sram_ctrl_execution_main.1177190215 Jul 03 08:09:19 PM PDT 24 Jul 03 08:24:33 PM PDT 24 6941599045 ps
T961 /workspace/coverage/default/2.chip_sw_aes_enc_jitter_en.3065195635 Jul 03 08:09:30 PM PDT 24 Jul 03 08:13:59 PM PDT 24 3291104915 ps
T962 /workspace/coverage/default/2.chip_sw_rstmgr_sw_rst.3784146792 Jul 03 08:05:43 PM PDT 24 Jul 03 08:09:48 PM PDT 24 2780031982 ps
T40 /workspace/coverage/default/0.chip_sw_gpio.2948926601 Jul 03 07:48:20 PM PDT 24 Jul 03 07:55:45 PM PDT 24 4464391042 ps
T963 /workspace/coverage/default/2.chip_sw_otp_ctrl_ecc_error_vendor_test.1883052527 Jul 03 08:05:17 PM PDT 24 Jul 03 08:10:03 PM PDT 24 2637371404 ps
T671 /workspace/coverage/default/45.chip_sw_all_escalation_resets.15667199 Jul 03 08:19:25 PM PDT 24 Jul 03 08:30:21 PM PDT 24 4278449504 ps
T964 /workspace/coverage/default/98.chip_sw_all_escalation_resets.427468637 Jul 03 08:22:06 PM PDT 24 Jul 03 08:31:49 PM PDT 24 6084701940 ps
T699 /workspace/coverage/default/73.chip_sw_all_escalation_resets.1828784593 Jul 03 08:22:13 PM PDT 24 Jul 03 08:32:49 PM PDT 24 4580883944 ps
T679 /workspace/coverage/default/55.chip_sw_all_escalation_resets.3697175906 Jul 03 08:18:59 PM PDT 24 Jul 03 08:28:45 PM PDT 24 4392968088 ps
T965 /workspace/coverage/default/1.chip_sw_clkmgr_jitter_reduced_freq.1619185240 Jul 03 08:01:24 PM PDT 24 Jul 03 08:05:49 PM PDT 24 2414106964 ps
T169 /workspace/coverage/default/1.chip_sw_spi_device_pass_through.3219173649 Jul 03 07:53:36 PM PDT 24 Jul 03 08:07:17 PM PDT 24 7011413589 ps
T966 /workspace/coverage/default/1.chip_sw_rv_core_ibex_rnd.1879924806 Jul 03 07:55:29 PM PDT 24 Jul 03 08:12:22 PM PDT 24 5789191852 ps
T712 /workspace/coverage/default/49.chip_sw_all_escalation_resets.2109675597 Jul 03 08:21:59 PM PDT 24 Jul 03 08:30:52 PM PDT 24 4854114932 ps
T967 /workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq.3899082200 Jul 03 08:15:52 PM PDT 24 Jul 03 08:25:53 PM PDT 24 4044645298 ps
T968 /workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_meas.722921080 Jul 03 08:16:28 PM PDT 24 Jul 03 09:09:21 PM PDT 24 15480552832 ps
T969 /workspace/coverage/default/0.chip_sw_otp_ctrl_dai_lock.2595674434 Jul 03 07:47:37 PM PDT 24 Jul 03 09:15:06 PM PDT 24 27613739240 ps
T970 /workspace/coverage/default/2.chip_sw_pwrmgr_usb_clk_disabled_when_active.427046104 Jul 03 08:05:51 PM PDT 24 Jul 03 08:13:33 PM PDT 24 4159203836 ps
T971 /workspace/coverage/default/1.chip_sw_otbn_randomness.4140445032 Jul 03 07:57:42 PM PDT 24 Jul 03 08:13:59 PM PDT 24 6180736750 ps
T972 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_prod.3815882045 Jul 03 08:02:18 PM PDT 24 Jul 03 09:21:03 PM PDT 24 15406803440 ps
T973 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_dev.4006825052 Jul 03 07:56:41 PM PDT 24 Jul 03 09:00:54 PM PDT 24 14739233962 ps
T638 /workspace/coverage/default/0.chip_sw_plic_sw_irq.1534177991 Jul 03 07:53:03 PM PDT 24 Jul 03 07:58:28 PM PDT 24 2349817512 ps
T974 /workspace/coverage/default/2.chip_sw_edn_kat.451268109 Jul 03 08:08:38 PM PDT 24 Jul 03 08:19:16 PM PDT 24 3466635408 ps
T975 /workspace/coverage/default/2.chip_sw_sram_ctrl_smoketest.1597978290 Jul 03 08:13:10 PM PDT 24 Jul 03 08:17:08 PM PDT 24 2902173008 ps
T41 /workspace/coverage/default/2.chip_sw_gpio.1934256800 Jul 03 08:07:02 PM PDT 24 Jul 03 08:15:42 PM PDT 24 4271300996 ps
T976 /workspace/coverage/default/2.chip_sw_sleep_pwm_pulses.565914361 Jul 03 08:05:04 PM PDT 24 Jul 03 08:25:32 PM PDT 24 9323726032 ps
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