| T977 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_rma.3171392217 |
|
|
Jul 03 07:57:57 PM PDT 24 |
Jul 03 09:42:20 PM PDT 24 |
23108901000 ps |
| T706 |
/workspace/coverage/default/89.chip_sw_all_escalation_resets.905128907 |
|
|
Jul 03 08:22:59 PM PDT 24 |
Jul 03 08:31:36 PM PDT 24 |
6273188036 ps |
| T373 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.2291900587 |
|
|
Jul 03 07:56:27 PM PDT 24 |
Jul 03 09:30:42 PM PDT 24 |
22806263896 ps |
| T978 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.3922860715 |
|
|
Jul 03 08:02:14 PM PDT 24 |
Jul 03 09:19:14 PM PDT 24 |
15068258730 ps |
| T979 |
/workspace/coverage/default/7.chip_sw_uart_rand_baudrate.2867424357 |
|
|
Jul 03 08:15:05 PM PDT 24 |
Jul 03 08:43:35 PM PDT 24 |
8639188500 ps |
| T697 |
/workspace/coverage/default/19.chip_sw_alert_handler_lpg_sleep_mode_alerts.2748152854 |
|
|
Jul 03 08:17:35 PM PDT 24 |
Jul 03 08:23:55 PM PDT 24 |
3669308302 ps |
| T980 |
/workspace/coverage/default/16.chip_sw_uart_rand_baudrate.237933039 |
|
|
Jul 03 08:16:02 PM PDT 24 |
Jul 03 08:47:21 PM PDT 24 |
8712127880 ps |
| T238 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_lc_rw_en.1289993022 |
|
|
Jul 03 07:48:11 PM PDT 24 |
Jul 03 07:54:49 PM PDT 24 |
4185281902 ps |
| T981 |
/workspace/coverage/default/5.chip_sw_lc_ctrl_transition.3498105689 |
|
|
Jul 03 08:13:52 PM PDT 24 |
Jul 03 08:21:04 PM PDT 24 |
5013598854 ps |
| T982 |
/workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.2564849195 |
|
|
Jul 03 08:06:01 PM PDT 24 |
Jul 03 08:33:29 PM PDT 24 |
17379614687 ps |
| T90 |
/workspace/coverage/default/2.chip_jtag_mem_access.268216875 |
|
|
Jul 03 08:02:36 PM PDT 24 |
Jul 03 08:27:31 PM PDT 24 |
13701045605 ps |
| T983 |
/workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_no_meas.3748303251 |
|
|
Jul 03 07:57:24 PM PDT 24 |
Jul 03 08:59:22 PM PDT 24 |
14892199166 ps |
| T984 |
/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_por_reset.181227285 |
|
|
Jul 03 07:49:25 PM PDT 24 |
Jul 03 08:05:31 PM PDT 24 |
9722797642 ps |
| T985 |
/workspace/coverage/default/2.chip_sw_uart_tx_rx_idx3.1031946420 |
|
|
Jul 03 08:05:29 PM PDT 24 |
Jul 03 08:17:25 PM PDT 24 |
4387160048 ps |
| T629 |
/workspace/coverage/default/53.chip_sw_all_escalation_resets.490836075 |
|
|
Jul 03 08:21:14 PM PDT 24 |
Jul 03 08:33:57 PM PDT 24 |
5030907514 ps |
| T65 |
/workspace/coverage/default/2.chip_jtag_csr_rw.2875798918 |
|
|
Jul 03 08:02:27 PM PDT 24 |
Jul 03 08:18:48 PM PDT 24 |
9234631844 ps |
| T141 |
/workspace/coverage/default/2.chip_sw_sensor_ctrl_alert.4142722855 |
|
|
Jul 03 08:07:26 PM PDT 24 |
Jul 03 08:19:20 PM PDT 24 |
7595271876 ps |
| T986 |
/workspace/coverage/default/10.chip_sw_lc_ctrl_transition.1156508059 |
|
|
Jul 03 08:16:48 PM PDT 24 |
Jul 03 08:32:29 PM PDT 24 |
13075778161 ps |
| T234 |
/workspace/coverage/default/2.chip_sw_lc_walkthrough_prod.275416208 |
|
|
Jul 03 08:05:46 PM PDT 24 |
Jul 03 09:30:03 PM PDT 24 |
50473117813 ps |
| T987 |
/workspace/coverage/default/1.chip_sw_kmac_mode_kmac.1369239698 |
|
|
Jul 03 07:58:59 PM PDT 24 |
Jul 03 08:06:41 PM PDT 24 |
3040636048 ps |
| T988 |
/workspace/coverage/default/0.chip_sw_clkmgr_off_hmac_trans.4020853798 |
|
|
Jul 03 07:49:29 PM PDT 24 |
Jul 03 07:57:26 PM PDT 24 |
5279496720 ps |
| T989 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_mem_protection.1780238496 |
|
|
Jul 03 08:02:51 PM PDT 24 |
Jul 03 08:22:27 PM PDT 24 |
5423263428 ps |
| T227 |
/workspace/coverage/default/2.chip_sw_keymgr_sideload_otbn.1673538262 |
|
|
Jul 03 08:07:25 PM PDT 24 |
Jul 03 09:09:39 PM PDT 24 |
15204620912 ps |
| T703 |
/workspace/coverage/default/58.chip_sw_all_escalation_resets.3531380312 |
|
|
Jul 03 08:19:42 PM PDT 24 |
Jul 03 08:28:51 PM PDT 24 |
5295621702 ps |
| T188 |
/workspace/coverage/default/1.chip_sw_otp_ctrl_vendor_test_csr_access.1869132046 |
|
|
Jul 03 07:55:44 PM PDT 24 |
Jul 03 07:59:14 PM PDT 24 |
2861586741 ps |
| T68 |
/workspace/coverage/default/0.chip_sw_alert_test.3375083392 |
|
|
Jul 03 07:48:29 PM PDT 24 |
Jul 03 07:52:42 PM PDT 24 |
3416562000 ps |
| T990 |
/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx2.2019595380 |
|
|
Jul 03 08:13:18 PM PDT 24 |
Jul 03 08:24:15 PM PDT 24 |
4630763530 ps |
| T631 |
/workspace/coverage/default/2.chip_sw_power_idle_load.713168392 |
|
|
Jul 03 08:11:30 PM PDT 24 |
Jul 03 08:23:11 PM PDT 24 |
4789346600 ps |
| T707 |
/workspace/coverage/default/61.chip_sw_all_escalation_resets.3228690790 |
|
|
Jul 03 08:22:14 PM PDT 24 |
Jul 03 08:31:02 PM PDT 24 |
4649225702 ps |
| T241 |
/workspace/coverage/default/1.chip_sw_alert_handler_reverse_ping_in_deep_sleep.2044586970 |
|
|
Jul 03 07:57:19 PM PDT 24 |
Jul 03 11:22:44 PM PDT 24 |
255703617300 ps |
| T276 |
/workspace/coverage/default/2.chip_sw_otbn_mem_scramble.1607429581 |
|
|
Jul 03 08:06:57 PM PDT 24 |
Jul 03 08:17:20 PM PDT 24 |
3395642600 ps |
| T704 |
/workspace/coverage/default/88.chip_sw_all_escalation_resets.2164273714 |
|
|
Jul 03 08:21:00 PM PDT 24 |
Jul 03 08:31:04 PM PDT 24 |
5216459240 ps |
| T991 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_write_clear.2854589975 |
|
|
Jul 03 07:50:07 PM PDT 24 |
Jul 03 07:55:36 PM PDT 24 |
2734037602 ps |
| T992 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.2598743725 |
|
|
Jul 03 08:00:17 PM PDT 24 |
Jul 03 09:11:03 PM PDT 24 |
15781783416 ps |
| T993 |
/workspace/coverage/default/34.chip_sw_all_escalation_resets.2561187679 |
|
|
Jul 03 08:18:52 PM PDT 24 |
Jul 03 08:29:38 PM PDT 24 |
4726786164 ps |
| T994 |
/workspace/coverage/default/15.chip_sw_all_escalation_resets.4250729273 |
|
|
Jul 03 08:18:07 PM PDT 24 |
Jul 03 08:28:16 PM PDT 24 |
5732284350 ps |
| T244 |
/workspace/coverage/default/36.chip_sw_all_escalation_resets.3948575188 |
|
|
Jul 03 08:18:41 PM PDT 24 |
Jul 03 08:29:31 PM PDT 24 |
5077666136 ps |
| T995 |
/workspace/coverage/default/7.chip_sw_lc_ctrl_transition.2419171607 |
|
|
Jul 03 08:16:15 PM PDT 24 |
Jul 03 08:35:23 PM PDT 24 |
13330119876 ps |
| T996 |
/workspace/coverage/default/0.chip_tap_straps_dev.1417508783 |
|
|
Jul 03 07:49:33 PM PDT 24 |
Jul 03 07:59:06 PM PDT 24 |
5906883650 ps |
| T997 |
/workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_invalid_meas.1307424021 |
|
|
Jul 03 08:24:57 PM PDT 24 |
Jul 03 09:37:05 PM PDT 24 |
14328796704 ps |
| T998 |
/workspace/coverage/default/0.chip_sw_pwrmgr_smoketest.3923084891 |
|
|
Jul 03 07:56:57 PM PDT 24 |
Jul 03 08:03:33 PM PDT 24 |
5129910034 ps |
| T999 |
/workspace/coverage/default/2.chip_sw_example_concurrency.2346970740 |
|
|
Jul 03 08:04:07 PM PDT 24 |
Jul 03 08:07:51 PM PDT 24 |
2603212564 ps |
| T321 |
/workspace/coverage/default/2.chip_sw_i2c_device_tx_rx.2623810842 |
|
|
Jul 03 08:05:41 PM PDT 24 |
Jul 03 08:13:58 PM PDT 24 |
4093180264 ps |
| T753 |
/workspace/coverage/default/50.chip_sw_all_escalation_resets.840158267 |
|
|
Jul 03 08:20:34 PM PDT 24 |
Jul 03 08:32:50 PM PDT 24 |
5120531372 ps |
| T96 |
/workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_pings.1937142422 |
|
|
Jul 03 08:07:59 PM PDT 24 |
Jul 03 08:33:17 PM PDT 24 |
14198920990 ps |
| T1000 |
/workspace/coverage/default/1.chip_sw_csrng_fuse_en_sw_app_read_test.1480976888 |
|
|
Jul 03 07:59:23 PM PDT 24 |
Jul 03 08:08:12 PM PDT 24 |
4130952476 ps |
| T625 |
/workspace/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.4278236949 |
|
|
Jul 03 07:47:35 PM PDT 24 |
Jul 03 07:49:25 PM PDT 24 |
1863928725 ps |
| T1001 |
/workspace/coverage/default/5.chip_sw_alert_handler_lpg_sleep_mode_alerts.1209123210 |
|
|
Jul 03 08:14:28 PM PDT 24 |
Jul 03 08:20:51 PM PDT 24 |
3290741948 ps |
| T690 |
/workspace/coverage/default/32.chip_sw_alert_handler_lpg_sleep_mode_alerts.4153343956 |
|
|
Jul 03 08:17:39 PM PDT 24 |
Jul 03 08:23:43 PM PDT 24 |
4131088380 ps |
| T1002 |
/workspace/coverage/default/1.chip_sw_rv_timer_irq.1568149503 |
|
|
Jul 03 08:02:42 PM PDT 24 |
Jul 03 08:06:40 PM PDT 24 |
2347977512 ps |
| T1003 |
/workspace/coverage/default/2.rom_e2e_asm_init_test_unlocked0.4132043831 |
|
|
Jul 03 08:24:20 PM PDT 24 |
Jul 03 09:18:53 PM PDT 24 |
11323589038 ps |
| T1004 |
/workspace/coverage/default/2.chip_tap_straps_prod.787086113 |
|
|
Jul 03 08:10:18 PM PDT 24 |
Jul 03 08:12:55 PM PDT 24 |
2702217667 ps |
| T685 |
/workspace/coverage/default/64.chip_sw_alert_handler_lpg_sleep_mode_alerts.480626602 |
|
|
Jul 03 08:22:26 PM PDT 24 |
Jul 03 08:27:39 PM PDT 24 |
3904380034 ps |
| T732 |
/workspace/coverage/default/21.chip_sw_alert_handler_lpg_sleep_mode_alerts.256142126 |
|
|
Jul 03 08:20:17 PM PDT 24 |
Jul 03 08:29:13 PM PDT 24 |
4004879894 ps |
| T746 |
/workspace/coverage/default/49.chip_sw_alert_handler_lpg_sleep_mode_alerts.3494417431 |
|
|
Jul 03 08:18:09 PM PDT 24 |
Jul 03 08:25:43 PM PDT 24 |
4119116728 ps |
| T1005 |
/workspace/coverage/default/1.chip_sw_power_idle_load.3770050831 |
|
|
Jul 03 08:00:58 PM PDT 24 |
Jul 03 08:09:06 PM PDT 24 |
3706301320 ps |
| T1006 |
/workspace/coverage/default/1.chip_sw_example_flash.1137905211 |
|
|
Jul 03 07:53:26 PM PDT 24 |
Jul 03 07:56:58 PM PDT 24 |
3064156712 ps |
| T175 |
/workspace/coverage/default/1.chip_sw_sysrst_ctrl_reset.2584792729 |
|
|
Jul 03 08:00:28 PM PDT 24 |
Jul 03 08:32:36 PM PDT 24 |
23056419520 ps |
| T689 |
/workspace/coverage/default/38.chip_sw_alert_handler_lpg_sleep_mode_alerts.317048797 |
|
|
Jul 03 08:18:25 PM PDT 24 |
Jul 03 08:24:11 PM PDT 24 |
4015875688 ps |
| T1007 |
/workspace/coverage/default/2.chip_sw_kmac_mode_kmac.3234471249 |
|
|
Jul 03 08:07:30 PM PDT 24 |
Jul 03 08:13:04 PM PDT 24 |
3469668080 ps |
| T1008 |
/workspace/coverage/default/0.rom_e2e_shutdown_output.392113293 |
|
|
Jul 03 07:55:31 PM PDT 24 |
Jul 03 08:57:12 PM PDT 24 |
28001482560 ps |
| T425 |
/workspace/coverage/default/1.chip_sw_edn_entropy_reqs.1731139755 |
|
|
Jul 03 07:57:58 PM PDT 24 |
Jul 03 08:18:02 PM PDT 24 |
7250724396 ps |
| T1009 |
/workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_scramble.1855828291 |
|
|
Jul 03 07:50:30 PM PDT 24 |
Jul 03 08:02:39 PM PDT 24 |
8418961740 ps |
| T1010 |
/workspace/coverage/default/75.chip_sw_alert_handler_lpg_sleep_mode_alerts.3017556665 |
|
|
Jul 03 08:21:41 PM PDT 24 |
Jul 03 08:28:35 PM PDT 24 |
3644800256 ps |
| T277 |
/workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access.2752127325 |
|
|
Jul 03 08:09:29 PM PDT 24 |
Jul 03 08:22:52 PM PDT 24 |
5619759608 ps |
| T1011 |
/workspace/coverage/default/2.rom_e2e_shutdown_exception_c.1866165418 |
|
|
Jul 03 08:16:33 PM PDT 24 |
Jul 03 09:11:40 PM PDT 24 |
14371176970 ps |
| T1012 |
/workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.3896921457 |
|
|
Jul 03 08:05:01 PM PDT 24 |
Jul 03 08:22:48 PM PDT 24 |
8442645237 ps |
| T50 |
/workspace/coverage/default/0.chip_sw_spi_host_tx_rx.1901438336 |
|
|
Jul 03 07:47:59 PM PDT 24 |
Jul 03 07:52:47 PM PDT 24 |
3272407970 ps |
| T112 |
/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_wake_ups.197929653 |
|
|
Jul 03 07:51:08 PM PDT 24 |
Jul 03 08:18:51 PM PDT 24 |
25790366280 ps |
| T626 |
/workspace/coverage/default/1.rom_volatile_raw_unlock.108129209 |
|
|
Jul 03 08:04:05 PM PDT 24 |
Jul 03 08:06:02 PM PDT 24 |
2079496507 ps |
| T664 |
/workspace/coverage/default/78.chip_sw_all_escalation_resets.2578640198 |
|
|
Jul 03 08:21:00 PM PDT 24 |
Jul 03 08:30:10 PM PDT 24 |
4669506450 ps |
| T278 |
/workspace/coverage/default/0.chip_sw_otbn_mem_scramble.1222325608 |
|
|
Jul 03 07:48:12 PM PDT 24 |
Jul 03 07:55:06 PM PDT 24 |
3202402824 ps |
| T352 |
/workspace/coverage/default/1.chip_sw_uart_tx_rx_bootstrap.1426639682 |
|
|
Jul 03 07:53:11 PM PDT 24 |
Jul 03 11:29:54 PM PDT 24 |
78601209440 ps |
| T298 |
/workspace/coverage/default/70.chip_sw_all_escalation_resets.2585754895 |
|
|
Jul 03 08:20:13 PM PDT 24 |
Jul 03 08:29:19 PM PDT 24 |
5763747918 ps |
| T1013 |
/workspace/coverage/default/2.chip_sw_aon_timer_wdog_lc_escalate.2256547359 |
|
|
Jul 03 08:06:16 PM PDT 24 |
Jul 03 08:17:24 PM PDT 24 |
6317369608 ps |
| T1014 |
/workspace/coverage/default/0.chip_sw_aon_timer_sleep_wdog_sleep_pause.2328886123 |
|
|
Jul 03 07:49:14 PM PDT 24 |
Jul 03 07:56:38 PM PDT 24 |
7908209736 ps |
| T1015 |
/workspace/coverage/default/0.chip_sw_rv_plic_smoketest.2032600372 |
|
|
Jul 03 07:55:04 PM PDT 24 |
Jul 03 07:59:10 PM PDT 24 |
3150646000 ps |
| T723 |
/workspace/coverage/default/13.chip_sw_all_escalation_resets.3536703269 |
|
|
Jul 03 08:16:04 PM PDT 24 |
Jul 03 08:25:54 PM PDT 24 |
5350740588 ps |
| T1016 |
/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.3906088074 |
|
|
Jul 03 07:52:53 PM PDT 24 |
Jul 03 08:05:06 PM PDT 24 |
5223965850 ps |
| T1017 |
/workspace/coverage/default/2.chip_sw_kmac_mode_cshake.4051891336 |
|
|
Jul 03 08:08:09 PM PDT 24 |
Jul 03 08:13:44 PM PDT 24 |
2808337634 ps |
| T1018 |
/workspace/coverage/default/3.chip_sw_csrng_edn_concurrency.620173267 |
|
|
Jul 03 08:14:17 PM PDT 24 |
Jul 03 09:55:18 PM PDT 24 |
26846831048 ps |
| T1019 |
/workspace/coverage/default/2.chip_sw_edn_entropy_reqs_jitter.2971191762 |
|
|
Jul 03 08:09:30 PM PDT 24 |
Jul 03 08:28:14 PM PDT 24 |
7229622707 ps |
| T759 |
/workspace/coverage/default/90.chip_sw_all_escalation_resets.2239504033 |
|
|
Jul 03 08:21:24 PM PDT 24 |
Jul 03 08:28:20 PM PDT 24 |
5482003468 ps |
| T1020 |
/workspace/coverage/default/30.chip_sw_alert_handler_lpg_sleep_mode_alerts.714417238 |
|
|
Jul 03 08:17:03 PM PDT 24 |
Jul 03 08:21:47 PM PDT 24 |
3701665250 ps |
| T1021 |
/workspace/coverage/default/2.rom_e2e_asm_init_rma.701617403 |
|
|
Jul 03 08:15:45 PM PDT 24 |
Jul 03 09:10:08 PM PDT 24 |
14201270019 ps |
| T627 |
/workspace/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.552501741 |
|
|
Jul 03 07:57:07 PM PDT 24 |
Jul 03 07:59:12 PM PDT 24 |
2191819013 ps |
| T1022 |
/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.2695816366 |
|
|
Jul 03 08:09:39 PM PDT 24 |
Jul 03 08:20:51 PM PDT 24 |
4707780096 ps |
| T193 |
/workspace/coverage/default/2.chip_sw_lc_ctrl_program_error.1163194389 |
|
|
Jul 03 08:10:25 PM PDT 24 |
Jul 03 08:21:00 PM PDT 24 |
5094221222 ps |
| T1023 |
/workspace/coverage/default/4.chip_sw_aon_timer_sleep_wdog_sleep_pause.3369704110 |
|
|
Jul 03 08:14:46 PM PDT 24 |
Jul 03 08:25:29 PM PDT 24 |
8463086360 ps |
| T1024 |
/workspace/coverage/default/1.rom_e2e_smoke.374796314 |
|
|
Jul 03 08:06:07 PM PDT 24 |
Jul 03 09:05:27 PM PDT 24 |
15342185190 ps |
| T322 |
/workspace/coverage/default/1.chip_sw_i2c_device_tx_rx.2370530977 |
|
|
Jul 03 07:56:20 PM PDT 24 |
Jul 03 08:05:24 PM PDT 24 |
3899310040 ps |
| T499 |
/workspace/coverage/default/0.chip_sw_rv_core_ibex_nmi_irq.3114619177 |
|
|
Jul 03 07:49:57 PM PDT 24 |
Jul 03 08:07:52 PM PDT 24 |
5267509816 ps |
| T729 |
/workspace/coverage/default/78.chip_sw_alert_handler_lpg_sleep_mode_alerts.379380604 |
|
|
Jul 03 08:21:06 PM PDT 24 |
Jul 03 08:27:07 PM PDT 24 |
3473083446 ps |
| T1025 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_clock_freqs.187421745 |
|
|
Jul 03 08:08:20 PM PDT 24 |
Jul 03 08:27:24 PM PDT 24 |
5623330890 ps |
| T1026 |
/workspace/coverage/default/0.rom_e2e_asm_init_rma.1772458049 |
|
|
Jul 03 07:56:45 PM PDT 24 |
Jul 03 09:00:33 PM PDT 24 |
14904625760 ps |
| T1027 |
/workspace/coverage/default/2.chip_sw_pwrmgr_smoketest.1921502766 |
|
|
Jul 03 08:12:58 PM PDT 24 |
Jul 03 08:22:35 PM PDT 24 |
7119245384 ps |
| T176 |
/workspace/coverage/default/1.chip_sw_sysrst_ctrl_in_irq.3884269681 |
|
|
Jul 03 08:02:37 PM PDT 24 |
Jul 03 08:13:38 PM PDT 24 |
3790951619 ps |
| T754 |
/workspace/coverage/default/47.chip_sw_all_escalation_resets.2844019607 |
|
|
Jul 03 08:18:32 PM PDT 24 |
Jul 03 08:28:23 PM PDT 24 |
5082331550 ps |
| T1028 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.3505330116 |
|
|
Jul 03 07:59:16 PM PDT 24 |
Jul 03 09:46:06 PM PDT 24 |
18040125280 ps |
| T1029 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod.3717150858 |
|
|
Jul 03 08:01:24 PM PDT 24 |
Jul 03 09:11:21 PM PDT 24 |
14784414671 ps |
| T1030 |
/workspace/coverage/default/1.chip_sw_uart_tx_rx_idx1.1209460968 |
|
|
Jul 03 07:55:08 PM PDT 24 |
Jul 03 08:07:20 PM PDT 24 |
3862075730 ps |
| T1031 |
/workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq.1281475740 |
|
|
Jul 03 07:52:40 PM PDT 24 |
Jul 03 08:23:56 PM PDT 24 |
9129065480 ps |
| T1032 |
/workspace/coverage/default/2.chip_sw_rv_timer_irq.1704988979 |
|
|
Jul 03 08:05:53 PM PDT 24 |
Jul 03 08:10:47 PM PDT 24 |
2758336078 ps |
| T628 |
/workspace/coverage/default/1.chip_sw_lc_ctrl_rand_to_scrap.2453703695 |
|
|
Jul 03 07:53:28 PM PDT 24 |
Jul 03 07:55:45 PM PDT 24 |
3188086623 ps |
| T1033 |
/workspace/coverage/default/0.chip_sw_hmac_enc_idle.2289795526 |
|
|
Jul 03 07:48:38 PM PDT 24 |
Jul 03 07:53:36 PM PDT 24 |
2636972440 ps |
| T1034 |
/workspace/coverage/default/1.chip_sw_pwrmgr_wdog_reset.1828967110 |
|
|
Jul 03 07:55:53 PM PDT 24 |
Jul 03 08:05:14 PM PDT 24 |
4880066920 ps |
| T1035 |
/workspace/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock.706024005 |
|
|
Jul 03 07:54:18 PM PDT 24 |
Jul 03 07:56:07 PM PDT 24 |
2344634255 ps |
| T1036 |
/workspace/coverage/default/0.chip_sw_example_concurrency.1074012513 |
|
|
Jul 03 07:48:39 PM PDT 24 |
Jul 03 07:53:25 PM PDT 24 |
3027280496 ps |
| T694 |
/workspace/coverage/default/46.chip_sw_alert_handler_lpg_sleep_mode_alerts.3908854523 |
|
|
Jul 03 08:19:36 PM PDT 24 |
Jul 03 08:27:17 PM PDT 24 |
4071867710 ps |
| T669 |
/workspace/coverage/default/83.chip_sw_all_escalation_resets.4013238842 |
|
|
Jul 03 08:21:06 PM PDT 24 |
Jul 03 08:31:03 PM PDT 24 |
6043321672 ps |
| T1037 |
/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.556682652 |
|
|
Jul 03 07:51:33 PM PDT 24 |
Jul 03 08:04:42 PM PDT 24 |
4638675952 ps |
| T354 |
/workspace/coverage/default/0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.921211202 |
|
|
Jul 03 07:51:22 PM PDT 24 |
Jul 03 07:57:16 PM PDT 24 |
5134807200 ps |
| T1038 |
/workspace/coverage/default/2.chip_sw_csrng_lc_hw_debug_en_test.2598605123 |
|
|
Jul 03 08:07:21 PM PDT 24 |
Jul 03 08:18:26 PM PDT 24 |
7384655500 ps |
| T695 |
/workspace/coverage/default/38.chip_sw_all_escalation_resets.2057179068 |
|
|
Jul 03 08:24:59 PM PDT 24 |
Jul 03 08:37:06 PM PDT 24 |
6239840840 ps |
| T1039 |
/workspace/coverage/default/3.chip_sw_uart_tx_rx_idx1.597387786 |
|
|
Jul 03 08:14:05 PM PDT 24 |
Jul 03 08:24:46 PM PDT 24 |
4604434776 ps |
| T1040 |
/workspace/coverage/default/0.chip_sw_example_manufacturer.1610068045 |
|
|
Jul 03 07:51:19 PM PDT 24 |
Jul 03 07:55:58 PM PDT 24 |
2943727220 ps |
| T194 |
/workspace/coverage/default/0.chip_sw_lc_ctrl_program_error.373829494 |
|
|
Jul 03 07:51:52 PM PDT 24 |
Jul 03 07:59:57 PM PDT 24 |
4468041506 ps |
| T228 |
/workspace/coverage/default/0.chip_sw_lc_walkthrough_dev.2476147000 |
|
|
Jul 03 07:51:17 PM PDT 24 |
Jul 03 09:29:44 PM PDT 24 |
46912402100 ps |
| T1041 |
/workspace/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en.2030852622 |
|
|
Jul 03 08:08:16 PM PDT 24 |
Jul 03 08:13:19 PM PDT 24 |
3175040208 ps |
| T1042 |
/workspace/coverage/default/0.chip_sw_pwrmgr_wdog_reset.117397825 |
|
|
Jul 03 07:49:32 PM PDT 24 |
Jul 03 07:57:36 PM PDT 24 |
3812459320 ps |
| T1043 |
/workspace/coverage/default/2.chip_sw_aes_enc.1726579973 |
|
|
Jul 03 08:07:35 PM PDT 24 |
Jul 03 08:11:57 PM PDT 24 |
2436701896 ps |
| T1044 |
/workspace/coverage/default/1.chip_tap_straps_dev.905431545 |
|
|
Jul 03 08:00:15 PM PDT 24 |
Jul 03 08:14:09 PM PDT 24 |
8174753310 ps |
| T733 |
/workspace/coverage/default/65.chip_sw_all_escalation_resets.3294417626 |
|
|
Jul 03 08:23:01 PM PDT 24 |
Jul 03 08:32:59 PM PDT 24 |
5449080892 ps |
| T245 |
/workspace/coverage/default/48.chip_sw_all_escalation_resets.3224409316 |
|
|
Jul 03 08:18:21 PM PDT 24 |
Jul 03 08:26:28 PM PDT 24 |
4836353660 ps |
| T235 |
/workspace/coverage/default/0.chip_sw_flash_init_reduced_freq.3789356740 |
|
|
Jul 03 07:49:27 PM PDT 24 |
Jul 03 08:27:27 PM PDT 24 |
25394110997 ps |
| T1045 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_idle_low_power.1684693865 |
|
|
Jul 03 08:05:01 PM PDT 24 |
Jul 03 08:11:01 PM PDT 24 |
3519569124 ps |
| T1046 |
/workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq.3338929943 |
|
|
Jul 03 08:06:31 PM PDT 24 |
Jul 03 08:17:04 PM PDT 24 |
3858541735 ps |
| T1047 |
/workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_no_meas.2267652164 |
|
|
Jul 03 08:10:52 PM PDT 24 |
Jul 03 09:21:57 PM PDT 24 |
14598919570 ps |
| T1048 |
/workspace/coverage/default/1.chip_sw_alert_handler_lpg_reset_toggle.3943475881 |
|
|
Jul 03 07:56:36 PM PDT 24 |
Jul 03 08:24:04 PM PDT 24 |
7017685992 ps |
| T1049 |
/workspace/coverage/default/1.chip_sw_inject_scramble_seed.1057406979 |
|
|
Jul 03 07:52:17 PM PDT 24 |
Jul 03 11:14:42 PM PDT 24 |
65835253338 ps |
| T1050 |
/workspace/coverage/default/2.chip_sw_pwrmgr_main_power_glitch_reset.3549192915 |
|
|
Jul 03 08:08:27 PM PDT 24 |
Jul 03 08:15:40 PM PDT 24 |
4108319574 ps |
| T1051 |
/workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_reset_reqs.2537152916 |
|
|
Jul 03 08:06:28 PM PDT 24 |
Jul 03 08:55:45 PM PDT 24 |
26686078013 ps |
| T665 |
/workspace/coverage/default/9.chip_sw_all_escalation_resets.4041524372 |
|
|
Jul 03 08:16:29 PM PDT 24 |
Jul 03 08:25:25 PM PDT 24 |
6156197700 ps |
| T1052 |
/workspace/coverage/default/0.chip_sw_uart_tx_rx_bootstrap.4047488671 |
|
|
Jul 03 07:48:15 PM PDT 24 |
Jul 03 11:25:31 PM PDT 24 |
78517767450 ps |
| T1053 |
/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_lc.3610074982 |
|
|
Jul 03 08:08:47 PM PDT 24 |
Jul 03 08:18:36 PM PDT 24 |
6493989025 ps |
| T1054 |
/workspace/coverage/default/1.chip_sw_example_rom.513681299 |
|
|
Jul 03 07:52:55 PM PDT 24 |
Jul 03 07:54:43 PM PDT 24 |
1981661190 ps |
| T1055 |
/workspace/coverage/default/1.chip_sw_clkmgr_off_aes_trans.2478833471 |
|
|
Jul 03 08:00:41 PM PDT 24 |
Jul 03 08:09:39 PM PDT 24 |
4426648068 ps |
| T1056 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_access.2930715790 |
|
|
Jul 03 07:56:28 PM PDT 24 |
Jul 03 08:11:26 PM PDT 24 |
4977914352 ps |
| T748 |
/workspace/coverage/default/33.chip_sw_all_escalation_resets.2990756122 |
|
|
Jul 03 08:17:52 PM PDT 24 |
Jul 03 08:25:48 PM PDT 24 |
4359200932 ps |
| T1057 |
/workspace/coverage/default/1.chip_sw_clkmgr_reset_frequency.530322765 |
|
|
Jul 03 08:00:31 PM PDT 24 |
Jul 03 08:09:34 PM PDT 24 |
3748000084 ps |
| T1058 |
/workspace/coverage/default/3.chip_sw_lc_ctrl_transition.3544304337 |
|
|
Jul 03 08:13:28 PM PDT 24 |
Jul 03 08:26:00 PM PDT 24 |
12499750054 ps |
| T722 |
/workspace/coverage/default/57.chip_sw_all_escalation_resets.2940576233 |
|
|
Jul 03 08:19:19 PM PDT 24 |
Jul 03 08:30:55 PM PDT 24 |
5424546608 ps |
| T357 |
/workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_alerts.1855736282 |
|
|
Jul 03 07:56:09 PM PDT 24 |
Jul 03 08:03:19 PM PDT 24 |
3743314200 ps |
| T1059 |
/workspace/coverage/default/0.chip_sw_lc_ctrl_transition.1179829331 |
|
|
Jul 03 07:47:46 PM PDT 24 |
Jul 03 08:09:15 PM PDT 24 |
8954675156 ps |
| T1060 |
/workspace/coverage/default/19.chip_sw_uart_rand_baudrate.3453000588 |
|
|
Jul 03 08:18:07 PM PDT 24 |
Jul 03 08:25:54 PM PDT 24 |
4332141824 ps |
| T1061 |
/workspace/coverage/default/1.chip_sw_lc_walkthrough_prodend.2455043397 |
|
|
Jul 03 07:54:01 PM PDT 24 |
Jul 03 08:09:34 PM PDT 24 |
10011657856 ps |
| T1062 |
/workspace/coverage/default/2.chip_sw_flash_crash_alert.968240698 |
|
|
Jul 03 08:11:39 PM PDT 24 |
Jul 03 08:23:05 PM PDT 24 |
6046189784 ps |
| T637 |
/workspace/coverage/default/2.chip_sw_pwrmgr_sleep_disabled.678172504 |
|
|
Jul 03 08:06:38 PM PDT 24 |
Jul 03 08:13:17 PM PDT 24 |
3419154060 ps |
| T1063 |
/workspace/coverage/default/2.chip_sw_rstmgr_sw_req.2459431299 |
|
|
Jul 03 08:06:15 PM PDT 24 |
Jul 03 08:14:40 PM PDT 24 |
3535314760 ps |
| T735 |
/workspace/coverage/default/5.chip_sw_all_escalation_resets.3959290692 |
|
|
Jul 03 08:14:11 PM PDT 24 |
Jul 03 08:24:00 PM PDT 24 |
5321410756 ps |
| T1064 |
/workspace/coverage/default/2.chip_sw_csrng_edn_concurrency.1003779318 |
|
|
Jul 03 08:08:15 PM PDT 24 |
Jul 03 08:53:48 PM PDT 24 |
13350406700 ps |
| T1065 |
/workspace/coverage/default/1.chip_sw_sleep_sram_ret_contents_no_scramble.152700339 |
|
|
Jul 03 07:59:34 PM PDT 24 |
Jul 03 08:08:27 PM PDT 24 |
6043379832 ps |
| T1066 |
/workspace/coverage/default/2.chip_sw_csrng_fuse_en_sw_app_read_test.514265147 |
|
|
Jul 03 08:08:19 PM PDT 24 |
Jul 03 08:16:38 PM PDT 24 |
4330720944 ps |
| T1067 |
/workspace/coverage/default/1.chip_sw_otp_ctrl_smoketest.3202884606 |
|
|
Jul 03 08:05:25 PM PDT 24 |
Jul 03 08:10:09 PM PDT 24 |
2780898630 ps |
| T1068 |
/workspace/coverage/default/14.chip_sw_lc_ctrl_transition.2034843228 |
|
|
Jul 03 08:16:31 PM PDT 24 |
Jul 03 08:25:12 PM PDT 24 |
8012241558 ps |
| T1069 |
/workspace/coverage/default/0.chip_sw_edn_kat.1535391861 |
|
|
Jul 03 07:49:51 PM PDT 24 |
Jul 03 07:59:17 PM PDT 24 |
2900229448 ps |
| T279 |
/workspace/coverage/default/2.chip_sw_data_integrity_escalation.1317297004 |
|
|
Jul 03 08:05:20 PM PDT 24 |
Jul 03 08:17:12 PM PDT 24 |
4687387800 ps |
| T1070 |
/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.3440156293 |
|
|
Jul 03 08:08:58 PM PDT 24 |
Jul 03 08:18:46 PM PDT 24 |
4357788276 ps |
| T1071 |
/workspace/coverage/default/0.chip_sw_flash_scrambling_smoketest.2355500094 |
|
|
Jul 03 08:00:51 PM PDT 24 |
Jul 03 08:05:31 PM PDT 24 |
2797997482 ps |
| T223 |
/workspace/coverage/default/0.chip_sw_keymgr_sideload_aes.1813518532 |
|
|
Jul 03 07:49:29 PM PDT 24 |
Jul 03 08:31:39 PM PDT 24 |
11613709368 ps |
| T1072 |
/workspace/coverage/default/1.chip_sw_hmac_enc_idle.3452118747 |
|
|
Jul 03 07:57:52 PM PDT 24 |
Jul 03 08:04:58 PM PDT 24 |
2958932200 ps |
| T1073 |
/workspace/coverage/default/4.chip_sw_data_integrity_escalation.1580038365 |
|
|
Jul 03 08:13:40 PM PDT 24 |
Jul 03 08:24:18 PM PDT 24 |
5508733868 ps |
| T75 |
/workspace/coverage/default/0.chip_tap_straps_rma.565802348 |
|
|
Jul 03 07:53:29 PM PDT 24 |
Jul 03 07:57:34 PM PDT 24 |
3204161887 ps |
| T293 |
/workspace/coverage/default/1.chip_sw_sram_ctrl_execution_main.3682332882 |
|
|
Jul 03 07:59:41 PM PDT 24 |
Jul 03 08:11:23 PM PDT 24 |
7186814595 ps |
| T1074 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_access.3082592687 |
|
|
Jul 03 08:06:01 PM PDT 24 |
Jul 03 08:24:47 PM PDT 24 |
5550222632 ps |
| T1075 |
/workspace/coverage/default/2.chip_sw_uart_tx_rx_bootstrap.3893218688 |
|
|
Jul 03 08:06:31 PM PDT 24 |
Jul 04 12:06:27 AM PDT 24 |
78418541584 ps |
| T1076 |
/workspace/coverage/default/0.chip_sw_inject_scramble_seed.170590555 |
|
|
Jul 03 07:48:03 PM PDT 24 |
Jul 03 11:23:30 PM PDT 24 |
64830145509 ps |
| T1077 |
/workspace/coverage/default/0.chip_sw_uart_rand_baudrate.2656326526 |
|
|
Jul 03 07:52:01 PM PDT 24 |
Jul 03 08:03:16 PM PDT 24 |
3846083144 ps |
| T730 |
/workspace/coverage/default/74.chip_sw_all_escalation_resets.1249740636 |
|
|
Jul 03 08:23:24 PM PDT 24 |
Jul 03 08:31:50 PM PDT 24 |
4351163880 ps |
| T202 |
/workspace/coverage/default/1.chip_sw_rv_core_ibex_icache_invalidate.2783591250 |
|
|
Jul 03 08:01:34 PM PDT 24 |
Jul 03 08:06:33 PM PDT 24 |
2911961063 ps |
| T708 |
/workspace/coverage/default/88.chip_sw_alert_handler_lpg_sleep_mode_alerts.2494532570 |
|
|
Jul 03 08:21:37 PM PDT 24 |
Jul 03 08:29:05 PM PDT 24 |
3790683936 ps |
| T1078 |
/workspace/coverage/default/2.rom_e2e_asm_init_prod.2200084305 |
|
|
Jul 03 08:24:43 PM PDT 24 |
Jul 03 09:38:35 PM PDT 24 |
15303460496 ps |
| T1079 |
/workspace/coverage/default/2.chip_sw_aes_masking_off.920428454 |
|
|
Jul 03 08:07:22 PM PDT 24 |
Jul 03 08:12:57 PM PDT 24 |
2815161043 ps |
| T1080 |
/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.2358620417 |
|
|
Jul 03 07:48:42 PM PDT 24 |
Jul 03 07:58:07 PM PDT 24 |
4964307568 ps |
| T1081 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_prod.1776533062 |
|
|
Jul 03 07:59:56 PM PDT 24 |
Jul 03 09:34:52 PM PDT 24 |
23337674802 ps |
| T736 |
/workspace/coverage/default/31.chip_sw_all_escalation_resets.856024152 |
|
|
Jul 03 08:17:41 PM PDT 24 |
Jul 03 08:26:51 PM PDT 24 |
4085525040 ps |
| T1082 |
/workspace/coverage/default/6.chip_sw_uart_rand_baudrate.3122636164 |
|
|
Jul 03 08:14:27 PM PDT 24 |
Jul 03 08:39:24 PM PDT 24 |
8836798780 ps |
| T1083 |
/workspace/coverage/default/2.chip_sw_aes_smoketest.804018473 |
|
|
Jul 03 08:12:30 PM PDT 24 |
Jul 03 08:16:39 PM PDT 24 |
2239884776 ps |
| T1084 |
/workspace/coverage/default/1.chip_sw_entropy_src_smoketest.2201392711 |
|
|
Jul 03 08:05:20 PM PDT 24 |
Jul 03 08:12:28 PM PDT 24 |
3521142536 ps |
| T1085 |
/workspace/coverage/default/0.chip_sw_aes_masking_off.2937816315 |
|
|
Jul 03 07:49:37 PM PDT 24 |
Jul 03 07:55:06 PM PDT 24 |
3065701547 ps |
| T1086 |
/workspace/coverage/default/1.chip_sw_sleep_pwm_pulses.1709031647 |
|
|
Jul 03 07:54:36 PM PDT 24 |
Jul 03 08:21:47 PM PDT 24 |
9205435504 ps |
| T324 |
/workspace/coverage/default/0.chip_sw_pwrmgr_lowpower_cancel.1916463645 |
|
|
Jul 03 07:53:26 PM PDT 24 |
Jul 03 07:59:47 PM PDT 24 |
3916637768 ps |
| T1087 |
/workspace/coverage/default/0.chip_sw_lc_walkthrough_prodend.2112252880 |
|
|
Jul 03 07:50:16 PM PDT 24 |
Jul 03 08:05:44 PM PDT 24 |
8857607593 ps |
| T325 |
/workspace/coverage/default/1.chip_sw_pwrmgr_lowpower_cancel.2584976015 |
|
|
Jul 03 08:00:34 PM PDT 24 |
Jul 03 08:06:34 PM PDT 24 |
3422548240 ps |
| T1088 |
/workspace/coverage/default/0.chip_sw_uart_tx_rx.945537284 |
|
|
Jul 03 07:49:02 PM PDT 24 |
Jul 03 08:01:57 PM PDT 24 |
3876712260 ps |
| T1089 |
/workspace/coverage/default/2.chip_sw_edn_auto_mode.2951056094 |
|
|
Jul 03 08:07:49 PM PDT 24 |
Jul 03 08:20:04 PM PDT 24 |
3120425716 ps |
| T1090 |
/workspace/coverage/default/2.chip_sw_clkmgr_off_peri.3065539570 |
|
|
Jul 03 08:08:39 PM PDT 24 |
Jul 03 08:28:53 PM PDT 24 |
10014553080 ps |
| T1091 |
/workspace/coverage/default/1.chip_sw_pwrmgr_full_aon_reset.203664100 |
|
|
Jul 03 07:55:41 PM PDT 24 |
Jul 03 08:03:32 PM PDT 24 |
6989253118 ps |
| T1092 |
/workspace/coverage/default/0.chip_sw_pwrmgr_b2b_sleep_reset_req.491858345 |
|
|
Jul 03 07:50:15 PM PDT 24 |
Jul 03 08:34:30 PM PDT 24 |
26736274197 ps |
| T1093 |
/workspace/coverage/default/1.chip_sw_keymgr_key_derivation.1002961114 |
|
|
Jul 03 07:59:05 PM PDT 24 |
Jul 03 08:30:39 PM PDT 24 |
9545983206 ps |
| T1094 |
/workspace/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en.2029939754 |
|
|
Jul 03 08:00:30 PM PDT 24 |
Jul 03 08:07:03 PM PDT 24 |
2959227318 ps |
| T260 |
/workspace/coverage/default/1.chip_sw_rstmgr_cpu_info.2380410875 |
|
|
Jul 03 07:54:25 PM PDT 24 |
Jul 03 08:07:05 PM PDT 24 |
5251334420 ps |
| T1095 |
/workspace/coverage/default/0.rom_e2e_asm_init_prod_end.2608737438 |
|
|
Jul 03 07:55:37 PM PDT 24 |
Jul 03 08:48:50 PM PDT 24 |
15183045022 ps |
| T1096 |
/workspace/coverage/default/1.chip_sw_pwrmgr_sleep_power_glitch_reset.3600273393 |
|
|
Jul 03 07:56:05 PM PDT 24 |
Jul 03 08:03:12 PM PDT 24 |
4956048373 ps |
| T1097 |
/workspace/coverage/default/2.chip_sw_lc_ctrl_rand_to_scrap.1483588518 |
|
|
Jul 03 08:06:53 PM PDT 24 |
Jul 03 08:09:14 PM PDT 24 |
3039975979 ps |
| T358 |
/workspace/coverage/default/72.chip_sw_alert_handler_lpg_sleep_mode_alerts.4026315613 |
|
|
Jul 03 08:21:32 PM PDT 24 |
Jul 03 08:27:02 PM PDT 24 |
4020332648 ps |
| T1098 |
/workspace/coverage/default/1.chip_sw_hmac_oneshot.1484263862 |
|
|
Jul 03 07:58:38 PM PDT 24 |
Jul 03 08:04:31 PM PDT 24 |
3131168896 ps |
| T195 |
/workspace/coverage/default/1.chip_sw_lc_ctrl_program_error.493860175 |
|
|
Jul 03 08:00:49 PM PDT 24 |
Jul 03 08:10:46 PM PDT 24 |
4478843692 ps |
| T1099 |
/workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.2864948954 |
|
|
Jul 03 07:50:01 PM PDT 24 |
Jul 03 07:59:02 PM PDT 24 |
4500053317 ps |
| T1100 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_rma.3353532933 |
|
|
Jul 03 07:59:12 PM PDT 24 |
Jul 03 09:04:05 PM PDT 24 |
14877745680 ps |
| T1101 |
/workspace/coverage/default/1.chip_sw_aon_timer_smoketest.2589972692 |
|
|
Jul 03 08:04:51 PM PDT 24 |
Jul 03 08:09:34 PM PDT 24 |
3261130270 ps |
| T1102 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_clock_freqs.3539903354 |
|
|
Jul 03 07:54:34 PM PDT 24 |
Jul 03 08:16:14 PM PDT 24 |
6303159688 ps |
| T1103 |
/workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_dev.2963672336 |
|
|
Jul 03 07:48:14 PM PDT 24 |
Jul 03 08:07:51 PM PDT 24 |
9210798614 ps |
| T726 |
/workspace/coverage/default/65.chip_sw_alert_handler_lpg_sleep_mode_alerts.4061073933 |
|
|
Jul 03 08:19:45 PM PDT 24 |
Jul 03 08:26:06 PM PDT 24 |
3178613864 ps |
| T1104 |
/workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.2817044079 |
|
|
Jul 03 07:47:44 PM PDT 24 |
Jul 03 08:13:53 PM PDT 24 |
13300016510 ps |
| T280 |
/workspace/coverage/default/12.chip_sw_all_escalation_resets.1033223899 |
|
|
Jul 03 08:18:17 PM PDT 24 |
Jul 03 08:27:27 PM PDT 24 |
4161979800 ps |
| T171 |
/workspace/coverage/default/0.chip_jtag_mem_access.3676013587 |
|
|
Jul 03 07:41:50 PM PDT 24 |
Jul 03 08:07:28 PM PDT 24 |
13213718280 ps |
| T319 |
/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx.1165461732 |
|
|
Jul 03 07:47:59 PM PDT 24 |
Jul 03 08:02:46 PM PDT 24 |
4550343508 ps |
| T1105 |
/workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_por_reset.763423407 |
|
|
Jul 03 08:05:30 PM PDT 24 |
Jul 03 08:21:22 PM PDT 24 |
8734149000 ps |
| T229 |
/workspace/coverage/default/0.chip_sw_flash_init.3771867086 |
|
|
Jul 03 07:46:50 PM PDT 24 |
Jul 03 08:24:44 PM PDT 24 |
23682463208 ps |
| T1106 |
/workspace/coverage/default/2.chip_sw_entropy_src_ast_rng_req.828721648 |
|
|
Jul 03 08:08:27 PM PDT 24 |
Jul 03 08:12:37 PM PDT 24 |
2491720694 ps |
| T1107 |
/workspace/coverage/default/0.chip_sw_gpio_smoketest.9542692 |
|
|
Jul 03 07:51:28 PM PDT 24 |
Jul 03 07:56:31 PM PDT 24 |
2349609419 ps |
| T82 |
/workspace/coverage/default/3.chip_tap_straps_rma.1184774817 |
|
|
Jul 03 08:13:21 PM PDT 24 |
Jul 03 08:18:27 PM PDT 24 |
4700739728 ps |
| T1108 |
/workspace/coverage/default/1.chip_sw_rstmgr_smoketest.3073925804 |
|
|
Jul 03 08:04:44 PM PDT 24 |
Jul 03 08:08:35 PM PDT 24 |
2734547472 ps |
| T1109 |
/workspace/coverage/default/2.chip_sw_lc_walkthrough_prodend.2911218533 |
|
|
Jul 03 08:05:08 PM PDT 24 |
Jul 03 08:24:29 PM PDT 24 |
10328007370 ps |
| T143 |
/workspace/coverage/default/2.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.1864408454 |
|
|
Jul 03 08:12:45 PM PDT 24 |
Jul 03 08:20:16 PM PDT 24 |
5379080750 ps |
| T1110 |
/workspace/coverage/default/1.chip_sw_exit_test_unlocked_bootstrap.3908626556 |
|
|
Jul 03 07:55:05 PM PDT 24 |
Jul 03 10:50:12 PM PDT 24 |
59327966984 ps |
| T1111 |
/workspace/coverage/default/0.rom_e2e_static_critical.2605910318 |
|
|
Jul 03 07:58:17 PM PDT 24 |
Jul 03 09:18:04 PM PDT 24 |
17652879408 ps |
| T309 |
/workspace/coverage/default/1.chip_plic_all_irqs_0.138558755 |
|
|
Jul 03 07:59:53 PM PDT 24 |
Jul 03 08:18:45 PM PDT 24 |
6092017720 ps |
| T1112 |
/workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_power_glitch_reset.2301999394 |
|
|
Jul 03 07:49:56 PM PDT 24 |
Jul 03 08:45:15 PM PDT 24 |
34761717948 ps |
| T177 |
/workspace/coverage/default/0.chip_sw_sysrst_ctrl_reset.3922905164 |
|
|
Jul 03 07:48:46 PM PDT 24 |
Jul 03 08:13:22 PM PDT 24 |
21920130852 ps |
| T1113 |
/workspace/coverage/default/1.chip_sw_power_sleep_load.493990356 |
|
|
Jul 03 08:01:33 PM PDT 24 |
Jul 03 08:11:12 PM PDT 24 |
10800804904 ps |
| T1114 |
/workspace/coverage/default/1.chip_sw_rstmgr_rst_cnsty_escalation.1203214997 |
|
|
Jul 03 07:52:39 PM PDT 24 |
Jul 03 08:05:39 PM PDT 24 |
4982816040 ps |
| T1115 |
/workspace/coverage/default/2.chip_sw_gpio_smoketest.2484423965 |
|
|
Jul 03 08:11:33 PM PDT 24 |
Jul 03 08:17:38 PM PDT 24 |
3424620904 ps |
| T348 |
/workspace/coverage/default/2.chip_sw_hmac_enc_jitter_en.3864146898 |
|
|
Jul 03 08:09:46 PM PDT 24 |
Jul 03 08:14:14 PM PDT 24 |
3337032073 ps |
| T178 |
/workspace/coverage/default/1.chip_sw_sysrst_ctrl_outputs.2242885406 |
|
|
Jul 03 07:56:11 PM PDT 24 |
Jul 03 08:01:48 PM PDT 24 |
3076043568 ps |
| T724 |
/workspace/coverage/default/67.chip_sw_alert_handler_lpg_sleep_mode_alerts.3797600432 |
|
|
Jul 03 08:20:32 PM PDT 24 |
Jul 03 08:28:46 PM PDT 24 |
4497325616 ps |
| T1116 |
/workspace/coverage/default/5.chip_sw_csrng_edn_concurrency.3486479843 |
|
|
Jul 03 08:15:14 PM PDT 24 |
Jul 03 09:19:25 PM PDT 24 |
18249384112 ps |
| T1117 |
/workspace/coverage/default/2.chip_sw_hmac_multistream.561395969 |
|
|
Jul 03 08:08:27 PM PDT 24 |
Jul 03 08:35:09 PM PDT 24 |
7966795412 ps |
| T1118 |
/workspace/coverage/default/9.chip_sw_csrng_edn_concurrency.7209040 |
|
|
Jul 03 08:17:07 PM PDT 24 |
Jul 03 09:17:28 PM PDT 24 |
18068511760 ps |
| T1119 |
/workspace/coverage/default/3.chip_sw_uart_tx_rx_idx3.2460708089 |
|
|
Jul 03 08:12:39 PM PDT 24 |
Jul 03 08:25:05 PM PDT 24 |
4596741488 ps |
| T15 |
/workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_wake_ups.3672555632 |
|
|
Jul 03 08:11:48 PM PDT 24 |
Jul 03 08:46:17 PM PDT 24 |
25465364100 ps |
| T1120 |
/workspace/coverage/default/2.chip_sival_flash_info_access.2301225223 |
|
|
Jul 03 08:05:43 PM PDT 24 |
Jul 03 08:11:21 PM PDT 24 |
3353456728 ps |
| T1121 |
/workspace/coverage/default/2.rom_e2e_asm_init_prod_end.2748242952 |
|
|
Jul 03 08:17:33 PM PDT 24 |
Jul 03 09:11:38 PM PDT 24 |
15631885690 ps |
| T755 |
/workspace/coverage/default/20.chip_sw_all_escalation_resets.2221373620 |
|
|
Jul 03 08:17:16 PM PDT 24 |
Jul 03 08:29:16 PM PDT 24 |
6094238998 ps |
| T181 |
/workspace/coverage/default/2.chip_plic_all_irqs_10.2086116382 |
|
|
Jul 03 08:09:45 PM PDT 24 |
Jul 03 08:18:44 PM PDT 24 |
4031518470 ps |
| T389 |
/workspace/coverage/default/2.chip_rv_dm_ndm_reset_req.2424548900 |
|
|
Jul 03 08:11:36 PM PDT 24 |
Jul 03 08:20:53 PM PDT 24 |
4298412980 ps |
| T1122 |
/workspace/coverage/default/0.chip_sw_aes_enc_jitter_en.2279456697 |
|
|
Jul 03 07:51:03 PM PDT 24 |
Jul 03 07:56:48 PM PDT 24 |
2345643959 ps |
| T1123 |
/workspace/coverage/default/2.chip_tap_straps_testunlock0.3939592952 |
|
|
Jul 03 08:11:29 PM PDT 24 |
Jul 03 08:17:12 PM PDT 24 |
3498365339 ps |
| T1124 |
/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.2775273060 |
|
|
Jul 03 08:09:32 PM PDT 24 |
Jul 03 08:19:42 PM PDT 24 |
3620335992 ps |
| T1125 |
/workspace/coverage/default/2.rom_e2e_static_critical.1843695214 |
|
|
Jul 03 08:17:29 PM PDT 24 |
Jul 03 09:24:00 PM PDT 24 |
17788620134 ps |
| T1126 |
/workspace/coverage/default/2.chip_sw_clkmgr_smoketest.2557026617 |
|
|
Jul 03 08:12:34 PM PDT 24 |
Jul 03 08:16:13 PM PDT 24 |
2836544484 ps |
| T189 |
/workspace/coverage/default/0.chip_sw_otp_ctrl_vendor_test_csr_access.3849813598 |
|
|
Jul 03 07:48:35 PM PDT 24 |
Jul 03 07:51:59 PM PDT 24 |
2951153627 ps |
| T1127 |
/workspace/coverage/default/1.chip_sw_clkmgr_off_kmac_trans.1221855526 |
|
|
Jul 03 07:59:59 PM PDT 24 |
Jul 03 08:10:33 PM PDT 24 |
4085891720 ps |
| T1128 |
/workspace/coverage/default/1.chip_sw_alert_handler_entropy.1240942253 |
|
|
Jul 03 07:56:48 PM PDT 24 |
Jul 03 08:01:39 PM PDT 24 |
3748265848 ps |
| T1129 |
/workspace/coverage/default/0.chip_sw_aes_entropy.737943937 |
|
|
Jul 03 07:50:38 PM PDT 24 |
Jul 03 07:55:39 PM PDT 24 |
3537939620 ps |
| T1130 |
/workspace/coverage/default/2.chip_sw_clkmgr_jitter.1998011089 |
|
|
Jul 03 08:10:08 PM PDT 24 |
Jul 03 08:13:53 PM PDT 24 |
2648930891 ps |
| T1131 |
/workspace/coverage/default/0.chip_sw_ast_clk_outputs.981648024 |
|
|
Jul 03 07:52:10 PM PDT 24 |
Jul 03 08:08:58 PM PDT 24 |
7615511318 ps |
| T1132 |
/workspace/coverage/default/1.chip_sw_pwrmgr_main_power_glitch_reset.1004935199 |
|
|
Jul 03 07:55:35 PM PDT 24 |
Jul 03 08:00:26 PM PDT 24 |
3961292912 ps |
| T686 |
/workspace/coverage/default/58.chip_sw_alert_handler_lpg_sleep_mode_alerts.2785956161 |
|
|
Jul 03 08:19:45 PM PDT 24 |
Jul 03 08:24:53 PM PDT 24 |
3659929708 ps |