| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 96.04 | 95.43 | 93.74 | 95.53 | 94.46 | 97.53 | 99.53 |
| T2764 | /workspace/coverage/cover_reg_top/45.xbar_access_same_device.1326437980 | Jul 03 07:30:45 PM PDT 24 | Jul 03 07:31:47 PM PDT 24 | 649261957 ps | ||
| T2765 | /workspace/coverage/cover_reg_top/29.xbar_access_same_device_slow_rsp.2167494381 | Jul 03 07:27:41 PM PDT 24 | Jul 03 07:34:50 PM PDT 24 | 23617935098 ps | ||
| T2766 | /workspace/coverage/cover_reg_top/68.xbar_stress_all_with_rand_reset.3848473610 | Jul 03 07:34:45 PM PDT 24 | Jul 03 07:42:10 PM PDT 24 | 4114871294 ps | ||
| T2767 | /workspace/coverage/cover_reg_top/47.xbar_stress_all_with_rand_reset.2883878229 | Jul 03 07:31:16 PM PDT 24 | Jul 03 07:40:22 PM PDT 24 | 4581870514 ps | ||
| T2768 | /workspace/coverage/cover_reg_top/92.xbar_access_same_device_slow_rsp.751878988 | Jul 03 07:38:46 PM PDT 24 | Jul 03 08:11:04 PM PDT 24 | 102456584660 ps | ||
| T2769 | /workspace/coverage/cover_reg_top/93.xbar_random.2580613249 | Jul 03 07:38:56 PM PDT 24 | Jul 03 07:39:48 PM PDT 24 | 1514057458 ps | ||
| T2770 | /workspace/coverage/cover_reg_top/68.xbar_random_slow_rsp.1356006840 | Jul 03 07:34:39 PM PDT 24 | Jul 03 07:51:08 PM PDT 24 | 52658501831 ps | ||
| T2771 | /workspace/coverage/cover_reg_top/20.chip_tl_errors.3466706833 | Jul 03 07:25:51 PM PDT 24 | Jul 03 07:27:30 PM PDT 24 | 2579410224 ps | ||
| T2772 | /workspace/coverage/cover_reg_top/69.xbar_random_large_delays.3696123121 | Jul 03 07:35:03 PM PDT 24 | Jul 03 07:38:49 PM PDT 24 | 21634730217 ps | ||
| T2773 | /workspace/coverage/cover_reg_top/35.xbar_random_large_delays.3932291464 | Jul 03 07:28:54 PM PDT 24 | Jul 03 07:35:41 PM PDT 24 | 41343476386 ps | ||
| T2774 | /workspace/coverage/cover_reg_top/50.xbar_random_zero_delays.1887929098 | Jul 03 07:31:39 PM PDT 24 | Jul 03 07:32:29 PM PDT 24 | 532010504 ps | ||
| T2775 | /workspace/coverage/cover_reg_top/60.xbar_random_slow_rsp.1613106872 | Jul 03 07:33:24 PM PDT 24 | Jul 03 07:50:02 PM PDT 24 | 54503952204 ps | ||
| T2776 | /workspace/coverage/cover_reg_top/14.xbar_stress_all_with_error.838756818 | Jul 03 07:24:35 PM PDT 24 | Jul 03 07:28:01 PM PDT 24 | 2416135401 ps | ||
| T2777 | /workspace/coverage/cover_reg_top/59.xbar_unmapped_addr.1616659517 | Jul 03 07:33:13 PM PDT 24 | Jul 03 07:33:59 PM PDT 24 | 1111739820 ps | ||
| T2778 | /workspace/coverage/cover_reg_top/23.xbar_stress_all_with_rand_reset.1126628291 | Jul 03 07:26:24 PM PDT 24 | Jul 03 07:31:28 PM PDT 24 | 3001775471 ps | ||
| T2779 | /workspace/coverage/cover_reg_top/7.chip_csr_rw.2305466249 | Jul 03 07:23:20 PM PDT 24 | Jul 03 07:33:10 PM PDT 24 | 6135990631 ps | ||
| T2780 | /workspace/coverage/cover_reg_top/75.xbar_error_random.2801967750 | Jul 03 07:35:58 PM PDT 24 | Jul 03 07:36:23 PM PDT 24 | 702975083 ps | ||
| T2781 | /workspace/coverage/cover_reg_top/65.xbar_smoke.4179027993 | Jul 03 07:34:13 PM PDT 24 | Jul 03 07:34:22 PM PDT 24 | 150271416 ps | ||
| T2782 | /workspace/coverage/cover_reg_top/20.xbar_stress_all_with_error.2589514814 | Jul 03 07:25:56 PM PDT 24 | Jul 03 07:32:12 PM PDT 24 | 9640714821 ps | ||
| T2783 | /workspace/coverage/cover_reg_top/7.xbar_unmapped_addr.2279358671 | Jul 03 07:23:17 PM PDT 24 | Jul 03 07:23:39 PM PDT 24 | 146754110 ps | ||
| T2784 | /workspace/coverage/cover_reg_top/86.xbar_same_source.170184584 | Jul 03 07:37:50 PM PDT 24 | Jul 03 07:39:02 PM PDT 24 | 2350893077 ps | ||
| T2785 | /workspace/coverage/cover_reg_top/86.xbar_stress_all.1032843440 | Jul 03 07:37:51 PM PDT 24 | Jul 03 07:39:48 PM PDT 24 | 3766539890 ps | ||
| T2786 | /workspace/coverage/cover_reg_top/13.xbar_random_zero_delays.768241877 | Jul 03 07:24:20 PM PDT 24 | Jul 03 07:24:52 PM PDT 24 | 309965472 ps | ||
| T2787 | /workspace/coverage/cover_reg_top/8.xbar_random_zero_delays.4040209397 | Jul 03 07:23:26 PM PDT 24 | Jul 03 07:24:07 PM PDT 24 | 490719143 ps | ||
| T2788 | /workspace/coverage/cover_reg_top/44.xbar_access_same_device_slow_rsp.50267126 | Jul 03 07:30:35 PM PDT 24 | Jul 03 07:37:54 PM PDT 24 | 24348051661 ps | ||
| T2789 | /workspace/coverage/cover_reg_top/33.xbar_stress_all_with_reset_error.4165261257 | Jul 03 07:28:33 PM PDT 24 | Jul 03 07:30:49 PM PDT 24 | 567655434 ps | ||
| T2790 | /workspace/coverage/cover_reg_top/17.xbar_error_random.1987308225 | Jul 03 07:25:11 PM PDT 24 | Jul 03 07:25:41 PM PDT 24 | 841248796 ps | ||
| T2791 | /workspace/coverage/cover_reg_top/52.xbar_error_random.980011673 | Jul 03 07:32:08 PM PDT 24 | Jul 03 07:32:18 PM PDT 24 | 186883019 ps | ||
| T2792 | /workspace/coverage/cover_reg_top/78.xbar_access_same_device_slow_rsp.824877458 | Jul 03 07:36:23 PM PDT 24 | Jul 03 08:23:35 PM PDT 24 | 150031915711 ps | ||
| T2793 | /workspace/coverage/cover_reg_top/76.xbar_random.1103491876 | Jul 03 07:36:03 PM PDT 24 | Jul 03 07:36:55 PM PDT 24 | 1456064455 ps | ||
| T2794 | /workspace/coverage/cover_reg_top/94.xbar_same_source.3846637975 | Jul 03 07:39:05 PM PDT 24 | Jul 03 07:39:57 PM PDT 24 | 1699835411 ps | ||
| T2795 | /workspace/coverage/cover_reg_top/56.xbar_error_random.69519132 | Jul 03 07:32:47 PM PDT 24 | Jul 03 07:33:01 PM PDT 24 | 360813350 ps | ||
| T2796 | /workspace/coverage/cover_reg_top/91.xbar_stress_all_with_reset_error.2600057468 | Jul 03 07:38:37 PM PDT 24 | Jul 03 07:38:48 PM PDT 24 | 23097809 ps | ||
| T2797 | /workspace/coverage/cover_reg_top/41.xbar_smoke.1979742179 | Jul 03 07:29:57 PM PDT 24 | Jul 03 07:30:07 PM PDT 24 | 210193579 ps | ||
| T2798 | /workspace/coverage/cover_reg_top/4.xbar_stress_all_with_rand_reset.1929226364 | Jul 03 07:22:44 PM PDT 24 | Jul 03 07:30:51 PM PDT 24 | 9387627282 ps | ||
| T2799 | /workspace/coverage/cover_reg_top/39.xbar_same_source.3425863689 | Jul 03 07:29:31 PM PDT 24 | Jul 03 07:29:57 PM PDT 24 | 302639603 ps | ||
| T2800 | /workspace/coverage/cover_reg_top/92.xbar_random_large_delays.997657337 | Jul 03 07:38:45 PM PDT 24 | Jul 03 07:47:03 PM PDT 24 | 47176646318 ps | ||
| T2801 | /workspace/coverage/cover_reg_top/71.xbar_stress_all.261782006 | Jul 03 07:35:17 PM PDT 24 | Jul 03 07:36:17 PM PDT 24 | 725005826 ps | ||
| T2802 | /workspace/coverage/cover_reg_top/27.xbar_random_slow_rsp.915406073 | Jul 03 07:27:19 PM PDT 24 | Jul 03 07:44:52 PM PDT 24 | 60655983075 ps | ||
| T2803 | /workspace/coverage/cover_reg_top/37.xbar_smoke_large_delays.3487711380 | Jul 03 07:29:08 PM PDT 24 | Jul 03 07:30:53 PM PDT 24 | 8872152335 ps | ||
| T2804 | /workspace/coverage/cover_reg_top/52.xbar_stress_all.1134840343 | Jul 03 07:32:10 PM PDT 24 | Jul 03 07:39:11 PM PDT 24 | 11978550291 ps | ||
| T2805 | /workspace/coverage/cover_reg_top/20.xbar_random.3891572640 | Jul 03 07:25:46 PM PDT 24 | Jul 03 07:26:21 PM PDT 24 | 946761037 ps | ||
| T2806 | /workspace/coverage/cover_reg_top/97.xbar_stress_all.3164956937 | Jul 03 07:39:50 PM PDT 24 | Jul 03 07:41:42 PM PDT 24 | 1281493869 ps | ||
| T2807 | /workspace/coverage/cover_reg_top/95.xbar_stress_all_with_reset_error.3504088227 | Jul 03 07:39:19 PM PDT 24 | Jul 03 07:40:46 PM PDT 24 | 303908160 ps | ||
| T2808 | /workspace/coverage/cover_reg_top/43.xbar_random_slow_rsp.1659288892 | Jul 03 07:30:23 PM PDT 24 | Jul 03 07:45:50 PM PDT 24 | 52808544474 ps | ||
| T2809 | /workspace/coverage/cover_reg_top/33.xbar_unmapped_addr.172978476 | Jul 03 07:28:29 PM PDT 24 | Jul 03 07:29:18 PM PDT 24 | 1066962727 ps | ||
| T2810 | /workspace/coverage/cover_reg_top/37.xbar_random.2020780201 | Jul 03 07:29:07 PM PDT 24 | Jul 03 07:30:03 PM PDT 24 | 1455594515 ps | ||
| T2811 | /workspace/coverage/cover_reg_top/53.xbar_random_large_delays.2451883046 | Jul 03 07:32:08 PM PDT 24 | Jul 03 07:50:42 PM PDT 24 | 105666110823 ps | ||
| T2812 | /workspace/coverage/cover_reg_top/20.xbar_stress_all_with_reset_error.1668020560 | Jul 03 07:26:03 PM PDT 24 | Jul 03 07:30:02 PM PDT 24 | 747479027 ps | ||
| T2813 | /workspace/coverage/cover_reg_top/2.chip_csr_rw.2387697566 | Jul 03 07:22:26 PM PDT 24 | Jul 03 07:31:04 PM PDT 24 | 5396746296 ps | ||
| T2814 | /workspace/coverage/cover_reg_top/12.chip_csr_rw.3427997723 | Jul 03 07:24:16 PM PDT 24 | Jul 03 07:31:24 PM PDT 24 | 4744977210 ps | ||
| T2815 | /workspace/coverage/cover_reg_top/39.xbar_smoke_large_delays.704293133 | Jul 03 07:29:31 PM PDT 24 | Jul 03 07:31:08 PM PDT 24 | 8657369649 ps | ||
| T2816 | /workspace/coverage/cover_reg_top/88.xbar_access_same_device.2236846135 | Jul 03 07:38:09 PM PDT 24 | Jul 03 07:38:32 PM PDT 24 | 293818634 ps | ||
| T642 | /workspace/coverage/cover_reg_top/21.chip_tl_errors.3984672795 | Jul 03 07:25:56 PM PDT 24 | Jul 03 07:33:01 PM PDT 24 | 4127952008 ps | ||
| T2817 | /workspace/coverage/cover_reg_top/14.xbar_smoke_zero_delays.3624461863 | Jul 03 07:24:31 PM PDT 24 | Jul 03 07:24:40 PM PDT 24 | 51202150 ps | ||
| T2818 | /workspace/coverage/cover_reg_top/53.xbar_unmapped_addr.2327262357 | Jul 03 07:32:18 PM PDT 24 | Jul 03 07:32:51 PM PDT 24 | 261681843 ps | ||
| T2819 | /workspace/coverage/cover_reg_top/44.xbar_stress_all.389006151 | Jul 03 07:30:42 PM PDT 24 | Jul 03 07:36:59 PM PDT 24 | 9598474183 ps | ||
| T2820 | /workspace/coverage/cover_reg_top/84.xbar_random.1178925063 | Jul 03 07:37:29 PM PDT 24 | Jul 03 07:38:39 PM PDT 24 | 1804773293 ps | ||
| T2821 | /workspace/coverage/cover_reg_top/6.xbar_access_same_device_slow_rsp.2012307751 | Jul 03 07:23:00 PM PDT 24 | Jul 03 07:36:34 PM PDT 24 | 45882147877 ps | ||
| T2822 | /workspace/coverage/cover_reg_top/28.xbar_smoke_slow_rsp.2337429223 | Jul 03 07:27:27 PM PDT 24 | Jul 03 07:28:33 PM PDT 24 | 3778870208 ps | ||
| T2823 | /workspace/coverage/cover_reg_top/66.xbar_smoke_zero_delays.398767519 | Jul 03 07:34:23 PM PDT 24 | Jul 03 07:34:30 PM PDT 24 | 38833017 ps | ||
| T2824 | /workspace/coverage/cover_reg_top/49.xbar_same_source.844521140 | Jul 03 07:31:34 PM PDT 24 | Jul 03 07:32:40 PM PDT 24 | 2091692368 ps | ||
| T2825 | /workspace/coverage/cover_reg_top/53.xbar_error_and_unmapped_addr.3321300644 | Jul 03 07:32:12 PM PDT 24 | Jul 03 07:32:53 PM PDT 24 | 1030025225 ps | ||
| T2826 | /workspace/coverage/cover_reg_top/61.xbar_smoke.1106162955 | Jul 03 07:33:28 PM PDT 24 | Jul 03 07:33:36 PM PDT 24 | 52665441 ps | ||
| T2827 | /workspace/coverage/cover_reg_top/0.xbar_random_zero_delays.1318033209 | Jul 03 07:21:58 PM PDT 24 | Jul 03 07:22:37 PM PDT 24 | 444720064 ps | ||
| T2828 | /workspace/coverage/cover_reg_top/20.xbar_random_zero_delays.1886140389 | Jul 03 07:25:51 PM PDT 24 | Jul 03 07:26:32 PM PDT 24 | 421237269 ps | ||
| T2829 | /workspace/coverage/cover_reg_top/41.xbar_same_source.1728007690 | Jul 03 07:30:03 PM PDT 24 | Jul 03 07:30:38 PM PDT 24 | 384210212 ps | ||
| T2830 | /workspace/coverage/cover_reg_top/62.xbar_random.1217981487 | Jul 03 07:33:38 PM PDT 24 | Jul 03 07:34:35 PM PDT 24 | 1575649709 ps | ||
| T2831 | /workspace/coverage/cover_reg_top/96.xbar_smoke.2183507432 | Jul 03 07:39:20 PM PDT 24 | Jul 03 07:39:30 PM PDT 24 | 218868256 ps | ||
| T2832 | /workspace/coverage/cover_reg_top/69.xbar_smoke_slow_rsp.1802321338 | Jul 03 07:34:48 PM PDT 24 | Jul 03 07:36:39 PM PDT 24 | 6251112689 ps | ||
| T2833 | /workspace/coverage/cover_reg_top/31.xbar_smoke.4098718263 | Jul 03 07:28:06 PM PDT 24 | Jul 03 07:28:16 PM PDT 24 | 177942852 ps | ||
| T2834 | /workspace/coverage/cover_reg_top/2.chip_same_csr_outstanding.1357365972 | Jul 03 07:22:18 PM PDT 24 | Jul 03 08:34:06 PM PDT 24 | 30813232140 ps | ||
| T577 | /workspace/coverage/cover_reg_top/41.xbar_stress_all_with_reset_error.851759054 | Jul 03 07:30:09 PM PDT 24 | Jul 03 07:43:24 PM PDT 24 | 9720236586 ps | ||
| T2835 | /workspace/coverage/cover_reg_top/12.xbar_random_slow_rsp.2797236938 | Jul 03 07:24:12 PM PDT 24 | Jul 03 07:26:47 PM PDT 24 | 8565251477 ps | ||
| T2836 | /workspace/coverage/cover_reg_top/88.xbar_stress_all_with_rand_reset.3038218895 | Jul 03 07:38:04 PM PDT 24 | Jul 03 07:43:54 PM PDT 24 | 4886027253 ps | ||
| T2837 | /workspace/coverage/cover_reg_top/17.xbar_smoke.914263064 | Jul 03 07:25:09 PM PDT 24 | Jul 03 07:25:18 PM PDT 24 | 208698416 ps | ||
| T2838 | /workspace/coverage/cover_reg_top/8.xbar_random_slow_rsp.1871239887 | Jul 03 07:23:26 PM PDT 24 | Jul 03 07:36:38 PM PDT 24 | 44081769732 ps | ||
| T2839 | /workspace/coverage/cover_reg_top/84.xbar_error_random.1843610739 | Jul 03 07:37:34 PM PDT 24 | Jul 03 07:38:25 PM PDT 24 | 1495787536 ps | ||
| T2840 | /workspace/coverage/cover_reg_top/94.xbar_error_random.3503308325 | Jul 03 07:39:05 PM PDT 24 | Jul 03 07:39:24 PM PDT 24 | 487682023 ps | ||
| T2841 | /workspace/coverage/cover_reg_top/23.xbar_stress_all_with_error.1717402552 | Jul 03 07:26:29 PM PDT 24 | Jul 03 07:27:34 PM PDT 24 | 663860252 ps | ||
| T2842 | /workspace/coverage/cover_reg_top/81.xbar_unmapped_addr.2127354834 | Jul 03 07:36:55 PM PDT 24 | Jul 03 07:37:24 PM PDT 24 | 253006040 ps | ||
| T2843 | /workspace/coverage/cover_reg_top/68.xbar_same_source.1651060230 | Jul 03 07:34:40 PM PDT 24 | Jul 03 07:34:50 PM PDT 24 | 218890958 ps | ||
| T2844 | /workspace/coverage/cover_reg_top/55.xbar_smoke_slow_rsp.639108908 | Jul 03 07:32:28 PM PDT 24 | Jul 03 07:34:04 PM PDT 24 | 6289655752 ps | ||
| T2845 | /workspace/coverage/cover_reg_top/35.xbar_smoke_slow_rsp.1718343502 | Jul 03 07:28:55 PM PDT 24 | Jul 03 07:30:23 PM PDT 24 | 4961268618 ps | ||
| T2846 | /workspace/coverage/cover_reg_top/95.xbar_error_and_unmapped_addr.3314807629 | Jul 03 07:39:16 PM PDT 24 | Jul 03 07:39:33 PM PDT 24 | 340601291 ps | ||
| T2847 | /workspace/coverage/cover_reg_top/22.chip_tl_errors.3601203725 | Jul 03 07:26:05 PM PDT 24 | Jul 03 07:30:29 PM PDT 24 | 4343668006 ps | ||
| T2848 | /workspace/coverage/cover_reg_top/73.xbar_stress_all_with_reset_error.582348576 | Jul 03 07:35:38 PM PDT 24 | Jul 03 07:37:50 PM PDT 24 | 227456682 ps | ||
| T2849 | /workspace/coverage/cover_reg_top/3.xbar_smoke.1150786935 | Jul 03 07:22:26 PM PDT 24 | Jul 03 07:22:35 PM PDT 24 | 191053733 ps | ||
| T2850 | /workspace/coverage/cover_reg_top/74.xbar_random_zero_delays.1788368886 | Jul 03 07:35:45 PM PDT 24 | Jul 03 07:36:36 PM PDT 24 | 576989056 ps | ||
| T2851 | /workspace/coverage/cover_reg_top/55.xbar_smoke_large_delays.2503027736 | Jul 03 07:32:29 PM PDT 24 | Jul 03 07:34:01 PM PDT 24 | 9341645827 ps | ||
| T2852 | /workspace/coverage/cover_reg_top/30.xbar_stress_all.2131572183 | Jul 03 07:28:02 PM PDT 24 | Jul 03 07:30:56 PM PDT 24 | 1936962638 ps | ||
| T2853 | /workspace/coverage/cover_reg_top/0.xbar_stress_all_with_error.103823064 | Jul 03 07:22:04 PM PDT 24 | Jul 03 07:25:35 PM PDT 24 | 3119477328 ps | ||
| T2854 | /workspace/coverage/cover_reg_top/43.xbar_error_and_unmapped_addr.2428482357 | Jul 03 07:30:31 PM PDT 24 | Jul 03 07:30:38 PM PDT 24 | 23232740 ps | ||
| T2855 | /workspace/coverage/cover_reg_top/42.xbar_random_zero_delays.3258692552 | Jul 03 07:30:16 PM PDT 24 | Jul 03 07:30:50 PM PDT 24 | 369769254 ps | ||
| T2856 | /workspace/coverage/cover_reg_top/63.xbar_smoke.1532466294 | Jul 03 07:33:50 PM PDT 24 | Jul 03 07:34:01 PM PDT 24 | 196719613 ps | ||
| T2857 | /workspace/coverage/cover_reg_top/79.xbar_stress_all.9721962 | Jul 03 07:36:36 PM PDT 24 | Jul 03 07:38:15 PM PDT 24 | 1124601210 ps | ||
| T2858 | /workspace/coverage/cover_reg_top/31.xbar_random_large_delays.1107463602 | Jul 03 07:28:08 PM PDT 24 | Jul 03 07:44:39 PM PDT 24 | 96611600981 ps | ||
| T2859 | /workspace/coverage/cover_reg_top/72.xbar_error_and_unmapped_addr.1686199176 | Jul 03 07:35:26 PM PDT 24 | Jul 03 07:35:53 PM PDT 24 | 249351222 ps | ||
| T2860 | /workspace/coverage/cover_reg_top/18.xbar_unmapped_addr.1672344756 | Jul 03 07:25:32 PM PDT 24 | Jul 03 07:25:45 PM PDT 24 | 98031021 ps | ||
| T2861 | /workspace/coverage/cover_reg_top/76.xbar_access_same_device.3030951815 | Jul 03 07:36:01 PM PDT 24 | Jul 03 07:36:58 PM PDT 24 | 601404710 ps | ||
| T2862 | /workspace/coverage/cover_reg_top/50.xbar_error_and_unmapped_addr.1016622071 | Jul 03 07:31:46 PM PDT 24 | Jul 03 07:31:55 PM PDT 24 | 93236379 ps | ||
| T2863 | /workspace/coverage/cover_reg_top/23.xbar_unmapped_addr.2262197973 | Jul 03 07:26:25 PM PDT 24 | Jul 03 07:27:15 PM PDT 24 | 1260352824 ps | ||
| T2864 | /workspace/coverage/cover_reg_top/26.xbar_smoke.3562803594 | Jul 03 07:26:57 PM PDT 24 | Jul 03 07:27:10 PM PDT 24 | 239398081 ps | ||
| T2865 | /workspace/coverage/cover_reg_top/18.xbar_stress_all.2159514529 | Jul 03 07:25:29 PM PDT 24 | Jul 03 07:29:43 PM PDT 24 | 3168150980 ps | ||
| T2866 | /workspace/coverage/cover_reg_top/77.xbar_error_random.317431475 | Jul 03 07:36:19 PM PDT 24 | Jul 03 07:36:54 PM PDT 24 | 408563472 ps | ||
| T635 | /workspace/coverage/cover_reg_top/98.xbar_stress_all_with_reset_error.1207944261 | Jul 03 07:39:47 PM PDT 24 | Jul 03 07:41:45 PM PDT 24 | 378817276 ps | ||
| T2867 | /workspace/coverage/cover_reg_top/34.xbar_error_and_unmapped_addr.3251901120 | Jul 03 07:28:42 PM PDT 24 | Jul 03 07:28:51 PM PDT 24 | 98420785 ps | ||
| T2868 | /workspace/coverage/cover_reg_top/40.xbar_random_large_delays.2711106649 | Jul 03 07:29:53 PM PDT 24 | Jul 03 07:39:31 PM PDT 24 | 56472542199 ps | ||
| T2869 | /workspace/coverage/cover_reg_top/4.chip_csr_aliasing.1851519400 | Jul 03 07:22:44 PM PDT 24 | Jul 03 09:09:02 PM PDT 24 | 36644893979 ps | ||
| T2870 | /workspace/coverage/cover_reg_top/83.xbar_stress_all_with_error.3994585474 | Jul 03 07:37:23 PM PDT 24 | Jul 03 07:40:50 PM PDT 24 | 5254837870 ps | ||
| T2871 | /workspace/coverage/cover_reg_top/30.xbar_random.942174347 | Jul 03 07:27:54 PM PDT 24 | Jul 03 07:28:30 PM PDT 24 | 824537759 ps | ||
| T2872 | /workspace/coverage/cover_reg_top/21.xbar_access_same_device.3189079121 | Jul 03 07:26:02 PM PDT 24 | Jul 03 07:28:05 PM PDT 24 | 3075303140 ps | ||
| T2873 | /workspace/coverage/cover_reg_top/85.xbar_stress_all.1059698314 | Jul 03 07:37:42 PM PDT 24 | Jul 03 07:48:42 PM PDT 24 | 16335943098 ps | ||
| T2874 | /workspace/coverage/cover_reg_top/17.xbar_stress_all_with_rand_reset.1346159040 | Jul 03 07:25:21 PM PDT 24 | Jul 03 07:31:45 PM PDT 24 | 3676684850 ps | ||
| T2875 | /workspace/coverage/cover_reg_top/20.xbar_smoke_large_delays.1081479357 | Jul 03 07:25:49 PM PDT 24 | Jul 03 07:27:21 PM PDT 24 | 8758969603 ps | ||
| T2876 | /workspace/coverage/cover_reg_top/21.xbar_smoke_slow_rsp.2153933746 | Jul 03 07:26:01 PM PDT 24 | Jul 03 07:28:03 PM PDT 24 | 6805144449 ps | ||
| T2877 | /workspace/coverage/cover_reg_top/68.xbar_error_random.1869381002 | Jul 03 07:34:39 PM PDT 24 | Jul 03 07:35:21 PM PDT 24 | 495730396 ps | ||
| T2878 | /workspace/coverage/cover_reg_top/25.xbar_error_and_unmapped_addr.1011110259 | Jul 03 07:26:50 PM PDT 24 | Jul 03 07:27:24 PM PDT 24 | 870252483 ps | ||
| T2879 | /workspace/coverage/cover_reg_top/15.xbar_access_same_device_slow_rsp.679327848 | Jul 03 07:24:46 PM PDT 24 | Jul 03 07:59:39 PM PDT 24 | 115385502970 ps | ||
| T2880 | /workspace/coverage/cover_reg_top/83.xbar_same_source.3327957556 | Jul 03 07:37:20 PM PDT 24 | Jul 03 07:37:32 PM PDT 24 | 283987144 ps | ||
| T2881 | /workspace/coverage/cover_reg_top/19.chip_same_csr_outstanding.2199510028 | Jul 03 07:25:33 PM PDT 24 | Jul 03 07:56:19 PM PDT 24 | 14025799459 ps | ||
| T2882 | /workspace/coverage/cover_reg_top/53.xbar_stress_all_with_rand_reset.1526475123 | Jul 03 07:32:14 PM PDT 24 | Jul 03 07:39:08 PM PDT 24 | 9431794441 ps | ||
| T2883 | /workspace/coverage/cover_reg_top/15.xbar_stress_all_with_error.1255109071 | Jul 03 07:24:54 PM PDT 24 | Jul 03 07:29:14 PM PDT 24 | 8785215274 ps | ||
| T2884 | /workspace/coverage/cover_reg_top/29.xbar_access_same_device.2213862449 | Jul 03 07:27:41 PM PDT 24 | Jul 03 07:29:10 PM PDT 24 | 2084253226 ps | ||
| T2885 | /workspace/coverage/cover_reg_top/24.xbar_access_same_device_slow_rsp.1893132051 | Jul 03 07:26:38 PM PDT 24 | Jul 03 08:05:03 PM PDT 24 | 114590966574 ps | ||
| T2886 | /workspace/coverage/cover_reg_top/60.xbar_stress_all_with_error.2716430220 | Jul 03 07:33:29 PM PDT 24 | Jul 03 07:37:15 PM PDT 24 | 6203371484 ps | ||
| T2887 | /workspace/coverage/cover_reg_top/0.xbar_smoke_large_delays.3625633281 | Jul 03 07:22:08 PM PDT 24 | Jul 03 07:23:53 PM PDT 24 | 10494845591 ps | ||
| T2888 | /workspace/coverage/cover_reg_top/44.xbar_error_random.3989613266 | Jul 03 07:30:40 PM PDT 24 | Jul 03 07:30:50 PM PDT 24 | 141316028 ps | ||
| T2889 | /workspace/coverage/cover_reg_top/75.xbar_error_and_unmapped_addr.965012841 | Jul 03 07:35:59 PM PDT 24 | Jul 03 07:36:19 PM PDT 24 | 458532087 ps | ||
| T2890 | /workspace/coverage/cover_reg_top/81.xbar_smoke_zero_delays.1400070696 | Jul 03 07:36:52 PM PDT 24 | Jul 03 07:37:01 PM PDT 24 | 60616933 ps | ||
| T2891 | /workspace/coverage/cover_reg_top/67.xbar_stress_all.2773023686 | Jul 03 07:34:36 PM PDT 24 | Jul 03 07:47:37 PM PDT 24 | 17764969862 ps | ||
| T2892 | /workspace/coverage/cover_reg_top/82.xbar_random_zero_delays.1199575834 | Jul 03 07:37:07 PM PDT 24 | Jul 03 07:37:30 PM PDT 24 | 245949062 ps | ||
| T42 | /workspace/coverage/pad_ctrl_test_mode/3.chip_padctrl_attributes.1969252307 | Jul 03 08:15:09 PM PDT 24 | Jul 03 08:18:53 PM PDT 24 | 4550479518 ps | ||
| T43 | /workspace/coverage/pad_ctrl_test_mode/8.chip_padctrl_attributes.622221941 | Jul 03 08:15:18 PM PDT 24 | Jul 03 08:19:01 PM PDT 24 | 5277469376 ps | ||
| T44 | /workspace/coverage/pad_ctrl_test_mode/1.chip_padctrl_attributes.1462776219 | Jul 03 08:15:11 PM PDT 24 | Jul 03 08:21:25 PM PDT 24 | 5225342139 ps | ||
| T159 | /workspace/coverage/pad_ctrl_test_mode/6.chip_padctrl_attributes.4081546994 | Jul 03 08:15:11 PM PDT 24 | Jul 03 08:20:12 PM PDT 24 | 5820225464 ps | ||
| T160 | /workspace/coverage/pad_ctrl_test_mode/2.chip_padctrl_attributes.960370577 | Jul 03 08:15:21 PM PDT 24 | Jul 03 08:19:23 PM PDT 24 | 5121814232 ps | ||
| T161 | /workspace/coverage/pad_ctrl_test_mode/7.chip_padctrl_attributes.2456845028 | Jul 03 08:15:06 PM PDT 24 | Jul 03 08:18:43 PM PDT 24 | 5257495710 ps | ||
| T162 | /workspace/coverage/pad_ctrl_test_mode/5.chip_padctrl_attributes.4159115290 | Jul 03 08:15:05 PM PDT 24 | Jul 03 08:19:01 PM PDT 24 | 4855770448 ps | ||
| T163 | /workspace/coverage/pad_ctrl_test_mode/0.chip_padctrl_attributes.2762272223 | Jul 03 08:15:12 PM PDT 24 | Jul 03 08:21:01 PM PDT 24 | 4812965576 ps | ||
| T164 | /workspace/coverage/pad_ctrl_test_mode/4.chip_padctrl_attributes.3047392244 | Jul 03 08:15:05 PM PDT 24 | Jul 03 08:18:24 PM PDT 24 | 4160849810 ps | ||
| T165 | /workspace/coverage/pad_ctrl_test_mode/9.chip_padctrl_attributes.1566138032 | Jul 03 08:15:21 PM PDT 24 | Jul 03 08:20:10 PM PDT 24 | 4142155695 ps |
| Test location | /workspace/coverage/default/2.chip_sw_keymgr_sideload_aes.1283022062 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 7007283440 ps |
| CPU time | 1102.88 seconds |
| Started | Jul 03 08:09:26 PM PDT 24 |
| Finished | Jul 03 08:27:49 PM PDT 24 |
| Peak memory | 610780 kb |
| Host | smart-fb093661-fbce-42be-aeb3-69ef35a73c02 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_aes_test:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=128302 2062 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_sideload_aes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_sideload_aes.1283022062 |
| Directory | /workspace/2.chip_sw_keymgr_sideload_aes/latest |
| Test location | /workspace/coverage/cover_reg_top/15.chip_csr_rw.1205579652 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 6756466950 ps |
| CPU time | 697.17 seconds |
| Started | Jul 03 07:24:55 PM PDT 24 |
| Finished | Jul 03 07:36:34 PM PDT 24 |
| Peak memory | 598216 kb |
| Host | smart-032911ed-5c0d-4772-9f8b-ed41224cdffa |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1205579652 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.chip_csr_rw.1205579652 |
| Directory | /workspace/15.chip_csr_rw/latest |
| Test location | /workspace/coverage/default/2.chip_plic_all_irqs_20.1834643842 |
| Short name | T272 |
| Test name | |
| Test status | |
| Simulation time | 4600964888 ps |
| CPU time | 933.22 seconds |
| Started | Jul 03 08:08:55 PM PDT 24 |
| Finished | Jul 03 08:24:29 PM PDT 24 |
| Peak memory | 610620 kb |
| Host | smart-c71682e9-bf0f-4204-86d1-5befc482a069 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_20:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1834643842 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 2.chip_plic_all_irqs_20.1834643842 |
| Directory | /workspace/2.chip_plic_all_irqs_20/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_access_same_device.581281851 |
| Short name | T500 |
| Test name | |
| Test status | |
| Simulation time | 1269549083 ps |
| CPU time | 90.99 seconds |
| Started | Jul 03 07:28:57 PM PDT 24 |
| Finished | Jul 03 07:30:34 PM PDT 24 |
| Peak memory | 574232 kb |
| Host | smart-86165366-b51a-411e-8652-3aa0b977272a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=581281851 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_access_same_device. 581281851 |
| Directory | /workspace/36.xbar_access_same_device/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/3.chip_padctrl_attributes.1969252307 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 4550479518 ps |
| CPU time | 223.56 seconds |
| Started | Jul 03 08:15:09 PM PDT 24 |
| Finished | Jul 03 08:18:53 PM PDT 24 |
| Peak memory | 640924 kb |
| Host | smart-9182c5e0-b3ea-43cf-8bf1-dfb95d78bf75 |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1969252307 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/ null -cm_name 3.chip_padctrl_attributes.1969252307 |
| Directory | /workspace/3.chip_padctrl_attributes/latest |
| Test location | /workspace/coverage/default/18.chip_sw_alert_handler_lpg_sleep_mode_alerts.3240897319 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 3859230630 ps |
| CPU time | 568.8 seconds |
| Started | Jul 03 08:20:00 PM PDT 24 |
| Finished | Jul 03 08:29:31 PM PDT 24 |
| Peak memory | 641240 kb |
| Host | smart-723d1e6b-fe46-4f2f-9a1b-515b7bb05713 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3240897319 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3240897319 |
| Directory | /workspace/18.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_access_same_device_slow_rsp.3810029016 |
| Short name | T594 |
| Test name | |
| Test status | |
| Simulation time | 129183447735 ps |
| CPU time | 2638.79 seconds |
| Started | Jul 03 07:37:15 PM PDT 24 |
| Finished | Jul 03 08:21:15 PM PDT 24 |
| Peak memory | 574344 kb |
| Host | smart-732f7a7a-f094-49d3-bc5d-016687fcc803 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3810029016 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_access_same_ device_slow_rsp.3810029016 |
| Directory | /workspace/83.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_access_same_device_slow_rsp.1539426158 |
| Short name | T392 |
| Test name | |
| Test status | |
| Simulation time | 82003794698 ps |
| CPU time | 1534.44 seconds |
| Started | Jul 03 07:36:48 PM PDT 24 |
| Finished | Jul 03 08:02:23 PM PDT 24 |
| Peak memory | 574308 kb |
| Host | smart-d92fe7d5-8b1d-4b10-a4c2-a965e467c449 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1539426158 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_access_same_ device_slow_rsp.1539426158 |
| Directory | /workspace/80.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_access_same_device_slow_rsp.4180861367 |
| Short name | T793 |
| Test name | |
| Test status | |
| Simulation time | 105135059983 ps |
| CPU time | 1947.33 seconds |
| Started | Jul 03 07:22:16 PM PDT 24 |
| Finished | Jul 03 07:54:47 PM PDT 24 |
| Peak memory | 574260 kb |
| Host | smart-0f4e9b73-ab76-41f1-8a65-26a85f1a3981 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4180861367 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_access_same_d evice_slow_rsp.4180861367 |
| Directory | /workspace/1.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/default/1.chip_sw_lc_walkthrough_dev.673202023 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 49764897352 ps |
| CPU time | 5980.88 seconds |
| Started | Jul 03 07:55:16 PM PDT 24 |
| Finished | Jul 03 09:34:58 PM PDT 24 |
| Peak memory | 624168 kb |
| Host | smart-d6218649-908c-4d0f-a7c6-24f71e7c7a61 |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStDev +sw_test_timeout_ns=200_000_000 +sw_build_de vice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=673202023 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=ch ip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_ sw_lc_walkthrough_dev.673202023 |
| Directory | /workspace/1.chip_sw_lc_walkthrough_dev/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sleep_pin_mio_dio_val.2216942720 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 2942846769 ps |
| CPU time | 309.65 seconds |
| Started | Jul 03 07:54:19 PM PDT 24 |
| Finished | Jul 03 07:59:29 PM PDT 24 |
| Peak memory | 608656 kb |
| Host | smart-9e036749-0c0f-4129-bbf0-ad9f19c4cf42 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +sw_build_device=sim_dv +sw_images=sleep_pin_mio_dio_val_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2216 942720 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_mio_dio_val_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sleep_pin_mio_dio_val.2216942720 |
| Directory | /workspace/1.chip_sw_sleep_pin_mio_dio_val/latest |
| Test location | /workspace/coverage/default/0.chip_plic_all_irqs_0.2605233833 |
| Short name | T306 |
| Test name | |
| Test status | |
| Simulation time | 6540908690 ps |
| CPU time | 1393.17 seconds |
| Started | Jul 03 07:49:37 PM PDT 24 |
| Finished | Jul 03 08:12:51 PM PDT 24 |
| Peak memory | 610616 kb |
| Host | smart-37c992d3-213f-43fb-8ecc-68033cac464e |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_0:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2605233833 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 0.chip_plic_all_irqs_0.2605233833 |
| Directory | /workspace/0.chip_plic_all_irqs_0/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_error_and_unmapped_addr.1962730194 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 1084130144 ps |
| CPU time | 42.62 seconds |
| Started | Jul 03 07:33:14 PM PDT 24 |
| Finished | Jul 03 07:33:57 PM PDT 24 |
| Peak memory | 574436 kb |
| Host | smart-22cc58e4-a67b-4c40-9893-2d3349af3157 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1962730194 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_error_and_unmapped_add r.1962730194 |
| Directory | /workspace/59.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_access_same_device_slow_rsp.3879619089 |
| Short name | T1546 |
| Test name | |
| Test status | |
| Simulation time | 116755136803 ps |
| CPU time | 2224.22 seconds |
| Started | Jul 03 07:32:35 PM PDT 24 |
| Finished | Jul 03 08:09:40 PM PDT 24 |
| Peak memory | 574684 kb |
| Host | smart-e48b3a37-2f8b-401a-8e75-ace8c3a97dcf |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3879619089 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_access_same_ device_slow_rsp.3879619089 |
| Directory | /workspace/55.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.1928644894 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 24199404018 ps |
| CPU time | 6308.85 seconds |
| Started | Jul 03 08:00:18 PM PDT 24 |
| Finished | Jul 03 09:45:28 PM PDT 24 |
| Peak memory | 608964 kb |
| Host | smart-72e1366b-2a41-44ee-ab3f-a8690241f9e5 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1928644894 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.1928644894 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_access_same_device_slow_rsp.2935426241 |
| Short name | T766 |
| Test name | |
| Test status | |
| Simulation time | 90419122951 ps |
| CPU time | 1548.66 seconds |
| Started | Jul 03 07:37:08 PM PDT 24 |
| Finished | Jul 03 08:02:58 PM PDT 24 |
| Peak memory | 574336 kb |
| Host | smart-6d23b2cd-bc3e-45de-b07f-2f5121560e44 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935426241 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_access_same_ device_slow_rsp.2935426241 |
| Directory | /workspace/82.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rv_core_ibex_address_translation.3256113109 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 3438422014 ps |
| CPU time | 282.57 seconds |
| Started | Jul 03 07:50:16 PM PDT 24 |
| Finished | Jul 03 07:54:59 PM PDT 24 |
| Peak memory | 610580 kb |
| Host | smart-575c9540-6a69-4fdf-af7e-9c958417fbfd |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=7_000_000 +sw_build_device=sim_dv +sw_images=rv_core_ibex_address_translation_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=3256113109 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_core_ibex_address_translation.3256113109 |
| Directory | /workspace/0.chip_sw_rv_core_ibex_address_translation/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sleep_pin_retention.1454143564 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 3019854902 ps |
| CPU time | 277.18 seconds |
| Started | Jul 03 07:53:33 PM PDT 24 |
| Finished | Jul 03 07:58:12 PM PDT 24 |
| Peak memory | 608096 kb |
| Host | smart-2e3dcabc-bd74-4a69-838a-9494ad76cc44 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sleep_pin_retention_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1454143564 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_retention_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 1.chip_sw_sleep_pin_retention.1454143564 |
| Directory | /workspace/1.chip_sw_sleep_pin_retention/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_stress_all_with_rand_reset.3868298833 |
| Short name | T393 |
| Test name | |
| Test status | |
| Simulation time | 14663881044 ps |
| CPU time | 822.16 seconds |
| Started | Jul 03 07:23:19 PM PDT 24 |
| Finished | Jul 03 07:37:03 PM PDT 24 |
| Peak memory | 574732 kb |
| Host | smart-2766c0d9-8de1-4ea5-9fc8-ae06aa318e5e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3868298833 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_ with_rand_reset.3868298833 |
| Directory | /workspace/7.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_alert_test.256744080 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 3260084196 ps |
| CPU time | 401.35 seconds |
| Started | Jul 03 07:59:03 PM PDT 24 |
| Finished | Jul 03 08:05:45 PM PDT 24 |
| Peak memory | 610572 kb |
| Host | smart-ba3644be-fc0c-4c07-9f62-232e1ef1ebae |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=alert_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=256744080 -assert nopostproc +UVM_TESTNAME=chip_bas e_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 1.chip_sw_alert_test.256744080 |
| Directory | /workspace/1.chip_sw_alert_test/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_access_same_device_slow_rsp.2228302229 |
| Short name | T421 |
| Test name | |
| Test status | |
| Simulation time | 73441250835 ps |
| CPU time | 1346.15 seconds |
| Started | Jul 03 07:27:03 PM PDT 24 |
| Finished | Jul 03 07:49:31 PM PDT 24 |
| Peak memory | 574256 kb |
| Host | smart-cfe64654-fc1a-492d-95b3-ca0cfa496a0a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2228302229 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_access_same_ device_slow_rsp.2228302229 |
| Directory | /workspace/26.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_access_same_device.2517760205 |
| Short name | T446 |
| Test name | |
| Test status | |
| Simulation time | 2404594464 ps |
| CPU time | 106.05 seconds |
| Started | Jul 03 07:36:35 PM PDT 24 |
| Finished | Jul 03 07:38:22 PM PDT 24 |
| Peak memory | 574224 kb |
| Host | smart-2529d73a-e22f-4fa6-a40e-b7a48a6f3ed4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2517760205 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_access_same_device .2517760205 |
| Directory | /workspace/79.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/3.chip_tl_errors.3226045812 |
| Short name | T506 |
| Test name | |
| Test status | |
| Simulation time | 4086515544 ps |
| CPU time | 242.95 seconds |
| Started | Jul 03 07:22:28 PM PDT 24 |
| Finished | Jul 03 07:26:33 PM PDT 24 |
| Peak memory | 599072 kb |
| Host | smart-12b2eb17-0e32-4a28-a7a4-cebb7d45617f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3226045812 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.chip_tl_errors.3226045812 |
| Directory | /workspace/3.chip_tl_errors/latest |
| Test location | /workspace/coverage/default/1.chip_sw_gpio.2474619986 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 3583501044 ps |
| CPU time | 484.56 seconds |
| Started | Jul 03 07:56:05 PM PDT 24 |
| Finished | Jul 03 08:04:10 PM PDT 24 |
| Peak memory | 610628 kb |
| Host | smart-2bcaed64-6e4e-4d14-a406-8b83c41d3b3d |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=gpio_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2474619986 -assert nopostproc +UVM_TESTNAME=chip_bas e_test +UVM_TEST_SEQ=chip_sw_gpio_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 1.chip_sw_gpio.2474619986 |
| Directory | /workspace/1.chip_sw_gpio/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.743530723 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 5528711364 ps |
| CPU time | 440.1 seconds |
| Started | Jul 03 07:52:34 PM PDT 24 |
| Finished | Jul 03 07:59:55 PM PDT 24 |
| Peak memory | 610684 kb |
| Host | smart-8f83b0df-76c3-47ba-8b92-2fa063ef668c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=8_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_wakeup_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74353072 3 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace /coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.743530723 |
| Directory | /workspace/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup/latest |
| Test location | /workspace/coverage/default/1.chip_plic_all_irqs_10.2552397123 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 4122031976 ps |
| CPU time | 501.24 seconds |
| Started | Jul 03 08:01:18 PM PDT 24 |
| Finished | Jul 03 08:09:40 PM PDT 24 |
| Peak memory | 607828 kb |
| Host | smart-0dce31da-9907-4b76-b843-2c85f40cc4a8 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_10:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552397123 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 1.chip_plic_all_irqs_10.2552397123 |
| Directory | /workspace/1.chip_plic_all_irqs_10/latest |
| Test location | /workspace/coverage/default/5.chip_sw_data_integrity_escalation.3616596386 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 4716646184 ps |
| CPU time | 561.16 seconds |
| Started | Jul 03 08:14:15 PM PDT 24 |
| Finished | Jul 03 08:23:37 PM PDT 24 |
| Peak memory | 609780 kb |
| Host | smart-bfd332f2-f49e-483f-b53e-4fea074986e7 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=data_integrity_escalation_reset_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3616596386 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_data_integrity_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.chip_sw_data_integrity_escalation.3616596386 |
| Directory | /workspace/5.chip_sw_data_integrity_escalation/latest |
| Test location | /workspace/coverage/default/7.chip_sw_csrng_edn_concurrency.3142486802 |
| Short name | T257 |
| Test name | |
| Test status | |
| Simulation time | 23877277376 ps |
| CPU time | 5501.29 seconds |
| Started | Jul 03 08:17:04 PM PDT 24 |
| Finished | Jul 03 09:48:46 PM PDT 24 |
| Peak memory | 608756 kb |
| Host | smart-d65dd9cc-732f-4815-ad13-b8c5e66a4f45 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +accelerate_cold_power_up_time=3 +accelerate_r egulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3142486802 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 7.chip_sw_csrng_edn_concurrency.3142486802 |
| Directory | /workspace/7.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspace/coverage/default/2.chip_jtag_csr_rw.2875798918 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 9234631844 ps |
| CPU time | 979.78 seconds |
| Started | Jul 03 08:02:27 PM PDT 24 |
| Finished | Jul 03 08:18:48 PM PDT 24 |
| Peak memory | 607904 kb |
| Host | smart-cb8dfcb5-5b05-4452-998d-6e8ce046676c |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +csr_rw +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875798918 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_T EST_SEQ=chip_jtag_csr_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.c hip_jtag_csr_rw.2875798918 |
| Directory | /workspace/2.chip_jtag_csr_rw/latest |
| Test location | /workspace/coverage/default/0.chip_sw_spi_device_pass_through_collision.380701375 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 4919204360 ps |
| CPU time | 672.75 seconds |
| Started | Jul 03 07:48:12 PM PDT 24 |
| Finished | Jul 03 07:59:26 PM PDT 24 |
| Peak memory | 624936 kb |
| Host | smart-bdaf8928-6262-4bb6-9099-766a233ef26a |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_passthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=380701375 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_passthrough_collision_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 0.chip_sw_spi_device_pass_through_collision.380701375 |
| Directory | /workspace/0.chip_sw_spi_device_pass_through_collision/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_stress_all_with_reset_error.706962773 |
| Short name | T617 |
| Test name | |
| Test status | |
| Simulation time | 11432681282 ps |
| CPU time | 558.45 seconds |
| Started | Jul 03 07:23:43 PM PDT 24 |
| Finished | Jul 03 07:33:03 PM PDT 24 |
| Peak memory | 574736 kb |
| Host | smart-abd9d6de-b9c5-4a1d-8d2a-5547bff6cec3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=706962773 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_ with_reset_error.706962773 |
| Directory | /workspace/9.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_random_large_delays.3127703844 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 66043523370 ps |
| CPU time | 727.79 seconds |
| Started | Jul 03 07:28:18 PM PDT 24 |
| Finished | Jul 03 07:40:28 PM PDT 24 |
| Peak memory | 574356 kb |
| Host | smart-a9d3a1a1-515f-43f4-9cfe-ed2f08ca4aef |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3127703844 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_random_large_delays.3127703844 |
| Directory | /workspace/32.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/18.chip_same_csr_outstanding.1144671046 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 29146481736 ps |
| CPU time | 3736.78 seconds |
| Started | Jul 03 07:25:18 PM PDT 24 |
| Finished | Jul 03 08:27:38 PM PDT 24 |
| Peak memory | 592488 kb |
| Host | smart-b82bb8aa-a3ae-4a32-b961-4e15f7f4a5a0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1144671046 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 18.chip_same_csr_outstanding.1144671046 |
| Directory | /workspace/18.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_rma_unlocked.2584749696 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 44649787960 ps |
| CPU time | 5108.9 seconds |
| Started | Jul 03 07:52:22 PM PDT 24 |
| Finished | Jul 03 09:17:32 PM PDT 24 |
| Peak memory | 619776 kb |
| Host | smart-618783a7-67b7-4dc5-8fea-3e6d88464ca0 |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=flash_rma_unlocked_test:0:test_in_ rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=2584749696 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_rma_unlocked_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_rma_unlocked.2584749696 |
| Directory | /workspace/1.chip_sw_flash_rma_unlocked/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sleep_pin_mio_dio_val.952059584 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 3017631825 ps |
| CPU time | 241.6 seconds |
| Started | Jul 03 08:04:20 PM PDT 24 |
| Finished | Jul 03 08:08:22 PM PDT 24 |
| Peak memory | 608696 kb |
| Host | smart-bf3bf39b-4003-4124-8b27-10b1e4192a35 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +sw_build_device=sim_dv +sw_images=sleep_pin_mio_dio_val_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9520 59584 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_mio_dio_val_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sleep_pin_mio_dio_val.952059584 |
| Directory | /workspace/2.chip_sw_sleep_pin_mio_dio_val/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_all_reset_reqs.3988209624 |
| Short name | T218 |
| Test name | |
| Test status | |
| Simulation time | 9540179552 ps |
| CPU time | 2025.05 seconds |
| Started | Jul 03 07:54:44 PM PDT 24 |
| Finished | Jul 03 08:28:29 PM PDT 24 |
| Peak memory | 610732 kb |
| Host | smart-8915d979-a3e8-4168-95c4-92b76c89b4ec |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3988 209624 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_all_reset_reqs.3988209624 |
| Directory | /workspace/1.chip_sw_pwrmgr_all_reset_reqs/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_stress_all_with_error.1209500646 |
| Short name | T787 |
| Test name | |
| Test status | |
| Simulation time | 12989897741 ps |
| CPU time | 489.36 seconds |
| Started | Jul 03 07:38:10 PM PDT 24 |
| Finished | Jul 03 07:46:20 PM PDT 24 |
| Peak memory | 574704 kb |
| Host | smart-ab35561a-856d-48ee-8df2-89db68e934de |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1209500646 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_stress_all_with_error.1209500646 |
| Directory | /workspace/88.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_pings.1737327463 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 12161398934 ps |
| CPU time | 1803.36 seconds |
| Started | Jul 03 07:51:23 PM PDT 24 |
| Finished | Jul 03 08:21:27 PM PDT 24 |
| Peak memory | 610260 kb |
| Host | smart-8b23e15e-0682-4e9f-8bb0-435db37c13b4 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler _lpg_sleep_mode_pings_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1737327463 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_han dler_shorten_ping_wait_cycle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_lpg_sleep_mode_pings.1737327463 |
| Directory | /workspace/0.chip_sw_alert_handler_lpg_sleep_mode_pings/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otp_ctrl_escalation.1852364165 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 5455404850 ps |
| CPU time | 758.1 seconds |
| Started | Jul 03 07:50:23 PM PDT 24 |
| Finished | Jul 03 08:03:02 PM PDT 24 |
| Peak memory | 610620 kb |
| Host | smart-ef526138-e116-499d-849b-e7fba90f1a48 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1852364165 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_escalation.1852364165 |
| Directory | /workspace/0.chip_sw_otp_ctrl_escalation/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sysrst_ctrl_inputs.951624285 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 3163540387 ps |
| CPU time | 339.83 seconds |
| Started | Jul 03 07:51:37 PM PDT 24 |
| Finished | Jul 03 07:57:18 PM PDT 24 |
| Peak memory | 612740 kb |
| Host | smart-d1f0524f-43db-4ec4-b68c-679702312810 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_inputs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=951624285 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_inputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul t.vdb -cm_log /dev/null -cm_name 0.chip_sw_sysrst_ctrl_inputs.951624285 |
| Directory | /workspace/0.chip_sw_sysrst_ctrl_inputs/latest |
| Test location | /workspace/coverage/cover_reg_top/18.chip_tl_errors.3854113516 |
| Short name | T519 |
| Test name | |
| Test status | |
| Simulation time | 4513341532 ps |
| CPU time | 423.63 seconds |
| Started | Jul 03 07:25:19 PM PDT 24 |
| Finished | Jul 03 07:32:25 PM PDT 24 |
| Peak memory | 599096 kb |
| Host | smart-0e15fca5-a5d1-4e55-b92c-bfada3e796a1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3854113516 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.chip_tl_errors.3854113516 |
| Directory | /workspace/18.chip_tl_errors/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sleep_pin_mio_dio_val.1207945439 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 3226685015 ps |
| CPU time | 283.41 seconds |
| Started | Jul 03 07:47:03 PM PDT 24 |
| Finished | Jul 03 07:51:47 PM PDT 24 |
| Peak memory | 608704 kb |
| Host | smart-6a1adebc-af6e-40a7-9cdb-f8b23e779529 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +sw_build_device=sim_dv +sw_images=sleep_pin_mio_dio_val_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207 945439 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_mio_dio_val_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sleep_pin_mio_dio_val.1207945439 |
| Directory | /workspace/0.chip_sw_sleep_pin_mio_dio_val/latest |
| Test location | /workspace/coverage/default/16.chip_sw_all_escalation_resets.353288743 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 5884321984 ps |
| CPU time | 546.7 seconds |
| Started | Jul 03 08:16:10 PM PDT 24 |
| Finished | Jul 03 08:25:18 PM PDT 24 |
| Peak memory | 641792 kb |
| Host | smart-fecdc701-4283-4088-b799-d78b97070b08 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 353288743 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.chip_sw_all_escalation_resets.353288743 |
| Directory | /workspace/16.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_wake_ups.678844652 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 24995264656 ps |
| CPU time | 1906.86 seconds |
| Started | Jul 03 08:01:10 PM PDT 24 |
| Finished | Jul 03 08:32:58 PM PDT 24 |
| Peak memory | 610040 kb |
| Host | smart-faa743b8-4e19-43dd-a386-bdfc39eeb002 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_all_wake_ups:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=678844652 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_random_sleep_all_wake_ups.678844652 |
| Directory | /workspace/1.chip_sw_pwrmgr_random_sleep_all_wake_ups/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_ctrl_lc_rw_en.832607973 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 4467596247 ps |
| CPU time | 416.54 seconds |
| Started | Jul 03 08:04:27 PM PDT 24 |
| Finished | Jul 03 08:11:25 PM PDT 24 |
| Peak memory | 610636 kb |
| Host | smart-96801458-3664-426f-9934-77e8bd51338b |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_lc_rw_en_test:1:new_rules,test_rom:0 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83 2607973 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_ctrl_lc_rw_en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_lc_rw_en.832607973 |
| Directory | /workspace/2.chip_sw_flash_ctrl_lc_rw_en/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_stress_all_with_error.3779499089 |
| Short name | T505 |
| Test name | |
| Test status | |
| Simulation time | 2618161224 ps |
| CPU time | 203.23 seconds |
| Started | Jul 03 07:28:02 PM PDT 24 |
| Finished | Jul 03 07:31:26 PM PDT 24 |
| Peak memory | 574728 kb |
| Host | smart-683d2d5c-d1fa-4a45-bc85-6e1050514348 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3779499089 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_error.3779499089 |
| Directory | /workspace/30.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_shutdown_output.3261493267 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 30663300376 ps |
| CPU time | 4099.62 seconds |
| Started | Jul 03 08:05:43 PM PDT 24 |
| Finished | Jul 03 09:14:03 PM PDT 24 |
| Peak memory | 611092 kb |
| Host | smart-351e22f5-ff41-49a0-906f-a83419045330 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_unsigned:1:ot_f lash_binary,otp_img_shutdown_output_test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3261493267 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chi p_sw_rom_e2e_shutdown_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_shutdown_output.3261493267 |
| Directory | /workspace/1.rom_e2e_shutdown_output/latest |
| Test location | /workspace/coverage/default/0.chip_tap_straps_testunlock0.2648577772 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 4783504114 ps |
| CPU time | 395.92 seconds |
| Started | Jul 03 07:50:21 PM PDT 24 |
| Finished | Jul 03 07:56:58 PM PDT 24 |
| Peak memory | 624100 kb |
| Host | smart-3d7f6603-54ec-4f2a-b36a-1589297bfbd6 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:te st_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2648577772 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_tap_straps_testunlock0.2648577772 |
| Directory | /workspace/0.chip_tap_straps_testunlock0/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_ctrl_rand_to_scrap.4043261996 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 3681850403 ps |
| CPU time | 156.1 seconds |
| Started | Jul 03 07:48:09 PM PDT 24 |
| Finished | Jul 03 07:50:46 PM PDT 24 |
| Peak memory | 619424 kb |
| Host | smart-b4bfec1e-90cd-4a7b-905a-5a53e71b6b94 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=lc_ctrl_scrap_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40432619 96 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_scrap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_rand_to_scrap.4043261996 |
| Directory | /workspace/0.chip_sw_lc_ctrl_rand_to_scrap/latest |
| Test location | /workspace/coverage/default/1.chip_sw_kmac_idle.3295534959 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 2772293282 ps |
| CPU time | 200.06 seconds |
| Started | Jul 03 07:59:26 PM PDT 24 |
| Finished | Jul 03 08:02:47 PM PDT 24 |
| Peak memory | 610632 kb |
| Host | smart-ba173c7e-fd74-4b92-b739-7152fc20a32c |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3295534959 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 1.chip_sw_kmac_idle.3295534959 |
| Directory | /workspace/1.chip_sw_kmac_idle/latest |
| Test location | /workspace/coverage/cover_reg_top/26.chip_tl_errors.3528115597 |
| Short name | T518 |
| Test name | |
| Test status | |
| Simulation time | 3974427848 ps |
| CPU time | 291.91 seconds |
| Started | Jul 03 07:26:58 PM PDT 24 |
| Finished | Jul 03 07:31:52 PM PDT 24 |
| Peak memory | 595996 kb |
| Host | smart-757c3199-c7d7-42d7-aaf1-f0f4da3949b5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3528115597 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.chip_tl_errors.3528115597 |
| Directory | /workspace/26.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_stress_all_with_rand_reset.1948650669 |
| Short name | T513 |
| Test name | |
| Test status | |
| Simulation time | 11450501686 ps |
| CPU time | 677.77 seconds |
| Started | Jul 03 07:27:31 PM PDT 24 |
| Finished | Jul 03 07:38:52 PM PDT 24 |
| Peak memory | 574680 kb |
| Host | smart-4f60ff72-79c7-4e24-913c-24b91e2d7168 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1948650669 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all _with_rand_reset.1948650669 |
| Directory | /workspace/28.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_rma_unlocked.336603902 |
| Short name | T203 |
| Test name | |
| Test status | |
| Simulation time | 43681886928 ps |
| CPU time | 4495.26 seconds |
| Started | Jul 03 08:04:16 PM PDT 24 |
| Finished | Jul 03 09:19:12 PM PDT 24 |
| Peak memory | 624936 kb |
| Host | smart-f02706f3-0a1d-4c27-98ed-c39c467cf32e |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=flash_rma_unlocked_test:0:test_in_ rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=336603902 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_rma_unlocked_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_rma_unlocked.336603902 |
| Directory | /workspace/2.chip_sw_flash_rma_unlocked/latest |
| Test location | /workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_alerts.1855736282 |
| Short name | T357 |
| Test name | |
| Test status | |
| Simulation time | 3743314200 ps |
| CPU time | 429.9 seconds |
| Started | Jul 03 07:56:09 PM PDT 24 |
| Finished | Jul 03 08:03:19 PM PDT 24 |
| Peak memory | 648288 kb |
| Host | smart-fdc51f51-7171-45b7-be81-2dc4c848f9b0 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1855736282 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_s w_alert_handler_lpg_sleep_mode_alerts.1855736282 |
| Directory | /workspace/1.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/36.chip_sw_all_escalation_resets.3948575188 |
| Short name | T244 |
| Test name | |
| Test status | |
| Simulation time | 5077666136 ps |
| CPU time | 648.91 seconds |
| Started | Jul 03 08:18:41 PM PDT 24 |
| Finished | Jul 03 08:29:31 PM PDT 24 |
| Peak memory | 641672 kb |
| Host | smart-8c19607f-74c2-4d07-8bec-fa4cb04af154 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3948575188 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.chip_sw_all_escalation_resets.3948575188 |
| Directory | /workspace/36.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/cover_reg_top/4.chip_csr_hw_reset.2551303709 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 4637443944 ps |
| CPU time | 262.78 seconds |
| Started | Jul 03 07:22:43 PM PDT 24 |
| Finished | Jul 03 07:27:07 PM PDT 24 |
| Peak memory | 659544 kb |
| Host | smart-30053a60-9b8a-4b8a-9921-6149725a2622 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2551303709 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.chip_csr_hw_r eset.2551303709 |
| Directory | /workspace/4.chip_csr_hw_reset/latest |
| Test location | /workspace/coverage/default/70.chip_sw_all_escalation_resets.2585754895 |
| Short name | T298 |
| Test name | |
| Test status | |
| Simulation time | 5763747918 ps |
| CPU time | 545.52 seconds |
| Started | Jul 03 08:20:13 PM PDT 24 |
| Finished | Jul 03 08:29:19 PM PDT 24 |
| Peak memory | 641612 kb |
| Host | smart-6b21e26e-0a87-47f1-a32c-54454cd80455 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2585754895 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.chip_sw_all_escalation_resets.2585754895 |
| Directory | /workspace/70.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/12.chip_sw_all_escalation_resets.1033223899 |
| Short name | T280 |
| Test name | |
| Test status | |
| Simulation time | 4161979800 ps |
| CPU time | 547.45 seconds |
| Started | Jul 03 08:18:17 PM PDT 24 |
| Finished | Jul 03 08:27:27 PM PDT 24 |
| Peak memory | 649184 kb |
| Host | smart-db3b3e98-6a63-41e0-89ce-c71b8aa3c619 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1033223899 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.chip_sw_all_escalation_resets.1033223899 |
| Directory | /workspace/12.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/0.chip_sw_data_integrity_escalation.1628043980 |
| Short name | T216 |
| Test name | |
| Test status | |
| Simulation time | 5843918048 ps |
| CPU time | 893.58 seconds |
| Started | Jul 03 07:47:53 PM PDT 24 |
| Finished | Jul 03 08:02:48 PM PDT 24 |
| Peak memory | 610720 kb |
| Host | smart-297f87d6-d200-4abc-a4ec-0017d02701d2 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=data_integrity_escalation_reset_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1628043980 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_data_integrity_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_data_integrity_escalation.1628043980 |
| Directory | /workspace/0.chip_sw_data_integrity_escalation/latest |
| Test location | /workspace/coverage/default/1.chip_sw_edn_entropy_reqs_jitter.467172402 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 7406043803 ps |
| CPU time | 1167.82 seconds |
| Started | Jul 03 07:58:00 PM PDT 24 |
| Finished | Jul 03 08:17:29 PM PDT 24 |
| Peak memory | 610764 kb |
| Host | smart-71dfe1c6-ea0e-46fa-8819-f469269154a4 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15000000 +rng_srate_value_min=15 +rng_srate_value_max=30 +en_jitter=1 +sw_build_device=sim_dv +sw_images=e ntropy_src_edn_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=467172402 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_edn_entropy_reqs_jitter.467172402 |
| Directory | /workspace/1.chip_sw_edn_entropy_reqs_jitter/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_stress_all_with_rand_reset.2505980851 |
| Short name | T453 |
| Test name | |
| Test status | |
| Simulation time | 4557013432 ps |
| CPU time | 607.19 seconds |
| Started | Jul 03 07:28:15 PM PDT 24 |
| Finished | Jul 03 07:38:25 PM PDT 24 |
| Peak memory | 574720 kb |
| Host | smart-dcb1fce0-83d1-41ec-97b5-717b704bdd11 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2505980851 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all _with_rand_reset.2505980851 |
| Directory | /workspace/31.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sensor_ctrl_alert.4142722855 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 7595271876 ps |
| CPU time | 713.92 seconds |
| Started | Jul 03 08:07:26 PM PDT 24 |
| Finished | Jul 03 08:19:20 PM PDT 24 |
| Peak memory | 610592 kb |
| Host | smart-adf3b726-34cb-4cf5-9ca6-3eddea50024f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_alert_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41427228 55 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sensor_ctrl_alert.4142722855 |
| Directory | /workspace/2.chip_sw_sensor_ctrl_alert/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sleep_pin_wake.1809988152 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 3063429600 ps |
| CPU time | 247.24 seconds |
| Started | Jul 03 07:48:09 PM PDT 24 |
| Finished | Jul 03 07:52:17 PM PDT 24 |
| Peak memory | 608484 kb |
| Host | smart-339594f2-3ca0-49f4-97f2-509330414947 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +sw_build_device=sim_dv +sw_images=sleep_pin_wake_test:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1809988152 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sleep_pin_wake.1809988152 |
| Directory | /workspace/0.chip_sw_sleep_pin_wake/latest |
| Test location | /workspace/coverage/default/2.chip_plic_all_irqs_0.3277766369 |
| Short name | T308 |
| Test name | |
| Test status | |
| Simulation time | 6222495420 ps |
| CPU time | 1168.75 seconds |
| Started | Jul 03 08:08:34 PM PDT 24 |
| Finished | Jul 03 08:28:03 PM PDT 24 |
| Peak memory | 608044 kb |
| Host | smart-3e52a4a3-e39b-47ca-9099-86241c2f3590 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_0:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3277766369 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 2.chip_plic_all_irqs_0.3277766369 |
| Directory | /workspace/2.chip_plic_all_irqs_0/latest |
| Test location | /workspace/coverage/cover_reg_top/6.chip_tl_errors.1963216876 |
| Short name | T644 |
| Test name | |
| Test status | |
| Simulation time | 6120725732 ps |
| CPU time | 539.08 seconds |
| Started | Jul 03 07:22:57 PM PDT 24 |
| Finished | Jul 03 07:31:58 PM PDT 24 |
| Peak memory | 603052 kb |
| Host | smart-442f67a8-3cbd-4400-a3b8-f127676edbe9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1963216876 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.chip_tl_errors.1963216876 |
| Directory | /workspace/6.chip_tl_errors/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sleep_pin_wake.3016754265 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 4555123838 ps |
| CPU time | 363.3 seconds |
| Started | Jul 03 08:05:36 PM PDT 24 |
| Finished | Jul 03 08:11:40 PM PDT 24 |
| Peak memory | 610116 kb |
| Host | smart-d1f3946e-4a21-4a96-9cad-61d066af90c4 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +sw_build_device=sim_dv +sw_images=sleep_pin_wake_test:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3016754265 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sleep_pin_wake.3016754265 |
| Directory | /workspace/2.chip_sw_sleep_pin_wake/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sleep_pin_wake.1877211665 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 3488005000 ps |
| CPU time | 325.85 seconds |
| Started | Jul 03 07:58:03 PM PDT 24 |
| Finished | Jul 03 08:03:29 PM PDT 24 |
| Peak memory | 609672 kb |
| Host | smart-06ac581e-c8a6-46ff-92d2-2ea9d9b1a087 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +sw_build_device=sim_dv +sw_images=sleep_pin_wake_test:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1877211665 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sleep_pin_wake.1877211665 |
| Directory | /workspace/1.chip_sw_sleep_pin_wake/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/0.chip_padctrl_attributes.2762272223 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 4812965576 ps |
| CPU time | 348.11 seconds |
| Started | Jul 03 08:15:12 PM PDT 24 |
| Finished | Jul 03 08:21:01 PM PDT 24 |
| Peak memory | 644100 kb |
| Host | smart-c16f2818-445a-4889-b0a8-3855ba4a0f0e |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2762272223 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/ null -cm_name 0.chip_padctrl_attributes.2762272223 |
| Directory | /workspace/0.chip_padctrl_attributes/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sram_ctrl_execution_main.1177190215 |
| Short name | T201 |
| Test name | |
| Test status | |
| Simulation time | 6941599045 ps |
| CPU time | 914.3 seconds |
| Started | Jul 03 08:09:19 PM PDT 24 |
| Finished | Jul 03 08:24:33 PM PDT 24 |
| Peak memory | 610688 kb |
| Host | smart-674292c5-7eb1-4388-812a-3cb852b77f35 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sram_ctrl_execution_main_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1177190215 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_execution_main_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sram_ctrl_execution_main.1177190215 |
| Directory | /workspace/2.chip_sw_sram_ctrl_execution_main/latest |
| Test location | /workspace/coverage/default/1.chip_plic_all_irqs_20.4249834997 |
| Short name | T310 |
| Test name | |
| Test status | |
| Simulation time | 5187181100 ps |
| CPU time | 799.31 seconds |
| Started | Jul 03 07:59:53 PM PDT 24 |
| Finished | Jul 03 08:13:13 PM PDT 24 |
| Peak memory | 610612 kb |
| Host | smart-310ac880-9fba-4631-969e-defb15fd38f8 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_20:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4249834997 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 1.chip_plic_all_irqs_20.4249834997 |
| Directory | /workspace/1.chip_plic_all_irqs_20/latest |
| Test location | /workspace/coverage/default/1.chip_sw_hmac_enc.2355998390 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 3191686904 ps |
| CPU time | 321.94 seconds |
| Started | Jul 03 07:59:10 PM PDT 24 |
| Finished | Jul 03 08:04:32 PM PDT 24 |
| Peak memory | 607656 kb |
| Host | smart-e712d54a-bd39-483e-a5db-54c7a3ac77af |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2355998390 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_hmac_enc.2355998390 |
| Directory | /workspace/1.chip_sw_hmac_enc/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_stress_all.2261311205 |
| Short name | T443 |
| Test name | |
| Test status | |
| Simulation time | 13955227488 ps |
| CPU time | 612.42 seconds |
| Started | Jul 03 07:34:09 PM PDT 24 |
| Finished | Jul 03 07:44:23 PM PDT 24 |
| Peak memory | 574704 kb |
| Host | smart-4e54e334-7f7c-489c-b9da-36e64771d6bf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2261311205 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_stress_all.2261311205 |
| Directory | /workspace/64.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/2.chip_csr_hw_reset.357775261 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 7870559669 ps |
| CPU time | 323.47 seconds |
| Started | Jul 03 07:22:27 PM PDT 24 |
| Finished | Jul 03 07:27:52 PM PDT 24 |
| Peak memory | 661744 kb |
| Host | smart-ee4897c4-709a-44c4-b463-fed5725077e5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=357775261 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.chip_csr_hw_re set.357775261 |
| Directory | /workspace/2.chip_csr_hw_reset/latest |
| Test location | /workspace/coverage/default/1.chip_plic_all_irqs_0.138558755 |
| Short name | T309 |
| Test name | |
| Test status | |
| Simulation time | 6092017720 ps |
| CPU time | 1130.4 seconds |
| Started | Jul 03 07:59:53 PM PDT 24 |
| Finished | Jul 03 08:18:45 PM PDT 24 |
| Peak memory | 610624 kb |
| Host | smart-685f8a6b-061e-4faf-9b5f-c29dea9d85c7 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_0:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=138558755 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 1.chip_plic_all_irqs_0.138558755 |
| Directory | /workspace/1.chip_plic_all_irqs_0/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_stress_all_with_rand_reset.3184971537 |
| Short name | T442 |
| Test name | |
| Test status | |
| Simulation time | 17195031993 ps |
| CPU time | 841.06 seconds |
| Started | Jul 03 07:30:31 PM PDT 24 |
| Finished | Jul 03 07:44:34 PM PDT 24 |
| Peak memory | 574720 kb |
| Host | smart-0ff763c1-621b-4758-8863-3398785b900f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3184971537 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all _with_rand_reset.3184971537 |
| Directory | /workspace/43.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_usbdev_aon_pullup.2184065907 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 3537388686 ps |
| CPU time | 475.6 seconds |
| Started | Jul 03 07:49:25 PM PDT 24 |
| Finished | Jul 03 07:57:22 PM PDT 24 |
| Peak memory | 610672 kb |
| Host | smart-477eea0e-8790-4491-9559-f4a0a9e3fee4 |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=usbdev_aon_pullup_test:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218406 5907 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_aon_pullup.2184065907 |
| Directory | /workspace/0.chip_sw_usbdev_aon_pullup/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_stress_all.1279340094 |
| Short name | T436 |
| Test name | |
| Test status | |
| Simulation time | 3479189110 ps |
| CPU time | 280.75 seconds |
| Started | Jul 03 07:22:06 PM PDT 24 |
| Finished | Jul 03 07:26:48 PM PDT 24 |
| Peak memory | 574696 kb |
| Host | smart-fa57c5c1-0e6c-435e-b5d2-9cb6ce807b68 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1279340094 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all.1279340094 |
| Directory | /workspace/0.xbar_stress_all/latest |
| Test location | /workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq.705338743 |
| Short name | T210 |
| Test name | |
| Test status | |
| Simulation time | 4863966450 ps |
| CPU time | 708.33 seconds |
| Started | Jul 03 07:47:47 PM PDT 24 |
| Finished | Jul 03 07:59:37 PM PDT 24 |
| Peak memory | 621372 kb |
| Host | smart-aebc0c88-b8ea-4871-a102-1e42a30f162e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=705338743 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_ba udrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx_ alt_clk_freq.705338743 |
| Directory | /workspace/0.chip_sw_uart_tx_rx_alt_clk_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access.2971107198 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 4435864640 ps |
| CPU time | 466.6 seconds |
| Started | Jul 03 07:50:30 PM PDT 24 |
| Finished | Jul 03 07:58:18 PM PDT 24 |
| Peak memory | 609796 kb |
| Host | smart-aca6dd42-e796-4af4-a0f8-d72fe436cbbc |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=12_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2971107198 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctr l_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw _sram_ctrl_scrambled_access.2971107198 |
| Directory | /workspace/0.chip_sw_sram_ctrl_scrambled_access/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_rma_unlocked.1959080907 |
| Short name | T205 |
| Test name | |
| Test status | |
| Simulation time | 43890738843 ps |
| CPU time | 4843.3 seconds |
| Started | Jul 03 07:47:58 PM PDT 24 |
| Finished | Jul 03 09:08:43 PM PDT 24 |
| Peak memory | 619920 kb |
| Host | smart-8834580f-9c25-4eec-b776-35c5d6bd4950 |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=flash_rma_unlocked_test:0:test_in_ rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=1959080907 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_rma_unlocked_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_rma_unlocked.1959080907 |
| Directory | /workspace/0.chip_sw_flash_rma_unlocked/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_stress_all_with_reset_error.1082248021 |
| Short name | T803 |
| Test name | |
| Test status | |
| Simulation time | 2475527518 ps |
| CPU time | 373.93 seconds |
| Started | Jul 03 07:23:38 PM PDT 24 |
| Finished | Jul 03 07:29:54 PM PDT 24 |
| Peak memory | 574692 kb |
| Host | smart-e98b1043-1bd9-469b-88a1-e55c678874d6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1082248021 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all _with_reset_error.1082248021 |
| Directory | /workspace/8.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/8.chip_tl_errors.1433712204 |
| Short name | T515 |
| Test name | |
| Test status | |
| Simulation time | 3489883406 ps |
| CPU time | 267.46 seconds |
| Started | Jul 03 07:23:20 PM PDT 24 |
| Finished | Jul 03 07:27:49 PM PDT 24 |
| Peak memory | 599076 kb |
| Host | smart-ca6a8ea9-9c93-4a8d-8199-f2d2062a6353 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1433712204 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.chip_tl_errors.1433712204 |
| Directory | /workspace/8.chip_tl_errors/latest |
| Test location | /workspace/coverage/default/0.chip_rv_dm_ndm_reset_req.271205789 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 4363911294 ps |
| CPU time | 576.14 seconds |
| Started | Jul 03 07:53:35 PM PDT 24 |
| Finished | Jul 03 08:03:12 PM PDT 24 |
| Peak memory | 619084 kb |
| Host | smart-5cf05b1f-f08f-4da6-8d2b-662cc1f60f43 |
| User | root |
| Command | /workspace/default/simv +en_scb_tl_err_chk=0 +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_ndm_reset_req_rma:1:new_rules,test_rom:0 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2 71205789 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_rv_dm_ndm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_rv_dm_ndm_reset_req.271205789 |
| Directory | /workspace/0.chip_rv_dm_ndm_reset_req/latest |
| Test location | /workspace/coverage/default/0.chip_plic_all_irqs_10.2701994111 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 4302404404 ps |
| CPU time | 447.24 seconds |
| Started | Jul 03 07:50:39 PM PDT 24 |
| Finished | Jul 03 07:58:07 PM PDT 24 |
| Peak memory | 609028 kb |
| Host | smart-afbf06d7-416c-4177-960f-a41d850cc7ea |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_10:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2701994111 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 0.chip_plic_all_irqs_10.2701994111 |
| Directory | /workspace/0.chip_plic_all_irqs_10/latest |
| Test location | /workspace/coverage/default/0.chip_sw_spi_host_tx_rx.1901438336 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 3272407970 ps |
| CPU time | 287.44 seconds |
| Started | Jul 03 07:47:59 PM PDT 24 |
| Finished | Jul 03 07:52:47 PM PDT 24 |
| Peak memory | 608196 kb |
| Host | smart-f266ba1d-f258-45a7-a9b5-f4b28f81f134 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1901438336 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 0.chip_sw_spi_host_tx_rx.1901438336 |
| Directory | /workspace/0.chip_sw_spi_host_tx_rx/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sensor_ctrl_alert.4242040667 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 7437971384 ps |
| CPU time | 1017.99 seconds |
| Started | Jul 03 07:49:19 PM PDT 24 |
| Finished | Jul 03 08:06:19 PM PDT 24 |
| Peak memory | 610636 kb |
| Host | smart-da37db84-cf9b-4188-9dbf-96dbe8887418 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_alert_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42420406 67 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sensor_ctrl_alert.4242040667 |
| Directory | /workspace/0.chip_sw_sensor_ctrl_alert/latest |
| Test location | /workspace/coverage/cover_reg_top/16.chip_same_csr_outstanding.2575334517 |
| Short name | T378 |
| Test name | |
| Test status | |
| Simulation time | 31714773096 ps |
| CPU time | 3105.72 seconds |
| Started | Jul 03 07:24:59 PM PDT 24 |
| Finished | Jul 03 08:16:46 PM PDT 24 |
| Peak memory | 592304 kb |
| Host | smart-9bb5b628-a115-4173-92a9-2c971e24331e |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2575334517 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 16.chip_same_csr_outstanding.2575334517 |
| Directory | /workspace/16.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/default/0.chip_plic_all_irqs_20.1587440122 |
| Short name | T307 |
| Test name | |
| Test status | |
| Simulation time | 4488644682 ps |
| CPU time | 738.16 seconds |
| Started | Jul 03 07:50:42 PM PDT 24 |
| Finished | Jul 03 08:03:00 PM PDT 24 |
| Peak memory | 610652 kb |
| Host | smart-230e2a04-f54e-488a-b085-9f829981abda |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_20:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1587440122 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 0.chip_plic_all_irqs_20.1587440122 |
| Directory | /workspace/0.chip_plic_all_irqs_20/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_stress_all_with_rand_reset.1547423441 |
| Short name | T1831 |
| Test name | |
| Test status | |
| Simulation time | 4430456169 ps |
| CPU time | 384.78 seconds |
| Started | Jul 03 07:30:40 PM PDT 24 |
| Finished | Jul 03 07:37:06 PM PDT 24 |
| Peak memory | 574712 kb |
| Host | smart-ebd2b61c-b216-4ca7-8a36-f9de4d33d244 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1547423441 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all _with_rand_reset.1547423441 |
| Directory | /workspace/44.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_exit_test_unlocked_bootstrap.2756420778 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 58308912522 ps |
| CPU time | 11214.7 seconds |
| Started | Jul 03 07:50:03 PM PDT 24 |
| Finished | Jul 03 10:57:00 PM PDT 24 |
| Peak memory | 624832 kb |
| Host | smart-528b3c7c-cf6d-4d50-b184-5f8d02820fa3 |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=exit_test_unlocked_bootstrap:1:new _rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/s im.tcl +ntb_random_seed=2756420778 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_exit_test_unlocked_bootstrap_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_exit_test_unlocked_bootstrap.2756420778 |
| Directory | /workspace/0.chip_sw_exit_test_unlocked_bootstrap/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otp_ctrl_vendor_test_csr_access.3849813598 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 2951153627 ps |
| CPU time | 202.65 seconds |
| Started | Jul 03 07:48:35 PM PDT 24 |
| Finished | Jul 03 07:51:59 PM PDT 24 |
| Peak memory | 618848 kb |
| Host | smart-98be951f-fbaf-4f5f-b802-aff0b0ff5104 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_vendor_test_csr_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3849813598 -assert nopost proc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_vendor_test_csr_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_vendor_test_csr_access.3849813598 |
| Directory | /workspace/0.chip_sw_otp_ctrl_vendor_test_csr_access/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sysrst_ctrl_ec_rst_l.1639900944 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 20868020733 ps |
| CPU time | 3960.91 seconds |
| Started | Jul 03 08:07:31 PM PDT 24 |
| Finished | Jul 03 09:13:33 PM PDT 24 |
| Peak memory | 609728 kb |
| Host | smart-ef3ddf9b-d296-42de-bdf4-a2a48bf29914 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_ec_rst_l_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1639900944 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_ec_rst_l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d efault.vdb -cm_log /dev/null -cm_name 2.chip_sw_sysrst_ctrl_ec_rst_l.1639900944 |
| Directory | /workspace/2.chip_sw_sysrst_ctrl_ec_rst_l/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_stress_all_with_reset_error.3225889090 |
| Short name | T800 |
| Test name | |
| Test status | |
| Simulation time | 1543672633 ps |
| CPU time | 236.86 seconds |
| Started | Jul 03 07:32:11 PM PDT 24 |
| Finished | Jul 03 07:36:09 PM PDT 24 |
| Peak memory | 574492 kb |
| Host | smart-8882abf4-4a0b-41ea-92bf-a5e0cfbe7dc7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3225889090 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_stress_al l_with_reset_error.3225889090 |
| Directory | /workspace/52.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/default/4.chip_sw_uart_tx_rx.2099420365 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 4507037320 ps |
| CPU time | 698.62 seconds |
| Started | Jul 03 08:14:09 PM PDT 24 |
| Finished | Jul 03 08:25:48 PM PDT 24 |
| Peak memory | 622240 kb |
| Host | smart-ec2b2053-e669-46a8-badf-c511909271d8 |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2099420365 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_tx_rx.2099420365 |
| Directory | /workspace/4.chip_sw_uart_tx_rx/latest |
| Test location | /workspace/coverage/default/1.chip_sw_uart_rand_baudrate.4103698817 |
| Short name | T291 |
| Test name | |
| Test status | |
| Simulation time | 8196771776 ps |
| CPU time | 1592.05 seconds |
| Started | Jul 03 07:57:53 PM PDT 24 |
| Finished | Jul 03 08:24:26 PM PDT 24 |
| Peak memory | 620260 kb |
| Host | smart-1d97b314-9858-4164-ae3b-95bff962a413 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=4103698817 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_rand_baudrate.4103698817 |
| Directory | /workspace/1.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.2798155240 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 19407845176 ps |
| CPU time | 596.65 seconds |
| Started | Jul 03 07:49:16 PM PDT 24 |
| Finished | Jul 03 07:59:13 PM PDT 24 |
| Peak memory | 619220 kb |
| Host | smart-2fa208eb-0f32-4672-85ec-0e86441bd77d |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=adc_ctrl_sleep_debug_cable_wakeup_test:1:new_rules,test_rom: 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=2798155240 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.2798155240 |
| Directory | /workspace/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup/latest |
| Test location | /workspace/coverage/default/0.chip_sw_uart_tx_rx_idx3.2420089433 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 3819105400 ps |
| CPU time | 560.29 seconds |
| Started | Jul 03 07:47:41 PM PDT 24 |
| Finished | Jul 03 07:57:02 PM PDT 24 |
| Peak memory | 621956 kb |
| Host | smart-f64156c6-e35a-4a10-824e-8ea9eb427596 |
| User | root |
| Command | /workspace/default/simv +uart_idx=3 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2420089433 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx_idx3.2420089433 |
| Directory | /workspace/0.chip_sw_uart_tx_rx_idx3/latest |
| Test location | /workspace/coverage/default/0.chip_sw_power_sleep_load.2287308074 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 4830813464 ps |
| CPU time | 526.14 seconds |
| Started | Jul 03 07:49:45 PM PDT 24 |
| Finished | Jul 03 07:58:32 PM PDT 24 |
| Peak memory | 608552 kb |
| Host | smart-44b09965-dcd3-4350-8591-3c9f7e25e807 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=chip_power_sleep_load:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2287308074 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_sleep_load_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 0.chip_sw_power_sleep_load.2287308074 |
| Directory | /workspace/0.chip_sw_power_sleep_load/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_stress_all_with_rand_reset.4183175362 |
| Short name | T463 |
| Test name | |
| Test status | |
| Simulation time | 7962400270 ps |
| CPU time | 875.3 seconds |
| Started | Jul 03 07:36:52 PM PDT 24 |
| Finished | Jul 03 07:51:30 PM PDT 24 |
| Peak memory | 574744 kb |
| Host | smart-364576e2-f260-4c36-8ae5-c5b3c2db18dd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4183175362 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_stress_all _with_rand_reset.4183175362 |
| Directory | /workspace/80.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.72465416 |
| Short name | T953 |
| Test name | |
| Test status | |
| Simulation time | 4493818674 ps |
| CPU time | 711.01 seconds |
| Started | Jul 03 07:50:11 PM PDT 24 |
| Finished | Jul 03 08:02:03 PM PDT 24 |
| Peak memory | 614312 kb |
| Host | smart-eb0f4c3d-c0cc-4766-9e67-0de45e68e6b7 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStTestUnlocked0 +sw_build_device=sim_ dv +sw_images=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72465416 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_ TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.c hip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.72465416 |
| Directory | /workspace/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0/latest |
| Test location | /workspace/coverage/default/0.chip_sw_keymgr_sideload_otbn.1054452434 |
| Short name | T220 |
| Test name | |
| Test status | |
| Simulation time | 13727945298 ps |
| CPU time | 4143.94 seconds |
| Started | Jul 03 07:49:21 PM PDT 24 |
| Finished | Jul 03 08:58:26 PM PDT 24 |
| Peak memory | 610748 kb |
| Host | smart-cda85cce-6cf6-4d9b-9677-a103c8b60450 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_otbn_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10544 52434 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_sideload_otbn.1054452434 |
| Directory | /workspace/0.chip_sw_keymgr_sideload_otbn/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_init.1820072205 |
| Short name | T232 |
| Test name | |
| Test status | |
| Simulation time | 17320371076 ps |
| CPU time | 2195.04 seconds |
| Started | Jul 03 07:56:00 PM PDT 24 |
| Finished | Jul 03 08:32:36 PM PDT 24 |
| Peak memory | 615636 kb |
| Host | smart-e8dd807b-9d55-493e-aa2a-ece4f982d6d9 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=25_000_000 +sw_build_device=sim_dv +sw_images=flash_init_test:0:test_in_rom:new_rules +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1820072205 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_init.1820072205 |
| Directory | /workspace/1.chip_sw_flash_init/latest |
| Test location | /workspace/coverage/default/2.chip_sw_all_escalation_resets.1680887206 |
| Short name | T682 |
| Test name | |
| Test status | |
| Simulation time | 4820676484 ps |
| CPU time | 574.97 seconds |
| Started | Jul 03 08:05:37 PM PDT 24 |
| Finished | Jul 03 08:15:13 PM PDT 24 |
| Peak memory | 641240 kb |
| Host | smart-3e1f4b79-c068-4133-8a44-1082856906ad |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1680887206 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_all_escalation_resets.1680887206 |
| Directory | /workspace/2.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_ctrl_ops.889781003 |
| Short name | T330 |
| Test name | |
| Test status | |
| Simulation time | 4086741908 ps |
| CPU time | 774.87 seconds |
| Started | Jul 03 08:07:35 PM PDT 24 |
| Finished | Jul 03 08:20:30 PM PDT 24 |
| Peak memory | 610624 kb |
| Host | smart-213b6c2f-f5ee-4d53-8840-979d58577acb |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889781003 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_ops.889781003 |
| Directory | /workspace/2.chip_sw_flash_ctrl_ops/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_stress_all_with_rand_reset.403704771 |
| Short name | T811 |
| Test name | |
| Test status | |
| Simulation time | 2389165987 ps |
| CPU time | 212.14 seconds |
| Started | Jul 03 07:25:53 PM PDT 24 |
| Finished | Jul 03 07:29:27 PM PDT 24 |
| Peak memory | 574732 kb |
| Host | smart-6570bf70-b6c2-4bf0-b136-d649da6b6dc7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=403704771 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_ with_rand_reset.403704771 |
| Directory | /workspace/20.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_stress_all_with_rand_reset.2339642178 |
| Short name | T815 |
| Test name | |
| Test status | |
| Simulation time | 1607003468 ps |
| CPU time | 246.35 seconds |
| Started | Jul 03 07:34:16 PM PDT 24 |
| Finished | Jul 03 07:38:23 PM PDT 24 |
| Peak memory | 574668 kb |
| Host | smart-5dfbd60a-11b7-4819-a0cd-f49579f33346 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2339642178 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_stress_all _with_rand_reset.2339642178 |
| Directory | /workspace/65.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_csrng_lc_hw_debug_en_test.1818067554 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 6883236086 ps |
| CPU time | 758.16 seconds |
| Started | Jul 03 07:56:59 PM PDT 24 |
| Finished | Jul 03 08:09:38 PM PDT 24 |
| Peak memory | 610820 kb |
| Host | smart-a6caa8ae-cecb-45f6-a1ca-a06818f84ab8 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +rng_srate_value_min=15 +use_otp_image=OtpTypeLcStTestUnlocked0 +sw_build_device=sim_dv +sw_ima ges=csrng_lc_hw_debug_en_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818067554 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_csrng_ lc_hw_debug_en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_csr ng_lc_hw_debug_en_test.1818067554 |
| Directory | /workspace/1.chip_sw_csrng_lc_hw_debug_en_test/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otp_ctrl_vendor_test_csr_access.1869132046 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 2861586741 ps |
| CPU time | 209.89 seconds |
| Started | Jul 03 07:55:44 PM PDT 24 |
| Finished | Jul 03 07:59:14 PM PDT 24 |
| Peak memory | 618888 kb |
| Host | smart-2b8ab93d-3246-4b6c-a2c8-4f73c9c9d815 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_vendor_test_csr_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1869132046 -assert nopost proc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_vendor_test_csr_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otp_ctrl_vendor_test_csr_access.1869132046 |
| Directory | /workspace/1.chip_sw_otp_ctrl_vendor_test_csr_access/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_stress_all_with_rand_reset.3365072425 |
| Short name | T2401 |
| Test name | |
| Test status | |
| Simulation time | 7402710673 ps |
| CPU time | 544.72 seconds |
| Started | Jul 03 07:37:12 PM PDT 24 |
| Finished | Jul 03 07:46:18 PM PDT 24 |
| Peak memory | 574772 kb |
| Host | smart-01e02f9b-df59-4468-9a20-6cb908fafaf9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3365072425 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_stress_all _with_rand_reset.3365072425 |
| Directory | /workspace/82.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/10.chip_tl_errors.17039121 |
| Short name | T530 |
| Test name | |
| Test status | |
| Simulation time | 3538813880 ps |
| CPU time | 246.49 seconds |
| Started | Jul 03 07:23:52 PM PDT 24 |
| Finished | Jul 03 07:27:59 PM PDT 24 |
| Peak memory | 598068 kb |
| Host | smart-4ff27b91-7e9d-4887-8894-e43e4d4a6495 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17039121 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.chip_tl_errors.17039121 |
| Directory | /workspace/10.chip_tl_errors/latest |
| Test location | /workspace/coverage/default/34.chip_sw_all_escalation_resets.2561187679 |
| Short name | T993 |
| Test name | |
| Test status | |
| Simulation time | 4726786164 ps |
| CPU time | 645.27 seconds |
| Started | Jul 03 08:18:52 PM PDT 24 |
| Finished | Jul 03 08:29:38 PM PDT 24 |
| Peak memory | 641376 kb |
| Host | smart-5e9cc569-874d-45a8-a32c-bd388c2b5456 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2561187679 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.chip_sw_all_escalation_resets.2561187679 |
| Directory | /workspace/34.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_access_same_device_slow_rsp.435373713 |
| Short name | T430 |
| Test name | |
| Test status | |
| Simulation time | 99287692949 ps |
| CPU time | 1881.53 seconds |
| Started | Jul 03 07:30:24 PM PDT 24 |
| Finished | Jul 03 08:01:48 PM PDT 24 |
| Peak memory | 574284 kb |
| Host | smart-a2090be1-774b-4b25-a3e9-69286f964e9d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=435373713 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_access_same_d evice_slow_rsp.435373713 |
| Directory | /workspace/43.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/default/1.chip_sw_entropy_src_csrng.2026217572 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 5587229768 ps |
| CPU time | 1434.9 seconds |
| Started | Jul 03 07:57:28 PM PDT 24 |
| Finished | Jul 03 08:21:24 PM PDT 24 |
| Peak memory | 610772 kb |
| Host | smart-6a6ba68f-ba5c-43f7-9e66-c2536516709b |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_ csrng_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2026217572 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_entropy_src_csrng.2026217572 |
| Directory | /workspace/1.chip_sw_entropy_src_csrng/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.3725627261 |
| Short name | T338 |
| Test name | |
| Test status | |
| Simulation time | 4966149270 ps |
| CPU time | 895.71 seconds |
| Started | Jul 03 08:02:19 PM PDT 24 |
| Finished | Jul 03 08:17:16 PM PDT 24 |
| Peak memory | 609396 kb |
| Host | smart-05e8c79c-e011-45d8-8fb8-0d558760542a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_ rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si m.tcl +ntb_random_seed=3725627261 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.3725627261 |
| Directory | /workspace/1.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_usbdev_config_host.4240065041 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 8066915424 ps |
| CPU time | 2157.74 seconds |
| Started | Jul 03 07:49:35 PM PDT 24 |
| Finished | Jul 03 08:25:34 PM PDT 24 |
| Peak memory | 610712 kb |
| Host | smart-236503d9-dfdd-4dce-842b-ce11a633d37d |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=usbdev_config_host_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42400 65041 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_config_host.4240065041 |
| Directory | /workspace/0.chip_sw_usbdev_config_host/latest |
| Test location | /workspace/coverage/default/2.chip_sw_lc_walkthrough_prod.275416208 |
| Short name | T234 |
| Test name | |
| Test status | |
| Simulation time | 50473117813 ps |
| CPU time | 5055.32 seconds |
| Started | Jul 03 08:05:46 PM PDT 24 |
| Finished | Jul 03 09:30:03 PM PDT 24 |
| Peak memory | 615844 kb |
| Host | smart-93bba11f-a926-4bf1-95a7-b78f596da0a8 |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStProd +sw_test_timeout_ns=200_000_000 +sw_build_d evice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=275416208 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=c hip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip _sw_lc_walkthrough_prod.275416208 |
| Directory | /workspace/2.chip_sw_lc_walkthrough_prod/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_stress_all_with_rand_reset.2710545550 |
| Short name | T820 |
| Test name | |
| Test status | |
| Simulation time | 658540491 ps |
| CPU time | 272.24 seconds |
| Started | Jul 03 07:22:17 PM PDT 24 |
| Finished | Jul 03 07:26:53 PM PDT 24 |
| Peak memory | 574652 kb |
| Host | smart-41068aaa-8768-44e1-967b-e7ba790077ff |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2710545550 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_ with_rand_reset.2710545550 |
| Directory | /workspace/1.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_stress_all_with_rand_reset.980387511 |
| Short name | T804 |
| Test name | |
| Test status | |
| Simulation time | 14859487347 ps |
| CPU time | 780.48 seconds |
| Started | Jul 03 07:24:47 PM PDT 24 |
| Finished | Jul 03 07:37:49 PM PDT 24 |
| Peak memory | 574740 kb |
| Host | smart-b6c30f83-1ec2-4452-9025-b40a326f227e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=980387511 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_ with_rand_reset.980387511 |
| Directory | /workspace/14.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_access_same_device_slow_rsp.617533293 |
| Short name | T788 |
| Test name | |
| Test status | |
| Simulation time | 145037562356 ps |
| CPU time | 2643.35 seconds |
| Started | Jul 03 07:25:43 PM PDT 24 |
| Finished | Jul 03 08:09:48 PM PDT 24 |
| Peak memory | 574628 kb |
| Host | smart-d3cefadd-795a-4532-8289-3adb7d89d092 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=617533293 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_access_same_d evice_slow_rsp.617533293 |
| Directory | /workspace/19.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_alerts.1016473370 |
| Short name | T662 |
| Test name | |
| Test status | |
| Simulation time | 4192867872 ps |
| CPU time | 516.17 seconds |
| Started | Jul 03 07:52:45 PM PDT 24 |
| Finished | Jul 03 08:01:22 PM PDT 24 |
| Peak memory | 648728 kb |
| Host | smart-e0aa5520-e061-4c13-af4a-0a15bc529e89 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1016473370 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_s w_alert_handler_lpg_sleep_mode_alerts.1016473370 |
| Directory | /workspace/0.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/0.chip_sw_all_escalation_resets.2119367887 |
| Short name | T691 |
| Test name | |
| Test status | |
| Simulation time | 5417557430 ps |
| CPU time | 633.98 seconds |
| Started | Jul 03 07:46:36 PM PDT 24 |
| Finished | Jul 03 07:57:11 PM PDT 24 |
| Peak memory | 641204 kb |
| Host | smart-9240e70e-ad28-4d50-84ed-e61b166c6667 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2119367887 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_all_escalation_resets.2119367887 |
| Directory | /workspace/0.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/1.chip_sw_all_escalation_resets.1391719034 |
| Short name | T752 |
| Test name | |
| Test status | |
| Simulation time | 5284711696 ps |
| CPU time | 636.1 seconds |
| Started | Jul 03 07:54:00 PM PDT 24 |
| Finished | Jul 03 08:04:37 PM PDT 24 |
| Peak memory | 649480 kb |
| Host | smart-b046e64a-b0c9-4f42-80cc-6b9d0eb2c2e9 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1391719034 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_all_escalation_resets.1391719034 |
| Directory | /workspace/1.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/10.chip_sw_all_escalation_resets.3299355694 |
| Short name | T734 |
| Test name | |
| Test status | |
| Simulation time | 6561649642 ps |
| CPU time | 749.91 seconds |
| Started | Jul 03 08:15:11 PM PDT 24 |
| Finished | Jul 03 08:27:42 PM PDT 24 |
| Peak memory | 649572 kb |
| Host | smart-37ccb641-6747-4aa3-99df-2bf8713c39f2 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3299355694 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.chip_sw_all_escalation_resets.3299355694 |
| Directory | /workspace/10.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/11.chip_sw_alert_handler_lpg_sleep_mode_alerts.2860487276 |
| Short name | T615 |
| Test name | |
| Test status | |
| Simulation time | 4018892126 ps |
| CPU time | 449.22 seconds |
| Started | Jul 03 08:17:04 PM PDT 24 |
| Finished | Jul 03 08:24:34 PM PDT 24 |
| Peak memory | 641272 kb |
| Host | smart-707ba0b3-0045-4d4b-a8c0-ae4d5e20c51c |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2860487276 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2860487276 |
| Directory | /workspace/11.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/12.chip_sw_alert_handler_lpg_sleep_mode_alerts.18060673 |
| Short name | T738 |
| Test name | |
| Test status | |
| Simulation time | 4145594136 ps |
| CPU time | 411.63 seconds |
| Started | Jul 03 08:18:17 PM PDT 24 |
| Finished | Jul 03 08:25:11 PM PDT 24 |
| Peak memory | 648344 kb |
| Host | smart-836ac53c-0723-406e-912d-bcf2ff3b9aca |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18060673 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_ escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.chip_sw _alert_handler_lpg_sleep_mode_alerts.18060673 |
| Directory | /workspace/12.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/13.chip_sw_all_escalation_resets.3536703269 |
| Short name | T723 |
| Test name | |
| Test status | |
| Simulation time | 5350740588 ps |
| CPU time | 589.47 seconds |
| Started | Jul 03 08:16:04 PM PDT 24 |
| Finished | Jul 03 08:25:54 PM PDT 24 |
| Peak memory | 649488 kb |
| Host | smart-43eb2499-d1a4-485b-932d-a15e7b156379 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3536703269 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.chip_sw_all_escalation_resets.3536703269 |
| Directory | /workspace/13.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/14.chip_sw_all_escalation_resets.1703967428 |
| Short name | T409 |
| Test name | |
| Test status | |
| Simulation time | 5288514770 ps |
| CPU time | 642.24 seconds |
| Started | Jul 03 08:16:21 PM PDT 24 |
| Finished | Jul 03 08:27:04 PM PDT 24 |
| Peak memory | 641316 kb |
| Host | smart-6a38aa23-845a-4ecf-af77-05bda1c7b292 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1703967428 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.chip_sw_all_escalation_resets.1703967428 |
| Directory | /workspace/14.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/16.chip_sw_alert_handler_lpg_sleep_mode_alerts.1950198921 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 3769842352 ps |
| CPU time | 493.99 seconds |
| Started | Jul 03 08:15:57 PM PDT 24 |
| Finished | Jul 03 08:24:12 PM PDT 24 |
| Peak memory | 641200 kb |
| Host | smart-b2e2dbc0-184e-42e1-af25-521cd98ba064 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950198921 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1950198921 |
| Directory | /workspace/16.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/17.chip_sw_alert_handler_lpg_sleep_mode_alerts.3656083205 |
| Short name | T246 |
| Test name | |
| Test status | |
| Simulation time | 3436924552 ps |
| CPU time | 467.2 seconds |
| Started | Jul 03 08:16:16 PM PDT 24 |
| Finished | Jul 03 08:24:04 PM PDT 24 |
| Peak memory | 641240 kb |
| Host | smart-22287824-5191-4e57-bd32-b30efd8e2791 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3656083205 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3656083205 |
| Directory | /workspace/17.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/17.chip_sw_all_escalation_resets.1688260882 |
| Short name | T739 |
| Test name | |
| Test status | |
| Simulation time | 5494359980 ps |
| CPU time | 548.1 seconds |
| Started | Jul 03 08:16:44 PM PDT 24 |
| Finished | Jul 03 08:25:53 PM PDT 24 |
| Peak memory | 649576 kb |
| Host | smart-ed9d942e-9abd-484f-96a6-a09b11b2f88e |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1688260882 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.chip_sw_all_escalation_resets.1688260882 |
| Directory | /workspace/17.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/18.chip_sw_all_escalation_resets.2318647450 |
| Short name | T742 |
| Test name | |
| Test status | |
| Simulation time | 6036651480 ps |
| CPU time | 826.77 seconds |
| Started | Jul 03 08:16:13 PM PDT 24 |
| Finished | Jul 03 08:30:00 PM PDT 24 |
| Peak memory | 649588 kb |
| Host | smart-e5099513-1cd0-4531-8486-9ca4050b7a64 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2318647450 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.chip_sw_all_escalation_resets.2318647450 |
| Directory | /workspace/18.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/19.chip_sw_alert_handler_lpg_sleep_mode_alerts.2748152854 |
| Short name | T697 |
| Test name | |
| Test status | |
| Simulation time | 3669308302 ps |
| CPU time | 378.67 seconds |
| Started | Jul 03 08:17:35 PM PDT 24 |
| Finished | Jul 03 08:23:55 PM PDT 24 |
| Peak memory | 648708 kb |
| Host | smart-e3656c9f-bd90-4a00-a525-3bb7161fc15e |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748152854 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2748152854 |
| Directory | /workspace/19.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/19.chip_sw_all_escalation_resets.2722900073 |
| Short name | T666 |
| Test name | |
| Test status | |
| Simulation time | 4981344620 ps |
| CPU time | 823.81 seconds |
| Started | Jul 03 08:19:21 PM PDT 24 |
| Finished | Jul 03 08:33:07 PM PDT 24 |
| Peak memory | 649548 kb |
| Host | smart-b3f1c09b-10b0-42c9-b595-e0ba687f0875 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2722900073 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.chip_sw_all_escalation_resets.2722900073 |
| Directory | /workspace/19.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/20.chip_sw_alert_handler_lpg_sleep_mode_alerts.3707089887 |
| Short name | T1159 |
| Test name | |
| Test status | |
| Simulation time | 4017295482 ps |
| CPU time | 434.56 seconds |
| Started | Jul 03 08:19:21 PM PDT 24 |
| Finished | Jul 03 08:26:37 PM PDT 24 |
| Peak memory | 648352 kb |
| Host | smart-6fc43870-3ffc-4e34-977e-604baffd1d01 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3707089887 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3707089887 |
| Directory | /workspace/20.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/20.chip_sw_all_escalation_resets.2221373620 |
| Short name | T755 |
| Test name | |
| Test status | |
| Simulation time | 6094238998 ps |
| CPU time | 719.33 seconds |
| Started | Jul 03 08:17:16 PM PDT 24 |
| Finished | Jul 03 08:29:16 PM PDT 24 |
| Peak memory | 649520 kb |
| Host | smart-92ea5757-88b9-46af-9e33-f29251ddd844 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2221373620 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.chip_sw_all_escalation_resets.2221373620 |
| Directory | /workspace/20.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/21.chip_sw_all_escalation_resets.3871942545 |
| Short name | T700 |
| Test name | |
| Test status | |
| Simulation time | 4562683960 ps |
| CPU time | 505.81 seconds |
| Started | Jul 03 08:16:56 PM PDT 24 |
| Finished | Jul 03 08:25:23 PM PDT 24 |
| Peak memory | 649780 kb |
| Host | smart-0280f2a1-bfdb-4ba7-8e12-b85d4d69c7ce |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3871942545 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.chip_sw_all_escalation_resets.3871942545 |
| Directory | /workspace/21.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/22.chip_sw_all_escalation_resets.2172865739 |
| Short name | T675 |
| Test name | |
| Test status | |
| Simulation time | 6118398616 ps |
| CPU time | 708.18 seconds |
| Started | Jul 03 08:17:36 PM PDT 24 |
| Finished | Jul 03 08:29:25 PM PDT 24 |
| Peak memory | 649552 kb |
| Host | smart-2e7f0535-110d-44bf-8f17-24e25847f52c |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2172865739 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.chip_sw_all_escalation_resets.2172865739 |
| Directory | /workspace/22.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/23.chip_sw_alert_handler_lpg_sleep_mode_alerts.2132399819 |
| Short name | T687 |
| Test name | |
| Test status | |
| Simulation time | 3451321588 ps |
| CPU time | 430.43 seconds |
| Started | Jul 03 08:17:34 PM PDT 24 |
| Finished | Jul 03 08:24:45 PM PDT 24 |
| Peak memory | 648360 kb |
| Host | smart-340c8e97-657b-4817-b7cd-4be663080f70 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2132399819 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2132399819 |
| Directory | /workspace/23.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/25.chip_sw_alert_handler_lpg_sleep_mode_alerts.2971026837 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 3412147392 ps |
| CPU time | 486.69 seconds |
| Started | Jul 03 08:17:56 PM PDT 24 |
| Finished | Jul 03 08:26:04 PM PDT 24 |
| Peak memory | 640508 kb |
| Host | smart-4474db44-8cc6-49b9-976a-f19ba48b5d99 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2971026837 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2971026837 |
| Directory | /workspace/25.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/25.chip_sw_all_escalation_resets.1879092954 |
| Short name | T412 |
| Test name | |
| Test status | |
| Simulation time | 4557113024 ps |
| CPU time | 542.57 seconds |
| Started | Jul 03 08:17:51 PM PDT 24 |
| Finished | Jul 03 08:26:54 PM PDT 24 |
| Peak memory | 649660 kb |
| Host | smart-830c3a99-f861-4e38-9172-2df07557d5b8 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1879092954 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.chip_sw_all_escalation_resets.1879092954 |
| Directory | /workspace/25.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/26.chip_sw_alert_handler_lpg_sleep_mode_alerts.2536919505 |
| Short name | T361 |
| Test name | |
| Test status | |
| Simulation time | 3988678600 ps |
| CPU time | 407.72 seconds |
| Started | Jul 03 08:17:21 PM PDT 24 |
| Finished | Jul 03 08:24:10 PM PDT 24 |
| Peak memory | 648336 kb |
| Host | smart-323d8164-e9e0-434d-8496-7b5c97d606c8 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2536919505 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2536919505 |
| Directory | /workspace/26.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/26.chip_sw_all_escalation_resets.222829087 |
| Short name | T1261 |
| Test name | |
| Test status | |
| Simulation time | 5357760784 ps |
| CPU time | 659.87 seconds |
| Started | Jul 03 08:18:48 PM PDT 24 |
| Finished | Jul 03 08:29:48 PM PDT 24 |
| Peak memory | 649576 kb |
| Host | smart-758f5b90-31ac-4088-9a4a-59a034cc4c66 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 222829087 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.chip_sw_all_escalation_resets.222829087 |
| Directory | /workspace/26.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/27.chip_sw_alert_handler_lpg_sleep_mode_alerts.489703474 |
| Short name | T702 |
| Test name | |
| Test status | |
| Simulation time | 3846785470 ps |
| CPU time | 433 seconds |
| Started | Jul 03 08:17:36 PM PDT 24 |
| Finished | Jul 03 08:24:50 PM PDT 24 |
| Peak memory | 648400 kb |
| Host | smart-9460414e-de69-4724-8eef-0185cd3c1e8c |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=489703474 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.chip_s w_alert_handler_lpg_sleep_mode_alerts.489703474 |
| Directory | /workspace/27.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/28.chip_sw_all_escalation_resets.3416739577 |
| Short name | T731 |
| Test name | |
| Test status | |
| Simulation time | 4531996000 ps |
| CPU time | 538.8 seconds |
| Started | Jul 03 08:19:43 PM PDT 24 |
| Finished | Jul 03 08:28:42 PM PDT 24 |
| Peak memory | 641424 kb |
| Host | smart-2f8af7e9-dd1d-4d79-b935-9f8a68e22b79 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3416739577 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.chip_sw_all_escalation_resets.3416739577 |
| Directory | /workspace/28.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/29.chip_sw_alert_handler_lpg_sleep_mode_alerts.2100322509 |
| Short name | T760 |
| Test name | |
| Test status | |
| Simulation time | 3704362696 ps |
| CPU time | 381.53 seconds |
| Started | Jul 03 08:17:52 PM PDT 24 |
| Finished | Jul 03 08:24:15 PM PDT 24 |
| Peak memory | 640044 kb |
| Host | smart-8bd1fb92-16ec-4060-8f16-3fe073970eb9 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2100322509 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2100322509 |
| Directory | /workspace/29.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/3.chip_sw_alert_handler_lpg_sleep_mode_alerts.2493245881 |
| Short name | T299 |
| Test name | |
| Test status | |
| Simulation time | 3852258172 ps |
| CPU time | 462.08 seconds |
| Started | Jul 03 08:13:29 PM PDT 24 |
| Finished | Jul 03 08:21:11 PM PDT 24 |
| Peak memory | 648448 kb |
| Host | smart-48d3d9da-94d8-4c50-b58c-5bea785acb1c |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2493245881 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_s w_alert_handler_lpg_sleep_mode_alerts.2493245881 |
| Directory | /workspace/3.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/30.chip_sw_all_escalation_resets.3167351116 |
| Short name | T709 |
| Test name | |
| Test status | |
| Simulation time | 5964437928 ps |
| CPU time | 579.39 seconds |
| Started | Jul 03 08:19:45 PM PDT 24 |
| Finished | Jul 03 08:29:25 PM PDT 24 |
| Peak memory | 649572 kb |
| Host | smart-64262e17-ce3d-44cb-b2b6-e11ec42c2c95 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3167351116 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.chip_sw_all_escalation_resets.3167351116 |
| Directory | /workspace/30.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/31.chip_sw_alert_handler_lpg_sleep_mode_alerts.3361924354 |
| Short name | T744 |
| Test name | |
| Test status | |
| Simulation time | 3886055216 ps |
| CPU time | 440.89 seconds |
| Started | Jul 03 08:17:38 PM PDT 24 |
| Finished | Jul 03 08:24:59 PM PDT 24 |
| Peak memory | 648472 kb |
| Host | smart-ccb13d3a-7ffe-444c-8562-f94750f4af72 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3361924354 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3361924354 |
| Directory | /workspace/31.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/31.chip_sw_all_escalation_resets.856024152 |
| Short name | T736 |
| Test name | |
| Test status | |
| Simulation time | 4085525040 ps |
| CPU time | 548.7 seconds |
| Started | Jul 03 08:17:41 PM PDT 24 |
| Finished | Jul 03 08:26:51 PM PDT 24 |
| Peak memory | 649228 kb |
| Host | smart-59d0d331-df1c-40d5-b942-5647c9d7ee05 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 856024152 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.chip_sw_all_escalation_resets.856024152 |
| Directory | /workspace/31.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/32.chip_sw_alert_handler_lpg_sleep_mode_alerts.4153343956 |
| Short name | T690 |
| Test name | |
| Test status | |
| Simulation time | 4131088380 ps |
| CPU time | 363.09 seconds |
| Started | Jul 03 08:17:39 PM PDT 24 |
| Finished | Jul 03 08:23:43 PM PDT 24 |
| Peak memory | 648360 kb |
| Host | smart-3f3c950c-8e46-44f4-8976-89a5c9c4082b |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4153343956 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.chip_ sw_alert_handler_lpg_sleep_mode_alerts.4153343956 |
| Directory | /workspace/32.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/33.chip_sw_all_escalation_resets.2990756122 |
| Short name | T748 |
| Test name | |
| Test status | |
| Simulation time | 4359200932 ps |
| CPU time | 474.45 seconds |
| Started | Jul 03 08:17:52 PM PDT 24 |
| Finished | Jul 03 08:25:48 PM PDT 24 |
| Peak memory | 649512 kb |
| Host | smart-8ae828d5-1360-4910-8e81-446d43a5bed9 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2990756122 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.chip_sw_all_escalation_resets.2990756122 |
| Directory | /workspace/33.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/34.chip_sw_alert_handler_lpg_sleep_mode_alerts.3507979650 |
| Short name | T710 |
| Test name | |
| Test status | |
| Simulation time | 4342255394 ps |
| CPU time | 546.96 seconds |
| Started | Jul 03 08:17:53 PM PDT 24 |
| Finished | Jul 03 08:27:02 PM PDT 24 |
| Peak memory | 648676 kb |
| Host | smart-a30984d3-44cd-4fbc-a0c9-0ab5770ae200 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3507979650 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3507979650 |
| Directory | /workspace/34.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/35.chip_sw_alert_handler_lpg_sleep_mode_alerts.1137887320 |
| Short name | T650 |
| Test name | |
| Test status | |
| Simulation time | 4135431700 ps |
| CPU time | 453.45 seconds |
| Started | Jul 03 08:18:33 PM PDT 24 |
| Finished | Jul 03 08:26:07 PM PDT 24 |
| Peak memory | 648532 kb |
| Host | smart-81a000fd-16dc-4c04-a9dc-e8be16530136 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1137887320 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1137887320 |
| Directory | /workspace/35.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/35.chip_sw_all_escalation_resets.2745223279 |
| Short name | T370 |
| Test name | |
| Test status | |
| Simulation time | 4639756888 ps |
| CPU time | 540.79 seconds |
| Started | Jul 03 08:18:19 PM PDT 24 |
| Finished | Jul 03 08:27:21 PM PDT 24 |
| Peak memory | 641152 kb |
| Host | smart-c76de9bc-083b-4927-b4d4-1c84be26b517 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2745223279 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.chip_sw_all_escalation_resets.2745223279 |
| Directory | /workspace/35.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/37.chip_sw_alert_handler_lpg_sleep_mode_alerts.1783769869 |
| Short name | T266 |
| Test name | |
| Test status | |
| Simulation time | 3851214988 ps |
| CPU time | 371.18 seconds |
| Started | Jul 03 08:18:57 PM PDT 24 |
| Finished | Jul 03 08:25:09 PM PDT 24 |
| Peak memory | 648612 kb |
| Host | smart-152660a2-4072-4d13-89ea-4de0fce9176e |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1783769869 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1783769869 |
| Directory | /workspace/37.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/38.chip_sw_alert_handler_lpg_sleep_mode_alerts.317048797 |
| Short name | T689 |
| Test name | |
| Test status | |
| Simulation time | 4015875688 ps |
| CPU time | 345.58 seconds |
| Started | Jul 03 08:18:25 PM PDT 24 |
| Finished | Jul 03 08:24:11 PM PDT 24 |
| Peak memory | 648320 kb |
| Host | smart-0f90a2c7-8016-4806-a70b-84f77865f22c |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317048797 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.chip_s w_alert_handler_lpg_sleep_mode_alerts.317048797 |
| Directory | /workspace/38.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/38.chip_sw_all_escalation_resets.2057179068 |
| Short name | T695 |
| Test name | |
| Test status | |
| Simulation time | 6239840840 ps |
| CPU time | 725.16 seconds |
| Started | Jul 03 08:24:59 PM PDT 24 |
| Finished | Jul 03 08:37:06 PM PDT 24 |
| Peak memory | 641224 kb |
| Host | smart-55d86ba4-0d3f-4a03-90d0-a3659ec3ce81 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2057179068 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.chip_sw_all_escalation_resets.2057179068 |
| Directory | /workspace/38.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/4.chip_sw_all_escalation_resets.2967519236 |
| Short name | T657 |
| Test name | |
| Test status | |
| Simulation time | 4696094678 ps |
| CPU time | 770.69 seconds |
| Started | Jul 03 08:13:50 PM PDT 24 |
| Finished | Jul 03 08:26:42 PM PDT 24 |
| Peak memory | 641292 kb |
| Host | smart-ff8fef3e-bce2-4128-b817-27927006e512 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2967519236 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_all_escalation_resets.2967519236 |
| Directory | /workspace/4.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/40.chip_sw_alert_handler_lpg_sleep_mode_alerts.3580270799 |
| Short name | T660 |
| Test name | |
| Test status | |
| Simulation time | 4206177750 ps |
| CPU time | 467.02 seconds |
| Started | Jul 03 08:18:35 PM PDT 24 |
| Finished | Jul 03 08:26:23 PM PDT 24 |
| Peak memory | 648324 kb |
| Host | smart-8515fc5b-c61e-45ba-85b2-f98b64e32853 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3580270799 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3580270799 |
| Directory | /workspace/40.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/40.chip_sw_all_escalation_resets.1041883900 |
| Short name | T714 |
| Test name | |
| Test status | |
| Simulation time | 5006804900 ps |
| CPU time | 666.68 seconds |
| Started | Jul 03 08:18:45 PM PDT 24 |
| Finished | Jul 03 08:29:52 PM PDT 24 |
| Peak memory | 649804 kb |
| Host | smart-b4796664-29e1-4263-a659-dc4e61dab0c3 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1041883900 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.chip_sw_all_escalation_resets.1041883900 |
| Directory | /workspace/40.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/41.chip_sw_alert_handler_lpg_sleep_mode_alerts.3217905531 |
| Short name | T701 |
| Test name | |
| Test status | |
| Simulation time | 3962589420 ps |
| CPU time | 475.11 seconds |
| Started | Jul 03 08:22:04 PM PDT 24 |
| Finished | Jul 03 08:30:00 PM PDT 24 |
| Peak memory | 641236 kb |
| Host | smart-1868d135-94cb-4488-b164-28bf9d874ed0 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3217905531 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3217905531 |
| Directory | /workspace/41.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/42.chip_sw_alert_handler_lpg_sleep_mode_alerts.3223806049 |
| Short name | T674 |
| Test name | |
| Test status | |
| Simulation time | 4125523552 ps |
| CPU time | 375.14 seconds |
| Started | Jul 03 08:18:34 PM PDT 24 |
| Finished | Jul 03 08:24:50 PM PDT 24 |
| Peak memory | 648472 kb |
| Host | smart-4a645a25-52a6-484a-b5ef-da3a8b411a27 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3223806049 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3223806049 |
| Directory | /workspace/42.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/42.chip_sw_all_escalation_resets.2853374731 |
| Short name | T262 |
| Test name | |
| Test status | |
| Simulation time | 5971811630 ps |
| CPU time | 625.71 seconds |
| Started | Jul 03 08:20:00 PM PDT 24 |
| Finished | Jul 03 08:30:26 PM PDT 24 |
| Peak memory | 649748 kb |
| Host | smart-ed05e624-bf3e-43e4-8df4-60bb13b30060 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2853374731 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.chip_sw_all_escalation_resets.2853374731 |
| Directory | /workspace/42.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/45.chip_sw_all_escalation_resets.15667199 |
| Short name | T671 |
| Test name | |
| Test status | |
| Simulation time | 4278449504 ps |
| CPU time | 655.24 seconds |
| Started | Jul 03 08:19:25 PM PDT 24 |
| Finished | Jul 03 08:30:21 PM PDT 24 |
| Peak memory | 649236 kb |
| Host | smart-c9b70fd8-9c57-4ba0-9a37-0eb1cfee3e75 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 15667199 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.chip_sw_all_escalation_resets.15667199 |
| Directory | /workspace/45.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/47.chip_sw_all_escalation_resets.2844019607 |
| Short name | T754 |
| Test name | |
| Test status | |
| Simulation time | 5082331550 ps |
| CPU time | 591.18 seconds |
| Started | Jul 03 08:18:32 PM PDT 24 |
| Finished | Jul 03 08:28:23 PM PDT 24 |
| Peak memory | 649520 kb |
| Host | smart-63243041-3dcb-4f0d-9fbd-f1f989e07665 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2844019607 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.chip_sw_all_escalation_resets.2844019607 |
| Directory | /workspace/47.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/49.chip_sw_all_escalation_resets.2109675597 |
| Short name | T712 |
| Test name | |
| Test status | |
| Simulation time | 4854114932 ps |
| CPU time | 531.89 seconds |
| Started | Jul 03 08:21:59 PM PDT 24 |
| Finished | Jul 03 08:30:52 PM PDT 24 |
| Peak memory | 641080 kb |
| Host | smart-45247354-03fa-4cf7-8667-bdbc078acf03 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2109675597 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.chip_sw_all_escalation_resets.2109675597 |
| Directory | /workspace/49.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/50.chip_sw_alert_handler_lpg_sleep_mode_alerts.1799815439 |
| Short name | T668 |
| Test name | |
| Test status | |
| Simulation time | 3498474490 ps |
| CPU time | 478.18 seconds |
| Started | Jul 03 08:21:08 PM PDT 24 |
| Finished | Jul 03 08:29:07 PM PDT 24 |
| Peak memory | 648412 kb |
| Host | smart-cfa51760-6959-43ec-8c41-a6db9a153ee4 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1799815439 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1799815439 |
| Directory | /workspace/50.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/56.chip_sw_alert_handler_lpg_sleep_mode_alerts.572641918 |
| Short name | T684 |
| Test name | |
| Test status | |
| Simulation time | 3494264312 ps |
| CPU time | 343.74 seconds |
| Started | Jul 03 08:23:53 PM PDT 24 |
| Finished | Jul 03 08:29:38 PM PDT 24 |
| Peak memory | 648388 kb |
| Host | smart-bf7de281-b119-4d45-8cac-dc84445d7291 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=572641918 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.chip_s w_alert_handler_lpg_sleep_mode_alerts.572641918 |
| Directory | /workspace/56.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/56.chip_sw_all_escalation_resets.493759986 |
| Short name | T648 |
| Test name | |
| Test status | |
| Simulation time | 4906798262 ps |
| CPU time | 560.24 seconds |
| Started | Jul 03 08:20:31 PM PDT 24 |
| Finished | Jul 03 08:29:52 PM PDT 24 |
| Peak memory | 649480 kb |
| Host | smart-61915c9d-cc8f-47e1-bfce-e0155692d771 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 493759986 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.chip_sw_all_escalation_resets.493759986 |
| Directory | /workspace/56.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/57.chip_sw_alert_handler_lpg_sleep_mode_alerts.2154425671 |
| Short name | T295 |
| Test name | |
| Test status | |
| Simulation time | 4199866112 ps |
| CPU time | 372.06 seconds |
| Started | Jul 03 08:20:26 PM PDT 24 |
| Finished | Jul 03 08:26:39 PM PDT 24 |
| Peak memory | 648536 kb |
| Host | smart-c7bf0227-866b-4330-a720-957854a7d5f5 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2154425671 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2154425671 |
| Directory | /workspace/57.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/58.chip_sw_all_escalation_resets.3531380312 |
| Short name | T703 |
| Test name | |
| Test status | |
| Simulation time | 5295621702 ps |
| CPU time | 548.18 seconds |
| Started | Jul 03 08:19:42 PM PDT 24 |
| Finished | Jul 03 08:28:51 PM PDT 24 |
| Peak memory | 649532 kb |
| Host | smart-a34d0e62-99f5-4340-a444-d3d6e6d93664 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3531380312 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.chip_sw_all_escalation_resets.3531380312 |
| Directory | /workspace/58.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/59.chip_sw_alert_handler_lpg_sleep_mode_alerts.1509951566 |
| Short name | T676 |
| Test name | |
| Test status | |
| Simulation time | 3861665960 ps |
| CPU time | 469.03 seconds |
| Started | Jul 03 08:20:40 PM PDT 24 |
| Finished | Jul 03 08:28:30 PM PDT 24 |
| Peak memory | 648300 kb |
| Host | smart-2a748d12-f339-4a06-a142-832f252ee849 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1509951566 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1509951566 |
| Directory | /workspace/59.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/6.chip_sw_all_escalation_resets.1310178813 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 5194897656 ps |
| CPU time | 535.54 seconds |
| Started | Jul 03 08:13:48 PM PDT 24 |
| Finished | Jul 03 08:22:44 PM PDT 24 |
| Peak memory | 649592 kb |
| Host | smart-6dd162bb-10ea-4b45-b334-bed3b71c0ad0 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1310178813 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.chip_sw_all_escalation_resets.1310178813 |
| Directory | /workspace/6.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/62.chip_sw_alert_handler_lpg_sleep_mode_alerts.1994490518 |
| Short name | T720 |
| Test name | |
| Test status | |
| Simulation time | 3326289892 ps |
| CPU time | 520.02 seconds |
| Started | Jul 03 08:20:34 PM PDT 24 |
| Finished | Jul 03 08:29:15 PM PDT 24 |
| Peak memory | 648432 kb |
| Host | smart-01f9d344-0945-4be4-a4cb-ffe8d9fa6c17 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994490518 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1994490518 |
| Directory | /workspace/62.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/68.chip_sw_alert_handler_lpg_sleep_mode_alerts.1105842218 |
| Short name | T672 |
| Test name | |
| Test status | |
| Simulation time | 3472823156 ps |
| CPU time | 300.51 seconds |
| Started | Jul 03 08:20:36 PM PDT 24 |
| Finished | Jul 03 08:25:38 PM PDT 24 |
| Peak memory | 648308 kb |
| Host | smart-f7d0e517-8b81-4641-881e-34a27440675a |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1105842218 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1105842218 |
| Directory | /workspace/68.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/69.chip_sw_all_escalation_resets.377125737 |
| Short name | T334 |
| Test name | |
| Test status | |
| Simulation time | 4656701572 ps |
| CPU time | 440.32 seconds |
| Started | Jul 03 08:22:33 PM PDT 24 |
| Finished | Jul 03 08:29:54 PM PDT 24 |
| Peak memory | 649620 kb |
| Host | smart-a13c3ce7-e2ba-46bf-882e-19593cd03a7d |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 377125737 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.chip_sw_all_escalation_resets.377125737 |
| Directory | /workspace/69.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/71.chip_sw_alert_handler_lpg_sleep_mode_alerts.3871468824 |
| Short name | T423 |
| Test name | |
| Test status | |
| Simulation time | 3374181832 ps |
| CPU time | 391.13 seconds |
| Started | Jul 03 08:20:40 PM PDT 24 |
| Finished | Jul 03 08:27:12 PM PDT 24 |
| Peak memory | 648320 kb |
| Host | smart-094b3608-851b-46fa-a359-91c324c34e54 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3871468824 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3871468824 |
| Directory | /workspace/71.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/71.chip_sw_all_escalation_resets.1524196641 |
| Short name | T403 |
| Test name | |
| Test status | |
| Simulation time | 5544104648 ps |
| CPU time | 555.58 seconds |
| Started | Jul 03 08:23:05 PM PDT 24 |
| Finished | Jul 03 08:32:21 PM PDT 24 |
| Peak memory | 649684 kb |
| Host | smart-aabbdc55-c336-40b6-baa2-3fbbc26adfc9 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1524196641 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.chip_sw_all_escalation_resets.1524196641 |
| Directory | /workspace/71.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/73.chip_sw_all_escalation_resets.1828784593 |
| Short name | T699 |
| Test name | |
| Test status | |
| Simulation time | 4580883944 ps |
| CPU time | 635.52 seconds |
| Started | Jul 03 08:22:13 PM PDT 24 |
| Finished | Jul 03 08:32:49 PM PDT 24 |
| Peak memory | 641376 kb |
| Host | smart-f8fc1fa9-4422-463b-95a6-311f1b30efec |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1828784593 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.chip_sw_all_escalation_resets.1828784593 |
| Directory | /workspace/73.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/89.chip_sw_all_escalation_resets.905128907 |
| Short name | T706 |
| Test name | |
| Test status | |
| Simulation time | 6273188036 ps |
| CPU time | 516 seconds |
| Started | Jul 03 08:22:59 PM PDT 24 |
| Finished | Jul 03 08:31:36 PM PDT 24 |
| Peak memory | 649556 kb |
| Host | smart-238e7a5b-0443-4049-b7ae-5ddddfd02cb4 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 905128907 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.chip_sw_all_escalation_resets.905128907 |
| Directory | /workspace/89.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/91.chip_sw_all_escalation_resets.3401135564 |
| Short name | T663 |
| Test name | |
| Test status | |
| Simulation time | 5116799750 ps |
| CPU time | 688.45 seconds |
| Started | Jul 03 08:23:01 PM PDT 24 |
| Finished | Jul 03 08:34:31 PM PDT 24 |
| Peak memory | 649668 kb |
| Host | smart-14728ef5-427a-42f0-8f40-4f05d1554c56 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3401135564 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.chip_sw_all_escalation_resets.3401135564 |
| Directory | /workspace/91.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/cover_reg_top/3.chip_same_csr_outstanding.903004143 |
| Short name | T1851 |
| Test name | |
| Test status | |
| Simulation time | 31105462311 ps |
| CPU time | 3034.92 seconds |
| Started | Jul 03 07:22:29 PM PDT 24 |
| Finished | Jul 03 08:13:05 PM PDT 24 |
| Peak memory | 592472 kb |
| Host | smart-13f1df4d-2caa-4bc4-a503-c9743140e7a0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=903004143 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 3.chip_same_csr_outstanding.903004143 |
| Directory | /workspace/3.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otp_ctrl_vendor_test_csr_access.2575613728 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 2995676041 ps |
| CPU time | 277 seconds |
| Started | Jul 03 08:05:55 PM PDT 24 |
| Finished | Jul 03 08:10:32 PM PDT 24 |
| Peak memory | 618888 kb |
| Host | smart-c302e2d8-5c77-4a84-b8af-c6d49232e730 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_vendor_test_csr_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2575613728 -assert nopost proc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_vendor_test_csr_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otp_ctrl_vendor_test_csr_access.2575613728 |
| Directory | /workspace/2.chip_sw_otp_ctrl_vendor_test_csr_access/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_stress_all_with_reset_error.2954717360 |
| Short name | T503 |
| Test name | |
| Test status | |
| Simulation time | 3236356278 ps |
| CPU time | 422.26 seconds |
| Started | Jul 03 07:34:26 PM PDT 24 |
| Finished | Jul 03 07:41:29 PM PDT 24 |
| Peak memory | 574824 kb |
| Host | smart-62411de7-2396-4fb8-a36d-45ffc529f02d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2954717360 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_stress_al l_with_reset_error.2954717360 |
| Directory | /workspace/66.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.921211202 |
| Short name | T354 |
| Test name | |
| Test status | |
| Simulation time | 5134807200 ps |
| CPU time | 352.66 seconds |
| Started | Jul 03 07:51:22 PM PDT 24 |
| Finished | Jul 03 07:57:16 PM PDT 24 |
| Peak memory | 610800 kb |
| Host | smart-1627f03a-ab20-46de-9542-12483d026962 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sensor_ctrl_deep_sleep_wake_up:1:new_rul es,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=921211202 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_sensor_ctrl_deep_sl eep_wake_up.921211202 |
| Directory | /workspace/0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rstmgr_alert_info.2738077695 |
| Short name | T312 |
| Test name | |
| Test status | |
| Simulation time | 13519082104 ps |
| CPU time | 1672.4 seconds |
| Started | Jul 03 07:53:57 PM PDT 24 |
| Finished | Jul 03 08:21:50 PM PDT 24 |
| Peak memory | 610612 kb |
| Host | smart-bb36371c-eae2-4d12-bd14-5a41a7ccc8dc |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=30_000_000 +en_scb_tl_err_chk=0 +sw_build_device=sim_dv +sw_images=rstmgr_alert_info_test:1:new_rules,test _rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb _random_seed=2738077695 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rstmgr_alert_info.2738077695 |
| Directory | /workspace/1.chip_sw_rstmgr_alert_info/latest |
| Test location | /workspace/coverage/default/2.chip_plic_all_irqs_10.2086116382 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 4031518470 ps |
| CPU time | 538.93 seconds |
| Started | Jul 03 08:09:45 PM PDT 24 |
| Finished | Jul 03 08:18:44 PM PDT 24 |
| Peak memory | 610644 kb |
| Host | smart-81ce967b-d88b-47ab-9ff8-a93b884d5b11 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_10:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2086116382 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 2.chip_plic_all_irqs_10.2086116382 |
| Directory | /workspace/2.chip_plic_all_irqs_10/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_lowpower_cancel.2775442945 |
| Short name | T323 |
| Test name | |
| Test status | |
| Simulation time | 3825943040 ps |
| CPU time | 465.76 seconds |
| Started | Jul 03 08:09:38 PM PDT 24 |
| Finished | Jul 03 08:17:24 PM PDT 24 |
| Peak memory | 611020 kb |
| Host | smart-a99126f3-28ab-42ea-8492-20daf17f532c |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_lowpower_cancel_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2775442945 -assert nopostproc +UVM _TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 2.chip_sw_pwrmgr_lowpower_cancel.2775442945 |
| Directory | /workspace/2.chip_sw_pwrmgr_lowpower_cancel/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rv_core_ibex_lockstep_glitch.1028799190 |
| Short name | T259 |
| Test name | |
| Test status | |
| Simulation time | 2587364720 ps |
| CPU time | 169.43 seconds |
| Started | Jul 03 07:53:55 PM PDT 24 |
| Finished | Jul 03 07:56:45 PM PDT 24 |
| Peak memory | 615288 kb |
| Host | smart-f3e08773-660f-4cc9-97d3-78c07c1ea0f6 |
| User | root |
| Command | /workspace/default/simv +disable_assert_final_checks +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1028799190 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_core_ibex_lockstep_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_core_ibex_lockstep_glitch.1028799190 |
| Directory | /workspace/0.chip_sw_rv_core_ibex_lockstep_glitch/latest |
| Test location | /workspace/coverage/default/53.chip_sw_all_escalation_resets.490836075 |
| Short name | T629 |
| Test name | |
| Test status | |
| Simulation time | 5030907514 ps |
| CPU time | 762.78 seconds |
| Started | Jul 03 08:21:14 PM PDT 24 |
| Finished | Jul 03 08:33:57 PM PDT 24 |
| Peak memory | 610704 kb |
| Host | smart-91aad7cc-cca9-4f26-aece-f46847777976 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 490836075 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.chip_sw_all_escalation_resets.490836075 |
| Directory | /workspace/53.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/0.chip_sw_plic_sw_irq.1534177991 |
| Short name | T638 |
| Test name | |
| Test status | |
| Simulation time | 2349817512 ps |
| CPU time | 324.24 seconds |
| Started | Jul 03 07:53:03 PM PDT 24 |
| Finished | Jul 03 07:58:28 PM PDT 24 |
| Peak memory | 610644 kb |
| Host | smart-7b26fd49-4095-4c88-9792-465558aa3aaa |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_sw_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1534177991 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 0.chip_sw_plic_sw_irq.1534177991 |
| Directory | /workspace/0.chip_sw_plic_sw_irq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_full_aon_reset.282288729 |
| Short name | T1244 |
| Test name | |
| Test status | |
| Simulation time | 7003453586 ps |
| CPU time | 346.04 seconds |
| Started | Jul 03 07:50:25 PM PDT 24 |
| Finished | Jul 03 07:56:11 PM PDT 24 |
| Peak memory | 610636 kb |
| Host | smart-8d157982-4346-4168-a268-e4078af40702 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=282288729 -assert nopostproc +UVM_TESTNAME=ch ip_base_test +UVM_TEST_SEQ=chip_sw_full_aon_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 0.chip_sw_pwrmgr_full_aon_reset.282288729 |
| Directory | /workspace/0.chip_sw_pwrmgr_full_aon_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.2824249596 |
| Short name | T1152 |
| Test name | |
| Test status | |
| Simulation time | 3594027018 ps |
| CPU time | 458.56 seconds |
| Started | Jul 03 07:52:12 PM PDT 24 |
| Finished | Jul 03 07:59:52 PM PDT 24 |
| Peak memory | 618136 kb |
| Host | smart-8626047c-5068-466b-8c44-3398677fe842 |
| User | root |
| Command | /workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_ndm_reset_req_when_cpu_halted_rma:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=282424 9596 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_ndm_reset_when_cpu_halted_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.2824249596 |
| Directory | /workspace/0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rv_dm_access_after_escalation_reset.2482599419 |
| Short name | T622 |
| Test name | |
| Test status | |
| Simulation time | 4610701976 ps |
| CPU time | 607.22 seconds |
| Started | Jul 03 07:50:13 PM PDT 24 |
| Finished | Jul 03 08:00:22 PM PDT 24 |
| Peak memory | 624772 kb |
| Host | smart-6ed23e73-a3ac-402f-a00b-e84dd949ae75 |
| User | root |
| Command | /workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=alert_handler_escalation_test:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2482599419 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_access_after_escalation_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_dm_access_after_escalation_reset.2482599419 |
| Directory | /workspace/0.chip_sw_rv_dm_access_after_escalation_reset/latest |
| Test location | /workspace/coverage/default/3.chip_tap_straps_dev.1069644224 |
| Short name | T623 |
| Test name | |
| Test status | |
| Simulation time | 10314436513 ps |
| CPU time | 875.65 seconds |
| Started | Jul 03 08:12:39 PM PDT 24 |
| Finished | Jul 03 08:27:15 PM PDT 24 |
| Peak memory | 624032 kb |
| Host | smart-cfc9343a-c3b3-434a-baf9-bb29ff1636fd |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStDev +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom: new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1069644224 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_tap_straps_dev.1069644224 |
| Directory | /workspace/3.chip_tap_straps_dev/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_access_same_device_slow_rsp.806710841 |
| Short name | T486 |
| Test name | |
| Test status | |
| Simulation time | 64642718878 ps |
| CPU time | 1166.85 seconds |
| Started | Jul 03 07:25:29 PM PDT 24 |
| Finished | Jul 03 07:44:58 PM PDT 24 |
| Peak memory | 574096 kb |
| Host | smart-d083c17f-06c4-4fb0-946f-17451b4c5ba8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=806710841 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_access_same_d evice_slow_rsp.806710841 |
| Directory | /workspace/18.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/23.chip_tl_errors.116405011 |
| Short name | T645 |
| Test name | |
| Test status | |
| Simulation time | 2781531316 ps |
| CPU time | 144.5 seconds |
| Started | Jul 03 07:26:19 PM PDT 24 |
| Finished | Jul 03 07:28:45 PM PDT 24 |
| Peak memory | 595992 kb |
| Host | smart-1af954df-cb9e-4fe4-95f7-032980edb34f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=116405011 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.chip_tl_errors.116405011 |
| Directory | /workspace/23.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_stress_all_with_reset_error.851759054 |
| Short name | T577 |
| Test name | |
| Test status | |
| Simulation time | 9720236586 ps |
| CPU time | 793.36 seconds |
| Started | Jul 03 07:30:09 PM PDT 24 |
| Finished | Jul 03 07:43:24 PM PDT 24 |
| Peak memory | 581924 kb |
| Host | smart-88ce2106-f554-48fe-a539-8e39ad99bfcd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=851759054 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all _with_reset_error.851759054 |
| Directory | /workspace/41.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/default/0.chip_sw_gpio.2948926601 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 4464391042 ps |
| CPU time | 444.22 seconds |
| Started | Jul 03 07:48:20 PM PDT 24 |
| Finished | Jul 03 07:55:45 PM PDT 24 |
| Peak memory | 608880 kb |
| Host | smart-b80ccd8d-7540-4852-a465-260ddf7bc116 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=gpio_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2948926601 -assert nopostproc +UVM_TESTNAME=chip_bas e_test +UVM_TEST_SEQ=chip_sw_gpio_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 0.chip_sw_gpio.2948926601 |
| Directory | /workspace/0.chip_sw_gpio/latest |
| Test location | /workspace/coverage/cover_reg_top/0.chip_csr_hw_reset.1920963327 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 6194147400 ps |
| CPU time | 371.65 seconds |
| Started | Jul 03 07:22:14 PM PDT 24 |
| Finished | Jul 03 07:28:29 PM PDT 24 |
| Peak memory | 661496 kb |
| Host | smart-a75f4f73-091d-44b8-9e1c-be5d0a13e0bf |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920963327 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.chip_csr_hw_r eset.1920963327 |
| Directory | /workspace/0.chip_csr_hw_reset/latest |
| Test location | /workspace/coverage/default/0.chip_tap_straps_rma.565802348 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 3204161887 ps |
| CPU time | 244.4 seconds |
| Started | Jul 03 07:53:29 PM PDT 24 |
| Finished | Jul 03 07:57:34 PM PDT 24 |
| Peak memory | 624220 kb |
| Host | smart-4341977d-c6ec-4d13-aeea-b7ba5520e7ab |
| User | root |
| Command | /workspace/default/simv +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=565802348 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 0.chip_tap_straps_rma.565802348 |
| Directory | /workspace/0.chip_tap_straps_rma/latest |
| Test location | /workspace/coverage/default/0.chip_sw_i2c_host_tx_rx.1165461732 |
| Short name | T319 |
| Test name | |
| Test status | |
| Simulation time | 4550343508 ps |
| CPU time | 886.05 seconds |
| Started | Jul 03 07:47:59 PM PDT 24 |
| Finished | Jul 03 08:02:46 PM PDT 24 |
| Peak memory | 608608 kb |
| Host | smart-c6a1b3ff-7de4-44d2-9e94-05400639c29b |
| User | root |
| Command | /workspace/default/simv +i2c_idx=0 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1165461732 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 0.chip_sw_i2c_host_tx_rx.1165461732 |
| Directory | /workspace/0.chip_sw_i2c_host_tx_rx/latest |
| Test location | /workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx1.2611310016 |
| Short name | T311 |
| Test name | |
| Test status | |
| Simulation time | 5564663634 ps |
| CPU time | 930.57 seconds |
| Started | Jul 03 07:50:39 PM PDT 24 |
| Finished | Jul 03 08:06:10 PM PDT 24 |
| Peak memory | 608212 kb |
| Host | smart-9e41a97b-182b-4aa3-9843-eb907daf453a |
| User | root |
| Command | /workspace/default/simv +i2c_idx=1 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2611310016 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 0.chip_sw_i2c_host_tx_rx_idx1.2611310016 |
| Directory | /workspace/0.chip_sw_i2c_host_tx_rx_idx1/latest |
| Test location | /workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx2.2143240600 |
| Short name | T1189 |
| Test name | |
| Test status | |
| Simulation time | 5076152128 ps |
| CPU time | 930.4 seconds |
| Started | Jul 03 07:51:03 PM PDT 24 |
| Finished | Jul 03 08:06:35 PM PDT 24 |
| Peak memory | 609488 kb |
| Host | smart-adf7e0c5-c38b-4273-8cba-007fa16b8cf8 |
| User | root |
| Command | /workspace/default/simv +i2c_idx=2 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2143240600 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 0.chip_sw_i2c_host_tx_rx_idx2.2143240600 |
| Directory | /workspace/0.chip_sw_i2c_host_tx_rx_idx2/latest |
| Test location | /workspace/coverage/default/1.chip_sw_csrng_edn_concurrency_reduced_freq.2819221867 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 166779566366 ps |
| CPU time | 22554.9 seconds |
| Started | Jul 03 08:02:32 PM PDT 24 |
| Finished | Jul 04 02:18:30 AM PDT 24 |
| Peak memory | 609832 kb |
| Host | smart-1e4aea66-0f28-45a0-9fe7-3ef6e8108615 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=360_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +cal_sys_clk_70mhz=1 +en_jitter=1 +accelerate_ cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=2819221867 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_csrng_edn_concurrency_reduced_freq.2819221867 |
| Directory | /workspace/1.chip_sw_csrng_edn_concurrency_reduced_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_edn_boot_mode.2730967746 |
| Short name | T371 |
| Test name | |
| Test status | |
| Simulation time | 2624614880 ps |
| CPU time | 706.02 seconds |
| Started | Jul 03 07:49:04 PM PDT 24 |
| Finished | Jul 03 08:00:52 PM PDT 24 |
| Peak memory | 610848 kb |
| Host | smart-76465697-4d2d-4753-b188-8785c1ff1b8b |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_ build_device=sim_dv +sw_images=edn_boot_mode:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2730967746 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_edn_ boot_mode.2730967746 |
| Directory | /workspace/0.chip_sw_edn_boot_mode/latest |
| Test location | /workspace/coverage/default/0.chip_sw_edn_entropy_reqs.1985429469 |
| Short name | T424 |
| Test name | |
| Test status | |
| Simulation time | 7083159832 ps |
| CPU time | 1237.43 seconds |
| Started | Jul 03 07:48:34 PM PDT 24 |
| Finished | Jul 03 08:09:12 PM PDT 24 |
| Peak memory | 610740 kb |
| Host | smart-00c7d875-d263-4a83-a051-70344cd407e9 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15000000 +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_ed n_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1985429469 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_edn_entropy_reqs.1985429469 |
| Directory | /workspace/0.chip_sw_edn_entropy_reqs/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_ctrl_program_error.373829494 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 4468041506 ps |
| CPU time | 483.04 seconds |
| Started | Jul 03 07:51:52 PM PDT 24 |
| Finished | Jul 03 07:59:57 PM PDT 24 |
| Peak memory | 610132 kb |
| Host | smart-2e54e854-6468-456c-9591-7c2fdf091ff9 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=lc_ctrl_program_error:1:new_rules,test_rom:0 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=373829494 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_program_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_program_error.373829494 |
| Directory | /workspace/0.chip_sw_lc_ctrl_program_error/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_main_power_glitch_reset.825341040 |
| Short name | T863 |
| Test name | |
| Test status | |
| Simulation time | 4944653354 ps |
| CPU time | 550.6 seconds |
| Started | Jul 03 07:47:12 PM PDT 24 |
| Finished | Jul 03 07:56:23 PM PDT 24 |
| Peak memory | 615668 kb |
| Host | smart-981b056d-87c8-47bb-82df-e24c5581f224 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_main_power_glitch_test:1:new_rules,test_rom:0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=825341040 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_main_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_main_power_glitch_reset.825341040 |
| Directory | /workspace/0.chip_sw_pwrmgr_main_power_glitch_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/1.chip_same_csr_outstanding.171617043 |
| Short name | T2151 |
| Test name | |
| Test status | |
| Simulation time | 27506512188 ps |
| CPU time | 4473.53 seconds |
| Started | Jul 03 07:22:14 PM PDT 24 |
| Finished | Jul 03 08:36:51 PM PDT 24 |
| Peak memory | 592168 kb |
| Host | smart-1b0a06ad-4e6c-4ee5-af4d-ad4aa66447d0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=171617043 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 1.chip_same_csr_outstanding.171617043 |
| Directory | /workspace/1.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_stress_all_with_error.2987806983 |
| Short name | T632 |
| Test name | |
| Test status | |
| Simulation time | 12119668814 ps |
| CPU time | 421.86 seconds |
| Started | Jul 03 07:24:08 PM PDT 24 |
| Finished | Jul 03 07:31:10 PM PDT 24 |
| Peak memory | 574660 kb |
| Host | smart-8da1fd37-1f14-494a-bcb7-6a5ffdb4e807 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2987806983 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_error.2987806983 |
| Directory | /workspace/11.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_stress_all_with_reset_error.4264483452 |
| Short name | T585 |
| Test name | |
| Test status | |
| Simulation time | 6601550644 ps |
| CPU time | 248.02 seconds |
| Started | Jul 03 07:24:29 PM PDT 24 |
| Finished | Jul 03 07:28:37 PM PDT 24 |
| Peak memory | 574716 kb |
| Host | smart-25ebd58a-b6cb-4178-851f-5e122330b7c0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264483452 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_stress_al l_with_reset_error.4264483452 |
| Directory | /workspace/13.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_stress_all.2492049812 |
| Short name | T590 |
| Test name | |
| Test status | |
| Simulation time | 720560336 ps |
| CPU time | 30.25 seconds |
| Started | Jul 03 07:26:03 PM PDT 24 |
| Finished | Jul 03 07:26:34 PM PDT 24 |
| Peak memory | 574268 kb |
| Host | smart-0a9ea54e-936e-4221-a909-ef49c57e7a13 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2492049812 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all.2492049812 |
| Directory | /workspace/20.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_stress_all_with_reset_error.2688176867 |
| Short name | T579 |
| Test name | |
| Test status | |
| Simulation time | 7319865586 ps |
| CPU time | 379.31 seconds |
| Started | Jul 03 07:22:41 PM PDT 24 |
| Finished | Jul 03 07:29:02 PM PDT 24 |
| Peak memory | 574712 kb |
| Host | smart-840488bb-1b96-4655-a466-aad935435a45 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2688176867 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all _with_reset_error.2688176867 |
| Directory | /workspace/3.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_stress_all_with_error.117774243 |
| Short name | T586 |
| Test name | |
| Test status | |
| Simulation time | 14100363314 ps |
| CPU time | 469 seconds |
| Started | Jul 03 07:28:41 PM PDT 24 |
| Finished | Jul 03 07:36:32 PM PDT 24 |
| Peak memory | 574728 kb |
| Host | smart-eb8350f6-da4a-423e-b1e6-5d06b00a9806 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=117774243 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_error.117774243 |
| Directory | /workspace/34.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_stress_all_with_error.143942403 |
| Short name | T634 |
| Test name | |
| Test status | |
| Simulation time | 8845509690 ps |
| CPU time | 373.25 seconds |
| Started | Jul 03 07:28:50 PM PDT 24 |
| Finished | Jul 03 07:35:07 PM PDT 24 |
| Peak memory | 574596 kb |
| Host | smart-31378c2b-1d5c-48a1-a94c-1f1d3035b9df |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=143942403 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_error.143942403 |
| Directory | /workspace/35.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_stress_all_with_reset_error.1141467531 |
| Short name | T581 |
| Test name | |
| Test status | |
| Simulation time | 3395405989 ps |
| CPU time | 304.66 seconds |
| Started | Jul 03 07:36:16 PM PDT 24 |
| Finished | Jul 03 07:41:21 PM PDT 24 |
| Peak memory | 574668 kb |
| Host | smart-3a044b66-a43f-4155-b730-7fa495981e78 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141467531 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_stress_al l_with_reset_error.1141467531 |
| Directory | /workspace/76.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/9.chip_tl_errors.132735934 |
| Short name | T546 |
| Test name | |
| Test status | |
| Simulation time | 3445482488 ps |
| CPU time | 171.85 seconds |
| Started | Jul 03 07:23:38 PM PDT 24 |
| Finished | Jul 03 07:26:31 PM PDT 24 |
| Peak memory | 597960 kb |
| Host | smart-41adcd7d-50e2-453d-bd79-3affb7f560ac |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=132735934 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.chip_tl_errors.132735934 |
| Directory | /workspace/9.chip_tl_errors/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_lowpower_cancel.1916463645 |
| Short name | T324 |
| Test name | |
| Test status | |
| Simulation time | 3916637768 ps |
| CPU time | 380.24 seconds |
| Started | Jul 03 07:53:26 PM PDT 24 |
| Finished | Jul 03 07:59:47 PM PDT 24 |
| Peak memory | 610684 kb |
| Host | smart-40a6058c-5fb1-4e0e-be33-fb67d3c20c2f |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_lowpower_cancel_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1916463645 -assert nopostproc +UVM _TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 0.chip_sw_pwrmgr_lowpower_cancel.1916463645 |
| Directory | /workspace/0.chip_sw_pwrmgr_lowpower_cancel/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rstmgr_alert_info.2540178782 |
| Short name | T313 |
| Test name | |
| Test status | |
| Simulation time | 13846547152 ps |
| CPU time | 2078.55 seconds |
| Started | Jul 03 07:48:12 PM PDT 24 |
| Finished | Jul 03 08:22:52 PM PDT 24 |
| Peak memory | 610652 kb |
| Host | smart-41216973-f09c-4b33-9f6c-146fa54cda78 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=30_000_000 +en_scb_tl_err_chk=0 +sw_build_device=sim_dv +sw_images=rstmgr_alert_info_test:1:new_rules,test _rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb _random_seed=2540178782 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rstmgr_alert_info.2540178782 |
| Directory | /workspace/0.chip_sw_rstmgr_alert_info/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rv_core_ibex_nmi_irq.3114619177 |
| Short name | T499 |
| Test name | |
| Test status | |
| Simulation time | 5267509816 ps |
| CPU time | 1074.09 seconds |
| Started | Jul 03 07:49:57 PM PDT 24 |
| Finished | Jul 03 08:07:52 PM PDT 24 |
| Peak memory | 608104 kb |
| Host | smart-1a1ca9cb-0286-4ff1-abfe-9db2c9e6cea2 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=10_000_000 +sw_build_device=sim_dv +sw_images=rv_core_ibex_nmi_irq_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31146 19177 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_core_ibex_nmi_irq.3114619177 |
| Directory | /workspace/0.chip_sw_rv_core_ibex_nmi_irq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_hmac_enc_jitter_en.3864146898 |
| Short name | T348 |
| Test name | |
| Test status | |
| Simulation time | 3337032073 ps |
| CPU time | 267.61 seconds |
| Started | Jul 03 08:09:46 PM PDT 24 |
| Finished | Jul 03 08:14:14 PM PDT 24 |
| Peak memory | 608728 kb |
| Host | smart-a92d591a-51c4-44ff-94a7-f2392866918f |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3864146898 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 2.chip_sw_hmac_enc_jitter_en.3864146898 |
| Directory | /workspace/2.chip_sw_hmac_enc_jitter_en/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/1.chip_padctrl_attributes.1462776219 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 5225342139 ps |
| CPU time | 373.41 seconds |
| Started | Jul 03 08:15:11 PM PDT 24 |
| Finished | Jul 03 08:21:25 PM PDT 24 |
| Peak memory | 649172 kb |
| Host | smart-5e4f93ac-5317-4686-a75b-c20cfbf845e7 |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1462776219 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/ null -cm_name 1.chip_padctrl_attributes.1462776219 |
| Directory | /workspace/1.chip_padctrl_attributes/latest |
| Test location | /workspace/coverage/default/0.chip_jtag_csr_rw.2085058159 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 15917412891 ps |
| CPU time | 1989.59 seconds |
| Started | Jul 03 07:42:05 PM PDT 24 |
| Finished | Jul 03 08:15:15 PM PDT 24 |
| Peak memory | 607900 kb |
| Host | smart-878328ae-03f2-4f3a-902f-e630bf4b27e5 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +csr_rw +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2085058159 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_T EST_SEQ=chip_jtag_csr_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.c hip_jtag_csr_rw.2085058159 |
| Directory | /workspace/0.chip_jtag_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/0.chip_rv_dm_lc_disabled.513136130 |
| Short name | T1661 |
| Test name | |
| Test status | |
| Simulation time | 10632417879 ps |
| CPU time | 472.51 seconds |
| Started | Jul 03 07:22:02 PM PDT 24 |
| Finished | Jul 03 07:29:56 PM PDT 24 |
| Peak memory | 590444 kb |
| Host | smart-a2570bce-b678-46b0-b801-2f7d70e8b210 |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +en_scb_tl_err_chk=0 +use_jtag_dmi=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=513136130 -assert nopostproc +UVM_TESTNAME=chip_base_te st +UVM_TEST_SEQ=chip_rv_dm_lc_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 0.chip_rv_dm_lc_disabled.513136130 |
| Directory | /workspace/0.chip_rv_dm_lc_disabled/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq.3504605791 |
| Short name | T902 |
| Test name | |
| Test status | |
| Simulation time | 17134748908 ps |
| CPU time | 3201.29 seconds |
| Started | Jul 03 07:49:07 PM PDT 24 |
| Finished | Jul 03 08:42:29 PM PDT 24 |
| Peak memory | 609436 kb |
| Host | smart-00f61b2d-5a47-4fda-92b7-a7a585588471 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=28_000_000 +rng_srate_value=30 +sw_build_device=sim_dv +sw_images=otbn_ecdsa_op_irq_test:1:new_rules,test_ rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ random_seed=3504605791 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otbn_ecdsa_op_irq.3504605791 |
| Directory | /workspace/0.chip_sw_otbn_ecdsa_op_irq/latest |
| Test location | /workspace/coverage/cover_reg_top/0.chip_csr_aliasing.255046163 |
| Short name | T618 |
| Test name | |
| Test status | |
| Simulation time | 41418238032 ps |
| CPU time | 6996.83 seconds |
| Started | Jul 03 07:22:00 PM PDT 24 |
| Finished | Jul 03 09:18:39 PM PDT 24 |
| Peak memory | 593108 kb |
| Host | smart-0345ab09-9696-47c9-ab5a-545efbfbd7d7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +csr_aliasing +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=255046163 -assert nopostproc +UVM_TESTNAME=chip_b ase_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n ull -cm_name 0.chip_csr_aliasing.255046163 |
| Directory | /workspace/0.chip_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/0.chip_csr_bit_bash.3324757940 |
| Short name | T1984 |
| Test name | |
| Test status | |
| Simulation time | 16561134360 ps |
| CPU time | 1887.16 seconds |
| Started | Jul 03 07:22:01 PM PDT 24 |
| Finished | Jul 03 07:53:29 PM PDT 24 |
| Peak memory | 590592 kb |
| Host | smart-cc24fd3a-885e-454f-850f-1bb1a5c7a2f1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +num_test_csrs=200 +csr_bit_bash +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3324757940 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 0.chip_csr_bit_bash.3324757940 |
| Directory | /workspace/0.chip_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/0.chip_csr_rw.1803546659 |
| Short name | T2182 |
| Test name | |
| Test status | |
| Simulation time | 6600804962 ps |
| CPU time | 681.23 seconds |
| Started | Jul 03 07:22:15 PM PDT 24 |
| Finished | Jul 03 07:33:39 PM PDT 24 |
| Peak memory | 597508 kb |
| Host | smart-0744ad73-34dc-48fa-bca0-b2bff7e1cad6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1803546659 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.chip_csr_rw.1803546659 |
| Directory | /workspace/0.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/0.chip_prim_tl_access.1266093228 |
| Short name | T1609 |
| Test name | |
| Test status | |
| Simulation time | 9369896822 ps |
| CPU time | 334.06 seconds |
| Started | Jul 03 07:22:00 PM PDT 24 |
| Finished | Jul 03 07:27:36 PM PDT 24 |
| Peak memory | 590752 kb |
| Host | smart-77a1a303-2973-4cc9-a3a2-8fd6588f79e4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +en_scb_tl_err_chk=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1266093228 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SE Q=chip_prim_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.chip_prim_tl_access.1266093228 |
| Directory | /workspace/0.chip_prim_tl_access/latest |
| Test location | /workspace/coverage/cover_reg_top/0.chip_same_csr_outstanding.119225976 |
| Short name | T367 |
| Test name | |
| Test status | |
| Simulation time | 15394370173 ps |
| CPU time | 1804.33 seconds |
| Started | Jul 03 07:22:01 PM PDT 24 |
| Finished | Jul 03 07:52:07 PM PDT 24 |
| Peak memory | 591788 kb |
| Host | smart-08830e7b-2120-4c30-b4b6-d5713f25416d |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=119225976 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 0.chip_same_csr_outstanding.119225976 |
| Directory | /workspace/0.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/0.chip_tl_errors.258964489 |
| Short name | T641 |
| Test name | |
| Test status | |
| Simulation time | 4098130116 ps |
| CPU time | 320.68 seconds |
| Started | Jul 03 07:22:01 PM PDT 24 |
| Finished | Jul 03 07:27:23 PM PDT 24 |
| Peak memory | 603096 kb |
| Host | smart-42751963-50a9-46f2-9769-0afe86ab6178 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=258964489 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.chip_tl_errors.258964489 |
| Directory | /workspace/0.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_access_same_device.1529712304 |
| Short name | T2404 |
| Test name | |
| Test status | |
| Simulation time | 840408552 ps |
| CPU time | 65.62 seconds |
| Started | Jul 03 07:22:06 PM PDT 24 |
| Finished | Jul 03 07:23:12 PM PDT 24 |
| Peak memory | 574288 kb |
| Host | smart-0c541958-e177-46fa-a5ef-d4e555d22b00 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1529712304 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_access_same_device. 1529712304 |
| Directory | /workspace/0.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_access_same_device_slow_rsp.2297899508 |
| Short name | T1885 |
| Test name | |
| Test status | |
| Simulation time | 55762373763 ps |
| CPU time | 943.56 seconds |
| Started | Jul 03 07:22:04 PM PDT 24 |
| Finished | Jul 03 07:37:49 PM PDT 24 |
| Peak memory | 574136 kb |
| Host | smart-a1b98fda-2d25-4298-be37-9f9244c2bb4c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297899508 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_access_same_d evice_slow_rsp.2297899508 |
| Directory | /workspace/0.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_error_and_unmapped_addr.1157712482 |
| Short name | T1948 |
| Test name | |
| Test status | |
| Simulation time | 681982051 ps |
| CPU time | 30.87 seconds |
| Started | Jul 03 07:22:04 PM PDT 24 |
| Finished | Jul 03 07:22:37 PM PDT 24 |
| Peak memory | 574504 kb |
| Host | smart-6bcd9efe-9028-477a-81dc-a37508c8159e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1157712482 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_error_and_unmapped_addr .1157712482 |
| Directory | /workspace/0.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_error_random.1186662669 |
| Short name | T2346 |
| Test name | |
| Test status | |
| Simulation time | 1650193984 ps |
| CPU time | 54.72 seconds |
| Started | Jul 03 07:22:04 PM PDT 24 |
| Finished | Jul 03 07:23:00 PM PDT 24 |
| Peak memory | 574408 kb |
| Host | smart-2fd67a3f-2f49-4499-8253-a41cab2a4bef |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1186662669 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_error_random.1186662669 |
| Directory | /workspace/0.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_random.2735040815 |
| Short name | T2510 |
| Test name | |
| Test status | |
| Simulation time | 398320176 ps |
| CPU time | 38.63 seconds |
| Started | Jul 03 07:22:00 PM PDT 24 |
| Finished | Jul 03 07:22:39 PM PDT 24 |
| Peak memory | 574216 kb |
| Host | smart-384f7630-2a79-45f4-81da-e235a23c50af |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2735040815 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_random.2735040815 |
| Directory | /workspace/0.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_random_large_delays.1076571399 |
| Short name | T2201 |
| Test name | |
| Test status | |
| Simulation time | 105252080706 ps |
| CPU time | 1054.51 seconds |
| Started | Jul 03 07:22:14 PM PDT 24 |
| Finished | Jul 03 07:39:52 PM PDT 24 |
| Peak memory | 574228 kb |
| Host | smart-23f02ffe-0532-41a1-93d7-e83a7970240b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1076571399 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_random_large_delays.1076571399 |
| Directory | /workspace/0.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_random_slow_rsp.610954136 |
| Short name | T2270 |
| Test name | |
| Test status | |
| Simulation time | 43739592844 ps |
| CPU time | 727.39 seconds |
| Started | Jul 03 07:22:05 PM PDT 24 |
| Finished | Jul 03 07:34:14 PM PDT 24 |
| Peak memory | 574340 kb |
| Host | smart-d7761ea5-6f30-45d1-8679-92aa3661e924 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=610954136 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_random_slow_rsp.610954136 |
| Directory | /workspace/0.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_random_zero_delays.1318033209 |
| Short name | T2827 |
| Test name | |
| Test status | |
| Simulation time | 444720064 ps |
| CPU time | 38.75 seconds |
| Started | Jul 03 07:21:58 PM PDT 24 |
| Finished | Jul 03 07:22:37 PM PDT 24 |
| Peak memory | 574236 kb |
| Host | smart-a244c911-c19b-4907-9aff-d3b493edfe32 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1318033209 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_random_zero_dela ys.1318033209 |
| Directory | /workspace/0.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_same_source.791413467 |
| Short name | T476 |
| Test name | |
| Test status | |
| Simulation time | 1497046088 ps |
| CPU time | 47.86 seconds |
| Started | Jul 03 07:22:04 PM PDT 24 |
| Finished | Jul 03 07:22:53 PM PDT 24 |
| Peak memory | 573944 kb |
| Host | smart-65fcbf5d-3b90-40fe-bb41-df58af4726ec |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791413467 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_same_source.791413467 |
| Directory | /workspace/0.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_smoke.961315546 |
| Short name | T1403 |
| Test name | |
| Test status | |
| Simulation time | 48830762 ps |
| CPU time | 6.56 seconds |
| Started | Jul 03 07:22:14 PM PDT 24 |
| Finished | Jul 03 07:22:24 PM PDT 24 |
| Peak memory | 574036 kb |
| Host | smart-d642960e-9f09-43f0-9f08-826f85d4f1c8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=961315546 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_smoke.961315546 |
| Directory | /workspace/0.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_smoke_large_delays.3625633281 |
| Short name | T2887 |
| Test name | |
| Test status | |
| Simulation time | 10494845591 ps |
| CPU time | 104.62 seconds |
| Started | Jul 03 07:22:08 PM PDT 24 |
| Finished | Jul 03 07:23:53 PM PDT 24 |
| Peak memory | 573256 kb |
| Host | smart-e32dbd42-05b8-4b2f-bfb6-7da6f25f6423 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3625633281 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_large_delays.3625633281 |
| Directory | /workspace/0.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_smoke_slow_rsp.890008107 |
| Short name | T2685 |
| Test name | |
| Test status | |
| Simulation time | 5381805077 ps |
| CPU time | 83.93 seconds |
| Started | Jul 03 07:22:13 PM PDT 24 |
| Finished | Jul 03 07:23:40 PM PDT 24 |
| Peak memory | 574024 kb |
| Host | smart-cfc76e80-4cea-4e8a-a12e-dae8a1f2bc9f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=890008107 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_slow_rsp.890008107 |
| Directory | /workspace/0.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_smoke_zero_delays.3771487919 |
| Short name | T2256 |
| Test name | |
| Test status | |
| Simulation time | 47532909 ps |
| CPU time | 6.23 seconds |
| Started | Jul 03 07:22:14 PM PDT 24 |
| Finished | Jul 03 07:22:23 PM PDT 24 |
| Peak memory | 574224 kb |
| Host | smart-3f49ce7f-58f8-437c-be59-96d2b142e3c6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3771487919 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_zero_delays .3771487919 |
| Directory | /workspace/0.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_stress_all_with_error.103823064 |
| Short name | T2853 |
| Test name | |
| Test status | |
| Simulation time | 3119477328 ps |
| CPU time | 209.01 seconds |
| Started | Jul 03 07:22:04 PM PDT 24 |
| Finished | Jul 03 07:25:35 PM PDT 24 |
| Peak memory | 574732 kb |
| Host | smart-978f37f9-13d0-4140-b743-15211815a8ee |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103823064 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_error.103823064 |
| Directory | /workspace/0.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_stress_all_with_rand_reset.597054255 |
| Short name | T432 |
| Test name | |
| Test status | |
| Simulation time | 2190805850 ps |
| CPU time | 325.66 seconds |
| Started | Jul 03 07:22:07 PM PDT 24 |
| Finished | Jul 03 07:27:33 PM PDT 24 |
| Peak memory | 574728 kb |
| Host | smart-a012536a-5ae5-4a20-b621-6db9895c0481 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=597054255 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_w ith_rand_reset.597054255 |
| Directory | /workspace/0.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_stress_all_with_reset_error.2757436598 |
| Short name | T2269 |
| Test name | |
| Test status | |
| Simulation time | 10970036092 ps |
| CPU time | 535.59 seconds |
| Started | Jul 03 07:22:03 PM PDT 24 |
| Finished | Jul 03 07:31:01 PM PDT 24 |
| Peak memory | 574696 kb |
| Host | smart-6c209d5a-d9af-44f4-807d-56153f2aa0f6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2757436598 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all _with_reset_error.2757436598 |
| Directory | /workspace/0.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_unmapped_addr.3150609335 |
| Short name | T592 |
| Test name | |
| Test status | |
| Simulation time | 311377126 ps |
| CPU time | 16.43 seconds |
| Started | Jul 03 07:22:06 PM PDT 24 |
| Finished | Jul 03 07:22:24 PM PDT 24 |
| Peak memory | 574196 kb |
| Host | smart-ef33874f-0b6d-4526-bb78-a0ee14a875a3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3150609335 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_unmapped_addr.3150609335 |
| Directory | /workspace/0.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/1.chip_csr_aliasing.576018169 |
| Short name | T2283 |
| Test name | |
| Test status | |
| Simulation time | 29111139659 ps |
| CPU time | 4707.59 seconds |
| Started | Jul 03 07:22:14 PM PDT 24 |
| Finished | Jul 03 08:40:45 PM PDT 24 |
| Peak memory | 592600 kb |
| Host | smart-1c435040-5fd2-4566-97b6-5d4adf345f59 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +csr_aliasing +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=576018169 -assert nopostproc +UVM_TESTNAME=chip_b ase_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n ull -cm_name 1.chip_csr_aliasing.576018169 |
| Directory | /workspace/1.chip_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/1.chip_csr_bit_bash.1061791408 |
| Short name | T1769 |
| Test name | |
| Test status | |
| Simulation time | 46336149085 ps |
| CPU time | 5397.75 seconds |
| Started | Jul 03 07:22:12 PM PDT 24 |
| Finished | Jul 03 08:52:13 PM PDT 24 |
| Peak memory | 590624 kb |
| Host | smart-516abcd6-d518-43e4-8ba8-2ee10ca2f677 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +num_test_csrs=200 +csr_bit_bash +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1061791408 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 1.chip_csr_bit_bash.1061791408 |
| Directory | /workspace/1.chip_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/1.chip_csr_hw_reset.1362576101 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 6402388648 ps |
| CPU time | 399.55 seconds |
| Started | Jul 03 07:22:16 PM PDT 24 |
| Finished | Jul 03 07:29:00 PM PDT 24 |
| Peak memory | 663992 kb |
| Host | smart-610420d6-074f-479d-af21-071bda41d33d |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1362576101 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.chip_csr_hw_r eset.1362576101 |
| Directory | /workspace/1.chip_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/1.chip_csr_rw.776119807 |
| Short name | T2013 |
| Test name | |
| Test status | |
| Simulation time | 4504304727 ps |
| CPU time | 339.88 seconds |
| Started | Jul 03 07:22:24 PM PDT 24 |
| Finished | Jul 03 07:28:06 PM PDT 24 |
| Peak memory | 596612 kb |
| Host | smart-2d0f645e-1ff3-4c64-92cd-9188964678e6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=776119807 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.chip_csr_rw.776119807 |
| Directory | /workspace/1.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/1.chip_prim_tl_access.365000075 |
| Short name | T1979 |
| Test name | |
| Test status | |
| Simulation time | 11003564988 ps |
| CPU time | 531.07 seconds |
| Started | Jul 03 07:22:10 PM PDT 24 |
| Finished | Jul 03 07:31:02 PM PDT 24 |
| Peak memory | 589152 kb |
| Host | smart-8e432008-098a-4eca-ba02-107f5c8645e6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +en_scb_tl_err_chk=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=365000075 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_prim_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1 .chip_prim_tl_access.365000075 |
| Directory | /workspace/1.chip_prim_tl_access/latest |
| Test location | /workspace/coverage/cover_reg_top/1.chip_rv_dm_lc_disabled.2332487981 |
| Short name | T2354 |
| Test name | |
| Test status | |
| Simulation time | 12783504810 ps |
| CPU time | 429.49 seconds |
| Started | Jul 03 07:22:10 PM PDT 24 |
| Finished | Jul 03 07:29:21 PM PDT 24 |
| Peak memory | 591616 kb |
| Host | smart-3c88cce8-ad04-4ecd-a67e-1a042f06456c |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +en_scb_tl_err_chk=0 +use_jtag_dmi=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2332487981 -assert nopostproc +UVM_TESTNAME=chip_base_t est +UVM_TEST_SEQ=chip_rv_dm_lc_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.chip_rv_dm_lc_disabled.2332487981 |
| Directory | /workspace/1.chip_rv_dm_lc_disabled/latest |
| Test location | /workspace/coverage/cover_reg_top/1.chip_tl_errors.1755283655 |
| Short name | T643 |
| Test name | |
| Test status | |
| Simulation time | 5250985600 ps |
| CPU time | 463.27 seconds |
| Started | Jul 03 07:22:14 PM PDT 24 |
| Finished | Jul 03 07:30:01 PM PDT 24 |
| Peak memory | 603068 kb |
| Host | smart-f32da7f8-b8ea-4c46-81c3-8f0b52733eb4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1755283655 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.chip_tl_errors.1755283655 |
| Directory | /workspace/1.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_access_same_device.2183125848 |
| Short name | T2585 |
| Test name | |
| Test status | |
| Simulation time | 2335476013 ps |
| CPU time | 100.99 seconds |
| Started | Jul 03 07:22:12 PM PDT 24 |
| Finished | Jul 03 07:23:56 PM PDT 24 |
| Peak memory | 574332 kb |
| Host | smart-03e20bc4-d618-4a71-8b1d-3e1b91a5fce4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2183125848 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_access_same_device. 2183125848 |
| Directory | /workspace/1.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_error_and_unmapped_addr.980599956 |
| Short name | T1561 |
| Test name | |
| Test status | |
| Simulation time | 1289734434 ps |
| CPU time | 45.22 seconds |
| Started | Jul 03 07:22:16 PM PDT 24 |
| Finished | Jul 03 07:23:05 PM PDT 24 |
| Peak memory | 574032 kb |
| Host | smart-e235bfda-5b9f-45d5-a48f-46e083cc24c9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=980599956 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_error_and_unmapped_addr. 980599956 |
| Directory | /workspace/1.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_error_random.3547292111 |
| Short name | T2248 |
| Test name | |
| Test status | |
| Simulation time | 523346369 ps |
| CPU time | 39.52 seconds |
| Started | Jul 03 07:22:24 PM PDT 24 |
| Finished | Jul 03 07:23:05 PM PDT 24 |
| Peak memory | 574012 kb |
| Host | smart-1a0e04a0-f87e-4a78-8b24-1269baed560c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3547292111 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_error_random.3547292111 |
| Directory | /workspace/1.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_random.690117154 |
| Short name | T2692 |
| Test name | |
| Test status | |
| Simulation time | 459819169 ps |
| CPU time | 41.54 seconds |
| Started | Jul 03 07:22:11 PM PDT 24 |
| Finished | Jul 03 07:22:53 PM PDT 24 |
| Peak memory | 574192 kb |
| Host | smart-44b01ffc-0510-457f-a412-bd576db8851b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=690117154 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_random.690117154 |
| Directory | /workspace/1.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_random_large_delays.2533317351 |
| Short name | T1906 |
| Test name | |
| Test status | |
| Simulation time | 60047038616 ps |
| CPU time | 659.27 seconds |
| Started | Jul 03 07:22:12 PM PDT 24 |
| Finished | Jul 03 07:33:14 PM PDT 24 |
| Peak memory | 574208 kb |
| Host | smart-13d75aaf-0ad7-484f-9cfb-d9c2887ab84b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2533317351 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_random_large_delays.2533317351 |
| Directory | /workspace/1.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_random_slow_rsp.1253594717 |
| Short name | T2002 |
| Test name | |
| Test status | |
| Simulation time | 49277803474 ps |
| CPU time | 837.43 seconds |
| Started | Jul 03 07:22:09 PM PDT 24 |
| Finished | Jul 03 07:36:08 PM PDT 24 |
| Peak memory | 574056 kb |
| Host | smart-e821be59-b0ae-476d-bd5b-3b3b33a5315b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1253594717 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_random_slow_rsp.1253594717 |
| Directory | /workspace/1.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_random_zero_delays.1587321567 |
| Short name | T1439 |
| Test name | |
| Test status | |
| Simulation time | 87476769 ps |
| CPU time | 10.88 seconds |
| Started | Jul 03 07:22:12 PM PDT 24 |
| Finished | Jul 03 07:22:25 PM PDT 24 |
| Peak memory | 574092 kb |
| Host | smart-ccdbc38b-c511-4541-b4aa-7643d2e7ccba |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1587321567 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_random_zero_dela ys.1587321567 |
| Directory | /workspace/1.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_same_source.4107844379 |
| Short name | T2342 |
| Test name | |
| Test status | |
| Simulation time | 289452138 ps |
| CPU time | 20.95 seconds |
| Started | Jul 03 07:22:18 PM PDT 24 |
| Finished | Jul 03 07:22:43 PM PDT 24 |
| Peak memory | 574000 kb |
| Host | smart-4072e07d-24d2-4e33-95d7-553c12add252 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4107844379 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_same_source.4107844379 |
| Directory | /workspace/1.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_smoke.213209107 |
| Short name | T1818 |
| Test name | |
| Test status | |
| Simulation time | 235346613 ps |
| CPU time | 9.16 seconds |
| Started | Jul 03 07:22:10 PM PDT 24 |
| Finished | Jul 03 07:22:20 PM PDT 24 |
| Peak memory | 573156 kb |
| Host | smart-ac71ce3b-2796-47e2-83c1-0e582f5f66a4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=213209107 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_smoke.213209107 |
| Directory | /workspace/1.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_smoke_large_delays.3424778301 |
| Short name | T1361 |
| Test name | |
| Test status | |
| Simulation time | 8202072860 ps |
| CPU time | 86.39 seconds |
| Started | Jul 03 07:22:14 PM PDT 24 |
| Finished | Jul 03 07:23:43 PM PDT 24 |
| Peak memory | 573148 kb |
| Host | smart-be22bd3e-8906-45ba-9266-f1dbd94a40d0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3424778301 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_large_delays.3424778301 |
| Directory | /workspace/1.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_smoke_slow_rsp.1206493585 |
| Short name | T2313 |
| Test name | |
| Test status | |
| Simulation time | 5530787855 ps |
| CPU time | 90.03 seconds |
| Started | Jul 03 07:22:11 PM PDT 24 |
| Finished | Jul 03 07:23:43 PM PDT 24 |
| Peak memory | 574196 kb |
| Host | smart-1271d01a-36d0-4ed4-914a-387566dfd4b9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206493585 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_slow_rsp.1206493585 |
| Directory | /workspace/1.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_smoke_zero_delays.894643524 |
| Short name | T1319 |
| Test name | |
| Test status | |
| Simulation time | 37711933 ps |
| CPU time | 5.91 seconds |
| Started | Jul 03 07:22:15 PM PDT 24 |
| Finished | Jul 03 07:22:24 PM PDT 24 |
| Peak memory | 573164 kb |
| Host | smart-3ee249b9-23fb-4369-b5c5-c810ee815ce2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=894643524 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_zero_delays. 894643524 |
| Directory | /workspace/1.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_stress_all.583831381 |
| Short name | T440 |
| Test name | |
| Test status | |
| Simulation time | 2119661154 ps |
| CPU time | 182.85 seconds |
| Started | Jul 03 07:22:20 PM PDT 24 |
| Finished | Jul 03 07:25:26 PM PDT 24 |
| Peak memory | 574556 kb |
| Host | smart-d3beab32-9d6d-4912-9650-eaee77057e25 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=583831381 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all.583831381 |
| Directory | /workspace/1.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_stress_all_with_error.1318627398 |
| Short name | T1641 |
| Test name | |
| Test status | |
| Simulation time | 5838637005 ps |
| CPU time | 226.11 seconds |
| Started | Jul 03 07:22:18 PM PDT 24 |
| Finished | Jul 03 07:26:08 PM PDT 24 |
| Peak memory | 574676 kb |
| Host | smart-225260cd-f31f-46a9-9090-098562988b45 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1318627398 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_error.1318627398 |
| Directory | /workspace/1.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_stress_all_with_reset_error.3144323578 |
| Short name | T2561 |
| Test name | |
| Test status | |
| Simulation time | 300175444 ps |
| CPU time | 69.19 seconds |
| Started | Jul 03 07:22:18 PM PDT 24 |
| Finished | Jul 03 07:23:31 PM PDT 24 |
| Peak memory | 574628 kb |
| Host | smart-447dbde8-b2f4-4d35-8b20-7967d6cc9bd0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3144323578 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all _with_reset_error.3144323578 |
| Directory | /workspace/1.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_unmapped_addr.3249160176 |
| Short name | T1820 |
| Test name | |
| Test status | |
| Simulation time | 135954550 ps |
| CPU time | 8.79 seconds |
| Started | Jul 03 07:22:17 PM PDT 24 |
| Finished | Jul 03 07:22:29 PM PDT 24 |
| Peak memory | 573112 kb |
| Host | smart-12f49ed1-ff90-40df-baa3-1b9e4b74f4e4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3249160176 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_unmapped_addr.3249160176 |
| Directory | /workspace/1.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/10.chip_csr_rw.3019720382 |
| Short name | T394 |
| Test name | |
| Test status | |
| Simulation time | 6451878695 ps |
| CPU time | 668.01 seconds |
| Started | Jul 03 07:24:02 PM PDT 24 |
| Finished | Jul 03 07:35:11 PM PDT 24 |
| Peak memory | 597680 kb |
| Host | smart-7bc78719-065e-485b-87b2-530320a7672d |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3019720382 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.chip_csr_rw.3019720382 |
| Directory | /workspace/10.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/10.chip_same_csr_outstanding.573844998 |
| Short name | T375 |
| Test name | |
| Test status | |
| Simulation time | 15201811526 ps |
| CPU time | 2124.01 seconds |
| Started | Jul 03 07:23:51 PM PDT 24 |
| Finished | Jul 03 07:59:17 PM PDT 24 |
| Peak memory | 592064 kb |
| Host | smart-1ab31fd9-37d2-4760-9e3b-2f8f887c9651 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=573844998 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 10.chip_same_csr_outstanding.573844998 |
| Directory | /workspace/10.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_access_same_device.3326497706 |
| Short name | T1550 |
| Test name | |
| Test status | |
| Simulation time | 713846591 ps |
| CPU time | 63.13 seconds |
| Started | Jul 03 07:23:59 PM PDT 24 |
| Finished | Jul 03 07:25:03 PM PDT 24 |
| Peak memory | 574144 kb |
| Host | smart-c045d135-d9bb-4870-a56c-7fe6dd22f5b1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3326497706 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_access_same_device .3326497706 |
| Directory | /workspace/10.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_access_same_device_slow_rsp.1089572713 |
| Short name | T2122 |
| Test name | |
| Test status | |
| Simulation time | 61870351495 ps |
| CPU time | 1122.82 seconds |
| Started | Jul 03 07:23:59 PM PDT 24 |
| Finished | Jul 03 07:42:43 PM PDT 24 |
| Peak memory | 574320 kb |
| Host | smart-22d5d24c-3dc5-46e7-9b4d-bbff22421f85 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1089572713 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_access_same_ device_slow_rsp.1089572713 |
| Directory | /workspace/10.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_error_and_unmapped_addr.3997473964 |
| Short name | T1832 |
| Test name | |
| Test status | |
| Simulation time | 982396350 ps |
| CPU time | 44.44 seconds |
| Started | Jul 03 07:23:56 PM PDT 24 |
| Finished | Jul 03 07:24:41 PM PDT 24 |
| Peak memory | 574092 kb |
| Host | smart-baf9704b-baa8-49df-bb23-41b5d7c20f78 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3997473964 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_error_and_unmapped_add r.3997473964 |
| Directory | /workspace/10.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_error_random.2832466480 |
| Short name | T2221 |
| Test name | |
| Test status | |
| Simulation time | 208408055 ps |
| CPU time | 20.95 seconds |
| Started | Jul 03 07:23:50 PM PDT 24 |
| Finished | Jul 03 07:24:11 PM PDT 24 |
| Peak memory | 574432 kb |
| Host | smart-402b4309-aa37-4abf-8237-a35de0cca667 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2832466480 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_error_random.2832466480 |
| Directory | /workspace/10.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_random.2574944202 |
| Short name | T2319 |
| Test name | |
| Test status | |
| Simulation time | 707301801 ps |
| CPU time | 26 seconds |
| Started | Jul 03 07:23:50 PM PDT 24 |
| Finished | Jul 03 07:24:17 PM PDT 24 |
| Peak memory | 574208 kb |
| Host | smart-3d3b2b65-7032-4f73-bd06-b1794cf8bc70 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2574944202 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_random.2574944202 |
| Directory | /workspace/10.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_random_large_delays.3794780543 |
| Short name | T2222 |
| Test name | |
| Test status | |
| Simulation time | 77468250798 ps |
| CPU time | 771.97 seconds |
| Started | Jul 03 07:23:49 PM PDT 24 |
| Finished | Jul 03 07:36:42 PM PDT 24 |
| Peak memory | 574252 kb |
| Host | smart-51920441-bee4-4358-9f8c-75f73d6c8bab |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3794780543 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_random_large_delays.3794780543 |
| Directory | /workspace/10.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_random_slow_rsp.449604197 |
| Short name | T1648 |
| Test name | |
| Test status | |
| Simulation time | 24970811429 ps |
| CPU time | 438.4 seconds |
| Started | Jul 03 07:23:58 PM PDT 24 |
| Finished | Jul 03 07:31:18 PM PDT 24 |
| Peak memory | 574212 kb |
| Host | smart-cf587e57-01f6-48fe-971c-01caa6d169ed |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=449604197 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_random_slow_rsp.449604197 |
| Directory | /workspace/10.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_random_zero_delays.1260268763 |
| Short name | T539 |
| Test name | |
| Test status | |
| Simulation time | 116635303 ps |
| CPU time | 13.42 seconds |
| Started | Jul 03 07:23:55 PM PDT 24 |
| Finished | Jul 03 07:24:10 PM PDT 24 |
| Peak memory | 573988 kb |
| Host | smart-c8142476-0b86-416c-a829-d79da3b2804f |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1260268763 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_random_zero_del ays.1260268763 |
| Directory | /workspace/10.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_same_source.114391804 |
| Short name | T1824 |
| Test name | |
| Test status | |
| Simulation time | 116754639 ps |
| CPU time | 11.2 seconds |
| Started | Jul 03 07:23:55 PM PDT 24 |
| Finished | Jul 03 07:24:07 PM PDT 24 |
| Peak memory | 573984 kb |
| Host | smart-bf19d1c2-6689-44d2-bdbd-04fe5170815a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114391804 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_same_source.114391804 |
| Directory | /workspace/10.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_smoke.2612319242 |
| Short name | T2350 |
| Test name | |
| Test status | |
| Simulation time | 155005446 ps |
| CPU time | 7.84 seconds |
| Started | Jul 03 07:23:51 PM PDT 24 |
| Finished | Jul 03 07:23:59 PM PDT 24 |
| Peak memory | 572864 kb |
| Host | smart-84dd3362-3701-496a-a789-227b8c540ea4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2612319242 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_smoke.2612319242 |
| Directory | /workspace/10.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_smoke_large_delays.3878847598 |
| Short name | T1374 |
| Test name | |
| Test status | |
| Simulation time | 10315612292 ps |
| CPU time | 109.37 seconds |
| Started | Jul 03 07:23:50 PM PDT 24 |
| Finished | Jul 03 07:25:40 PM PDT 24 |
| Peak memory | 573308 kb |
| Host | smart-502bdad1-9151-4382-b288-614a05de04fc |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3878847598 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_large_delays.3878847598 |
| Directory | /workspace/10.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_smoke_slow_rsp.1233814944 |
| Short name | T1685 |
| Test name | |
| Test status | |
| Simulation time | 5433510892 ps |
| CPU time | 90.94 seconds |
| Started | Jul 03 07:23:59 PM PDT 24 |
| Finished | Jul 03 07:25:31 PM PDT 24 |
| Peak memory | 574224 kb |
| Host | smart-f92826dc-e503-495c-83d4-a7ece5657caa |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233814944 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_slow_rsp.1233814944 |
| Directory | /workspace/10.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_smoke_zero_delays.3677887600 |
| Short name | T2119 |
| Test name | |
| Test status | |
| Simulation time | 38679297 ps |
| CPU time | 6.18 seconds |
| Started | Jul 03 07:23:58 PM PDT 24 |
| Finished | Jul 03 07:24:05 PM PDT 24 |
| Peak memory | 574160 kb |
| Host | smart-ee7939c4-ee90-41f8-bed9-33b64b184be9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3677887600 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_zero_delay s.3677887600 |
| Directory | /workspace/10.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_stress_all.634069215 |
| Short name | T2140 |
| Test name | |
| Test status | |
| Simulation time | 2791827305 ps |
| CPU time | 224.99 seconds |
| Started | Jul 03 07:23:57 PM PDT 24 |
| Finished | Jul 03 07:27:42 PM PDT 24 |
| Peak memory | 574660 kb |
| Host | smart-e9ea2802-11ad-4632-911b-9f5adb04b212 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=634069215 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all.634069215 |
| Directory | /workspace/10.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_stress_all_with_error.365380397 |
| Short name | T1336 |
| Test name | |
| Test status | |
| Simulation time | 1873663726 ps |
| CPU time | 199.58 seconds |
| Started | Jul 03 07:23:58 PM PDT 24 |
| Finished | Jul 03 07:27:19 PM PDT 24 |
| Peak memory | 574680 kb |
| Host | smart-647f5e20-3eeb-4311-af53-449a1865890e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=365380397 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_error.365380397 |
| Directory | /workspace/10.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_stress_all_with_rand_reset.1036081540 |
| Short name | T2049 |
| Test name | |
| Test status | |
| Simulation time | 143640630 ps |
| CPU time | 61.19 seconds |
| Started | Jul 03 07:23:55 PM PDT 24 |
| Finished | Jul 03 07:24:58 PM PDT 24 |
| Peak memory | 574616 kb |
| Host | smart-08a4259b-3d39-481d-a23c-1e21cc58f4e3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1036081540 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all _with_rand_reset.1036081540 |
| Directory | /workspace/10.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_stress_all_with_reset_error.1759301965 |
| Short name | T2451 |
| Test name | |
| Test status | |
| Simulation time | 7049389244 ps |
| CPU time | 470.91 seconds |
| Started | Jul 03 07:23:56 PM PDT 24 |
| Finished | Jul 03 07:31:48 PM PDT 24 |
| Peak memory | 574684 kb |
| Host | smart-ec75a5c9-e5b3-4e96-b6ac-daa31e8980d6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1759301965 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_stress_al l_with_reset_error.1759301965 |
| Directory | /workspace/10.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_unmapped_addr.1227430031 |
| Short name | T2121 |
| Test name | |
| Test status | |
| Simulation time | 1271651295 ps |
| CPU time | 59.59 seconds |
| Started | Jul 03 07:23:55 PM PDT 24 |
| Finished | Jul 03 07:24:55 PM PDT 24 |
| Peak memory | 574056 kb |
| Host | smart-a2a3818b-d9a2-46d0-a4bf-bab8546be7d4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1227430031 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_unmapped_addr.1227430031 |
| Directory | /workspace/10.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/11.chip_csr_rw.755337994 |
| Short name | T381 |
| Test name | |
| Test status | |
| Simulation time | 4201001200 ps |
| CPU time | 362.23 seconds |
| Started | Jul 03 07:24:06 PM PDT 24 |
| Finished | Jul 03 07:30:09 PM PDT 24 |
| Peak memory | 596172 kb |
| Host | smart-1d623ea6-abbe-4395-a276-e130345d4b4f |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=755337994 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.chip_csr_rw.755337994 |
| Directory | /workspace/11.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/11.chip_same_csr_outstanding.3023885661 |
| Short name | T2556 |
| Test name | |
| Test status | |
| Simulation time | 29591492764 ps |
| CPU time | 5132.33 seconds |
| Started | Jul 03 07:24:02 PM PDT 24 |
| Finished | Jul 03 08:49:36 PM PDT 24 |
| Peak memory | 591836 kb |
| Host | smart-811d39b1-792f-4ddd-8b82-ebbf9b677f14 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3023885661 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 11.chip_same_csr_outstanding.3023885661 |
| Directory | /workspace/11.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/11.chip_tl_errors.945589698 |
| Short name | T2499 |
| Test name | |
| Test status | |
| Simulation time | 3107064325 ps |
| CPU time | 186.02 seconds |
| Started | Jul 03 07:23:58 PM PDT 24 |
| Finished | Jul 03 07:27:05 PM PDT 24 |
| Peak memory | 601208 kb |
| Host | smart-f60540af-7f0a-4c65-8fcb-c049c83cab4d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=945589698 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.chip_tl_errors.945589698 |
| Directory | /workspace/11.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_access_same_device.3199153749 |
| Short name | T2714 |
| Test name | |
| Test status | |
| Simulation time | 764835595 ps |
| CPU time | 58.83 seconds |
| Started | Jul 03 07:24:06 PM PDT 24 |
| Finished | Jul 03 07:25:05 PM PDT 24 |
| Peak memory | 574212 kb |
| Host | smart-47b3b05c-c78d-48c0-84ff-28342fcfffba |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3199153749 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_access_same_device .3199153749 |
| Directory | /workspace/11.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_access_same_device_slow_rsp.3876003479 |
| Short name | T1878 |
| Test name | |
| Test status | |
| Simulation time | 24329831546 ps |
| CPU time | 445.92 seconds |
| Started | Jul 03 07:24:21 PM PDT 24 |
| Finished | Jul 03 07:31:50 PM PDT 24 |
| Peak memory | 574304 kb |
| Host | smart-ee71298d-f134-4170-997a-0278413a0e42 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3876003479 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_access_same_ device_slow_rsp.3876003479 |
| Directory | /workspace/11.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_error_and_unmapped_addr.3170036194 |
| Short name | T555 |
| Test name | |
| Test status | |
| Simulation time | 743065773 ps |
| CPU time | 37.17 seconds |
| Started | Jul 03 07:24:06 PM PDT 24 |
| Finished | Jul 03 07:24:44 PM PDT 24 |
| Peak memory | 574476 kb |
| Host | smart-520d635d-5f4d-4b41-8f97-d115b4d860aa |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3170036194 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_error_and_unmapped_add r.3170036194 |
| Directory | /workspace/11.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_error_random.211130277 |
| Short name | T1738 |
| Test name | |
| Test status | |
| Simulation time | 155570709 ps |
| CPU time | 14.73 seconds |
| Started | Jul 03 07:24:08 PM PDT 24 |
| Finished | Jul 03 07:24:24 PM PDT 24 |
| Peak memory | 574456 kb |
| Host | smart-e0a08c92-01e2-4258-8750-98636063bf25 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=211130277 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_error_random.211130277 |
| Directory | /workspace/11.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_random.794399258 |
| Short name | T523 |
| Test name | |
| Test status | |
| Simulation time | 144420934 ps |
| CPU time | 14.97 seconds |
| Started | Jul 03 07:24:01 PM PDT 24 |
| Finished | Jul 03 07:24:17 PM PDT 24 |
| Peak memory | 574240 kb |
| Host | smart-362a45a6-cda4-45ab-bb54-229126246a3b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=794399258 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_random.794399258 |
| Directory | /workspace/11.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_random_large_delays.2776565672 |
| Short name | T2678 |
| Test name | |
| Test status | |
| Simulation time | 90323215992 ps |
| CPU time | 936.32 seconds |
| Started | Jul 03 07:24:10 PM PDT 24 |
| Finished | Jul 03 07:39:47 PM PDT 24 |
| Peak memory | 574300 kb |
| Host | smart-12d047eb-70f6-4263-bf87-26879f0fe38c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2776565672 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_random_large_delays.2776565672 |
| Directory | /workspace/11.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_random_slow_rsp.1460931435 |
| Short name | T1817 |
| Test name | |
| Test status | |
| Simulation time | 42216308625 ps |
| CPU time | 738.24 seconds |
| Started | Jul 03 07:24:08 PM PDT 24 |
| Finished | Jul 03 07:36:27 PM PDT 24 |
| Peak memory | 574052 kb |
| Host | smart-eca16bf4-427f-43b4-bf38-ec8cffc04b14 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1460931435 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_random_slow_rsp.1460931435 |
| Directory | /workspace/11.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_random_zero_delays.2471094649 |
| Short name | T610 |
| Test name | |
| Test status | |
| Simulation time | 424948903 ps |
| CPU time | 36.3 seconds |
| Started | Jul 03 07:24:07 PM PDT 24 |
| Finished | Jul 03 07:24:44 PM PDT 24 |
| Peak memory | 574016 kb |
| Host | smart-1e101e4b-05c8-4aab-b9de-0f8409878911 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2471094649 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_random_zero_del ays.2471094649 |
| Directory | /workspace/11.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_same_source.4190677775 |
| Short name | T2763 |
| Test name | |
| Test status | |
| Simulation time | 1068690931 ps |
| CPU time | 34.37 seconds |
| Started | Jul 03 07:24:11 PM PDT 24 |
| Finished | Jul 03 07:24:47 PM PDT 24 |
| Peak memory | 574008 kb |
| Host | smart-b4bb77d8-fb53-45e8-991a-92296ef30177 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4190677775 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_same_source.4190677775 |
| Directory | /workspace/11.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_smoke.1886667143 |
| Short name | T2653 |
| Test name | |
| Test status | |
| Simulation time | 123651524 ps |
| CPU time | 7.45 seconds |
| Started | Jul 03 07:24:00 PM PDT 24 |
| Finished | Jul 03 07:24:09 PM PDT 24 |
| Peak memory | 573948 kb |
| Host | smart-8e5a630c-7922-4ff7-a51e-885d2d2efd61 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886667143 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_smoke.1886667143 |
| Directory | /workspace/11.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_smoke_large_delays.2852309397 |
| Short name | T2071 |
| Test name | |
| Test status | |
| Simulation time | 9997826300 ps |
| CPU time | 103.55 seconds |
| Started | Jul 03 07:23:58 PM PDT 24 |
| Finished | Jul 03 07:25:42 PM PDT 24 |
| Peak memory | 573212 kb |
| Host | smart-fdaf245e-9b83-4ae2-8845-187b1d85cdf2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2852309397 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_large_delays.2852309397 |
| Directory | /workspace/11.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_smoke_slow_rsp.3714966905 |
| Short name | T2373 |
| Test name | |
| Test status | |
| Simulation time | 6945824542 ps |
| CPU time | 120.69 seconds |
| Started | Jul 03 07:23:59 PM PDT 24 |
| Finished | Jul 03 07:26:01 PM PDT 24 |
| Peak memory | 573016 kb |
| Host | smart-0e3d4858-950b-4bb7-835b-5f93423a2fdd |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714966905 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_slow_rsp.3714966905 |
| Directory | /workspace/11.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_smoke_zero_delays.356242338 |
| Short name | T1536 |
| Test name | |
| Test status | |
| Simulation time | 48776247 ps |
| CPU time | 6.88 seconds |
| Started | Jul 03 07:23:59 PM PDT 24 |
| Finished | Jul 03 07:24:07 PM PDT 24 |
| Peak memory | 573964 kb |
| Host | smart-f525d2e8-63bd-4403-bdcb-bb7a087d6b9d |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=356242338 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_zero_delays .356242338 |
| Directory | /workspace/11.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_stress_all.858027911 |
| Short name | T1751 |
| Test name | |
| Test status | |
| Simulation time | 3327090372 ps |
| CPU time | 317.35 seconds |
| Started | Jul 03 07:24:07 PM PDT 24 |
| Finished | Jul 03 07:29:25 PM PDT 24 |
| Peak memory | 574688 kb |
| Host | smart-1e79aaed-d189-4070-b8cc-bd54f1b71633 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=858027911 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all.858027911 |
| Directory | /workspace/11.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_stress_all_with_rand_reset.2072797298 |
| Short name | T816 |
| Test name | |
| Test status | |
| Simulation time | 287279854 ps |
| CPU time | 179.13 seconds |
| Started | Jul 03 07:24:11 PM PDT 24 |
| Finished | Jul 03 07:27:12 PM PDT 24 |
| Peak memory | 574688 kb |
| Host | smart-8fb548ac-0399-4ead-ad10-2a8526d093da |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2072797298 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all _with_rand_reset.2072797298 |
| Directory | /workspace/11.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_stress_all_with_reset_error.2448657204 |
| Short name | T1871 |
| Test name | |
| Test status | |
| Simulation time | 4182054122 ps |
| CPU time | 198.61 seconds |
| Started | Jul 03 07:24:08 PM PDT 24 |
| Finished | Jul 03 07:27:27 PM PDT 24 |
| Peak memory | 574720 kb |
| Host | smart-943a3985-ed2d-462a-ba39-4c451ae623ce |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2448657204 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_stress_al l_with_reset_error.2448657204 |
| Directory | /workspace/11.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_unmapped_addr.2984014477 |
| Short name | T2365 |
| Test name | |
| Test status | |
| Simulation time | 524693920 ps |
| CPU time | 27.02 seconds |
| Started | Jul 03 07:24:08 PM PDT 24 |
| Finished | Jul 03 07:24:36 PM PDT 24 |
| Peak memory | 574192 kb |
| Host | smart-8f8d0f81-4644-4299-b402-f45d306a0735 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2984014477 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_unmapped_addr.2984014477 |
| Directory | /workspace/11.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/12.chip_csr_rw.3427997723 |
| Short name | T2814 |
| Test name | |
| Test status | |
| Simulation time | 4744977210 ps |
| CPU time | 425.78 seconds |
| Started | Jul 03 07:24:16 PM PDT 24 |
| Finished | Jul 03 07:31:24 PM PDT 24 |
| Peak memory | 597872 kb |
| Host | smart-c5ed8788-01b9-485f-907e-1addd4e63191 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3427997723 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.chip_csr_rw.3427997723 |
| Directory | /workspace/12.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/12.chip_same_csr_outstanding.3525464865 |
| Short name | T1553 |
| Test name | |
| Test status | |
| Simulation time | 16804120789 ps |
| CPU time | 2134.8 seconds |
| Started | Jul 03 07:24:22 PM PDT 24 |
| Finished | Jul 03 08:00:00 PM PDT 24 |
| Peak memory | 592072 kb |
| Host | smart-4a138d61-9670-456c-bac0-a42f20d44c1f |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3525464865 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 12.chip_same_csr_outstanding.3525464865 |
| Directory | /workspace/12.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/12.chip_tl_errors.3780194070 |
| Short name | T1386 |
| Test name | |
| Test status | |
| Simulation time | 3134021942 ps |
| CPU time | 93.64 seconds |
| Started | Jul 03 07:24:06 PM PDT 24 |
| Finished | Jul 03 07:25:41 PM PDT 24 |
| Peak memory | 591232 kb |
| Host | smart-c40029cd-13ae-474e-a1a8-3322a390ac31 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3780194070 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.chip_tl_errors.3780194070 |
| Directory | /workspace/12.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_access_same_device.4049313197 |
| Short name | T798 |
| Test name | |
| Test status | |
| Simulation time | 1382777047 ps |
| CPU time | 49.93 seconds |
| Started | Jul 03 07:24:13 PM PDT 24 |
| Finished | Jul 03 07:25:04 PM PDT 24 |
| Peak memory | 573972 kb |
| Host | smart-caf4f764-421c-4488-b775-3ec7d23020a0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049313197 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_access_same_device .4049313197 |
| Directory | /workspace/12.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_access_same_device_slow_rsp.1314710908 |
| Short name | T1788 |
| Test name | |
| Test status | |
| Simulation time | 113792307809 ps |
| CPU time | 1863.65 seconds |
| Started | Jul 03 07:24:11 PM PDT 24 |
| Finished | Jul 03 07:55:16 PM PDT 24 |
| Peak memory | 574252 kb |
| Host | smart-05372618-3d73-4ad1-9e8f-435fabfc94c5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1314710908 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_access_same_ device_slow_rsp.1314710908 |
| Directory | /workspace/12.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_error_and_unmapped_addr.987312223 |
| Short name | T1506 |
| Test name | |
| Test status | |
| Simulation time | 810275578 ps |
| CPU time | 34.32 seconds |
| Started | Jul 03 07:24:22 PM PDT 24 |
| Finished | Jul 03 07:24:59 PM PDT 24 |
| Peak memory | 574464 kb |
| Host | smart-f2de94cb-521b-4392-8949-e8ac36e16afe |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=987312223 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_error_and_unmapped_addr .987312223 |
| Directory | /workspace/12.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_error_random.4220836124 |
| Short name | T2209 |
| Test name | |
| Test status | |
| Simulation time | 89602065 ps |
| CPU time | 6.56 seconds |
| Started | Jul 03 07:24:09 PM PDT 24 |
| Finished | Jul 03 07:24:17 PM PDT 24 |
| Peak memory | 574392 kb |
| Host | smart-13af35d4-dbba-438a-99ed-2538c14e86e2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4220836124 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_error_random.4220836124 |
| Directory | /workspace/12.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_random.1997440954 |
| Short name | T1994 |
| Test name | |
| Test status | |
| Simulation time | 1849475615 ps |
| CPU time | 60.72 seconds |
| Started | Jul 03 07:24:08 PM PDT 24 |
| Finished | Jul 03 07:25:10 PM PDT 24 |
| Peak memory | 574300 kb |
| Host | smart-48316161-6e54-4fe9-aee4-52b7157b7907 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1997440954 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_random.1997440954 |
| Directory | /workspace/12.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_random_large_delays.2746123318 |
| Short name | T543 |
| Test name | |
| Test status | |
| Simulation time | 39984590880 ps |
| CPU time | 433.84 seconds |
| Started | Jul 03 07:24:09 PM PDT 24 |
| Finished | Jul 03 07:31:24 PM PDT 24 |
| Peak memory | 574056 kb |
| Host | smart-2d5c5938-0210-4c4d-8d97-a0b9ce94e660 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746123318 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_random_large_delays.2746123318 |
| Directory | /workspace/12.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_random_slow_rsp.2797236938 |
| Short name | T2835 |
| Test name | |
| Test status | |
| Simulation time | 8565251477 ps |
| CPU time | 153.87 seconds |
| Started | Jul 03 07:24:12 PM PDT 24 |
| Finished | Jul 03 07:26:47 PM PDT 24 |
| Peak memory | 574020 kb |
| Host | smart-bf443a99-f9f7-4248-8626-be5267bba26a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2797236938 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_random_slow_rsp.2797236938 |
| Directory | /workspace/12.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_random_zero_delays.225568358 |
| Short name | T2645 |
| Test name | |
| Test status | |
| Simulation time | 110836564 ps |
| CPU time | 11.82 seconds |
| Started | Jul 03 07:24:09 PM PDT 24 |
| Finished | Jul 03 07:24:22 PM PDT 24 |
| Peak memory | 573956 kb |
| Host | smart-202886f9-0a4d-44c6-b552-f694164709e4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=225568358 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_random_zero_dela ys.225568358 |
| Directory | /workspace/12.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_same_source.3046595818 |
| Short name | T548 |
| Test name | |
| Test status | |
| Simulation time | 269689101 ps |
| CPU time | 24.92 seconds |
| Started | Jul 03 07:24:11 PM PDT 24 |
| Finished | Jul 03 07:24:37 PM PDT 24 |
| Peak memory | 573916 kb |
| Host | smart-a0a1933c-7e19-4842-b2a8-b58079f10528 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3046595818 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_same_source.3046595818 |
| Directory | /workspace/12.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_smoke.1430859246 |
| Short name | T1339 |
| Test name | |
| Test status | |
| Simulation time | 197095297 ps |
| CPU time | 8.84 seconds |
| Started | Jul 03 07:24:04 PM PDT 24 |
| Finished | Jul 03 07:24:13 PM PDT 24 |
| Peak memory | 573016 kb |
| Host | smart-40c934fe-c597-4233-9a18-6c049a147965 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1430859246 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_smoke.1430859246 |
| Directory | /workspace/12.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_smoke_large_delays.701607158 |
| Short name | T2153 |
| Test name | |
| Test status | |
| Simulation time | 5176816875 ps |
| CPU time | 53.91 seconds |
| Started | Jul 03 07:24:08 PM PDT 24 |
| Finished | Jul 03 07:25:02 PM PDT 24 |
| Peak memory | 574340 kb |
| Host | smart-fec0d461-ccd1-4810-bd36-8fb0e41de12d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=701607158 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_large_delays.701607158 |
| Directory | /workspace/12.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_smoke_slow_rsp.1084304069 |
| Short name | T2247 |
| Test name | |
| Test status | |
| Simulation time | 4374635102 ps |
| CPU time | 77.13 seconds |
| Started | Jul 03 07:24:21 PM PDT 24 |
| Finished | Jul 03 07:25:41 PM PDT 24 |
| Peak memory | 573196 kb |
| Host | smart-1e7d331c-8cf2-45b6-af2a-7f09d73f7843 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084304069 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_slow_rsp.1084304069 |
| Directory | /workspace/12.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_smoke_zero_delays.1140673317 |
| Short name | T2705 |
| Test name | |
| Test status | |
| Simulation time | 40852526 ps |
| CPU time | 5.83 seconds |
| Started | Jul 03 07:24:22 PM PDT 24 |
| Finished | Jul 03 07:24:31 PM PDT 24 |
| Peak memory | 573136 kb |
| Host | smart-7dad0867-c0f6-443c-8434-1c8daffd97f7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1140673317 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_zero_delay s.1140673317 |
| Directory | /workspace/12.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_stress_all.4183010850 |
| Short name | T1724 |
| Test name | |
| Test status | |
| Simulation time | 737033322 ps |
| CPU time | 40.11 seconds |
| Started | Jul 03 07:24:16 PM PDT 24 |
| Finished | Jul 03 07:24:58 PM PDT 24 |
| Peak memory | 574260 kb |
| Host | smart-6edc16a2-75ef-4534-adfa-e9562bf7d83e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4183010850 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all.4183010850 |
| Directory | /workspace/12.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_stress_all_with_error.1297621349 |
| Short name | T1482 |
| Test name | |
| Test status | |
| Simulation time | 1475205157 ps |
| CPU time | 51.94 seconds |
| Started | Jul 03 07:24:19 PM PDT 24 |
| Finished | Jul 03 07:25:13 PM PDT 24 |
| Peak memory | 574504 kb |
| Host | smart-6e00f9bc-55f1-413e-9234-48a914e242ee |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1297621349 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_error.1297621349 |
| Directory | /workspace/12.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_stress_all_with_rand_reset.3454433609 |
| Short name | T2635 |
| Test name | |
| Test status | |
| Simulation time | 8084498607 ps |
| CPU time | 515.21 seconds |
| Started | Jul 03 07:24:15 PM PDT 24 |
| Finished | Jul 03 07:32:52 PM PDT 24 |
| Peak memory | 574680 kb |
| Host | smart-9dd49001-9f5a-4285-9986-ce995c853617 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3454433609 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all _with_rand_reset.3454433609 |
| Directory | /workspace/12.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_stress_all_with_reset_error.987457892 |
| Short name | T2149 |
| Test name | |
| Test status | |
| Simulation time | 347804580 ps |
| CPU time | 99.43 seconds |
| Started | Jul 03 07:24:15 PM PDT 24 |
| Finished | Jul 03 07:25:57 PM PDT 24 |
| Peak memory | 574744 kb |
| Host | smart-c415725c-bb25-4855-8211-ed1dfacbe8f1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=987457892 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all _with_reset_error.987457892 |
| Directory | /workspace/12.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_unmapped_addr.1969045106 |
| Short name | T2127 |
| Test name | |
| Test status | |
| Simulation time | 171980784 ps |
| CPU time | 9.12 seconds |
| Started | Jul 03 07:24:12 PM PDT 24 |
| Finished | Jul 03 07:24:22 PM PDT 24 |
| Peak memory | 573168 kb |
| Host | smart-7972ae4b-30f2-440a-bd97-4078ddf9551c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1969045106 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_unmapped_addr.1969045106 |
| Directory | /workspace/12.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/13.chip_csr_rw.635685756 |
| Short name | T2372 |
| Test name | |
| Test status | |
| Simulation time | 4430022887 ps |
| CPU time | 338.81 seconds |
| Started | Jul 03 07:24:29 PM PDT 24 |
| Finished | Jul 03 07:30:09 PM PDT 24 |
| Peak memory | 597960 kb |
| Host | smart-781fe7f9-bdb5-4d87-bb90-2e015515ae5d |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=635685756 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.chip_csr_rw.635685756 |
| Directory | /workspace/13.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/13.chip_same_csr_outstanding.2298356847 |
| Short name | T2655 |
| Test name | |
| Test status | |
| Simulation time | 16268321976 ps |
| CPU time | 2092.28 seconds |
| Started | Jul 03 07:24:16 PM PDT 24 |
| Finished | Jul 03 07:59:10 PM PDT 24 |
| Peak memory | 591864 kb |
| Host | smart-5a4bd97b-6123-45df-9e6a-804046ea3716 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2298356847 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 13.chip_same_csr_outstanding.2298356847 |
| Directory | /workspace/13.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/13.chip_tl_errors.1347272230 |
| Short name | T512 |
| Test name | |
| Test status | |
| Simulation time | 2981633160 ps |
| CPU time | 112.2 seconds |
| Started | Jul 03 07:24:16 PM PDT 24 |
| Finished | Jul 03 07:26:10 PM PDT 24 |
| Peak memory | 599044 kb |
| Host | smart-cd0b3c22-ef31-4cbe-b45f-e191643e8889 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347272230 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.chip_tl_errors.1347272230 |
| Directory | /workspace/13.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_access_same_device.2339232705 |
| Short name | T1603 |
| Test name | |
| Test status | |
| Simulation time | 4063068676 ps |
| CPU time | 154.45 seconds |
| Started | Jul 03 07:24:22 PM PDT 24 |
| Finished | Jul 03 07:26:59 PM PDT 24 |
| Peak memory | 574148 kb |
| Host | smart-87379f05-633c-4283-b3e2-d749c4473ec7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2339232705 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_access_same_device .2339232705 |
| Directory | /workspace/13.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_access_same_device_slow_rsp.3127141227 |
| Short name | T1560 |
| Test name | |
| Test status | |
| Simulation time | 46112138642 ps |
| CPU time | 781.08 seconds |
| Started | Jul 03 07:24:22 PM PDT 24 |
| Finished | Jul 03 07:37:26 PM PDT 24 |
| Peak memory | 574356 kb |
| Host | smart-16983f9d-774d-484f-93e7-5e175dce46c6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3127141227 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_access_same_ device_slow_rsp.3127141227 |
| Directory | /workspace/13.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_error_and_unmapped_addr.36746422 |
| Short name | T1364 |
| Test name | |
| Test status | |
| Simulation time | 276070567 ps |
| CPU time | 26.07 seconds |
| Started | Jul 03 07:24:27 PM PDT 24 |
| Finished | Jul 03 07:24:55 PM PDT 24 |
| Peak memory | 574432 kb |
| Host | smart-2527de7f-bac3-4939-b8c0-6aaa99faf006 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36746422 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_error_and_unmapped_addr.36746422 |
| Directory | /workspace/13.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_error_random.651432509 |
| Short name | T2738 |
| Test name | |
| Test status | |
| Simulation time | 705599011 ps |
| CPU time | 29.57 seconds |
| Started | Jul 03 07:24:22 PM PDT 24 |
| Finished | Jul 03 07:24:55 PM PDT 24 |
| Peak memory | 573972 kb |
| Host | smart-0832776e-218c-4896-a926-2462c974dfc7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=651432509 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_error_random.651432509 |
| Directory | /workspace/13.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_random.981499766 |
| Short name | T2262 |
| Test name | |
| Test status | |
| Simulation time | 726299545 ps |
| CPU time | 26.87 seconds |
| Started | Jul 03 07:24:20 PM PDT 24 |
| Finished | Jul 03 07:24:50 PM PDT 24 |
| Peak memory | 574152 kb |
| Host | smart-c178ea5c-3524-4a51-b261-c5427c53a69c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=981499766 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_random.981499766 |
| Directory | /workspace/13.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_random_large_delays.2321542452 |
| Short name | T570 |
| Test name | |
| Test status | |
| Simulation time | 57087305421 ps |
| CPU time | 601.86 seconds |
| Started | Jul 03 07:24:21 PM PDT 24 |
| Finished | Jul 03 07:34:26 PM PDT 24 |
| Peak memory | 574252 kb |
| Host | smart-99d2ed73-9f81-4f58-8321-49b151b69aa4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2321542452 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_random_large_delays.2321542452 |
| Directory | /workspace/13.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_random_slow_rsp.3323480207 |
| Short name | T1429 |
| Test name | |
| Test status | |
| Simulation time | 58883630092 ps |
| CPU time | 1029.12 seconds |
| Started | Jul 03 07:24:21 PM PDT 24 |
| Finished | Jul 03 07:41:33 PM PDT 24 |
| Peak memory | 574240 kb |
| Host | smart-ccc05e80-77d2-459f-a0d0-ad9d284d06d6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3323480207 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_random_slow_rsp.3323480207 |
| Directory | /workspace/13.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_random_zero_delays.768241877 |
| Short name | T2786 |
| Test name | |
| Test status | |
| Simulation time | 309965472 ps |
| CPU time | 28.15 seconds |
| Started | Jul 03 07:24:20 PM PDT 24 |
| Finished | Jul 03 07:24:52 PM PDT 24 |
| Peak memory | 574184 kb |
| Host | smart-01ae912b-e237-46b1-89ca-230aa5855fa6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768241877 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_random_zero_dela ys.768241877 |
| Directory | /workspace/13.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_same_source.2105544096 |
| Short name | T2388 |
| Test name | |
| Test status | |
| Simulation time | 470155661 ps |
| CPU time | 29.88 seconds |
| Started | Jul 03 07:24:22 PM PDT 24 |
| Finished | Jul 03 07:24:55 PM PDT 24 |
| Peak memory | 574152 kb |
| Host | smart-f89a35be-62ee-4e6c-8af0-8e25918898c2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2105544096 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_same_source.2105544096 |
| Directory | /workspace/13.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_smoke.1850181275 |
| Short name | T1687 |
| Test name | |
| Test status | |
| Simulation time | 225065031 ps |
| CPU time | 9.68 seconds |
| Started | Jul 03 07:24:15 PM PDT 24 |
| Finished | Jul 03 07:24:27 PM PDT 24 |
| Peak memory | 574124 kb |
| Host | smart-e94e8dea-1886-4479-b61e-f380ba0ccdf0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1850181275 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_smoke.1850181275 |
| Directory | /workspace/13.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_smoke_large_delays.805446339 |
| Short name | T2759 |
| Test name | |
| Test status | |
| Simulation time | 7619991108 ps |
| CPU time | 78.84 seconds |
| Started | Jul 03 07:24:16 PM PDT 24 |
| Finished | Jul 03 07:25:37 PM PDT 24 |
| Peak memory | 573024 kb |
| Host | smart-f58e1a5e-3291-4647-bd7f-f17a137cdd8b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=805446339 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_large_delays.805446339 |
| Directory | /workspace/13.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_smoke_slow_rsp.1835537311 |
| Short name | T2695 |
| Test name | |
| Test status | |
| Simulation time | 5453010810 ps |
| CPU time | 93.83 seconds |
| Started | Jul 03 07:24:16 PM PDT 24 |
| Finished | Jul 03 07:25:52 PM PDT 24 |
| Peak memory | 573176 kb |
| Host | smart-1cf39874-b3f9-4f3e-99b3-e3e47e23325e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1835537311 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_slow_rsp.1835537311 |
| Directory | /workspace/13.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_smoke_zero_delays.2085212131 |
| Short name | T1936 |
| Test name | |
| Test status | |
| Simulation time | 49075828 ps |
| CPU time | 6.7 seconds |
| Started | Jul 03 07:24:16 PM PDT 24 |
| Finished | Jul 03 07:24:25 PM PDT 24 |
| Peak memory | 574168 kb |
| Host | smart-20c8e947-9042-4b67-ac7a-c3fa61e47137 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2085212131 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_zero_delay s.2085212131 |
| Directory | /workspace/13.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_stress_all.1462537732 |
| Short name | T2116 |
| Test name | |
| Test status | |
| Simulation time | 5464166559 ps |
| CPU time | 216.33 seconds |
| Started | Jul 03 07:24:21 PM PDT 24 |
| Finished | Jul 03 07:28:00 PM PDT 24 |
| Peak memory | 574692 kb |
| Host | smart-0d2d2629-1c9c-4caa-9b8b-5254f0174d8e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1462537732 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all.1462537732 |
| Directory | /workspace/13.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_stress_all_with_error.1794536579 |
| Short name | T1888 |
| Test name | |
| Test status | |
| Simulation time | 2542589762 ps |
| CPU time | 235.7 seconds |
| Started | Jul 03 07:24:21 PM PDT 24 |
| Finished | Jul 03 07:28:20 PM PDT 24 |
| Peak memory | 574724 kb |
| Host | smart-52c20a09-ca61-4cf9-903f-3eda51b28a00 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1794536579 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_error.1794536579 |
| Directory | /workspace/13.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_stress_all_with_rand_reset.2570828763 |
| Short name | T1683 |
| Test name | |
| Test status | |
| Simulation time | 6662018693 ps |
| CPU time | 362.15 seconds |
| Started | Jul 03 07:24:20 PM PDT 24 |
| Finished | Jul 03 07:30:25 PM PDT 24 |
| Peak memory | 574704 kb |
| Host | smart-697ca39c-3ab9-4723-8ed1-220ddb0ddd2f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2570828763 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all _with_rand_reset.2570828763 |
| Directory | /workspace/13.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_unmapped_addr.3944751901 |
| Short name | T576 |
| Test name | |
| Test status | |
| Simulation time | 318216077 ps |
| CPU time | 36.51 seconds |
| Started | Jul 03 07:24:19 PM PDT 24 |
| Finished | Jul 03 07:24:58 PM PDT 24 |
| Peak memory | 574008 kb |
| Host | smart-f66d3375-ff93-486a-8a69-76f8f68efbe4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3944751901 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_unmapped_addr.3944751901 |
| Directory | /workspace/13.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/14.chip_csr_rw.3404024472 |
| Short name | T382 |
| Test name | |
| Test status | |
| Simulation time | 6366833380 ps |
| CPU time | 631.51 seconds |
| Started | Jul 03 07:24:39 PM PDT 24 |
| Finished | Jul 03 07:35:11 PM PDT 24 |
| Peak memory | 598324 kb |
| Host | smart-01390fac-3520-449e-987e-ed94c2f66df1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3404024472 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.chip_csr_rw.3404024472 |
| Directory | /workspace/14.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/14.chip_same_csr_outstanding.2770795945 |
| Short name | T366 |
| Test name | |
| Test status | |
| Simulation time | 14678593481 ps |
| CPU time | 2100.68 seconds |
| Started | Jul 03 07:24:27 PM PDT 24 |
| Finished | Jul 03 07:59:29 PM PDT 24 |
| Peak memory | 591960 kb |
| Host | smart-1ed69951-a265-4784-ad7b-dd39e2e0fedb |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2770795945 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 14.chip_same_csr_outstanding.2770795945 |
| Directory | /workspace/14.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/14.chip_tl_errors.1327228944 |
| Short name | T516 |
| Test name | |
| Test status | |
| Simulation time | 3655886272 ps |
| CPU time | 207.29 seconds |
| Started | Jul 03 07:24:29 PM PDT 24 |
| Finished | Jul 03 07:27:57 PM PDT 24 |
| Peak memory | 597936 kb |
| Host | smart-061c098c-07e2-4cff-a7f8-9280e3ae1a97 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1327228944 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.chip_tl_errors.1327228944 |
| Directory | /workspace/14.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_access_same_device.582047246 |
| Short name | T2756 |
| Test name | |
| Test status | |
| Simulation time | 149094259 ps |
| CPU time | 11.85 seconds |
| Started | Jul 03 07:24:32 PM PDT 24 |
| Finished | Jul 03 07:24:46 PM PDT 24 |
| Peak memory | 574160 kb |
| Host | smart-7040d945-e6cd-41b4-833c-da3b64e7ba9a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582047246 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_access_same_device. 582047246 |
| Directory | /workspace/14.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_access_same_device_slow_rsp.1393784954 |
| Short name | T2223 |
| Test name | |
| Test status | |
| Simulation time | 34502127572 ps |
| CPU time | 573.23 seconds |
| Started | Jul 03 07:24:31 PM PDT 24 |
| Finished | Jul 03 07:34:06 PM PDT 24 |
| Peak memory | 573988 kb |
| Host | smart-e0cd0bcb-c3e7-4179-b9fd-399e12b5d09a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1393784954 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_access_same_ device_slow_rsp.1393784954 |
| Directory | /workspace/14.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_error_and_unmapped_addr.3990062127 |
| Short name | T2728 |
| Test name | |
| Test status | |
| Simulation time | 292576449 ps |
| CPU time | 14.11 seconds |
| Started | Jul 03 07:24:35 PM PDT 24 |
| Finished | Jul 03 07:24:51 PM PDT 24 |
| Peak memory | 574016 kb |
| Host | smart-3bf04456-3c4f-4823-bb42-4460642490d4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3990062127 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_error_and_unmapped_add r.3990062127 |
| Directory | /workspace/14.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_error_random.2026574891 |
| Short name | T2225 |
| Test name | |
| Test status | |
| Simulation time | 178737273 ps |
| CPU time | 16.78 seconds |
| Started | Jul 03 07:24:30 PM PDT 24 |
| Finished | Jul 03 07:24:49 PM PDT 24 |
| Peak memory | 574468 kb |
| Host | smart-07cc4785-1805-44a7-86e2-f5abc044e150 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2026574891 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_error_random.2026574891 |
| Directory | /workspace/14.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_random.701576762 |
| Short name | T2543 |
| Test name | |
| Test status | |
| Simulation time | 2102497366 ps |
| CPU time | 80.25 seconds |
| Started | Jul 03 07:24:25 PM PDT 24 |
| Finished | Jul 03 07:25:47 PM PDT 24 |
| Peak memory | 574008 kb |
| Host | smart-acd77d39-0163-47be-b723-e97594bf82d9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=701576762 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_random.701576762 |
| Directory | /workspace/14.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_random_large_delays.1139764678 |
| Short name | T1505 |
| Test name | |
| Test status | |
| Simulation time | 45720926782 ps |
| CPU time | 530 seconds |
| Started | Jul 03 07:24:33 PM PDT 24 |
| Finished | Jul 03 07:33:25 PM PDT 24 |
| Peak memory | 574020 kb |
| Host | smart-6899524e-228a-474e-a972-b5789888c54b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1139764678 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_random_large_delays.1139764678 |
| Directory | /workspace/14.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_random_slow_rsp.3970765437 |
| Short name | T489 |
| Test name | |
| Test status | |
| Simulation time | 20933363713 ps |
| CPU time | 365.75 seconds |
| Started | Jul 03 07:24:31 PM PDT 24 |
| Finished | Jul 03 07:30:39 PM PDT 24 |
| Peak memory | 574248 kb |
| Host | smart-1d330b80-c89d-4b00-9fde-484a00dca3ad |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3970765437 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_random_slow_rsp.3970765437 |
| Directory | /workspace/14.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_random_zero_delays.2701425756 |
| Short name | T522 |
| Test name | |
| Test status | |
| Simulation time | 185852409 ps |
| CPU time | 16.38 seconds |
| Started | Jul 03 07:24:30 PM PDT 24 |
| Finished | Jul 03 07:24:48 PM PDT 24 |
| Peak memory | 574244 kb |
| Host | smart-617030a6-82ce-49b7-b5a4-cadc3b47301e |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2701425756 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_random_zero_del ays.2701425756 |
| Directory | /workspace/14.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_same_source.3471055052 |
| Short name | T2546 |
| Test name | |
| Test status | |
| Simulation time | 1529119370 ps |
| CPU time | 46.04 seconds |
| Started | Jul 03 07:24:31 PM PDT 24 |
| Finished | Jul 03 07:25:19 PM PDT 24 |
| Peak memory | 574104 kb |
| Host | smart-8e3f0f6f-0941-4dc1-8787-582b04eff863 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3471055052 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_same_source.3471055052 |
| Directory | /workspace/14.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_smoke.1045796734 |
| Short name | T2139 |
| Test name | |
| Test status | |
| Simulation time | 181711449 ps |
| CPU time | 8.42 seconds |
| Started | Jul 03 07:24:31 PM PDT 24 |
| Finished | Jul 03 07:24:42 PM PDT 24 |
| Peak memory | 572828 kb |
| Host | smart-9372e094-c30a-43ec-bba1-9c269a8f2d10 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1045796734 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_smoke.1045796734 |
| Directory | /workspace/14.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_smoke_large_delays.931270883 |
| Short name | T1876 |
| Test name | |
| Test status | |
| Simulation time | 7573257884 ps |
| CPU time | 78.71 seconds |
| Started | Jul 03 07:24:29 PM PDT 24 |
| Finished | Jul 03 07:25:48 PM PDT 24 |
| Peak memory | 574260 kb |
| Host | smart-d5a91f9a-32ae-4d05-8d56-e92e184de971 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=931270883 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_large_delays.931270883 |
| Directory | /workspace/14.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_smoke_slow_rsp.4111985522 |
| Short name | T1410 |
| Test name | |
| Test status | |
| Simulation time | 5066710790 ps |
| CPU time | 82.7 seconds |
| Started | Jul 03 07:24:31 PM PDT 24 |
| Finished | Jul 03 07:25:55 PM PDT 24 |
| Peak memory | 572964 kb |
| Host | smart-86173161-c0d2-48b5-a198-9bf6194e7fcf |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4111985522 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_slow_rsp.4111985522 |
| Directory | /workspace/14.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_smoke_zero_delays.3624461863 |
| Short name | T2817 |
| Test name | |
| Test status | |
| Simulation time | 51202150 ps |
| CPU time | 6.55 seconds |
| Started | Jul 03 07:24:31 PM PDT 24 |
| Finished | Jul 03 07:24:40 PM PDT 24 |
| Peak memory | 573840 kb |
| Host | smart-98f314a8-9d9b-4f1e-b592-0d55ef7afe34 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3624461863 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_zero_delay s.3624461863 |
| Directory | /workspace/14.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_stress_all.3386086218 |
| Short name | T582 |
| Test name | |
| Test status | |
| Simulation time | 1727883382 ps |
| CPU time | 156.58 seconds |
| Started | Jul 03 07:24:46 PM PDT 24 |
| Finished | Jul 03 07:27:24 PM PDT 24 |
| Peak memory | 574668 kb |
| Host | smart-ad8f8155-cd6e-4353-ae3c-c1edad160936 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3386086218 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all.3386086218 |
| Directory | /workspace/14.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_stress_all_with_error.838756818 |
| Short name | T2776 |
| Test name | |
| Test status | |
| Simulation time | 2416135401 ps |
| CPU time | 204.59 seconds |
| Started | Jul 03 07:24:35 PM PDT 24 |
| Finished | Jul 03 07:28:01 PM PDT 24 |
| Peak memory | 574708 kb |
| Host | smart-b6e0ef70-f52a-4413-9c05-03fbdc91891c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=838756818 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_error.838756818 |
| Directory | /workspace/14.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_stress_all_with_reset_error.1435828512 |
| Short name | T794 |
| Test name | |
| Test status | |
| Simulation time | 45441260 ps |
| CPU time | 21.04 seconds |
| Started | Jul 03 07:24:36 PM PDT 24 |
| Finished | Jul 03 07:24:58 PM PDT 24 |
| Peak memory | 574628 kb |
| Host | smart-43c8bfd9-e6d0-439a-86a5-9a3f68177754 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435828512 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_stress_al l_with_reset_error.1435828512 |
| Directory | /workspace/14.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_unmapped_addr.3617976085 |
| Short name | T1925 |
| Test name | |
| Test status | |
| Simulation time | 1107209996 ps |
| CPU time | 45.47 seconds |
| Started | Jul 03 07:24:46 PM PDT 24 |
| Finished | Jul 03 07:25:33 PM PDT 24 |
| Peak memory | 574080 kb |
| Host | smart-aee015f4-4599-408c-8af6-469a124b1231 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3617976085 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_unmapped_addr.3617976085 |
| Directory | /workspace/14.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/15.chip_same_csr_outstanding.2143583621 |
| Short name | T2111 |
| Test name | |
| Test status | |
| Simulation time | 31277837188 ps |
| CPU time | 4551.79 seconds |
| Started | Jul 03 07:24:37 PM PDT 24 |
| Finished | Jul 03 08:40:30 PM PDT 24 |
| Peak memory | 592152 kb |
| Host | smart-7abffa1b-5407-426d-b0be-2dea543159c5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2143583621 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 15.chip_same_csr_outstanding.2143583621 |
| Directory | /workspace/15.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/15.chip_tl_errors.3125599070 |
| Short name | T569 |
| Test name | |
| Test status | |
| Simulation time | 3396552800 ps |
| CPU time | 182.77 seconds |
| Started | Jul 03 07:24:45 PM PDT 24 |
| Finished | Jul 03 07:27:49 PM PDT 24 |
| Peak memory | 599084 kb |
| Host | smart-2580964f-fcb7-4d10-8b94-9444596e4796 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125599070 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.chip_tl_errors.3125599070 |
| Directory | /workspace/15.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_access_same_device.1027546388 |
| Short name | T2233 |
| Test name | |
| Test status | |
| Simulation time | 989324423 ps |
| CPU time | 41.22 seconds |
| Started | Jul 03 07:24:46 PM PDT 24 |
| Finished | Jul 03 07:25:29 PM PDT 24 |
| Peak memory | 574124 kb |
| Host | smart-6c975d62-ee21-45dc-abc1-451291f49b32 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1027546388 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_access_same_device .1027546388 |
| Directory | /workspace/15.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_access_same_device_slow_rsp.679327848 |
| Short name | T2879 |
| Test name | |
| Test status | |
| Simulation time | 115385502970 ps |
| CPU time | 2090.95 seconds |
| Started | Jul 03 07:24:46 PM PDT 24 |
| Finished | Jul 03 07:59:39 PM PDT 24 |
| Peak memory | 574224 kb |
| Host | smart-714d2c99-db8e-4838-b10f-f2ecd81795bc |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=679327848 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_access_same_d evice_slow_rsp.679327848 |
| Directory | /workspace/15.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_error_and_unmapped_addr.4252799216 |
| Short name | T1376 |
| Test name | |
| Test status | |
| Simulation time | 1109992577 ps |
| CPU time | 50.04 seconds |
| Started | Jul 03 07:24:50 PM PDT 24 |
| Finished | Jul 03 07:25:40 PM PDT 24 |
| Peak memory | 573992 kb |
| Host | smart-f44843cd-0dff-4ff7-bf05-64d0b4965ba2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4252799216 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_error_and_unmapped_add r.4252799216 |
| Directory | /workspace/15.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_error_random.1422125105 |
| Short name | T1341 |
| Test name | |
| Test status | |
| Simulation time | 51557280 ps |
| CPU time | 7.94 seconds |
| Started | Jul 03 07:24:50 PM PDT 24 |
| Finished | Jul 03 07:24:59 PM PDT 24 |
| Peak memory | 574072 kb |
| Host | smart-d88e29a6-0e45-499a-9c03-8701071c797a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1422125105 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_error_random.1422125105 |
| Directory | /workspace/15.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_random.4155538085 |
| Short name | T1757 |
| Test name | |
| Test status | |
| Simulation time | 771218908 ps |
| CPU time | 29.77 seconds |
| Started | Jul 03 07:24:44 PM PDT 24 |
| Finished | Jul 03 07:25:15 PM PDT 24 |
| Peak memory | 574152 kb |
| Host | smart-70cc4ace-011d-43b9-a3a2-c9f9b99b647d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4155538085 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_random.4155538085 |
| Directory | /workspace/15.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_random_large_delays.2570389534 |
| Short name | T2343 |
| Test name | |
| Test status | |
| Simulation time | 105701560906 ps |
| CPU time | 1193.56 seconds |
| Started | Jul 03 07:24:41 PM PDT 24 |
| Finished | Jul 03 07:44:35 PM PDT 24 |
| Peak memory | 574224 kb |
| Host | smart-a4d0d0b4-96cd-468a-b7d5-46ab8b5b6094 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2570389534 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_random_large_delays.2570389534 |
| Directory | /workspace/15.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_random_slow_rsp.1176104968 |
| Short name | T2544 |
| Test name | |
| Test status | |
| Simulation time | 56487569166 ps |
| CPU time | 1019.03 seconds |
| Started | Jul 03 07:24:45 PM PDT 24 |
| Finished | Jul 03 07:41:45 PM PDT 24 |
| Peak memory | 574404 kb |
| Host | smart-9f8c4579-f254-412d-ae53-ab271d57db12 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176104968 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_random_slow_rsp.1176104968 |
| Directory | /workspace/15.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_random_zero_delays.3957091650 |
| Short name | T2364 |
| Test name | |
| Test status | |
| Simulation time | 324229215 ps |
| CPU time | 30.9 seconds |
| Started | Jul 03 07:24:43 PM PDT 24 |
| Finished | Jul 03 07:25:15 PM PDT 24 |
| Peak memory | 574200 kb |
| Host | smart-12cf7800-3328-43d9-b7a9-4beebb87f5fd |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3957091650 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_random_zero_del ays.3957091650 |
| Directory | /workspace/15.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_same_source.2684731763 |
| Short name | T1952 |
| Test name | |
| Test status | |
| Simulation time | 1574224996 ps |
| CPU time | 48.59 seconds |
| Started | Jul 03 07:24:48 PM PDT 24 |
| Finished | Jul 03 07:25:38 PM PDT 24 |
| Peak memory | 574148 kb |
| Host | smart-3d2a3c0f-d57d-495c-81e9-6f0c8259b9ed |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2684731763 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_same_source.2684731763 |
| Directory | /workspace/15.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_smoke.2390086420 |
| Short name | T2192 |
| Test name | |
| Test status | |
| Simulation time | 53232679 ps |
| CPU time | 6.93 seconds |
| Started | Jul 03 07:24:45 PM PDT 24 |
| Finished | Jul 03 07:24:53 PM PDT 24 |
| Peak memory | 573140 kb |
| Host | smart-f76a73b4-b2e1-4a99-af28-f6d8a519bf32 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2390086420 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_smoke.2390086420 |
| Directory | /workspace/15.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_smoke_large_delays.501426170 |
| Short name | T1478 |
| Test name | |
| Test status | |
| Simulation time | 7027338249 ps |
| CPU time | 74.28 seconds |
| Started | Jul 03 07:24:45 PM PDT 24 |
| Finished | Jul 03 07:26:01 PM PDT 24 |
| Peak memory | 573212 kb |
| Host | smart-c2b29602-9855-4b04-86ef-cd4d92d6dc42 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=501426170 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_large_delays.501426170 |
| Directory | /workspace/15.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_smoke_slow_rsp.1719130974 |
| Short name | T1323 |
| Test name | |
| Test status | |
| Simulation time | 5409264731 ps |
| CPU time | 96.75 seconds |
| Started | Jul 03 07:24:42 PM PDT 24 |
| Finished | Jul 03 07:26:20 PM PDT 24 |
| Peak memory | 573332 kb |
| Host | smart-3ad4e31c-934e-4a59-a55d-0f195695866a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1719130974 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_slow_rsp.1719130974 |
| Directory | /workspace/15.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_smoke_zero_delays.3283437278 |
| Short name | T1413 |
| Test name | |
| Test status | |
| Simulation time | 50879637 ps |
| CPU time | 5.92 seconds |
| Started | Jul 03 07:24:44 PM PDT 24 |
| Finished | Jul 03 07:24:51 PM PDT 24 |
| Peak memory | 572940 kb |
| Host | smart-e1c84b58-568e-4e69-b1bb-afb00a58a47d |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3283437278 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_zero_delay s.3283437278 |
| Directory | /workspace/15.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_stress_all.2739029625 |
| Short name | T465 |
| Test name | |
| Test status | |
| Simulation time | 17673393962 ps |
| CPU time | 703.45 seconds |
| Started | Jul 03 07:24:52 PM PDT 24 |
| Finished | Jul 03 07:36:37 PM PDT 24 |
| Peak memory | 574696 kb |
| Host | smart-4b1336e5-33f3-48b9-9690-d495b6086b5e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2739029625 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all.2739029625 |
| Directory | /workspace/15.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_stress_all_with_error.1255109071 |
| Short name | T2883 |
| Test name | |
| Test status | |
| Simulation time | 8785215274 ps |
| CPU time | 260.27 seconds |
| Started | Jul 03 07:24:54 PM PDT 24 |
| Finished | Jul 03 07:29:14 PM PDT 24 |
| Peak memory | 574516 kb |
| Host | smart-c0ff7fdb-55d6-4f96-9162-e2d225fe3f29 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1255109071 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_error.1255109071 |
| Directory | /workspace/15.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_stress_all_with_rand_reset.3779484126 |
| Short name | T2158 |
| Test name | |
| Test status | |
| Simulation time | 6227802139 ps |
| CPU time | 483.75 seconds |
| Started | Jul 03 07:24:51 PM PDT 24 |
| Finished | Jul 03 07:32:56 PM PDT 24 |
| Peak memory | 574740 kb |
| Host | smart-aa362963-2dd7-4a6a-8a70-f090b135cf32 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3779484126 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all _with_rand_reset.3779484126 |
| Directory | /workspace/15.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_stress_all_with_reset_error.3090983339 |
| Short name | T1607 |
| Test name | |
| Test status | |
| Simulation time | 3506963298 ps |
| CPU time | 336.83 seconds |
| Started | Jul 03 07:24:57 PM PDT 24 |
| Finished | Jul 03 07:30:36 PM PDT 24 |
| Peak memory | 574732 kb |
| Host | smart-f3ed120e-375f-4f0c-abbe-5f35f8aed6b9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3090983339 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_stress_al l_with_reset_error.3090983339 |
| Directory | /workspace/15.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_unmapped_addr.3765806408 |
| Short name | T428 |
| Test name | |
| Test status | |
| Simulation time | 106167150 ps |
| CPU time | 14.21 seconds |
| Started | Jul 03 07:24:51 PM PDT 24 |
| Finished | Jul 03 07:25:06 PM PDT 24 |
| Peak memory | 574252 kb |
| Host | smart-b8de81e1-3997-451f-97cc-3b31cb022024 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3765806408 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_unmapped_addr.3765806408 |
| Directory | /workspace/15.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/16.chip_csr_rw.275159692 |
| Short name | T2715 |
| Test name | |
| Test status | |
| Simulation time | 4893810393 ps |
| CPU time | 498.44 seconds |
| Started | Jul 03 07:25:09 PM PDT 24 |
| Finished | Jul 03 07:33:28 PM PDT 24 |
| Peak memory | 597936 kb |
| Host | smart-137c8143-f926-426f-b281-6e87f96cdc96 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=275159692 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.chip_csr_rw.275159692 |
| Directory | /workspace/16.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/16.chip_tl_errors.4293861023 |
| Short name | T647 |
| Test name | |
| Test status | |
| Simulation time | 3284133604 ps |
| CPU time | 234.27 seconds |
| Started | Jul 03 07:24:55 PM PDT 24 |
| Finished | Jul 03 07:28:50 PM PDT 24 |
| Peak memory | 603128 kb |
| Host | smart-1e6d60bf-3043-4d81-a14f-1f2570cfc68c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4293861023 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.chip_tl_errors.4293861023 |
| Directory | /workspace/16.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_access_same_device.1385966320 |
| Short name | T2217 |
| Test name | |
| Test status | |
| Simulation time | 928811843 ps |
| CPU time | 74.47 seconds |
| Started | Jul 03 07:24:59 PM PDT 24 |
| Finished | Jul 03 07:26:15 PM PDT 24 |
| Peak memory | 574284 kb |
| Host | smart-a0cd70c1-4754-4510-acc4-9bd45a3173da |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385966320 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_access_same_device .1385966320 |
| Directory | /workspace/16.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_access_same_device_slow_rsp.3292423238 |
| Short name | T1721 |
| Test name | |
| Test status | |
| Simulation time | 42321005229 ps |
| CPU time | 751.03 seconds |
| Started | Jul 03 07:25:05 PM PDT 24 |
| Finished | Jul 03 07:37:38 PM PDT 24 |
| Peak memory | 574336 kb |
| Host | smart-ae173566-83bf-4432-bbee-36d9e70133aa |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292423238 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_access_same_ device_slow_rsp.3292423238 |
| Directory | /workspace/16.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_error_and_unmapped_addr.738879364 |
| Short name | T1962 |
| Test name | |
| Test status | |
| Simulation time | 130379862 ps |
| CPU time | 17.41 seconds |
| Started | Jul 03 07:25:01 PM PDT 24 |
| Finished | Jul 03 07:25:20 PM PDT 24 |
| Peak memory | 574108 kb |
| Host | smart-3c4e4dd7-3a87-4638-9cb2-69c0e0e32cea |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=738879364 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_error_and_unmapped_addr .738879364 |
| Directory | /workspace/16.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_error_random.1031034716 |
| Short name | T1318 |
| Test name | |
| Test status | |
| Simulation time | 824082239 ps |
| CPU time | 27.53 seconds |
| Started | Jul 03 07:25:06 PM PDT 24 |
| Finished | Jul 03 07:25:35 PM PDT 24 |
| Peak memory | 574084 kb |
| Host | smart-4836828f-c73e-4698-b11b-1cce300d941b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031034716 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_error_random.1031034716 |
| Directory | /workspace/16.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_random.597186199 |
| Short name | T2689 |
| Test name | |
| Test status | |
| Simulation time | 120345748 ps |
| CPU time | 14.66 seconds |
| Started | Jul 03 07:25:00 PM PDT 24 |
| Finished | Jul 03 07:25:16 PM PDT 24 |
| Peak memory | 574172 kb |
| Host | smart-f166ddf6-6a61-481f-be87-0698ca53f0f3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=597186199 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_random.597186199 |
| Directory | /workspace/16.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_random_large_delays.2643137508 |
| Short name | T517 |
| Test name | |
| Test status | |
| Simulation time | 106809756315 ps |
| CPU time | 1110.71 seconds |
| Started | Jul 03 07:25:05 PM PDT 24 |
| Finished | Jul 03 07:43:38 PM PDT 24 |
| Peak memory | 574080 kb |
| Host | smart-b6f54a71-c218-4ecf-9a79-0b29b016db61 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2643137508 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_random_large_delays.2643137508 |
| Directory | /workspace/16.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_random_slow_rsp.706838941 |
| Short name | T1938 |
| Test name | |
| Test status | |
| Simulation time | 63651446939 ps |
| CPU time | 1100.16 seconds |
| Started | Jul 03 07:25:02 PM PDT 24 |
| Finished | Jul 03 07:43:23 PM PDT 24 |
| Peak memory | 574060 kb |
| Host | smart-bea7d9fd-f95c-4049-bca1-78187c968b05 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=706838941 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_random_slow_rsp.706838941 |
| Directory | /workspace/16.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_random_zero_delays.3602662556 |
| Short name | T2706 |
| Test name | |
| Test status | |
| Simulation time | 587615973 ps |
| CPU time | 52.97 seconds |
| Started | Jul 03 07:24:58 PM PDT 24 |
| Finished | Jul 03 07:25:53 PM PDT 24 |
| Peak memory | 573956 kb |
| Host | smart-1aa1464a-bd66-49d8-a6c2-a1dace29c587 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602662556 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_random_zero_del ays.3602662556 |
| Directory | /workspace/16.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_same_source.952139811 |
| Short name | T1646 |
| Test name | |
| Test status | |
| Simulation time | 560480430 ps |
| CPU time | 21.15 seconds |
| Started | Jul 03 07:25:03 PM PDT 24 |
| Finished | Jul 03 07:25:25 PM PDT 24 |
| Peak memory | 573936 kb |
| Host | smart-4632a1d3-c43e-4255-8b15-9a26f0ac2998 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=952139811 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_same_source.952139811 |
| Directory | /workspace/16.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_smoke.2882043866 |
| Short name | T1398 |
| Test name | |
| Test status | |
| Simulation time | 47737766 ps |
| CPU time | 6.95 seconds |
| Started | Jul 03 07:24:55 PM PDT 24 |
| Finished | Jul 03 07:25:03 PM PDT 24 |
| Peak memory | 574140 kb |
| Host | smart-22e84473-fd18-4e08-a2d1-a6a3eabb5620 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2882043866 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_smoke.2882043866 |
| Directory | /workspace/16.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_smoke_large_delays.1535112552 |
| Short name | T1379 |
| Test name | |
| Test status | |
| Simulation time | 9933459331 ps |
| CPU time | 102.18 seconds |
| Started | Jul 03 07:24:55 PM PDT 24 |
| Finished | Jul 03 07:26:38 PM PDT 24 |
| Peak memory | 573176 kb |
| Host | smart-9969eb86-6b8e-492f-89b7-8ba3074a9f4c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1535112552 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_large_delays.1535112552 |
| Directory | /workspace/16.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_smoke_slow_rsp.195881130 |
| Short name | T2476 |
| Test name | |
| Test status | |
| Simulation time | 4566692383 ps |
| CPU time | 79.64 seconds |
| Started | Jul 03 07:24:58 PM PDT 24 |
| Finished | Jul 03 07:26:19 PM PDT 24 |
| Peak memory | 573004 kb |
| Host | smart-936a0128-eff2-4cd3-af5a-cc52b893e76b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=195881130 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_slow_rsp.195881130 |
| Directory | /workspace/16.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_smoke_zero_delays.2032841110 |
| Short name | T2168 |
| Test name | |
| Test status | |
| Simulation time | 45965626 ps |
| CPU time | 6.4 seconds |
| Started | Jul 03 07:24:57 PM PDT 24 |
| Finished | Jul 03 07:25:05 PM PDT 24 |
| Peak memory | 572864 kb |
| Host | smart-322c74ac-1661-4ae5-96f5-10fc608c6f1c |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2032841110 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_zero_delay s.2032841110 |
| Directory | /workspace/16.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_stress_all.644366572 |
| Short name | T448 |
| Test name | |
| Test status | |
| Simulation time | 14282743363 ps |
| CPU time | 515.25 seconds |
| Started | Jul 03 07:25:04 PM PDT 24 |
| Finished | Jul 03 07:33:40 PM PDT 24 |
| Peak memory | 574664 kb |
| Host | smart-af9709e2-31ad-4bbd-bebb-25b762c38b16 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=644366572 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all.644366572 |
| Directory | /workspace/16.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_stress_all_with_error.1826051615 |
| Short name | T2137 |
| Test name | |
| Test status | |
| Simulation time | 2526204079 ps |
| CPU time | 101.19 seconds |
| Started | Jul 03 07:24:59 PM PDT 24 |
| Finished | Jul 03 07:26:41 PM PDT 24 |
| Peak memory | 574604 kb |
| Host | smart-a8eb32ab-43fb-49dc-a829-319dbb975037 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1826051615 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_error.1826051615 |
| Directory | /workspace/16.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_stress_all_with_rand_reset.2192222802 |
| Short name | T481 |
| Test name | |
| Test status | |
| Simulation time | 200681652 ps |
| CPU time | 60.63 seconds |
| Started | Jul 03 07:25:02 PM PDT 24 |
| Finished | Jul 03 07:26:04 PM PDT 24 |
| Peak memory | 574652 kb |
| Host | smart-f54e2b2b-6d9e-439a-9554-93151f8509f6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2192222802 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all _with_rand_reset.2192222802 |
| Directory | /workspace/16.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_stress_all_with_reset_error.1516701484 |
| Short name | T819 |
| Test name | |
| Test status | |
| Simulation time | 138873285 ps |
| CPU time | 60.69 seconds |
| Started | Jul 03 07:25:01 PM PDT 24 |
| Finished | Jul 03 07:26:03 PM PDT 24 |
| Peak memory | 574612 kb |
| Host | smart-db439701-634b-4956-8480-9b941f488efe |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1516701484 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_stress_al l_with_reset_error.1516701484 |
| Directory | /workspace/16.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_unmapped_addr.3700489693 |
| Short name | T2457 |
| Test name | |
| Test status | |
| Simulation time | 748020862 ps |
| CPU time | 33.83 seconds |
| Started | Jul 03 07:24:59 PM PDT 24 |
| Finished | Jul 03 07:25:34 PM PDT 24 |
| Peak memory | 574280 kb |
| Host | smart-64237d21-08b2-4a97-957f-805b663abc22 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3700489693 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_unmapped_addr.3700489693 |
| Directory | /workspace/16.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/17.chip_csr_rw.3699261770 |
| Short name | T2128 |
| Test name | |
| Test status | |
| Simulation time | 5789685808 ps |
| CPU time | 588.08 seconds |
| Started | Jul 03 07:25:15 PM PDT 24 |
| Finished | Jul 03 07:35:06 PM PDT 24 |
| Peak memory | 597948 kb |
| Host | smart-03edfeb7-4be4-4cff-a5a7-70d583414d12 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699261770 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.chip_csr_rw.3699261770 |
| Directory | /workspace/17.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/17.chip_same_csr_outstanding.1140014506 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 15783354736 ps |
| CPU time | 2286.85 seconds |
| Started | Jul 03 07:25:09 PM PDT 24 |
| Finished | Jul 03 08:03:17 PM PDT 24 |
| Peak memory | 591052 kb |
| Host | smart-12f9936b-baab-482f-9d67-4beaf02466bc |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1140014506 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 17.chip_same_csr_outstanding.1140014506 |
| Directory | /workspace/17.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/17.chip_tl_errors.708777456 |
| Short name | T646 |
| Test name | |
| Test status | |
| Simulation time | 3968492920 ps |
| CPU time | 197.98 seconds |
| Started | Jul 03 07:25:07 PM PDT 24 |
| Finished | Jul 03 07:28:26 PM PDT 24 |
| Peak memory | 603128 kb |
| Host | smart-ebbd4f2e-0cc7-4ff1-b3ed-e07e22d09425 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=708777456 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.chip_tl_errors.708777456 |
| Directory | /workspace/17.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_access_same_device.3760762997 |
| Short name | T2108 |
| Test name | |
| Test status | |
| Simulation time | 902269933 ps |
| CPU time | 74.94 seconds |
| Started | Jul 03 07:25:14 PM PDT 24 |
| Finished | Jul 03 07:26:31 PM PDT 24 |
| Peak memory | 574216 kb |
| Host | smart-b2fbd3ee-badb-4f4c-88f3-fee14b841e95 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3760762997 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_access_same_device .3760762997 |
| Directory | /workspace/17.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_access_same_device_slow_rsp.1068274361 |
| Short name | T470 |
| Test name | |
| Test status | |
| Simulation time | 88179158456 ps |
| CPU time | 1532.72 seconds |
| Started | Jul 03 07:25:13 PM PDT 24 |
| Finished | Jul 03 07:50:47 PM PDT 24 |
| Peak memory | 574092 kb |
| Host | smart-cf6dd245-17dd-4619-b0f7-dbafe594ebe0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1068274361 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_access_same_ device_slow_rsp.1068274361 |
| Directory | /workspace/17.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_error_and_unmapped_addr.3805049259 |
| Short name | T2282 |
| Test name | |
| Test status | |
| Simulation time | 1257261907 ps |
| CPU time | 44.4 seconds |
| Started | Jul 03 07:25:11 PM PDT 24 |
| Finished | Jul 03 07:25:56 PM PDT 24 |
| Peak memory | 574028 kb |
| Host | smart-8c24be63-d541-4dd2-b83f-f01dc7885d02 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3805049259 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_error_and_unmapped_add r.3805049259 |
| Directory | /workspace/17.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_error_random.1987308225 |
| Short name | T2790 |
| Test name | |
| Test status | |
| Simulation time | 841248796 ps |
| CPU time | 29.47 seconds |
| Started | Jul 03 07:25:11 PM PDT 24 |
| Finished | Jul 03 07:25:41 PM PDT 24 |
| Peak memory | 574064 kb |
| Host | smart-f5532629-2c5c-4109-a5c6-51f8414bf665 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1987308225 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_error_random.1987308225 |
| Directory | /workspace/17.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_random.498271106 |
| Short name | T2393 |
| Test name | |
| Test status | |
| Simulation time | 1693203446 ps |
| CPU time | 55.81 seconds |
| Started | Jul 03 07:25:04 PM PDT 24 |
| Finished | Jul 03 07:26:01 PM PDT 24 |
| Peak memory | 573920 kb |
| Host | smart-b23f2082-714f-4f32-9e1a-3fd23587df44 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=498271106 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_random.498271106 |
| Directory | /workspace/17.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_random_large_delays.2248380605 |
| Short name | T2170 |
| Test name | |
| Test status | |
| Simulation time | 66578348711 ps |
| CPU time | 719.17 seconds |
| Started | Jul 03 07:25:13 PM PDT 24 |
| Finished | Jul 03 07:37:13 PM PDT 24 |
| Peak memory | 574276 kb |
| Host | smart-c719e383-de96-4681-b286-08c2dd6d397c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248380605 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_random_large_delays.2248380605 |
| Directory | /workspace/17.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_random_slow_rsp.2446601744 |
| Short name | T2632 |
| Test name | |
| Test status | |
| Simulation time | 38386539295 ps |
| CPU time | 679.39 seconds |
| Started | Jul 03 07:25:15 PM PDT 24 |
| Finished | Jul 03 07:36:36 PM PDT 24 |
| Peak memory | 574256 kb |
| Host | smart-5c857d20-f0af-4352-b506-886046598ab0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2446601744 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_random_slow_rsp.2446601744 |
| Directory | /workspace/17.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_random_zero_delays.3563849877 |
| Short name | T2134 |
| Test name | |
| Test status | |
| Simulation time | 98734709 ps |
| CPU time | 12.73 seconds |
| Started | Jul 03 07:25:06 PM PDT 24 |
| Finished | Jul 03 07:25:20 PM PDT 24 |
| Peak memory | 574220 kb |
| Host | smart-c955053a-f3ba-40cf-8cae-31aa10e4c290 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3563849877 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_random_zero_del ays.3563849877 |
| Directory | /workspace/17.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_same_source.3166390804 |
| Short name | T1650 |
| Test name | |
| Test status | |
| Simulation time | 53639901 ps |
| CPU time | 6.92 seconds |
| Started | Jul 03 07:25:13 PM PDT 24 |
| Finished | Jul 03 07:25:21 PM PDT 24 |
| Peak memory | 573064 kb |
| Host | smart-08c587a6-949a-457c-aeb5-38eafc4179ef |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3166390804 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_same_source.3166390804 |
| Directory | /workspace/17.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_smoke.914263064 |
| Short name | T2837 |
| Test name | |
| Test status | |
| Simulation time | 208698416 ps |
| CPU time | 8.6 seconds |
| Started | Jul 03 07:25:09 PM PDT 24 |
| Finished | Jul 03 07:25:18 PM PDT 24 |
| Peak memory | 572920 kb |
| Host | smart-6f64bec6-9b5c-40f4-8412-a4e9a93de2fb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914263064 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_smoke.914263064 |
| Directory | /workspace/17.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_smoke_large_delays.2885657757 |
| Short name | T1907 |
| Test name | |
| Test status | |
| Simulation time | 7137187905 ps |
| CPU time | 77.51 seconds |
| Started | Jul 03 07:25:06 PM PDT 24 |
| Finished | Jul 03 07:26:25 PM PDT 24 |
| Peak memory | 573208 kb |
| Host | smart-6adcc2b3-de2a-464b-bb88-a0f4aedbf8b1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885657757 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_large_delays.2885657757 |
| Directory | /workspace/17.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_smoke_slow_rsp.841773757 |
| Short name | T2721 |
| Test name | |
| Test status | |
| Simulation time | 5967672703 ps |
| CPU time | 104.1 seconds |
| Started | Jul 03 07:25:09 PM PDT 24 |
| Finished | Jul 03 07:26:54 PM PDT 24 |
| Peak memory | 572924 kb |
| Host | smart-d8b82e17-1e37-4193-b075-340be36bd553 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=841773757 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_slow_rsp.841773757 |
| Directory | /workspace/17.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_smoke_zero_delays.3782985750 |
| Short name | T1539 |
| Test name | |
| Test status | |
| Simulation time | 57616804 ps |
| CPU time | 7.53 seconds |
| Started | Jul 03 07:25:06 PM PDT 24 |
| Finished | Jul 03 07:25:16 PM PDT 24 |
| Peak memory | 574196 kb |
| Host | smart-a517fa09-b553-46ef-b4b3-f808d74bd554 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3782985750 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_zero_delay s.3782985750 |
| Directory | /workspace/17.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_stress_all.256573886 |
| Short name | T603 |
| Test name | |
| Test status | |
| Simulation time | 7789543554 ps |
| CPU time | 295.25 seconds |
| Started | Jul 03 07:25:12 PM PDT 24 |
| Finished | Jul 03 07:30:08 PM PDT 24 |
| Peak memory | 574668 kb |
| Host | smart-e86dd0f1-b7d7-47f3-ba08-002197ff5112 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=256573886 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all.256573886 |
| Directory | /workspace/17.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_stress_all_with_error.1114471409 |
| Short name | T1845 |
| Test name | |
| Test status | |
| Simulation time | 3349543287 ps |
| CPU time | 118.34 seconds |
| Started | Jul 03 07:25:21 PM PDT 24 |
| Finished | Jul 03 07:27:21 PM PDT 24 |
| Peak memory | 574676 kb |
| Host | smart-510d8124-5f18-4491-8150-5331b671ac20 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1114471409 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_error.1114471409 |
| Directory | /workspace/17.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_stress_all_with_rand_reset.1346159040 |
| Short name | T2874 |
| Test name | |
| Test status | |
| Simulation time | 3676684850 ps |
| CPU time | 381.96 seconds |
| Started | Jul 03 07:25:21 PM PDT 24 |
| Finished | Jul 03 07:31:45 PM PDT 24 |
| Peak memory | 574804 kb |
| Host | smart-5e8dcc3f-1a15-4fd4-af66-63ac0a23859b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1346159040 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all _with_rand_reset.1346159040 |
| Directory | /workspace/17.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_stress_all_with_reset_error.1724503870 |
| Short name | T777 |
| Test name | |
| Test status | |
| Simulation time | 11849358289 ps |
| CPU time | 657.12 seconds |
| Started | Jul 03 07:25:15 PM PDT 24 |
| Finished | Jul 03 07:36:14 PM PDT 24 |
| Peak memory | 574712 kb |
| Host | smart-4bac153f-24f8-4189-affa-f12790cbf6df |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724503870 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_stress_al l_with_reset_error.1724503870 |
| Directory | /workspace/17.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_unmapped_addr.3805774201 |
| Short name | T2016 |
| Test name | |
| Test status | |
| Simulation time | 166107828 ps |
| CPU time | 20.36 seconds |
| Started | Jul 03 07:25:14 PM PDT 24 |
| Finished | Jul 03 07:25:36 PM PDT 24 |
| Peak memory | 574020 kb |
| Host | smart-9956c127-d6e2-4d3a-a423-97adfce7f50a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3805774201 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_unmapped_addr.3805774201 |
| Directory | /workspace/17.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/18.chip_csr_rw.351275643 |
| Short name | T2643 |
| Test name | |
| Test status | |
| Simulation time | 3847209300 ps |
| CPU time | 256.37 seconds |
| Started | Jul 03 07:25:33 PM PDT 24 |
| Finished | Jul 03 07:29:51 PM PDT 24 |
| Peak memory | 596164 kb |
| Host | smart-0d1e2c65-a71a-4494-b976-3dc54a31f853 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=351275643 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.chip_csr_rw.351275643 |
| Directory | /workspace/18.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_access_same_device.1927369892 |
| Short name | T1350 |
| Test name | |
| Test status | |
| Simulation time | 1525382992 ps |
| CPU time | 57.16 seconds |
| Started | Jul 03 07:25:26 PM PDT 24 |
| Finished | Jul 03 07:26:24 PM PDT 24 |
| Peak memory | 574216 kb |
| Host | smart-51dfbd4a-e38d-4fe7-aac6-2e0b3fd2b7cf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1927369892 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_access_same_device .1927369892 |
| Directory | /workspace/18.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_error_and_unmapped_addr.2256595520 |
| Short name | T1434 |
| Test name | |
| Test status | |
| Simulation time | 339483279 ps |
| CPU time | 16.77 seconds |
| Started | Jul 03 07:25:27 PM PDT 24 |
| Finished | Jul 03 07:25:46 PM PDT 24 |
| Peak memory | 573948 kb |
| Host | smart-969d3a8a-88e2-43bc-b6d9-e81dfb09a7e7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2256595520 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_error_and_unmapped_add r.2256595520 |
| Directory | /workspace/18.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_error_random.2324010834 |
| Short name | T2206 |
| Test name | |
| Test status | |
| Simulation time | 2066740963 ps |
| CPU time | 69.91 seconds |
| Started | Jul 03 07:25:25 PM PDT 24 |
| Finished | Jul 03 07:26:36 PM PDT 24 |
| Peak memory | 574052 kb |
| Host | smart-037cf5f6-5932-4235-8fb3-827efd5fa09d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2324010834 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_error_random.2324010834 |
| Directory | /workspace/18.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_random.806258138 |
| Short name | T1622 |
| Test name | |
| Test status | |
| Simulation time | 2106540099 ps |
| CPU time | 87.5 seconds |
| Started | Jul 03 07:25:19 PM PDT 24 |
| Finished | Jul 03 07:26:50 PM PDT 24 |
| Peak memory | 574172 kb |
| Host | smart-febde8ee-048d-4918-9442-da6825452884 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=806258138 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_random.806258138 |
| Directory | /workspace/18.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_random_large_delays.3433183837 |
| Short name | T1722 |
| Test name | |
| Test status | |
| Simulation time | 38400873516 ps |
| CPU time | 415.13 seconds |
| Started | Jul 03 07:25:23 PM PDT 24 |
| Finished | Jul 03 07:32:20 PM PDT 24 |
| Peak memory | 574096 kb |
| Host | smart-239ac131-2228-4e0b-be2d-85d3cd4ac2ea |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433183837 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_random_large_delays.3433183837 |
| Directory | /workspace/18.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_random_slow_rsp.2517948086 |
| Short name | T2172 |
| Test name | |
| Test status | |
| Simulation time | 52925737014 ps |
| CPU time | 930.02 seconds |
| Started | Jul 03 07:25:26 PM PDT 24 |
| Finished | Jul 03 07:40:58 PM PDT 24 |
| Peak memory | 574308 kb |
| Host | smart-7b4d6ead-f4c3-4d3a-a953-3173be285c46 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2517948086 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_random_slow_rsp.2517948086 |
| Directory | /workspace/18.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_random_zero_delays.4094285852 |
| Short name | T2073 |
| Test name | |
| Test status | |
| Simulation time | 427429117 ps |
| CPU time | 39.41 seconds |
| Started | Jul 03 07:25:25 PM PDT 24 |
| Finished | Jul 03 07:26:06 PM PDT 24 |
| Peak memory | 574232 kb |
| Host | smart-8d16139e-ca07-4294-a7f2-e64bd40c7195 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094285852 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_random_zero_del ays.4094285852 |
| Directory | /workspace/18.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_same_source.2107743157 |
| Short name | T2098 |
| Test name | |
| Test status | |
| Simulation time | 473443369 ps |
| CPU time | 33.82 seconds |
| Started | Jul 03 07:25:26 PM PDT 24 |
| Finished | Jul 03 07:26:01 PM PDT 24 |
| Peak memory | 574168 kb |
| Host | smart-c5e0f095-db26-4ca9-a106-4e3b08d95a08 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2107743157 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_same_source.2107743157 |
| Directory | /workspace/18.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_smoke.1917872247 |
| Short name | T1776 |
| Test name | |
| Test status | |
| Simulation time | 248537340 ps |
| CPU time | 10.42 seconds |
| Started | Jul 03 07:25:18 PM PDT 24 |
| Finished | Jul 03 07:25:31 PM PDT 24 |
| Peak memory | 573112 kb |
| Host | smart-aa53802c-41ed-42c4-966c-81f8912f943d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1917872247 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_smoke.1917872247 |
| Directory | /workspace/18.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_smoke_large_delays.3275830707 |
| Short name | T1438 |
| Test name | |
| Test status | |
| Simulation time | 5998522022 ps |
| CPU time | 61.57 seconds |
| Started | Jul 03 07:25:21 PM PDT 24 |
| Finished | Jul 03 07:26:25 PM PDT 24 |
| Peak memory | 573212 kb |
| Host | smart-254798dd-fbd8-493c-8ecb-30d93a5b3616 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3275830707 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_large_delays.3275830707 |
| Directory | /workspace/18.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_smoke_slow_rsp.3170502185 |
| Short name | T2487 |
| Test name | |
| Test status | |
| Simulation time | 4348785198 ps |
| CPU time | 67.32 seconds |
| Started | Jul 03 07:25:24 PM PDT 24 |
| Finished | Jul 03 07:26:33 PM PDT 24 |
| Peak memory | 574320 kb |
| Host | smart-531308d0-8a8d-4f68-9ae8-3b98f983e7d4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3170502185 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_slow_rsp.3170502185 |
| Directory | /workspace/18.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_smoke_zero_delays.3789927459 |
| Short name | T558 |
| Test name | |
| Test status | |
| Simulation time | 43403258 ps |
| CPU time | 5.94 seconds |
| Started | Jul 03 07:25:23 PM PDT 24 |
| Finished | Jul 03 07:25:30 PM PDT 24 |
| Peak memory | 574140 kb |
| Host | smart-7dbf0a38-2e0a-47b2-bf97-572ebafc796a |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3789927459 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_zero_delay s.3789927459 |
| Directory | /workspace/18.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_stress_all.2159514529 |
| Short name | T2865 |
| Test name | |
| Test status | |
| Simulation time | 3168150980 ps |
| CPU time | 252.19 seconds |
| Started | Jul 03 07:25:29 PM PDT 24 |
| Finished | Jul 03 07:29:43 PM PDT 24 |
| Peak memory | 574732 kb |
| Host | smart-bf2aecc3-d5d5-42bb-a74f-9ff51dbab3bd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2159514529 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all.2159514529 |
| Directory | /workspace/18.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_stress_all_with_error.2844055922 |
| Short name | T1342 |
| Test name | |
| Test status | |
| Simulation time | 597048790 ps |
| CPU time | 55.49 seconds |
| Started | Jul 03 07:25:27 PM PDT 24 |
| Finished | Jul 03 07:26:25 PM PDT 24 |
| Peak memory | 574468 kb |
| Host | smart-975d1697-40da-41c0-9210-f801c9ce2976 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2844055922 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_error.2844055922 |
| Directory | /workspace/18.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_stress_all_with_rand_reset.4205957051 |
| Short name | T1993 |
| Test name | |
| Test status | |
| Simulation time | 692586755 ps |
| CPU time | 93.8 seconds |
| Started | Jul 03 07:25:27 PM PDT 24 |
| Finished | Jul 03 07:27:02 PM PDT 24 |
| Peak memory | 574624 kb |
| Host | smart-4b14df2f-b65d-4995-b220-b6817a12d6cd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4205957051 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all _with_rand_reset.4205957051 |
| Directory | /workspace/18.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_stress_all_with_reset_error.1942607655 |
| Short name | T2491 |
| Test name | |
| Test status | |
| Simulation time | 5025155642 ps |
| CPU time | 425.41 seconds |
| Started | Jul 03 07:25:29 PM PDT 24 |
| Finished | Jul 03 07:32:37 PM PDT 24 |
| Peak memory | 574840 kb |
| Host | smart-b2d47829-6068-45a6-99b7-9bcd7e555528 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942607655 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_stress_al l_with_reset_error.1942607655 |
| Directory | /workspace/18.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_unmapped_addr.1672344756 |
| Short name | T2860 |
| Test name | |
| Test status | |
| Simulation time | 98031021 ps |
| CPU time | 12.11 seconds |
| Started | Jul 03 07:25:32 PM PDT 24 |
| Finished | Jul 03 07:25:45 PM PDT 24 |
| Peak memory | 574092 kb |
| Host | smart-dffe7eee-3c8b-40c6-8715-c63dafeeedd3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1672344756 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_unmapped_addr.1672344756 |
| Directory | /workspace/18.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/19.chip_csr_rw.123846918 |
| Short name | T2285 |
| Test name | |
| Test status | |
| Simulation time | 5580305015 ps |
| CPU time | 567.53 seconds |
| Started | Jul 03 07:25:54 PM PDT 24 |
| Finished | Jul 03 07:35:22 PM PDT 24 |
| Peak memory | 596056 kb |
| Host | smart-f7913b16-8d3a-4fb1-a9ee-5bb2e97a2fe6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=123846918 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.chip_csr_rw.123846918 |
| Directory | /workspace/19.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/19.chip_same_csr_outstanding.2199510028 |
| Short name | T2881 |
| Test name | |
| Test status | |
| Simulation time | 14025799459 ps |
| CPU time | 1844.97 seconds |
| Started | Jul 03 07:25:33 PM PDT 24 |
| Finished | Jul 03 07:56:19 PM PDT 24 |
| Peak memory | 591792 kb |
| Host | smart-a2974d6f-8d27-44d7-addb-87a75b120608 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2199510028 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 19.chip_same_csr_outstanding.2199510028 |
| Directory | /workspace/19.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/19.chip_tl_errors.3167593571 |
| Short name | T525 |
| Test name | |
| Test status | |
| Simulation time | 3101839064 ps |
| CPU time | 122.88 seconds |
| Started | Jul 03 07:25:33 PM PDT 24 |
| Finished | Jul 03 07:27:37 PM PDT 24 |
| Peak memory | 603144 kb |
| Host | smart-65b986dd-3d80-471b-8c75-29186ca02a92 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3167593571 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.chip_tl_errors.3167593571 |
| Directory | /workspace/19.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_access_same_device.453613388 |
| Short name | T1512 |
| Test name | |
| Test status | |
| Simulation time | 2205488459 ps |
| CPU time | 96.13 seconds |
| Started | Jul 03 07:25:37 PM PDT 24 |
| Finished | Jul 03 07:27:14 PM PDT 24 |
| Peak memory | 574308 kb |
| Host | smart-ba0e0eca-66c2-4f01-b052-d3c886fd4c4c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=453613388 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_access_same_device. 453613388 |
| Directory | /workspace/19.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_error_and_unmapped_addr.2179720820 |
| Short name | T1822 |
| Test name | |
| Test status | |
| Simulation time | 95851577 ps |
| CPU time | 7.2 seconds |
| Started | Jul 03 07:25:44 PM PDT 24 |
| Finished | Jul 03 07:25:52 PM PDT 24 |
| Peak memory | 573432 kb |
| Host | smart-2753e48a-b069-4cde-81da-d9089ef9746a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179720820 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_error_and_unmapped_add r.2179720820 |
| Directory | /workspace/19.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_error_random.908573221 |
| Short name | T2727 |
| Test name | |
| Test status | |
| Simulation time | 516397902 ps |
| CPU time | 47.22 seconds |
| Started | Jul 03 07:25:42 PM PDT 24 |
| Finished | Jul 03 07:26:31 PM PDT 24 |
| Peak memory | 574564 kb |
| Host | smart-1dd514a4-5e15-4fb8-976e-f0e533937fdb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=908573221 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_error_random.908573221 |
| Directory | /workspace/19.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_random.2623276883 |
| Short name | T2452 |
| Test name | |
| Test status | |
| Simulation time | 379345051 ps |
| CPU time | 31.96 seconds |
| Started | Jul 03 07:25:35 PM PDT 24 |
| Finished | Jul 03 07:26:08 PM PDT 24 |
| Peak memory | 574120 kb |
| Host | smart-c4a6f371-e298-4845-8b7c-c8029ee3b495 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2623276883 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_random.2623276883 |
| Directory | /workspace/19.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_random_large_delays.3949785518 |
| Short name | T431 |
| Test name | |
| Test status | |
| Simulation time | 58190429924 ps |
| CPU time | 607.16 seconds |
| Started | Jul 03 07:25:37 PM PDT 24 |
| Finished | Jul 03 07:35:46 PM PDT 24 |
| Peak memory | 574268 kb |
| Host | smart-2ba5d6cc-97a2-4441-873a-91a560b576b4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3949785518 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_random_large_delays.3949785518 |
| Directory | /workspace/19.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_random_slow_rsp.1327475911 |
| Short name | T1623 |
| Test name | |
| Test status | |
| Simulation time | 12528199969 ps |
| CPU time | 220.27 seconds |
| Started | Jul 03 07:25:36 PM PDT 24 |
| Finished | Jul 03 07:29:17 PM PDT 24 |
| Peak memory | 574272 kb |
| Host | smart-fdbba215-84ff-41c0-889e-583c47108536 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1327475911 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_random_slow_rsp.1327475911 |
| Directory | /workspace/19.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_random_zero_delays.48104203 |
| Short name | T591 |
| Test name | |
| Test status | |
| Simulation time | 119255520 ps |
| CPU time | 13.17 seconds |
| Started | Jul 03 07:25:37 PM PDT 24 |
| Finished | Jul 03 07:25:51 PM PDT 24 |
| Peak memory | 574212 kb |
| Host | smart-12654329-1083-4985-b869-1dcbd27e9b72 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48104203 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_random_zero_delay s.48104203 |
| Directory | /workspace/19.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_same_source.94373979 |
| Short name | T1525 |
| Test name | |
| Test status | |
| Simulation time | 312259149 ps |
| CPU time | 26.61 seconds |
| Started | Jul 03 07:25:43 PM PDT 24 |
| Finished | Jul 03 07:26:11 PM PDT 24 |
| Peak memory | 574188 kb |
| Host | smart-33a8b154-4dd4-4380-8db9-33c77039ee51 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94373979 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_same_source.94373979 |
| Directory | /workspace/19.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_smoke.158370260 |
| Short name | T2567 |
| Test name | |
| Test status | |
| Simulation time | 184388466 ps |
| CPU time | 8.56 seconds |
| Started | Jul 03 07:25:34 PM PDT 24 |
| Finished | Jul 03 07:25:44 PM PDT 24 |
| Peak memory | 573124 kb |
| Host | smart-7ad19bef-cc97-4db2-bf13-6e48ac05cc8b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=158370260 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_smoke.158370260 |
| Directory | /workspace/19.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_smoke_large_delays.1626070414 |
| Short name | T2638 |
| Test name | |
| Test status | |
| Simulation time | 10637459900 ps |
| CPU time | 111.39 seconds |
| Started | Jul 03 07:25:34 PM PDT 24 |
| Finished | Jul 03 07:27:27 PM PDT 24 |
| Peak memory | 573256 kb |
| Host | smart-995cb302-889c-4831-b15a-9605627871be |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1626070414 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_large_delays.1626070414 |
| Directory | /workspace/19.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_smoke_slow_rsp.2134118300 |
| Short name | T1789 |
| Test name | |
| Test status | |
| Simulation time | 4629986255 ps |
| CPU time | 89.44 seconds |
| Started | Jul 03 07:25:36 PM PDT 24 |
| Finished | Jul 03 07:27:06 PM PDT 24 |
| Peak memory | 573184 kb |
| Host | smart-2c1248ba-c4c5-4921-a364-40e7f76ea3b4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2134118300 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_slow_rsp.2134118300 |
| Directory | /workspace/19.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_smoke_zero_delays.3263587228 |
| Short name | T1436 |
| Test name | |
| Test status | |
| Simulation time | 48899447 ps |
| CPU time | 6.18 seconds |
| Started | Jul 03 07:25:31 PM PDT 24 |
| Finished | Jul 03 07:25:39 PM PDT 24 |
| Peak memory | 573128 kb |
| Host | smart-3afc1781-11a6-4cd4-8b66-36bd019cdd8d |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3263587228 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_zero_delay s.3263587228 |
| Directory | /workspace/19.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_stress_all.2217597027 |
| Short name | T1799 |
| Test name | |
| Test status | |
| Simulation time | 3951013593 ps |
| CPU time | 124.73 seconds |
| Started | Jul 03 07:25:42 PM PDT 24 |
| Finished | Jul 03 07:27:48 PM PDT 24 |
| Peak memory | 574136 kb |
| Host | smart-179f9ade-c451-49e6-b06e-5c138d41326a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2217597027 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all.2217597027 |
| Directory | /workspace/19.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_stress_all_with_error.1490582262 |
| Short name | T1630 |
| Test name | |
| Test status | |
| Simulation time | 15382264628 ps |
| CPU time | 535.74 seconds |
| Started | Jul 03 07:25:42 PM PDT 24 |
| Finished | Jul 03 07:34:39 PM PDT 24 |
| Peak memory | 574204 kb |
| Host | smart-70b491f8-227a-4489-a8e0-5bc51dcccc09 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1490582262 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_error.1490582262 |
| Directory | /workspace/19.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_stress_all_with_rand_reset.3531402290 |
| Short name | T1914 |
| Test name | |
| Test status | |
| Simulation time | 5860904594 ps |
| CPU time | 324.73 seconds |
| Started | Jul 03 07:25:42 PM PDT 24 |
| Finished | Jul 03 07:31:08 PM PDT 24 |
| Peak memory | 574712 kb |
| Host | smart-26d1615c-a4f5-4dec-9801-b89668a2e8cd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531402290 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all _with_rand_reset.3531402290 |
| Directory | /workspace/19.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_stress_all_with_reset_error.408667948 |
| Short name | T2732 |
| Test name | |
| Test status | |
| Simulation time | 34921798 ps |
| CPU time | 15.47 seconds |
| Started | Jul 03 07:25:43 PM PDT 24 |
| Finished | Jul 03 07:26:00 PM PDT 24 |
| Peak memory | 573552 kb |
| Host | smart-6536dd24-92b8-407f-ba82-c7e2872b8ee5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=408667948 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all _with_reset_error.408667948 |
| Directory | /workspace/19.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_unmapped_addr.1530932782 |
| Short name | T1801 |
| Test name | |
| Test status | |
| Simulation time | 1089092368 ps |
| CPU time | 46.23 seconds |
| Started | Jul 03 07:25:44 PM PDT 24 |
| Finished | Jul 03 07:26:31 PM PDT 24 |
| Peak memory | 574252 kb |
| Host | smart-1d6f1420-c312-4796-871e-55e3d9ffe28f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1530932782 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_unmapped_addr.1530932782 |
| Directory | /workspace/19.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/2.chip_csr_aliasing.867352391 |
| Short name | T422 |
| Test name | |
| Test status | |
| Simulation time | 71283808295 ps |
| CPU time | 10209.8 seconds |
| Started | Jul 03 07:22:17 PM PDT 24 |
| Finished | Jul 03 10:12:32 PM PDT 24 |
| Peak memory | 637428 kb |
| Host | smart-32dbf827-418e-48e4-8615-2832ae14d307 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +csr_aliasing +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=867352391 -assert nopostproc +UVM_TESTNAME=chip_b ase_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n ull -cm_name 2.chip_csr_aliasing.867352391 |
| Directory | /workspace/2.chip_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/2.chip_csr_bit_bash.246207998 |
| Short name | T376 |
| Test name | |
| Test status | |
| Simulation time | 8426844864 ps |
| CPU time | 993.17 seconds |
| Started | Jul 03 07:22:17 PM PDT 24 |
| Finished | Jul 03 07:38:54 PM PDT 24 |
| Peak memory | 590688 kb |
| Host | smart-a328d2ff-b6f6-4e9b-91e7-d09cb5671ed9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +num_test_csrs=200 +csr_bit_bash +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=246207998 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 2.chip_csr_bit_bash.246207998 |
| Directory | /workspace/2.chip_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/2.chip_csr_rw.2387697566 |
| Short name | T2813 |
| Test name | |
| Test status | |
| Simulation time | 5396746296 ps |
| CPU time | 516.15 seconds |
| Started | Jul 03 07:22:26 PM PDT 24 |
| Finished | Jul 03 07:31:04 PM PDT 24 |
| Peak memory | 596460 kb |
| Host | smart-6f1ae717-8200-464d-8aa7-8a3e886da837 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2387697566 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.chip_csr_rw.2387697566 |
| Directory | /workspace/2.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/2.chip_prim_tl_access.4097974598 |
| Short name | T2080 |
| Test name | |
| Test status | |
| Simulation time | 8261799880 ps |
| CPU time | 363.57 seconds |
| Started | Jul 03 07:22:16 PM PDT 24 |
| Finished | Jul 03 07:28:23 PM PDT 24 |
| Peak memory | 589696 kb |
| Host | smart-086a2666-1c09-400d-955a-1a1f4bc1e4d4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +en_scb_tl_err_chk=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4097974598 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SE Q=chip_prim_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.chip_prim_tl_access.4097974598 |
| Directory | /workspace/2.chip_prim_tl_access/latest |
| Test location | /workspace/coverage/cover_reg_top/2.chip_rv_dm_lc_disabled.1362247969 |
| Short name | T2545 |
| Test name | |
| Test status | |
| Simulation time | 16698822645 ps |
| CPU time | 707.08 seconds |
| Started | Jul 03 07:22:19 PM PDT 24 |
| Finished | Jul 03 07:34:10 PM PDT 24 |
| Peak memory | 591640 kb |
| Host | smart-8d564bb1-ec9d-4224-8691-332bd5f3c7fa |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +en_scb_tl_err_chk=0 +use_jtag_dmi=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1362247969 -assert nopostproc +UVM_TESTNAME=chip_base_t est +UVM_TEST_SEQ=chip_rv_dm_lc_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.chip_rv_dm_lc_disabled.1362247969 |
| Directory | /workspace/2.chip_rv_dm_lc_disabled/latest |
| Test location | /workspace/coverage/cover_reg_top/2.chip_same_csr_outstanding.1357365972 |
| Short name | T2834 |
| Test name | |
| Test status | |
| Simulation time | 30813232140 ps |
| CPU time | 4303.66 seconds |
| Started | Jul 03 07:22:18 PM PDT 24 |
| Finished | Jul 03 08:34:06 PM PDT 24 |
| Peak memory | 592060 kb |
| Host | smart-91bf3f77-5421-4752-aa06-7d581e21d8dc |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1357365972 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 2.chip_same_csr_outstanding.1357365972 |
| Directory | /workspace/2.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/2.chip_tl_errors.2702553955 |
| Short name | T639 |
| Test name | |
| Test status | |
| Simulation time | 2986897045 ps |
| CPU time | 275.86 seconds |
| Started | Jul 03 07:22:24 PM PDT 24 |
| Finished | Jul 03 07:27:01 PM PDT 24 |
| Peak memory | 599076 kb |
| Host | smart-e92f2263-a121-4fa2-9132-27c2be62282a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2702553955 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.chip_tl_errors.2702553955 |
| Directory | /workspace/2.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_access_same_device.3747047215 |
| Short name | T1486 |
| Test name | |
| Test status | |
| Simulation time | 1595632518 ps |
| CPU time | 77.98 seconds |
| Started | Jul 03 07:22:22 PM PDT 24 |
| Finished | Jul 03 07:23:42 PM PDT 24 |
| Peak memory | 574236 kb |
| Host | smart-6e40ac89-f11e-4014-b864-9748a6e9acfe |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3747047215 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_access_same_device. 3747047215 |
| Directory | /workspace/2.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_access_same_device_slow_rsp.1488247816 |
| Short name | T2129 |
| Test name | |
| Test status | |
| Simulation time | 23084060725 ps |
| CPU time | 411.69 seconds |
| Started | Jul 03 07:22:20 PM PDT 24 |
| Finished | Jul 03 07:29:15 PM PDT 24 |
| Peak memory | 574284 kb |
| Host | smart-3bd0e2ad-0921-4d54-8ead-b6af3ecdded5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1488247816 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_access_same_d evice_slow_rsp.1488247816 |
| Directory | /workspace/2.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_error_and_unmapped_addr.1596180841 |
| Short name | T1473 |
| Test name | |
| Test status | |
| Simulation time | 439349090 ps |
| CPU time | 20.62 seconds |
| Started | Jul 03 07:22:21 PM PDT 24 |
| Finished | Jul 03 07:22:44 PM PDT 24 |
| Peak memory | 574572 kb |
| Host | smart-d12811b2-2e44-4f21-92ce-3e228ecf7402 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1596180841 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_error_and_unmapped_addr .1596180841 |
| Directory | /workspace/2.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_error_random.3836640865 |
| Short name | T2554 |
| Test name | |
| Test status | |
| Simulation time | 128194793 ps |
| CPU time | 8.06 seconds |
| Started | Jul 03 07:22:22 PM PDT 24 |
| Finished | Jul 03 07:22:32 PM PDT 24 |
| Peak memory | 574028 kb |
| Host | smart-9ff22c9f-1aa8-4f11-9dac-beab02c5060a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3836640865 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_error_random.3836640865 |
| Directory | /workspace/2.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_random.1405521645 |
| Short name | T2246 |
| Test name | |
| Test status | |
| Simulation time | 276985920 ps |
| CPU time | 11.21 seconds |
| Started | Jul 03 07:22:23 PM PDT 24 |
| Finished | Jul 03 07:22:36 PM PDT 24 |
| Peak memory | 574220 kb |
| Host | smart-f16a09f7-ae92-4f51-9b4a-e43695df6789 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1405521645 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_random.1405521645 |
| Directory | /workspace/2.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_random_large_delays.2523630943 |
| Short name | T1447 |
| Test name | |
| Test status | |
| Simulation time | 97877549664 ps |
| CPU time | 1140.06 seconds |
| Started | Jul 03 07:22:22 PM PDT 24 |
| Finished | Jul 03 07:41:24 PM PDT 24 |
| Peak memory | 574248 kb |
| Host | smart-ac253f24-8065-4206-b51b-ada19d8c8b8c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2523630943 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_random_large_delays.2523630943 |
| Directory | /workspace/2.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_random_slow_rsp.946881719 |
| Short name | T1411 |
| Test name | |
| Test status | |
| Simulation time | 31690565692 ps |
| CPU time | 541.25 seconds |
| Started | Jul 03 07:22:33 PM PDT 24 |
| Finished | Jul 03 07:31:37 PM PDT 24 |
| Peak memory | 574200 kb |
| Host | smart-183feb74-6110-4074-9225-9e6045ba6113 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=946881719 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_random_slow_rsp.946881719 |
| Directory | /workspace/2.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_random_zero_delays.1831220214 |
| Short name | T1496 |
| Test name | |
| Test status | |
| Simulation time | 305025135 ps |
| CPU time | 24.01 seconds |
| Started | Jul 03 07:22:22 PM PDT 24 |
| Finished | Jul 03 07:22:48 PM PDT 24 |
| Peak memory | 574016 kb |
| Host | smart-33cfed70-6a01-41e9-a09b-64bf747806a9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1831220214 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_random_zero_dela ys.1831220214 |
| Directory | /workspace/2.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_same_source.3952486627 |
| Short name | T1727 |
| Test name | |
| Test status | |
| Simulation time | 480525407 ps |
| CPU time | 16.38 seconds |
| Started | Jul 03 07:22:22 PM PDT 24 |
| Finished | Jul 03 07:22:40 PM PDT 24 |
| Peak memory | 573856 kb |
| Host | smart-3aaa56fc-ade1-4299-bd66-44880b1039a6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3952486627 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_same_source.3952486627 |
| Directory | /workspace/2.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_smoke.2123428559 |
| Short name | T1437 |
| Test name | |
| Test status | |
| Simulation time | 53177118 ps |
| CPU time | 6.4 seconds |
| Started | Jul 03 07:22:19 PM PDT 24 |
| Finished | Jul 03 07:22:29 PM PDT 24 |
| Peak memory | 572940 kb |
| Host | smart-4b459a63-c2f9-41f1-82e4-492e33e7d09a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2123428559 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_smoke.2123428559 |
| Directory | /workspace/2.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_smoke_large_delays.3992854549 |
| Short name | T2078 |
| Test name | |
| Test status | |
| Simulation time | 7558475102 ps |
| CPU time | 74.36 seconds |
| Started | Jul 03 07:22:34 PM PDT 24 |
| Finished | Jul 03 07:23:51 PM PDT 24 |
| Peak memory | 573184 kb |
| Host | smart-5ee67b95-948b-434f-9414-3e543f72f59c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3992854549 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_large_delays.3992854549 |
| Directory | /workspace/2.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_smoke_slow_rsp.3879490946 |
| Short name | T2058 |
| Test name | |
| Test status | |
| Simulation time | 6278116013 ps |
| CPU time | 101.13 seconds |
| Started | Jul 03 07:22:21 PM PDT 24 |
| Finished | Jul 03 07:24:05 PM PDT 24 |
| Peak memory | 574264 kb |
| Host | smart-666e05fa-c35e-4768-83fc-0b55f38ed8ad |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3879490946 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_slow_rsp.3879490946 |
| Directory | /workspace/2.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_smoke_zero_delays.3952418405 |
| Short name | T2611 |
| Test name | |
| Test status | |
| Simulation time | 44757742 ps |
| CPU time | 6.39 seconds |
| Started | Jul 03 07:22:17 PM PDT 24 |
| Finished | Jul 03 07:22:27 PM PDT 24 |
| Peak memory | 572952 kb |
| Host | smart-5b29da7e-3912-4384-b90c-c1717e6782a4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3952418405 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_zero_delays .3952418405 |
| Directory | /workspace/2.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_stress_all.2432129283 |
| Short name | T2591 |
| Test name | |
| Test status | |
| Simulation time | 1134711287 ps |
| CPU time | 96.31 seconds |
| Started | Jul 03 07:22:22 PM PDT 24 |
| Finished | Jul 03 07:24:01 PM PDT 24 |
| Peak memory | 574624 kb |
| Host | smart-8ec4b118-0b6b-4ffc-a3dd-3e7a4032e686 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432129283 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all.2432129283 |
| Directory | /workspace/2.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_stress_all_with_error.1907222018 |
| Short name | T1926 |
| Test name | |
| Test status | |
| Simulation time | 1115566912 ps |
| CPU time | 89.56 seconds |
| Started | Jul 03 07:22:33 PM PDT 24 |
| Finished | Jul 03 07:24:05 PM PDT 24 |
| Peak memory | 574168 kb |
| Host | smart-37723574-795c-4a74-9ea0-6e0779967d76 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1907222018 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_error.1907222018 |
| Directory | /workspace/2.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_stress_all_with_rand_reset.319598697 |
| Short name | T2688 |
| Test name | |
| Test status | |
| Simulation time | 205069246 ps |
| CPU time | 91.99 seconds |
| Started | Jul 03 07:22:21 PM PDT 24 |
| Finished | Jul 03 07:23:56 PM PDT 24 |
| Peak memory | 574572 kb |
| Host | smart-7a7426ac-5455-4328-9e3a-c4848242c7bb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319598697 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_w ith_rand_reset.319598697 |
| Directory | /workspace/2.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_stress_all_with_reset_error.2569992692 |
| Short name | T2092 |
| Test name | |
| Test status | |
| Simulation time | 6672736859 ps |
| CPU time | 666.65 seconds |
| Started | Jul 03 07:22:33 PM PDT 24 |
| Finished | Jul 03 07:33:42 PM PDT 24 |
| Peak memory | 579284 kb |
| Host | smart-9da95a77-765e-4cb0-a253-e27a17af8828 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2569992692 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all _with_reset_error.2569992692 |
| Directory | /workspace/2.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_unmapped_addr.735448510 |
| Short name | T1589 |
| Test name | |
| Test status | |
| Simulation time | 170607773 ps |
| CPU time | 23.36 seconds |
| Started | Jul 03 07:22:22 PM PDT 24 |
| Finished | Jul 03 07:22:48 PM PDT 24 |
| Peak memory | 574204 kb |
| Host | smart-4e3bf7a2-164d-4438-a624-edce4791ca97 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=735448510 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_unmapped_addr.735448510 |
| Directory | /workspace/2.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/20.chip_tl_errors.3466706833 |
| Short name | T2771 |
| Test name | |
| Test status | |
| Simulation time | 2579410224 ps |
| CPU time | 97.85 seconds |
| Started | Jul 03 07:25:51 PM PDT 24 |
| Finished | Jul 03 07:27:30 PM PDT 24 |
| Peak memory | 597940 kb |
| Host | smart-05feeb37-2622-4e30-8cb6-4427cc079bfc |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3466706833 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.chip_tl_errors.3466706833 |
| Directory | /workspace/20.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_access_same_device.3112749525 |
| Short name | T456 |
| Test name | |
| Test status | |
| Simulation time | 890781213 ps |
| CPU time | 76.98 seconds |
| Started | Jul 03 07:25:48 PM PDT 24 |
| Finished | Jul 03 07:27:06 PM PDT 24 |
| Peak memory | 574276 kb |
| Host | smart-1db1f31f-c2aa-4041-b4f4-091e0d626935 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3112749525 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_access_same_device .3112749525 |
| Directory | /workspace/20.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_access_same_device_slow_rsp.1173978420 |
| Short name | T792 |
| Test name | |
| Test status | |
| Simulation time | 41009212806 ps |
| CPU time | 720.55 seconds |
| Started | Jul 03 07:25:54 PM PDT 24 |
| Finished | Jul 03 07:37:55 PM PDT 24 |
| Peak memory | 574348 kb |
| Host | smart-2dd9ddb4-38bd-479a-bc67-c62416bdbdb0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1173978420 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_access_same_ device_slow_rsp.1173978420 |
| Directory | /workspace/20.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_error_and_unmapped_addr.2610525314 |
| Short name | T2422 |
| Test name | |
| Test status | |
| Simulation time | 1513665988 ps |
| CPU time | 60.98 seconds |
| Started | Jul 03 07:26:02 PM PDT 24 |
| Finished | Jul 03 07:27:05 PM PDT 24 |
| Peak memory | 574484 kb |
| Host | smart-4881a56f-2e22-409b-a0c4-360c7e3dcfaa |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610525314 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_error_and_unmapped_add r.2610525314 |
| Directory | /workspace/20.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_error_random.2080641031 |
| Short name | T2734 |
| Test name | |
| Test status | |
| Simulation time | 2475240807 ps |
| CPU time | 97.53 seconds |
| Started | Jul 03 07:25:55 PM PDT 24 |
| Finished | Jul 03 07:27:34 PM PDT 24 |
| Peak memory | 574100 kb |
| Host | smart-b9dab4d8-71e5-4b58-979d-7b55d2bbc4d3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2080641031 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_error_random.2080641031 |
| Directory | /workspace/20.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_random.3891572640 |
| Short name | T2805 |
| Test name | |
| Test status | |
| Simulation time | 946761037 ps |
| CPU time | 34.09 seconds |
| Started | Jul 03 07:25:46 PM PDT 24 |
| Finished | Jul 03 07:26:21 PM PDT 24 |
| Peak memory | 574132 kb |
| Host | smart-afd4c20e-1c16-442b-8536-9d757e592189 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3891572640 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_random.3891572640 |
| Directory | /workspace/20.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_random_large_delays.1514768643 |
| Short name | T2597 |
| Test name | |
| Test status | |
| Simulation time | 64291621988 ps |
| CPU time | 663.34 seconds |
| Started | Jul 03 07:25:54 PM PDT 24 |
| Finished | Jul 03 07:36:59 PM PDT 24 |
| Peak memory | 574288 kb |
| Host | smart-2daea948-d8e6-4c0f-8596-08f3ae5067b2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1514768643 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_random_large_delays.1514768643 |
| Directory | /workspace/20.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_random_slow_rsp.795371479 |
| Short name | T1456 |
| Test name | |
| Test status | |
| Simulation time | 15645829872 ps |
| CPU time | 269.16 seconds |
| Started | Jul 03 07:25:48 PM PDT 24 |
| Finished | Jul 03 07:30:19 PM PDT 24 |
| Peak memory | 574272 kb |
| Host | smart-bbc214b2-2e86-4a3c-91cf-9ab1c0ccc4b1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=795371479 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_random_slow_rsp.795371479 |
| Directory | /workspace/20.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_random_zero_delays.1886140389 |
| Short name | T2828 |
| Test name | |
| Test status | |
| Simulation time | 421237269 ps |
| CPU time | 38.51 seconds |
| Started | Jul 03 07:25:51 PM PDT 24 |
| Finished | Jul 03 07:26:32 PM PDT 24 |
| Peak memory | 573980 kb |
| Host | smart-61848d6d-e3ed-4b86-a02f-aeb1a614178d |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886140389 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_random_zero_del ays.1886140389 |
| Directory | /workspace/20.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_same_source.1098730425 |
| Short name | T1467 |
| Test name | |
| Test status | |
| Simulation time | 268786278 ps |
| CPU time | 23.71 seconds |
| Started | Jul 03 07:25:54 PM PDT 24 |
| Finished | Jul 03 07:26:19 PM PDT 24 |
| Peak memory | 574104 kb |
| Host | smart-f6529310-5add-44cf-aba3-b6a5711955fe |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098730425 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_same_source.1098730425 |
| Directory | /workspace/20.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_smoke.1824117107 |
| Short name | T2503 |
| Test name | |
| Test status | |
| Simulation time | 245624702 ps |
| CPU time | 9.67 seconds |
| Started | Jul 03 07:25:52 PM PDT 24 |
| Finished | Jul 03 07:26:03 PM PDT 24 |
| Peak memory | 572920 kb |
| Host | smart-2a3c8900-eaef-47c7-a716-8cfe4ee6d6f8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1824117107 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_smoke.1824117107 |
| Directory | /workspace/20.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_smoke_large_delays.1081479357 |
| Short name | T2875 |
| Test name | |
| Test status | |
| Simulation time | 8758969603 ps |
| CPU time | 90.55 seconds |
| Started | Jul 03 07:25:49 PM PDT 24 |
| Finished | Jul 03 07:27:21 PM PDT 24 |
| Peak memory | 574188 kb |
| Host | smart-0457563f-6933-4286-bad4-ddbf4cd622fa |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1081479357 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_large_delays.1081479357 |
| Directory | /workspace/20.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_smoke_slow_rsp.2182126482 |
| Short name | T1340 |
| Test name | |
| Test status | |
| Simulation time | 4552401737 ps |
| CPU time | 82.31 seconds |
| Started | Jul 03 07:25:54 PM PDT 24 |
| Finished | Jul 03 07:27:18 PM PDT 24 |
| Peak memory | 572948 kb |
| Host | smart-ac2b0552-840e-4b35-ab0e-dcad3e42608d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2182126482 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_slow_rsp.2182126482 |
| Directory | /workspace/20.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_smoke_zero_delays.702058198 |
| Short name | T1964 |
| Test name | |
| Test status | |
| Simulation time | 43498434 ps |
| CPU time | 6.08 seconds |
| Started | Jul 03 07:25:51 PM PDT 24 |
| Finished | Jul 03 07:26:00 PM PDT 24 |
| Peak memory | 573988 kb |
| Host | smart-6a2f3ea2-2fb5-4ca5-80eb-1668a2e5d29a |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=702058198 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_zero_delays .702058198 |
| Directory | /workspace/20.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_stress_all_with_error.2589514814 |
| Short name | T2782 |
| Test name | |
| Test status | |
| Simulation time | 9640714821 ps |
| CPU time | 374.31 seconds |
| Started | Jul 03 07:25:56 PM PDT 24 |
| Finished | Jul 03 07:32:12 PM PDT 24 |
| Peak memory | 574728 kb |
| Host | smart-1555e8d6-50e0-40da-ade9-1419f7d407ef |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2589514814 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_error.2589514814 |
| Directory | /workspace/20.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_stress_all_with_reset_error.1668020560 |
| Short name | T2812 |
| Test name | |
| Test status | |
| Simulation time | 747479027 ps |
| CPU time | 237.48 seconds |
| Started | Jul 03 07:26:03 PM PDT 24 |
| Finished | Jul 03 07:30:02 PM PDT 24 |
| Peak memory | 574652 kb |
| Host | smart-575f3c35-32c6-4431-a25f-e606115d3625 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668020560 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_stress_al l_with_reset_error.1668020560 |
| Directory | /workspace/20.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_unmapped_addr.3483581446 |
| Short name | T1579 |
| Test name | |
| Test status | |
| Simulation time | 176648352 ps |
| CPU time | 21.22 seconds |
| Started | Jul 03 07:26:03 PM PDT 24 |
| Finished | Jul 03 07:26:26 PM PDT 24 |
| Peak memory | 574280 kb |
| Host | smart-23f2f6a4-3885-42af-b90f-3219ef8a0ecb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3483581446 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_unmapped_addr.3483581446 |
| Directory | /workspace/20.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/21.chip_tl_errors.3984672795 |
| Short name | T642 |
| Test name | |
| Test status | |
| Simulation time | 4127952008 ps |
| CPU time | 423.23 seconds |
| Started | Jul 03 07:25:56 PM PDT 24 |
| Finished | Jul 03 07:33:01 PM PDT 24 |
| Peak memory | 599100 kb |
| Host | smart-169ce6c3-9c65-4f69-bf9c-39756b1ef981 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3984672795 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.chip_tl_errors.3984672795 |
| Directory | /workspace/21.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_access_same_device.3189079121 |
| Short name | T2872 |
| Test name | |
| Test status | |
| Simulation time | 3075303140 ps |
| CPU time | 121.13 seconds |
| Started | Jul 03 07:26:02 PM PDT 24 |
| Finished | Jul 03 07:28:05 PM PDT 24 |
| Peak memory | 574396 kb |
| Host | smart-bbe25567-d6aa-4167-b902-0e26d205a105 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3189079121 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_access_same_device .3189079121 |
| Directory | /workspace/21.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_access_same_device_slow_rsp.2629307798 |
| Short name | T1910 |
| Test name | |
| Test status | |
| Simulation time | 68445878667 ps |
| CPU time | 1178.09 seconds |
| Started | Jul 03 07:25:59 PM PDT 24 |
| Finished | Jul 03 07:45:39 PM PDT 24 |
| Peak memory | 574364 kb |
| Host | smart-2742cb6b-8244-46e3-98e4-615e120fb1f1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2629307798 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_access_same_ device_slow_rsp.2629307798 |
| Directory | /workspace/21.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_error_and_unmapped_addr.2986554095 |
| Short name | T1737 |
| Test name | |
| Test status | |
| Simulation time | 221530768 ps |
| CPU time | 24.36 seconds |
| Started | Jul 03 07:26:14 PM PDT 24 |
| Finished | Jul 03 07:26:41 PM PDT 24 |
| Peak memory | 574028 kb |
| Host | smart-3acfee92-8417-41ae-93ea-980bf2d65127 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2986554095 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_error_and_unmapped_add r.2986554095 |
| Directory | /workspace/21.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_error_random.3435768964 |
| Short name | T1896 |
| Test name | |
| Test status | |
| Simulation time | 522204543 ps |
| CPU time | 45.72 seconds |
| Started | Jul 03 07:25:59 PM PDT 24 |
| Finished | Jul 03 07:26:46 PM PDT 24 |
| Peak memory | 574064 kb |
| Host | smart-ed26d303-aab4-40d6-b279-c58e1f27c516 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3435768964 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_error_random.3435768964 |
| Directory | /workspace/21.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_random.2750856351 |
| Short name | T1898 |
| Test name | |
| Test status | |
| Simulation time | 2445691403 ps |
| CPU time | 88.74 seconds |
| Started | Jul 03 07:25:58 PM PDT 24 |
| Finished | Jul 03 07:27:28 PM PDT 24 |
| Peak memory | 574208 kb |
| Host | smart-3834a619-6b34-4010-9b34-f0743e0c6ac8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2750856351 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_random.2750856351 |
| Directory | /workspace/21.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_random_large_delays.188973487 |
| Short name | T2392 |
| Test name | |
| Test status | |
| Simulation time | 33686645660 ps |
| CPU time | 339.69 seconds |
| Started | Jul 03 07:25:58 PM PDT 24 |
| Finished | Jul 03 07:31:39 PM PDT 24 |
| Peak memory | 574056 kb |
| Host | smart-33f5bb16-5815-4f8f-9b1b-39a03edc17b3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=188973487 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_random_large_delays.188973487 |
| Directory | /workspace/21.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_random_slow_rsp.4238270178 |
| Short name | T1655 |
| Test name | |
| Test status | |
| Simulation time | 63893378177 ps |
| CPU time | 1099.9 seconds |
| Started | Jul 03 07:26:01 PM PDT 24 |
| Finished | Jul 03 07:44:23 PM PDT 24 |
| Peak memory | 574332 kb |
| Host | smart-4b3e9ffe-766c-46c7-9ccf-032fd5bf0b2d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4238270178 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_random_slow_rsp.4238270178 |
| Directory | /workspace/21.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_random_zero_delays.3044488056 |
| Short name | T1806 |
| Test name | |
| Test status | |
| Simulation time | 137043707 ps |
| CPU time | 14.9 seconds |
| Started | Jul 03 07:25:59 PM PDT 24 |
| Finished | Jul 03 07:26:16 PM PDT 24 |
| Peak memory | 574016 kb |
| Host | smart-d239267d-8772-4163-a144-bc67fc1ece16 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3044488056 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_random_zero_del ays.3044488056 |
| Directory | /workspace/21.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_same_source.1706319819 |
| Short name | T1856 |
| Test name | |
| Test status | |
| Simulation time | 342801273 ps |
| CPU time | 12.14 seconds |
| Started | Jul 03 07:25:59 PM PDT 24 |
| Finished | Jul 03 07:26:13 PM PDT 24 |
| Peak memory | 574116 kb |
| Host | smart-4fddc72b-7190-438f-b234-333c5da17b9c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706319819 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_same_source.1706319819 |
| Directory | /workspace/21.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_smoke.537217700 |
| Short name | T2021 |
| Test name | |
| Test status | |
| Simulation time | 195428459 ps |
| CPU time | 8.63 seconds |
| Started | Jul 03 07:26:00 PM PDT 24 |
| Finished | Jul 03 07:26:11 PM PDT 24 |
| Peak memory | 573144 kb |
| Host | smart-bdd09f57-95e1-4952-acc1-283b164f65e4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=537217700 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_smoke.537217700 |
| Directory | /workspace/21.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_smoke_large_delays.3105932775 |
| Short name | T2421 |
| Test name | |
| Test status | |
| Simulation time | 9435521587 ps |
| CPU time | 96.63 seconds |
| Started | Jul 03 07:26:08 PM PDT 24 |
| Finished | Jul 03 07:27:46 PM PDT 24 |
| Peak memory | 573040 kb |
| Host | smart-d6ae6228-076b-46aa-99c5-12e45e48c440 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3105932775 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_large_delays.3105932775 |
| Directory | /workspace/21.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_smoke_slow_rsp.2153933746 |
| Short name | T2876 |
| Test name | |
| Test status | |
| Simulation time | 6805144449 ps |
| CPU time | 120.76 seconds |
| Started | Jul 03 07:26:01 PM PDT 24 |
| Finished | Jul 03 07:28:03 PM PDT 24 |
| Peak memory | 573004 kb |
| Host | smart-047a3bef-cc15-4bfd-ac71-559b95ababf9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2153933746 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_slow_rsp.2153933746 |
| Directory | /workspace/21.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_smoke_zero_delays.1737297233 |
| Short name | T2665 |
| Test name | |
| Test status | |
| Simulation time | 48890489 ps |
| CPU time | 6.34 seconds |
| Started | Jul 03 07:26:03 PM PDT 24 |
| Finished | Jul 03 07:26:11 PM PDT 24 |
| Peak memory | 573008 kb |
| Host | smart-b8cd1dc1-d1c6-4568-9033-62d94aa984ae |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1737297233 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_zero_delay s.1737297233 |
| Directory | /workspace/21.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_stress_all.324849983 |
| Short name | T2532 |
| Test name | |
| Test status | |
| Simulation time | 11365740490 ps |
| CPU time | 377.89 seconds |
| Started | Jul 03 07:26:15 PM PDT 24 |
| Finished | Jul 03 07:32:35 PM PDT 24 |
| Peak memory | 574688 kb |
| Host | smart-51ebaf25-57ca-45f4-8d49-6b2b57c87d05 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=324849983 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all.324849983 |
| Directory | /workspace/21.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_stress_all_with_error.531202621 |
| Short name | T1825 |
| Test name | |
| Test status | |
| Simulation time | 12190558539 ps |
| CPU time | 482.81 seconds |
| Started | Jul 03 07:26:04 PM PDT 24 |
| Finished | Jul 03 07:34:08 PM PDT 24 |
| Peak memory | 574648 kb |
| Host | smart-d7b4ecaa-084a-4c34-96a1-839798239017 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=531202621 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_error.531202621 |
| Directory | /workspace/21.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_stress_all_with_rand_reset.3561334762 |
| Short name | T452 |
| Test name | |
| Test status | |
| Simulation time | 6786154631 ps |
| CPU time | 736.49 seconds |
| Started | Jul 03 07:26:03 PM PDT 24 |
| Finished | Jul 03 07:38:21 PM PDT 24 |
| Peak memory | 574728 kb |
| Host | smart-94729609-f75c-459d-b78f-0f4a846b62b6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3561334762 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all _with_rand_reset.3561334762 |
| Directory | /workspace/21.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_stress_all_with_reset_error.2892660216 |
| Short name | T2551 |
| Test name | |
| Test status | |
| Simulation time | 8852337 ps |
| CPU time | 11.55 seconds |
| Started | Jul 03 07:26:15 PM PDT 24 |
| Finished | Jul 03 07:26:28 PM PDT 24 |
| Peak memory | 573476 kb |
| Host | smart-5125b76d-d5f4-4e06-9b31-2731273fe056 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2892660216 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_stress_al l_with_reset_error.2892660216 |
| Directory | /workspace/21.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_unmapped_addr.1345994602 |
| Short name | T1743 |
| Test name | |
| Test status | |
| Simulation time | 568221224 ps |
| CPU time | 25.79 seconds |
| Started | Jul 03 07:26:04 PM PDT 24 |
| Finished | Jul 03 07:26:31 PM PDT 24 |
| Peak memory | 574264 kb |
| Host | smart-2ec0bf50-5920-46a9-bc06-f5d9e50a7665 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1345994602 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_unmapped_addr.1345994602 |
| Directory | /workspace/21.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/22.chip_tl_errors.3601203725 |
| Short name | T2847 |
| Test name | |
| Test status | |
| Simulation time | 4343668006 ps |
| CPU time | 263.84 seconds |
| Started | Jul 03 07:26:05 PM PDT 24 |
| Finished | Jul 03 07:30:29 PM PDT 24 |
| Peak memory | 598052 kb |
| Host | smart-10edca15-90f8-4a41-b5a9-fb87514d86e7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3601203725 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.chip_tl_errors.3601203725 |
| Directory | /workspace/22.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_access_same_device.721539087 |
| Short name | T2575 |
| Test name | |
| Test status | |
| Simulation time | 419501554 ps |
| CPU time | 37.08 seconds |
| Started | Jul 03 07:26:14 PM PDT 24 |
| Finished | Jul 03 07:26:54 PM PDT 24 |
| Peak memory | 574176 kb |
| Host | smart-f726527d-ba8c-4c07-9d33-fdf12f81a9a9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=721539087 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_access_same_device. 721539087 |
| Directory | /workspace/22.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_access_same_device_slow_rsp.3957051862 |
| Short name | T2034 |
| Test name | |
| Test status | |
| Simulation time | 105909177401 ps |
| CPU time | 1954.84 seconds |
| Started | Jul 03 07:26:15 PM PDT 24 |
| Finished | Jul 03 07:58:52 PM PDT 24 |
| Peak memory | 574668 kb |
| Host | smart-1545ab14-75a5-419d-ae42-64d67ce98be8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3957051862 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_access_same_ device_slow_rsp.3957051862 |
| Directory | /workspace/22.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_error_and_unmapped_addr.997804165 |
| Short name | T1372 |
| Test name | |
| Test status | |
| Simulation time | 1276061954 ps |
| CPU time | 52.32 seconds |
| Started | Jul 03 07:26:14 PM PDT 24 |
| Finished | Jul 03 07:27:08 PM PDT 24 |
| Peak memory | 574428 kb |
| Host | smart-150cf2c1-ff70-4aef-860d-d17a09bc5e9b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=997804165 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_error_and_unmapped_addr .997804165 |
| Directory | /workspace/22.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_error_random.1106003802 |
| Short name | T791 |
| Test name | |
| Test status | |
| Simulation time | 1399503933 ps |
| CPU time | 58.53 seconds |
| Started | Jul 03 07:26:19 PM PDT 24 |
| Finished | Jul 03 07:27:18 PM PDT 24 |
| Peak memory | 574484 kb |
| Host | smart-fea959fa-ee85-42b6-b439-72c25fd97eb2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1106003802 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_error_random.1106003802 |
| Directory | /workspace/22.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_random.558334937 |
| Short name | T2326 |
| Test name | |
| Test status | |
| Simulation time | 1658511635 ps |
| CPU time | 64.85 seconds |
| Started | Jul 03 07:26:04 PM PDT 24 |
| Finished | Jul 03 07:27:10 PM PDT 24 |
| Peak memory | 574152 kb |
| Host | smart-f23dbb5c-8be5-4729-8543-fedebde64a0b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558334937 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_random.558334937 |
| Directory | /workspace/22.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_random_large_delays.36652867 |
| Short name | T1559 |
| Test name | |
| Test status | |
| Simulation time | 65081653360 ps |
| CPU time | 699.41 seconds |
| Started | Jul 03 07:26:13 PM PDT 24 |
| Finished | Jul 03 07:37:54 PM PDT 24 |
| Peak memory | 574048 kb |
| Host | smart-275d0e97-79a8-417d-9692-1284f6314c62 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36652867 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_random_large_delays.36652867 |
| Directory | /workspace/22.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_random_slow_rsp.3473087906 |
| Short name | T553 |
| Test name | |
| Test status | |
| Simulation time | 20998419825 ps |
| CPU time | 376.76 seconds |
| Started | Jul 03 07:26:12 PM PDT 24 |
| Finished | Jul 03 07:32:30 PM PDT 24 |
| Peak memory | 574132 kb |
| Host | smart-901d016f-f91a-402a-9051-ca3693e8d7af |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3473087906 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_random_slow_rsp.3473087906 |
| Directory | /workspace/22.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_random_zero_delays.3494599814 |
| Short name | T1746 |
| Test name | |
| Test status | |
| Simulation time | 307138445 ps |
| CPU time | 26.78 seconds |
| Started | Jul 03 07:26:09 PM PDT 24 |
| Finished | Jul 03 07:26:38 PM PDT 24 |
| Peak memory | 574020 kb |
| Host | smart-72a1900c-feaf-41f1-b94a-75d6118eb62e |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3494599814 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_random_zero_del ays.3494599814 |
| Directory | /workspace/22.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_same_source.3137978243 |
| Short name | T1586 |
| Test name | |
| Test status | |
| Simulation time | 763273531 ps |
| CPU time | 25.9 seconds |
| Started | Jul 03 07:26:19 PM PDT 24 |
| Finished | Jul 03 07:26:46 PM PDT 24 |
| Peak memory | 574168 kb |
| Host | smart-a689459f-fdd8-4896-b977-214ff9c711e3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3137978243 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_same_source.3137978243 |
| Directory | /workspace/22.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_smoke.3190646071 |
| Short name | T2469 |
| Test name | |
| Test status | |
| Simulation time | 191179350 ps |
| CPU time | 8.68 seconds |
| Started | Jul 03 07:26:07 PM PDT 24 |
| Finished | Jul 03 07:26:16 PM PDT 24 |
| Peak memory | 573204 kb |
| Host | smart-37c2baf8-3155-4512-8905-ccbf0a727a26 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3190646071 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_smoke.3190646071 |
| Directory | /workspace/22.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_smoke_large_delays.2589720625 |
| Short name | T1522 |
| Test name | |
| Test status | |
| Simulation time | 9603609150 ps |
| CPU time | 106.28 seconds |
| Started | Jul 03 07:26:04 PM PDT 24 |
| Finished | Jul 03 07:27:51 PM PDT 24 |
| Peak memory | 574244 kb |
| Host | smart-f8bcc9f0-42be-4d57-b7ba-c259f8c582ba |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2589720625 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_large_delays.2589720625 |
| Directory | /workspace/22.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_smoke_slow_rsp.2952063424 |
| Short name | T2431 |
| Test name | |
| Test status | |
| Simulation time | 5387056640 ps |
| CPU time | 86.41 seconds |
| Started | Jul 03 07:26:15 PM PDT 24 |
| Finished | Jul 03 07:27:43 PM PDT 24 |
| Peak memory | 573044 kb |
| Host | smart-7d794b69-09ed-4da5-927b-fc67879b8ec1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2952063424 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_slow_rsp.2952063424 |
| Directory | /workspace/22.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_smoke_zero_delays.493983933 |
| Short name | T1416 |
| Test name | |
| Test status | |
| Simulation time | 41286066 ps |
| CPU time | 5.72 seconds |
| Started | Jul 03 07:26:14 PM PDT 24 |
| Finished | Jul 03 07:26:22 PM PDT 24 |
| Peak memory | 574192 kb |
| Host | smart-c4014248-9430-41a7-84ff-e49573f74d32 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=493983933 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_zero_delays .493983933 |
| Directory | /workspace/22.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_stress_all.1304950936 |
| Short name | T2174 |
| Test name | |
| Test status | |
| Simulation time | 5256677468 ps |
| CPU time | 187.29 seconds |
| Started | Jul 03 07:26:16 PM PDT 24 |
| Finished | Jul 03 07:29:25 PM PDT 24 |
| Peak memory | 574624 kb |
| Host | smart-3726dc9f-489d-4232-8554-d248bef6a8b6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1304950936 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all.1304950936 |
| Directory | /workspace/22.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_stress_all_with_error.1876948663 |
| Short name | T1966 |
| Test name | |
| Test status | |
| Simulation time | 1794776901 ps |
| CPU time | 61.98 seconds |
| Started | Jul 03 07:26:19 PM PDT 24 |
| Finished | Jul 03 07:27:22 PM PDT 24 |
| Peak memory | 574532 kb |
| Host | smart-59b3d270-9e27-4e86-809b-3893891ff4f1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1876948663 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_error.1876948663 |
| Directory | /workspace/22.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_stress_all_with_rand_reset.643007223 |
| Short name | T813 |
| Test name | |
| Test status | |
| Simulation time | 12802331162 ps |
| CPU time | 763.4 seconds |
| Started | Jul 03 07:26:13 PM PDT 24 |
| Finished | Jul 03 07:38:59 PM PDT 24 |
| Peak memory | 574752 kb |
| Host | smart-66b0657c-7386-46d0-84e2-023aab2af486 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=643007223 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_ with_rand_reset.643007223 |
| Directory | /workspace/22.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_stress_all_with_reset_error.1714194084 |
| Short name | T1829 |
| Test name | |
| Test status | |
| Simulation time | 2738931911 ps |
| CPU time | 225.67 seconds |
| Started | Jul 03 07:26:20 PM PDT 24 |
| Finished | Jul 03 07:30:07 PM PDT 24 |
| Peak memory | 574796 kb |
| Host | smart-5bd90b82-42a1-44f3-9dac-43d851c82605 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1714194084 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_stress_al l_with_reset_error.1714194084 |
| Directory | /workspace/22.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_unmapped_addr.3415854265 |
| Short name | T1570 |
| Test name | |
| Test status | |
| Simulation time | 984146500 ps |
| CPU time | 40.81 seconds |
| Started | Jul 03 07:26:12 PM PDT 24 |
| Finished | Jul 03 07:26:55 PM PDT 24 |
| Peak memory | 574268 kb |
| Host | smart-1554779e-a8bb-4e38-ba6b-6bc22a9ff26f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3415854265 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_unmapped_addr.3415854265 |
| Directory | /workspace/22.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_access_same_device.1554673710 |
| Short name | T2750 |
| Test name | |
| Test status | |
| Simulation time | 441621031 ps |
| CPU time | 38.13 seconds |
| Started | Jul 03 07:26:21 PM PDT 24 |
| Finished | Jul 03 07:27:00 PM PDT 24 |
| Peak memory | 574204 kb |
| Host | smart-c0a968a8-3968-46b5-82e9-80fded8e31ef |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1554673710 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_access_same_device .1554673710 |
| Directory | /workspace/23.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_access_same_device_slow_rsp.1255464261 |
| Short name | T429 |
| Test name | |
| Test status | |
| Simulation time | 21605432800 ps |
| CPU time | 385.37 seconds |
| Started | Jul 03 07:26:25 PM PDT 24 |
| Finished | Jul 03 07:32:51 PM PDT 24 |
| Peak memory | 574308 kb |
| Host | smart-62423dd3-a947-4ae8-b8ab-f14e1ef4befb |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1255464261 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_access_same_ device_slow_rsp.1255464261 |
| Directory | /workspace/23.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_error_and_unmapped_addr.3775964596 |
| Short name | T1943 |
| Test name | |
| Test status | |
| Simulation time | 55530585 ps |
| CPU time | 9.06 seconds |
| Started | Jul 03 07:26:28 PM PDT 24 |
| Finished | Jul 03 07:26:37 PM PDT 24 |
| Peak memory | 574496 kb |
| Host | smart-fc28c520-f2f8-48c1-aa37-edb050840f9b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3775964596 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_error_and_unmapped_add r.3775964596 |
| Directory | /workspace/23.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_error_random.964698282 |
| Short name | T1883 |
| Test name | |
| Test status | |
| Simulation time | 1553428463 ps |
| CPU time | 57.21 seconds |
| Started | Jul 03 07:26:24 PM PDT 24 |
| Finished | Jul 03 07:27:21 PM PDT 24 |
| Peak memory | 573984 kb |
| Host | smart-89766b47-7189-4061-8723-8cb106e26892 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=964698282 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_error_random.964698282 |
| Directory | /workspace/23.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_random.1444455250 |
| Short name | T2327 |
| Test name | |
| Test status | |
| Simulation time | 1753985426 ps |
| CPU time | 52.09 seconds |
| Started | Jul 03 07:26:19 PM PDT 24 |
| Finished | Jul 03 07:27:12 PM PDT 24 |
| Peak memory | 574172 kb |
| Host | smart-96dc3460-76cb-40c0-ba61-9a399a4eb5ae |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1444455250 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_random.1444455250 |
| Directory | /workspace/23.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_random_large_delays.2207264791 |
| Short name | T1924 |
| Test name | |
| Test status | |
| Simulation time | 58569606035 ps |
| CPU time | 646.43 seconds |
| Started | Jul 03 07:26:19 PM PDT 24 |
| Finished | Jul 03 07:37:07 PM PDT 24 |
| Peak memory | 574304 kb |
| Host | smart-dc83371d-2e4f-4240-92e5-6b4df8045e8b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2207264791 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_random_large_delays.2207264791 |
| Directory | /workspace/23.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_random_slow_rsp.1437296585 |
| Short name | T1961 |
| Test name | |
| Test status | |
| Simulation time | 60690031364 ps |
| CPU time | 1111.84 seconds |
| Started | Jul 03 07:26:21 PM PDT 24 |
| Finished | Jul 03 07:44:53 PM PDT 24 |
| Peak memory | 574264 kb |
| Host | smart-2edeb524-b7d0-473c-b204-550b28ac0771 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1437296585 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_random_slow_rsp.1437296585 |
| Directory | /workspace/23.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_random_zero_delays.3674336958 |
| Short name | T2028 |
| Test name | |
| Test status | |
| Simulation time | 482034045 ps |
| CPU time | 45.67 seconds |
| Started | Jul 03 07:26:22 PM PDT 24 |
| Finished | Jul 03 07:27:08 PM PDT 24 |
| Peak memory | 574116 kb |
| Host | smart-f82da0b7-7621-45bf-872e-ec3a0d9ef06c |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3674336958 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_random_zero_del ays.3674336958 |
| Directory | /workspace/23.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_same_source.3305504046 |
| Short name | T2065 |
| Test name | |
| Test status | |
| Simulation time | 700044386 ps |
| CPU time | 22.61 seconds |
| Started | Jul 03 07:26:25 PM PDT 24 |
| Finished | Jul 03 07:26:49 PM PDT 24 |
| Peak memory | 574168 kb |
| Host | smart-83888fb7-204f-4ca5-ac63-be37503afa38 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3305504046 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_same_source.3305504046 |
| Directory | /workspace/23.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_smoke.2616605278 |
| Short name | T1485 |
| Test name | |
| Test status | |
| Simulation time | 231880403 ps |
| CPU time | 9.96 seconds |
| Started | Jul 03 07:26:21 PM PDT 24 |
| Finished | Jul 03 07:26:31 PM PDT 24 |
| Peak memory | 574148 kb |
| Host | smart-c5b6988a-21b4-4e3f-9fd7-59bbcd9945b1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2616605278 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_smoke.2616605278 |
| Directory | /workspace/23.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_smoke_large_delays.3380689071 |
| Short name | T1764 |
| Test name | |
| Test status | |
| Simulation time | 6491512819 ps |
| CPU time | 73.57 seconds |
| Started | Jul 03 07:26:21 PM PDT 24 |
| Finished | Jul 03 07:27:35 PM PDT 24 |
| Peak memory | 573232 kb |
| Host | smart-65656c3f-0cde-4922-8c6e-841b4db65ce8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3380689071 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_large_delays.3380689071 |
| Directory | /workspace/23.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_smoke_slow_rsp.2062971575 |
| Short name | T2512 |
| Test name | |
| Test status | |
| Simulation time | 5538923498 ps |
| CPU time | 102.17 seconds |
| Started | Jul 03 07:26:21 PM PDT 24 |
| Finished | Jul 03 07:28:04 PM PDT 24 |
| Peak memory | 574332 kb |
| Host | smart-7584a531-d018-49d3-925e-225f39d84cdc |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062971575 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_slow_rsp.2062971575 |
| Directory | /workspace/23.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_smoke_zero_delays.1002312978 |
| Short name | T2573 |
| Test name | |
| Test status | |
| Simulation time | 45088681 ps |
| CPU time | 6.46 seconds |
| Started | Jul 03 07:26:20 PM PDT 24 |
| Finished | Jul 03 07:26:27 PM PDT 24 |
| Peak memory | 574164 kb |
| Host | smart-6471ce70-fe34-411a-98fc-a27f19a948d9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1002312978 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_zero_delay s.1002312978 |
| Directory | /workspace/23.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_stress_all.2664014915 |
| Short name | T2007 |
| Test name | |
| Test status | |
| Simulation time | 2108412709 ps |
| CPU time | 158.66 seconds |
| Started | Jul 03 07:26:26 PM PDT 24 |
| Finished | Jul 03 07:29:05 PM PDT 24 |
| Peak memory | 574648 kb |
| Host | smart-3e8d108f-4871-4dbe-9c2c-9bb1c67a99fe |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2664014915 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all.2664014915 |
| Directory | /workspace/23.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_stress_all_with_error.1717402552 |
| Short name | T2841 |
| Test name | |
| Test status | |
| Simulation time | 663860252 ps |
| CPU time | 64.26 seconds |
| Started | Jul 03 07:26:29 PM PDT 24 |
| Finished | Jul 03 07:27:34 PM PDT 24 |
| Peak memory | 574600 kb |
| Host | smart-1386068e-e064-4250-bd5b-f30fb690674e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1717402552 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_error.1717402552 |
| Directory | /workspace/23.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_stress_all_with_rand_reset.1126628291 |
| Short name | T2778 |
| Test name | |
| Test status | |
| Simulation time | 3001775471 ps |
| CPU time | 303.2 seconds |
| Started | Jul 03 07:26:24 PM PDT 24 |
| Finished | Jul 03 07:31:28 PM PDT 24 |
| Peak memory | 574724 kb |
| Host | smart-958070b4-c554-4d94-8c62-ad220d013b76 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1126628291 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all _with_rand_reset.1126628291 |
| Directory | /workspace/23.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_stress_all_with_reset_error.1085664449 |
| Short name | T801 |
| Test name | |
| Test status | |
| Simulation time | 5292036005 ps |
| CPU time | 322.42 seconds |
| Started | Jul 03 07:26:30 PM PDT 24 |
| Finished | Jul 03 07:31:54 PM PDT 24 |
| Peak memory | 574676 kb |
| Host | smart-b6071c34-4a29-4058-a83e-147f97c8497b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1085664449 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_stress_al l_with_reset_error.1085664449 |
| Directory | /workspace/23.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_unmapped_addr.2262197973 |
| Short name | T2863 |
| Test name | |
| Test status | |
| Simulation time | 1260352824 ps |
| CPU time | 48.57 seconds |
| Started | Jul 03 07:26:25 PM PDT 24 |
| Finished | Jul 03 07:27:15 PM PDT 24 |
| Peak memory | 574268 kb |
| Host | smart-40be2c58-fd6c-4094-8b25-432a986b06fd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2262197973 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_unmapped_addr.2262197973 |
| Directory | /workspace/23.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/24.chip_tl_errors.2908511699 |
| Short name | T514 |
| Test name | |
| Test status | |
| Simulation time | 3431672784 ps |
| CPU time | 218.81 seconds |
| Started | Jul 03 07:26:33 PM PDT 24 |
| Finished | Jul 03 07:30:13 PM PDT 24 |
| Peak memory | 597944 kb |
| Host | smart-b1000aa6-1bb3-48fe-8510-3f93b6571d10 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2908511699 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.chip_tl_errors.2908511699 |
| Directory | /workspace/24.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_access_same_device.4269536790 |
| Short name | T1629 |
| Test name | |
| Test status | |
| Simulation time | 2428497736 ps |
| CPU time | 109.13 seconds |
| Started | Jul 03 07:26:36 PM PDT 24 |
| Finished | Jul 03 07:28:26 PM PDT 24 |
| Peak memory | 574184 kb |
| Host | smart-238b40c7-5e65-449b-b258-6c3f2397662c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4269536790 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_access_same_device .4269536790 |
| Directory | /workspace/24.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_access_same_device_slow_rsp.1893132051 |
| Short name | T2885 |
| Test name | |
| Test status | |
| Simulation time | 114590966574 ps |
| CPU time | 2301.89 seconds |
| Started | Jul 03 07:26:38 PM PDT 24 |
| Finished | Jul 03 08:05:03 PM PDT 24 |
| Peak memory | 574132 kb |
| Host | smart-6258cbfa-303b-4a24-8805-c24e1fa06c13 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1893132051 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_access_same_ device_slow_rsp.1893132051 |
| Directory | /workspace/24.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_error_and_unmapped_addr.3632869845 |
| Short name | T2624 |
| Test name | |
| Test status | |
| Simulation time | 133089933 ps |
| CPU time | 17.66 seconds |
| Started | Jul 03 07:26:42 PM PDT 24 |
| Finished | Jul 03 07:27:03 PM PDT 24 |
| Peak memory | 574504 kb |
| Host | smart-0f10f194-b5eb-4653-a2b6-69a1e01cd52b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3632869845 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_error_and_unmapped_add r.3632869845 |
| Directory | /workspace/24.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_error_random.2229150200 |
| Short name | T2438 |
| Test name | |
| Test status | |
| Simulation time | 386351835 ps |
| CPU time | 34.46 seconds |
| Started | Jul 03 07:26:37 PM PDT 24 |
| Finished | Jul 03 07:27:13 PM PDT 24 |
| Peak memory | 574124 kb |
| Host | smart-66d3c9a8-6ec4-40da-8f90-8ba7dc868a50 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2229150200 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_error_random.2229150200 |
| Directory | /workspace/24.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_random.4000649309 |
| Short name | T1514 |
| Test name | |
| Test status | |
| Simulation time | 1830125227 ps |
| CPU time | 67.8 seconds |
| Started | Jul 03 07:26:36 PM PDT 24 |
| Finished | Jul 03 07:27:45 PM PDT 24 |
| Peak memory | 574176 kb |
| Host | smart-4708a1fd-9e60-443b-82ad-47c305984722 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4000649309 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_random.4000649309 |
| Directory | /workspace/24.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_random_large_delays.3073024750 |
| Short name | T2758 |
| Test name | |
| Test status | |
| Simulation time | 83963112275 ps |
| CPU time | 898.62 seconds |
| Started | Jul 03 07:26:37 PM PDT 24 |
| Finished | Jul 03 07:41:37 PM PDT 24 |
| Peak memory | 574348 kb |
| Host | smart-88914bfe-9a3b-4180-9306-5f2f4c2aff01 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3073024750 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_random_large_delays.3073024750 |
| Directory | /workspace/24.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_random_slow_rsp.1420792234 |
| Short name | T1477 |
| Test name | |
| Test status | |
| Simulation time | 25386540310 ps |
| CPU time | 447.38 seconds |
| Started | Jul 03 07:26:37 PM PDT 24 |
| Finished | Jul 03 07:34:06 PM PDT 24 |
| Peak memory | 574244 kb |
| Host | smart-8ea0b0d5-c29e-4817-81a6-9a5d72fcbf5f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1420792234 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_random_slow_rsp.1420792234 |
| Directory | /workspace/24.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_random_zero_delays.2514372298 |
| Short name | T1406 |
| Test name | |
| Test status | |
| Simulation time | 466502792 ps |
| CPU time | 44.18 seconds |
| Started | Jul 03 07:26:37 PM PDT 24 |
| Finished | Jul 03 07:27:24 PM PDT 24 |
| Peak memory | 574212 kb |
| Host | smart-16ffe8e8-bbc4-49e5-930f-a1549f769d50 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2514372298 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_random_zero_del ays.2514372298 |
| Directory | /workspace/24.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_same_source.3644737372 |
| Short name | T1923 |
| Test name | |
| Test status | |
| Simulation time | 2037948559 ps |
| CPU time | 64.02 seconds |
| Started | Jul 03 07:26:36 PM PDT 24 |
| Finished | Jul 03 07:27:41 PM PDT 24 |
| Peak memory | 574176 kb |
| Host | smart-116d6942-28d2-42e0-8c85-6583690812e0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3644737372 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_same_source.3644737372 |
| Directory | /workspace/24.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_smoke.3761266231 |
| Short name | T2175 |
| Test name | |
| Test status | |
| Simulation time | 207725757 ps |
| CPU time | 9.19 seconds |
| Started | Jul 03 07:26:32 PM PDT 24 |
| Finished | Jul 03 07:26:43 PM PDT 24 |
| Peak memory | 573096 kb |
| Host | smart-a03c274e-04b2-4196-80f0-61e8e54497a8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3761266231 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_smoke.3761266231 |
| Directory | /workspace/24.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_smoke_large_delays.3343029390 |
| Short name | T2010 |
| Test name | |
| Test status | |
| Simulation time | 9651278551 ps |
| CPU time | 97.54 seconds |
| Started | Jul 03 07:26:31 PM PDT 24 |
| Finished | Jul 03 07:28:10 PM PDT 24 |
| Peak memory | 572992 kb |
| Host | smart-3d36bdb1-778d-4bc0-a38b-a1fb80cbd71b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3343029390 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_large_delays.3343029390 |
| Directory | /workspace/24.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_smoke_slow_rsp.2925804570 |
| Short name | T1475 |
| Test name | |
| Test status | |
| Simulation time | 4417038227 ps |
| CPU time | 74.31 seconds |
| Started | Jul 03 07:26:31 PM PDT 24 |
| Finished | Jul 03 07:27:47 PM PDT 24 |
| Peak memory | 573244 kb |
| Host | smart-b46c865d-935b-49cd-a6e8-0b850259dd1a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2925804570 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_slow_rsp.2925804570 |
| Directory | /workspace/24.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_smoke_zero_delays.4157560543 |
| Short name | T1377 |
| Test name | |
| Test status | |
| Simulation time | 38818516 ps |
| CPU time | 6.44 seconds |
| Started | Jul 03 07:26:30 PM PDT 24 |
| Finished | Jul 03 07:26:39 PM PDT 24 |
| Peak memory | 574120 kb |
| Host | smart-6b916a77-a3aa-496c-81ad-a9db48c1ae10 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4157560543 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_zero_delay s.4157560543 |
| Directory | /workspace/24.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_stress_all.1613858570 |
| Short name | T2484 |
| Test name | |
| Test status | |
| Simulation time | 1524687319 ps |
| CPU time | 142.12 seconds |
| Started | Jul 03 07:26:43 PM PDT 24 |
| Finished | Jul 03 07:29:08 PM PDT 24 |
| Peak memory | 574696 kb |
| Host | smart-b93b3878-def1-4a2b-8ad4-58b32d1bd40b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1613858570 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all.1613858570 |
| Directory | /workspace/24.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_stress_all_with_error.561806004 |
| Short name | T1865 |
| Test name | |
| Test status | |
| Simulation time | 8442625253 ps |
| CPU time | 323.4 seconds |
| Started | Jul 03 07:26:41 PM PDT 24 |
| Finished | Jul 03 07:32:07 PM PDT 24 |
| Peak memory | 574604 kb |
| Host | smart-967af66a-bc56-4284-adf5-2bf914723c70 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=561806004 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_error.561806004 |
| Directory | /workspace/24.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_stress_all_with_rand_reset.2167952087 |
| Short name | T2312 |
| Test name | |
| Test status | |
| Simulation time | 1696268833 ps |
| CPU time | 319.12 seconds |
| Started | Jul 03 07:26:42 PM PDT 24 |
| Finished | Jul 03 07:32:04 PM PDT 24 |
| Peak memory | 574640 kb |
| Host | smart-cba25796-ebfc-4604-a410-2d211a298141 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2167952087 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all _with_rand_reset.2167952087 |
| Directory | /workspace/24.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_stress_all_with_reset_error.3290953149 |
| Short name | T2142 |
| Test name | |
| Test status | |
| Simulation time | 345899937 ps |
| CPU time | 89.13 seconds |
| Started | Jul 03 07:26:42 PM PDT 24 |
| Finished | Jul 03 07:28:14 PM PDT 24 |
| Peak memory | 574696 kb |
| Host | smart-8f70a514-72be-4cc3-b313-a04b651616ea |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3290953149 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_stress_al l_with_reset_error.3290953149 |
| Directory | /workspace/24.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_unmapped_addr.2356294362 |
| Short name | T2569 |
| Test name | |
| Test status | |
| Simulation time | 1164851246 ps |
| CPU time | 50.82 seconds |
| Started | Jul 03 07:26:45 PM PDT 24 |
| Finished | Jul 03 07:27:38 PM PDT 24 |
| Peak memory | 574024 kb |
| Host | smart-ed474b5f-67f6-4e65-9e7b-4e24828cd8cf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2356294362 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_unmapped_addr.2356294362 |
| Directory | /workspace/24.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/25.chip_tl_errors.2502316658 |
| Short name | T2113 |
| Test name | |
| Test status | |
| Simulation time | 3831186888 ps |
| CPU time | 268.13 seconds |
| Started | Jul 03 07:26:42 PM PDT 24 |
| Finished | Jul 03 07:31:13 PM PDT 24 |
| Peak memory | 603144 kb |
| Host | smart-6f217ec9-4afc-4a93-9a6b-40b90707481b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2502316658 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.chip_tl_errors.2502316658 |
| Directory | /workspace/25.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_access_same_device.492301787 |
| Short name | T1502 |
| Test name | |
| Test status | |
| Simulation time | 3268631963 ps |
| CPU time | 144.64 seconds |
| Started | Jul 03 07:26:48 PM PDT 24 |
| Finished | Jul 03 07:29:14 PM PDT 24 |
| Peak memory | 574144 kb |
| Host | smart-2d707698-0b62-43dd-8862-cb376a6a68a8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=492301787 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_access_same_device. 492301787 |
| Directory | /workspace/25.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_access_same_device_slow_rsp.855103817 |
| Short name | T2011 |
| Test name | |
| Test status | |
| Simulation time | 32084636573 ps |
| CPU time | 507.67 seconds |
| Started | Jul 03 07:26:47 PM PDT 24 |
| Finished | Jul 03 07:35:17 PM PDT 24 |
| Peak memory | 574216 kb |
| Host | smart-33e29767-8499-489c-b65f-c5bd64afdffa |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=855103817 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_access_same_d evice_slow_rsp.855103817 |
| Directory | /workspace/25.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_error_and_unmapped_addr.1011110259 |
| Short name | T2878 |
| Test name | |
| Test status | |
| Simulation time | 870252483 ps |
| CPU time | 32.93 seconds |
| Started | Jul 03 07:26:50 PM PDT 24 |
| Finished | Jul 03 07:27:24 PM PDT 24 |
| Peak memory | 574100 kb |
| Host | smart-cfcb0cb6-a379-4b7c-904e-de7dcf794fad |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1011110259 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_error_and_unmapped_add r.1011110259 |
| Directory | /workspace/25.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_error_random.3784496261 |
| Short name | T1670 |
| Test name | |
| Test status | |
| Simulation time | 1977713771 ps |
| CPU time | 71.87 seconds |
| Started | Jul 03 07:26:53 PM PDT 24 |
| Finished | Jul 03 07:28:07 PM PDT 24 |
| Peak memory | 574440 kb |
| Host | smart-d897489e-71ce-4cf8-900f-01297d9c9045 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3784496261 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_error_random.3784496261 |
| Directory | /workspace/25.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_random.1634472186 |
| Short name | T2602 |
| Test name | |
| Test status | |
| Simulation time | 479877218 ps |
| CPU time | 43.78 seconds |
| Started | Jul 03 07:26:41 PM PDT 24 |
| Finished | Jul 03 07:27:28 PM PDT 24 |
| Peak memory | 574144 kb |
| Host | smart-081bfe9c-dbb0-4c52-8084-cd76a96f9de2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1634472186 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_random.1634472186 |
| Directory | /workspace/25.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_random_large_delays.2817703537 |
| Short name | T1912 |
| Test name | |
| Test status | |
| Simulation time | 66294548283 ps |
| CPU time | 683.79 seconds |
| Started | Jul 03 07:26:48 PM PDT 24 |
| Finished | Jul 03 07:38:13 PM PDT 24 |
| Peak memory | 574368 kb |
| Host | smart-cbb10796-fcd8-4097-a852-84cbe0421408 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2817703537 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_random_large_delays.2817703537 |
| Directory | /workspace/25.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_random_slow_rsp.3830204230 |
| Short name | T599 |
| Test name | |
| Test status | |
| Simulation time | 40315738025 ps |
| CPU time | 740.61 seconds |
| Started | Jul 03 07:26:46 PM PDT 24 |
| Finished | Jul 03 07:39:09 PM PDT 24 |
| Peak memory | 574264 kb |
| Host | smart-6453d8b1-e969-43dc-82e4-d40bc7eb4786 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3830204230 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_random_slow_rsp.3830204230 |
| Directory | /workspace/25.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_random_zero_delays.4281542145 |
| Short name | T1460 |
| Test name | |
| Test status | |
| Simulation time | 388400950 ps |
| CPU time | 34.32 seconds |
| Started | Jul 03 07:26:47 PM PDT 24 |
| Finished | Jul 03 07:27:23 PM PDT 24 |
| Peak memory | 574240 kb |
| Host | smart-9cc31234-59bf-4623-89a5-56bec58907d8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4281542145 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_random_zero_del ays.4281542145 |
| Directory | /workspace/25.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_same_source.1851873514 |
| Short name | T2251 |
| Test name | |
| Test status | |
| Simulation time | 1240941820 ps |
| CPU time | 34.57 seconds |
| Started | Jul 03 07:26:52 PM PDT 24 |
| Finished | Jul 03 07:27:28 PM PDT 24 |
| Peak memory | 574016 kb |
| Host | smart-9dec4f3a-a295-41c7-a075-17bca383a566 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1851873514 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_same_source.1851873514 |
| Directory | /workspace/25.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_smoke.2770698151 |
| Short name | T2412 |
| Test name | |
| Test status | |
| Simulation time | 224266724 ps |
| CPU time | 9.71 seconds |
| Started | Jul 03 07:26:42 PM PDT 24 |
| Finished | Jul 03 07:26:54 PM PDT 24 |
| Peak memory | 572956 kb |
| Host | smart-f5511829-36d9-459d-b475-5af9338b7e3c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2770698151 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_smoke.2770698151 |
| Directory | /workspace/25.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_smoke_large_delays.1305326073 |
| Short name | T1608 |
| Test name | |
| Test status | |
| Simulation time | 8567328241 ps |
| CPU time | 92.29 seconds |
| Started | Jul 03 07:26:44 PM PDT 24 |
| Finished | Jul 03 07:28:19 PM PDT 24 |
| Peak memory | 573188 kb |
| Host | smart-86e9aa67-c04f-4efc-9859-63c0c205bc4d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1305326073 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_large_delays.1305326073 |
| Directory | /workspace/25.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_smoke_slow_rsp.2789799221 |
| Short name | T2617 |
| Test name | |
| Test status | |
| Simulation time | 4159589968 ps |
| CPU time | 67.8 seconds |
| Started | Jul 03 07:26:41 PM PDT 24 |
| Finished | Jul 03 07:27:52 PM PDT 24 |
| Peak memory | 573028 kb |
| Host | smart-0032294f-026d-4a34-bea2-5464360db595 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2789799221 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_slow_rsp.2789799221 |
| Directory | /workspace/25.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_smoke_zero_delays.3307865124 |
| Short name | T1310 |
| Test name | |
| Test status | |
| Simulation time | 41774392 ps |
| CPU time | 6.54 seconds |
| Started | Jul 03 07:26:45 PM PDT 24 |
| Finished | Jul 03 07:26:54 PM PDT 24 |
| Peak memory | 574096 kb |
| Host | smart-5249c064-f859-4431-bfa5-6623098490e7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3307865124 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_zero_delay s.3307865124 |
| Directory | /workspace/25.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_stress_all.287546278 |
| Short name | T1702 |
| Test name | |
| Test status | |
| Simulation time | 15301106181 ps |
| CPU time | 536.93 seconds |
| Started | Jul 03 07:26:50 PM PDT 24 |
| Finished | Jul 03 07:35:48 PM PDT 24 |
| Peak memory | 574696 kb |
| Host | smart-8597ce96-b511-4c7a-8e39-21793ed1212c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=287546278 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all.287546278 |
| Directory | /workspace/25.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_stress_all_with_error.918872260 |
| Short name | T2040 |
| Test name | |
| Test status | |
| Simulation time | 8135347762 ps |
| CPU time | 275.23 seconds |
| Started | Jul 03 07:26:55 PM PDT 24 |
| Finished | Jul 03 07:31:33 PM PDT 24 |
| Peak memory | 574760 kb |
| Host | smart-8c3494e0-994b-4946-9820-895322236dc2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=918872260 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_error.918872260 |
| Directory | /workspace/25.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_stress_all_with_rand_reset.2029988870 |
| Short name | T818 |
| Test name | |
| Test status | |
| Simulation time | 608149253 ps |
| CPU time | 162.59 seconds |
| Started | Jul 03 07:26:55 PM PDT 24 |
| Finished | Jul 03 07:29:40 PM PDT 24 |
| Peak memory | 574708 kb |
| Host | smart-7b95cff9-2783-4baa-b877-d75d68e3b318 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029988870 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all _with_rand_reset.2029988870 |
| Directory | /workspace/25.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_stress_all_with_reset_error.2224985095 |
| Short name | T2328 |
| Test name | |
| Test status | |
| Simulation time | 52388999 ps |
| CPU time | 16.78 seconds |
| Started | Jul 03 07:26:57 PM PDT 24 |
| Finished | Jul 03 07:27:17 PM PDT 24 |
| Peak memory | 573488 kb |
| Host | smart-fc378e7f-7241-41d6-ab8d-d356bbf32c5f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224985095 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_stress_al l_with_reset_error.2224985095 |
| Directory | /workspace/25.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_unmapped_addr.3466208232 |
| Short name | T1388 |
| Test name | |
| Test status | |
| Simulation time | 35969541 ps |
| CPU time | 7.29 seconds |
| Started | Jul 03 07:26:51 PM PDT 24 |
| Finished | Jul 03 07:26:59 PM PDT 24 |
| Peak memory | 572972 kb |
| Host | smart-c8d8a452-e427-48a0-b90f-488ea8d873b5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3466208232 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_unmapped_addr.3466208232 |
| Directory | /workspace/25.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_access_same_device.2749114919 |
| Short name | T2210 |
| Test name | |
| Test status | |
| Simulation time | 2757994575 ps |
| CPU time | 124.23 seconds |
| Started | Jul 03 07:27:03 PM PDT 24 |
| Finished | Jul 03 07:29:09 PM PDT 24 |
| Peak memory | 574320 kb |
| Host | smart-31b6f898-af1e-4cee-9d24-8e918b208b2e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2749114919 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_access_same_device .2749114919 |
| Directory | /workspace/26.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_error_and_unmapped_addr.4052757580 |
| Short name | T1691 |
| Test name | |
| Test status | |
| Simulation time | 978988800 ps |
| CPU time | 34.12 seconds |
| Started | Jul 03 07:27:08 PM PDT 24 |
| Finished | Jul 03 07:27:47 PM PDT 24 |
| Peak memory | 574028 kb |
| Host | smart-9db5bb9f-b920-44ef-bdf3-a5ea42e91eaa |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4052757580 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_error_and_unmapped_add r.4052757580 |
| Directory | /workspace/26.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_error_random.1726062632 |
| Short name | T2020 |
| Test name | |
| Test status | |
| Simulation time | 1409954742 ps |
| CPU time | 45.82 seconds |
| Started | Jul 03 07:27:04 PM PDT 24 |
| Finished | Jul 03 07:27:52 PM PDT 24 |
| Peak memory | 573956 kb |
| Host | smart-d902704c-50f5-4736-bb80-a622a5bebae3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1726062632 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_error_random.1726062632 |
| Directory | /workspace/26.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_random.3080597447 |
| Short name | T1976 |
| Test name | |
| Test status | |
| Simulation time | 2669872949 ps |
| CPU time | 101.36 seconds |
| Started | Jul 03 07:27:03 PM PDT 24 |
| Finished | Jul 03 07:28:47 PM PDT 24 |
| Peak memory | 574252 kb |
| Host | smart-b211a201-8eca-4a98-87a0-a677e9270d0b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080597447 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_random.3080597447 |
| Directory | /workspace/26.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_random_large_delays.3061667405 |
| Short name | T1847 |
| Test name | |
| Test status | |
| Simulation time | 40613978885 ps |
| CPU time | 442.69 seconds |
| Started | Jul 03 07:27:04 PM PDT 24 |
| Finished | Jul 03 07:34:30 PM PDT 24 |
| Peak memory | 574240 kb |
| Host | smart-f67943e2-ccf8-4fbc-a450-109d9eb2ad52 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3061667405 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_random_large_delays.3061667405 |
| Directory | /workspace/26.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_random_slow_rsp.687093448 |
| Short name | T1886 |
| Test name | |
| Test status | |
| Simulation time | 30424059910 ps |
| CPU time | 556.33 seconds |
| Started | Jul 03 07:27:03 PM PDT 24 |
| Finished | Jul 03 07:36:21 PM PDT 24 |
| Peak memory | 574244 kb |
| Host | smart-0a438054-7c03-4982-b8ad-ac7504ba73c8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=687093448 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_random_slow_rsp.687093448 |
| Directory | /workspace/26.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_random_zero_delays.2768878498 |
| Short name | T561 |
| Test name | |
| Test status | |
| Simulation time | 402491983 ps |
| CPU time | 34.21 seconds |
| Started | Jul 03 07:27:01 PM PDT 24 |
| Finished | Jul 03 07:27:36 PM PDT 24 |
| Peak memory | 574152 kb |
| Host | smart-bcfecb84-e9ab-4d3e-b7a6-ae21b125558a |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2768878498 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_random_zero_del ays.2768878498 |
| Directory | /workspace/26.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_same_source.1148988482 |
| Short name | T550 |
| Test name | |
| Test status | |
| Simulation time | 973868899 ps |
| CPU time | 29.01 seconds |
| Started | Jul 03 07:27:04 PM PDT 24 |
| Finished | Jul 03 07:27:36 PM PDT 24 |
| Peak memory | 574284 kb |
| Host | smart-230789d3-6b49-4aba-b143-1fc1bd6d3ed2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1148988482 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_same_source.1148988482 |
| Directory | /workspace/26.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_smoke.3562803594 |
| Short name | T2864 |
| Test name | |
| Test status | |
| Simulation time | 239398081 ps |
| CPU time | 10.72 seconds |
| Started | Jul 03 07:26:57 PM PDT 24 |
| Finished | Jul 03 07:27:10 PM PDT 24 |
| Peak memory | 574132 kb |
| Host | smart-b94ab9f3-07fc-44da-81b4-19a49453510f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3562803594 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_smoke.3562803594 |
| Directory | /workspace/26.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_smoke_large_delays.1806007638 |
| Short name | T1715 |
| Test name | |
| Test status | |
| Simulation time | 10183978914 ps |
| CPU time | 102.52 seconds |
| Started | Jul 03 07:26:57 PM PDT 24 |
| Finished | Jul 03 07:28:42 PM PDT 24 |
| Peak memory | 573208 kb |
| Host | smart-634f964c-c291-49a2-a12c-7a91576aa0ad |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1806007638 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_large_delays.1806007638 |
| Directory | /workspace/26.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_smoke_slow_rsp.143025938 |
| Short name | T1720 |
| Test name | |
| Test status | |
| Simulation time | 4578650956 ps |
| CPU time | 72.62 seconds |
| Started | Jul 03 07:27:05 PM PDT 24 |
| Finished | Jul 03 07:28:22 PM PDT 24 |
| Peak memory | 574204 kb |
| Host | smart-a52fc96c-26f0-4ad1-ad1b-69ace2a29dff |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=143025938 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_slow_rsp.143025938 |
| Directory | /workspace/26.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_smoke_zero_delays.364483410 |
| Short name | T565 |
| Test name | |
| Test status | |
| Simulation time | 49136098 ps |
| CPU time | 6.19 seconds |
| Started | Jul 03 07:26:57 PM PDT 24 |
| Finished | Jul 03 07:27:06 PM PDT 24 |
| Peak memory | 573164 kb |
| Host | smart-a2ee7f86-dd9c-48b5-8766-b76a58f14545 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=364483410 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_zero_delays .364483410 |
| Directory | /workspace/26.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_stress_all.2845364176 |
| Short name | T1908 |
| Test name | |
| Test status | |
| Simulation time | 2373495830 ps |
| CPU time | 182.92 seconds |
| Started | Jul 03 07:27:07 PM PDT 24 |
| Finished | Jul 03 07:30:16 PM PDT 24 |
| Peak memory | 574672 kb |
| Host | smart-be723cb3-40ff-47fa-8216-56af839cbefc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2845364176 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all.2845364176 |
| Directory | /workspace/26.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_stress_all_with_error.2488195528 |
| Short name | T2143 |
| Test name | |
| Test status | |
| Simulation time | 5096193750 ps |
| CPU time | 178.02 seconds |
| Started | Jul 03 07:27:06 PM PDT 24 |
| Finished | Jul 03 07:30:09 PM PDT 24 |
| Peak memory | 574592 kb |
| Host | smart-c8e366ba-4106-4a94-aca1-9054e0599b51 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2488195528 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_error.2488195528 |
| Directory | /workspace/26.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_stress_all_with_rand_reset.372267392 |
| Short name | T2475 |
| Test name | |
| Test status | |
| Simulation time | 1074262546 ps |
| CPU time | 382.99 seconds |
| Started | Jul 03 07:27:06 PM PDT 24 |
| Finished | Jul 03 07:33:34 PM PDT 24 |
| Peak memory | 574612 kb |
| Host | smart-8995d040-98f9-4fe2-af62-02795f7c3d74 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=372267392 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_ with_rand_reset.372267392 |
| Directory | /workspace/26.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_stress_all_with_reset_error.2117380505 |
| Short name | T1698 |
| Test name | |
| Test status | |
| Simulation time | 166003662 ps |
| CPU time | 72.31 seconds |
| Started | Jul 03 07:27:10 PM PDT 24 |
| Finished | Jul 03 07:28:28 PM PDT 24 |
| Peak memory | 574700 kb |
| Host | smart-c18145ec-797b-4230-a9e2-282dba01b0e1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2117380505 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_stress_al l_with_reset_error.2117380505 |
| Directory | /workspace/26.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_unmapped_addr.4019107194 |
| Short name | T1326 |
| Test name | |
| Test status | |
| Simulation time | 616587564 ps |
| CPU time | 26.14 seconds |
| Started | Jul 03 07:27:08 PM PDT 24 |
| Finished | Jul 03 07:27:39 PM PDT 24 |
| Peak memory | 574180 kb |
| Host | smart-94d60e9d-09fd-4293-acc7-4853ac8b7a0a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4019107194 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_unmapped_addr.4019107194 |
| Directory | /workspace/26.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/27.chip_tl_errors.2193681006 |
| Short name | T2662 |
| Test name | |
| Test status | |
| Simulation time | 2919089336 ps |
| CPU time | 163.1 seconds |
| Started | Jul 03 07:27:16 PM PDT 24 |
| Finished | Jul 03 07:30:01 PM PDT 24 |
| Peak memory | 597940 kb |
| Host | smart-387e73ea-299b-4b4d-b72c-0981ce5d0207 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2193681006 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.chip_tl_errors.2193681006 |
| Directory | /workspace/27.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_access_same_device.4022159917 |
| Short name | T451 |
| Test name | |
| Test status | |
| Simulation time | 2475518070 ps |
| CPU time | 99.93 seconds |
| Started | Jul 03 07:27:23 PM PDT 24 |
| Finished | Jul 03 07:29:04 PM PDT 24 |
| Peak memory | 574332 kb |
| Host | smart-3d3c3e8c-5ae4-4b55-bc60-273bc251ce1d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4022159917 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_access_same_device .4022159917 |
| Directory | /workspace/27.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_access_same_device_slow_rsp.1136221134 |
| Short name | T1837 |
| Test name | |
| Test status | |
| Simulation time | 9571141455 ps |
| CPU time | 171.88 seconds |
| Started | Jul 03 07:27:19 PM PDT 24 |
| Finished | Jul 03 07:30:12 PM PDT 24 |
| Peak memory | 574284 kb |
| Host | smart-e309ceb2-c7b3-4395-ba58-5c138f9f249f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1136221134 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_access_same_ device_slow_rsp.1136221134 |
| Directory | /workspace/27.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_error_and_unmapped_addr.2337487108 |
| Short name | T2160 |
| Test name | |
| Test status | |
| Simulation time | 519745773 ps |
| CPU time | 26.62 seconds |
| Started | Jul 03 07:27:22 PM PDT 24 |
| Finished | Jul 03 07:27:50 PM PDT 24 |
| Peak memory | 574492 kb |
| Host | smart-80d5bffd-f708-4806-865f-f080ca076854 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2337487108 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_error_and_unmapped_add r.2337487108 |
| Directory | /workspace/27.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_error_random.2537352371 |
| Short name | T2453 |
| Test name | |
| Test status | |
| Simulation time | 200927167 ps |
| CPU time | 20.36 seconds |
| Started | Jul 03 07:27:20 PM PDT 24 |
| Finished | Jul 03 07:27:41 PM PDT 24 |
| Peak memory | 574036 kb |
| Host | smart-7c83e92c-c947-445a-a35b-f888993dfe9f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537352371 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_error_random.2537352371 |
| Directory | /workspace/27.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_random.3861348102 |
| Short name | T2562 |
| Test name | |
| Test status | |
| Simulation time | 1612561461 ps |
| CPU time | 63.13 seconds |
| Started | Jul 03 07:27:15 PM PDT 24 |
| Finished | Jul 03 07:28:21 PM PDT 24 |
| Peak memory | 574236 kb |
| Host | smart-e18c9eb3-b122-431c-ab4f-69c2282cffd6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3861348102 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_random.3861348102 |
| Directory | /workspace/27.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_random_large_delays.2608338642 |
| Short name | T1316 |
| Test name | |
| Test status | |
| Simulation time | 78829091252 ps |
| CPU time | 800.64 seconds |
| Started | Jul 03 07:27:18 PM PDT 24 |
| Finished | Jul 03 07:40:40 PM PDT 24 |
| Peak memory | 574332 kb |
| Host | smart-303510a4-bce1-4806-86fe-b4fb228a7bb2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2608338642 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_random_large_delays.2608338642 |
| Directory | /workspace/27.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_random_slow_rsp.915406073 |
| Short name | T2802 |
| Test name | |
| Test status | |
| Simulation time | 60655983075 ps |
| CPU time | 1051.64 seconds |
| Started | Jul 03 07:27:19 PM PDT 24 |
| Finished | Jul 03 07:44:52 PM PDT 24 |
| Peak memory | 574144 kb |
| Host | smart-2832cf05-29b6-40f8-956f-7285710c85c2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=915406073 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_random_slow_rsp.915406073 |
| Directory | /workspace/27.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_random_zero_delays.1905120898 |
| Short name | T2627 |
| Test name | |
| Test status | |
| Simulation time | 334426918 ps |
| CPU time | 33.46 seconds |
| Started | Jul 03 07:27:18 PM PDT 24 |
| Finished | Jul 03 07:27:53 PM PDT 24 |
| Peak memory | 574220 kb |
| Host | smart-0ab7a7ac-b135-4c86-81b8-3cd1e5402e45 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1905120898 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_random_zero_del ays.1905120898 |
| Directory | /workspace/27.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_same_source.1650905003 |
| Short name | T2050 |
| Test name | |
| Test status | |
| Simulation time | 1337977633 ps |
| CPU time | 44.56 seconds |
| Started | Jul 03 07:27:22 PM PDT 24 |
| Finished | Jul 03 07:28:08 PM PDT 24 |
| Peak memory | 574004 kb |
| Host | smart-c7ab872c-339f-43cb-9cc3-1fef8ec7fefa |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1650905003 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_same_source.1650905003 |
| Directory | /workspace/27.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_smoke.3160604259 |
| Short name | T2198 |
| Test name | |
| Test status | |
| Simulation time | 121311715 ps |
| CPU time | 6.83 seconds |
| Started | Jul 03 07:27:13 PM PDT 24 |
| Finished | Jul 03 07:27:24 PM PDT 24 |
| Peak memory | 573144 kb |
| Host | smart-2cf371cd-e136-4883-8e92-dfa76607e541 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3160604259 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_smoke.3160604259 |
| Directory | /workspace/27.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_smoke_large_delays.2076034907 |
| Short name | T1668 |
| Test name | |
| Test status | |
| Simulation time | 7055049368 ps |
| CPU time | 69.68 seconds |
| Started | Jul 03 07:27:13 PM PDT 24 |
| Finished | Jul 03 07:28:27 PM PDT 24 |
| Peak memory | 574220 kb |
| Host | smart-39b6fbc4-98a1-4f89-ae3a-86b6d1d9e1c1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2076034907 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_large_delays.2076034907 |
| Directory | /workspace/27.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_smoke_slow_rsp.1594613985 |
| Short name | T2240 |
| Test name | |
| Test status | |
| Simulation time | 5318316053 ps |
| CPU time | 92.3 seconds |
| Started | Jul 03 07:27:14 PM PDT 24 |
| Finished | Jul 03 07:28:50 PM PDT 24 |
| Peak memory | 574016 kb |
| Host | smart-4e40c89c-c407-4355-ac5e-9e0bd7228a2f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1594613985 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_slow_rsp.1594613985 |
| Directory | /workspace/27.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_smoke_zero_delays.1814996984 |
| Short name | T2374 |
| Test name | |
| Test status | |
| Simulation time | 51504456 ps |
| CPU time | 7.07 seconds |
| Started | Jul 03 07:27:14 PM PDT 24 |
| Finished | Jul 03 07:27:25 PM PDT 24 |
| Peak memory | 574072 kb |
| Host | smart-04f22546-e861-45fc-9bb3-deaa384511a1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1814996984 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_zero_delay s.1814996984 |
| Directory | /workspace/27.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_stress_all.1530105743 |
| Short name | T461 |
| Test name | |
| Test status | |
| Simulation time | 8154739024 ps |
| CPU time | 314.49 seconds |
| Started | Jul 03 07:27:23 PM PDT 24 |
| Finished | Jul 03 07:32:39 PM PDT 24 |
| Peak memory | 574752 kb |
| Host | smart-5f20599f-c55a-4921-8667-066c8f1824ea |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1530105743 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all.1530105743 |
| Directory | /workspace/27.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_stress_all_with_error.2167377151 |
| Short name | T2578 |
| Test name | |
| Test status | |
| Simulation time | 3574066896 ps |
| CPU time | 273.67 seconds |
| Started | Jul 03 07:27:25 PM PDT 24 |
| Finished | Jul 03 07:32:00 PM PDT 24 |
| Peak memory | 574244 kb |
| Host | smart-7a5ffee7-d9c4-41e4-9d22-000600b27301 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2167377151 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_error.2167377151 |
| Directory | /workspace/27.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_stress_all_with_rand_reset.4073136941 |
| Short name | T2103 |
| Test name | |
| Test status | |
| Simulation time | 281337542 ps |
| CPU time | 111.61 seconds |
| Started | Jul 03 07:27:30 PM PDT 24 |
| Finished | Jul 03 07:29:24 PM PDT 24 |
| Peak memory | 574624 kb |
| Host | smart-0b442a4a-57f8-4f10-8dd7-2e822e5cf69d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073136941 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all _with_rand_reset.4073136941 |
| Directory | /workspace/27.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_stress_all_with_reset_error.2936428066 |
| Short name | T2439 |
| Test name | |
| Test status | |
| Simulation time | 5662809228 ps |
| CPU time | 266.82 seconds |
| Started | Jul 03 07:27:25 PM PDT 24 |
| Finished | Jul 03 07:31:54 PM PDT 24 |
| Peak memory | 574756 kb |
| Host | smart-36ed7bf9-1647-4c92-805c-43e7f2e8d14f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2936428066 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_stress_al l_with_reset_error.2936428066 |
| Directory | /workspace/27.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_unmapped_addr.2944873146 |
| Short name | T1476 |
| Test name | |
| Test status | |
| Simulation time | 129790234 ps |
| CPU time | 18.06 seconds |
| Started | Jul 03 07:27:18 PM PDT 24 |
| Finished | Jul 03 07:27:38 PM PDT 24 |
| Peak memory | 574024 kb |
| Host | smart-c834f666-6f9d-43f3-a264-353fb4f61faf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2944873146 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_unmapped_addr.2944873146 |
| Directory | /workspace/27.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/28.chip_tl_errors.3937319672 |
| Short name | T640 |
| Test name | |
| Test status | |
| Simulation time | 3240245264 ps |
| CPU time | 137.98 seconds |
| Started | Jul 03 07:27:24 PM PDT 24 |
| Finished | Jul 03 07:29:43 PM PDT 24 |
| Peak memory | 598064 kb |
| Host | smart-a5788751-c216-45e8-b31e-fa1d9231e46d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3937319672 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.chip_tl_errors.3937319672 |
| Directory | /workspace/28.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_access_same_device.883577973 |
| Short name | T1675 |
| Test name | |
| Test status | |
| Simulation time | 401355527 ps |
| CPU time | 33.49 seconds |
| Started | Jul 03 07:27:30 PM PDT 24 |
| Finished | Jul 03 07:28:06 PM PDT 24 |
| Peak memory | 574228 kb |
| Host | smart-a6b55808-4185-4ab9-ae7d-304022831167 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=883577973 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_access_same_device. 883577973 |
| Directory | /workspace/28.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_access_same_device_slow_rsp.3067215863 |
| Short name | T2586 |
| Test name | |
| Test status | |
| Simulation time | 106373355019 ps |
| CPU time | 1896.87 seconds |
| Started | Jul 03 07:27:31 PM PDT 24 |
| Finished | Jul 03 07:59:11 PM PDT 24 |
| Peak memory | 574216 kb |
| Host | smart-1b87c36e-cfbd-4a16-bb6a-ecde5f9ab3b9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3067215863 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_access_same_ device_slow_rsp.3067215863 |
| Directory | /workspace/28.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_error_and_unmapped_addr.1102967781 |
| Short name | T2332 |
| Test name | |
| Test status | |
| Simulation time | 764478555 ps |
| CPU time | 33.49 seconds |
| Started | Jul 03 07:27:31 PM PDT 24 |
| Finished | Jul 03 07:28:08 PM PDT 24 |
| Peak memory | 574472 kb |
| Host | smart-a372169c-0d43-45ac-9d50-071519bfba5d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1102967781 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_error_and_unmapped_add r.1102967781 |
| Directory | /workspace/28.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_error_random.2964323290 |
| Short name | T1594 |
| Test name | |
| Test status | |
| Simulation time | 183397329 ps |
| CPU time | 10.01 seconds |
| Started | Jul 03 07:27:30 PM PDT 24 |
| Finished | Jul 03 07:27:42 PM PDT 24 |
| Peak memory | 573984 kb |
| Host | smart-714eaa74-83d9-4a22-9871-a75ef623ffdc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2964323290 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_error_random.2964323290 |
| Directory | /workspace/28.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_random.1206457854 |
| Short name | T1669 |
| Test name | |
| Test status | |
| Simulation time | 238898332 ps |
| CPU time | 24.56 seconds |
| Started | Jul 03 07:27:29 PM PDT 24 |
| Finished | Jul 03 07:27:56 PM PDT 24 |
| Peak memory | 573952 kb |
| Host | smart-810b1c5d-0219-41b7-a55b-409cc2b80fcc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206457854 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_random.1206457854 |
| Directory | /workspace/28.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_random_large_delays.3714520482 |
| Short name | T1504 |
| Test name | |
| Test status | |
| Simulation time | 27004204380 ps |
| CPU time | 281.82 seconds |
| Started | Jul 03 07:27:25 PM PDT 24 |
| Finished | Jul 03 07:32:09 PM PDT 24 |
| Peak memory | 574060 kb |
| Host | smart-6f4e027f-1f0f-4a23-a99b-c02ab70b716c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714520482 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_random_large_delays.3714520482 |
| Directory | /workspace/28.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_random_slow_rsp.466685398 |
| Short name | T524 |
| Test name | |
| Test status | |
| Simulation time | 20925084080 ps |
| CPU time | 371.43 seconds |
| Started | Jul 03 07:27:24 PM PDT 24 |
| Finished | Jul 03 07:33:37 PM PDT 24 |
| Peak memory | 574360 kb |
| Host | smart-06d6cd04-675e-48f9-8161-f09c2ba38ab7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=466685398 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_random_slow_rsp.466685398 |
| Directory | /workspace/28.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_random_zero_delays.4279402948 |
| Short name | T526 |
| Test name | |
| Test status | |
| Simulation time | 537418288 ps |
| CPU time | 49.68 seconds |
| Started | Jul 03 07:27:29 PM PDT 24 |
| Finished | Jul 03 07:28:21 PM PDT 24 |
| Peak memory | 573988 kb |
| Host | smart-f37364ef-b89e-456c-a2df-04ffebec4ac1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4279402948 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_random_zero_del ays.4279402948 |
| Directory | /workspace/28.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_same_source.655131886 |
| Short name | T2305 |
| Test name | |
| Test status | |
| Simulation time | 1540696318 ps |
| CPU time | 48.06 seconds |
| Started | Jul 03 07:27:29 PM PDT 24 |
| Finished | Jul 03 07:28:19 PM PDT 24 |
| Peak memory | 574112 kb |
| Host | smart-61d20fb1-64f1-4d69-ab21-b685393cebdc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=655131886 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_same_source.655131886 |
| Directory | /workspace/28.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_smoke.3187862201 |
| Short name | T1451 |
| Test name | |
| Test status | |
| Simulation time | 193627435 ps |
| CPU time | 8.83 seconds |
| Started | Jul 03 07:27:29 PM PDT 24 |
| Finished | Jul 03 07:27:40 PM PDT 24 |
| Peak memory | 573132 kb |
| Host | smart-8d0a8575-ce48-4357-abde-246eba2bb1b1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3187862201 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_smoke.3187862201 |
| Directory | /workspace/28.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_smoke_large_delays.4172686398 |
| Short name | T1981 |
| Test name | |
| Test status | |
| Simulation time | 8831756387 ps |
| CPU time | 93.41 seconds |
| Started | Jul 03 07:27:25 PM PDT 24 |
| Finished | Jul 03 07:29:00 PM PDT 24 |
| Peak memory | 573052 kb |
| Host | smart-8638453c-3079-473d-ac39-515759929497 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4172686398 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_large_delays.4172686398 |
| Directory | /workspace/28.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_smoke_slow_rsp.2337429223 |
| Short name | T2822 |
| Test name | |
| Test status | |
| Simulation time | 3778870208 ps |
| CPU time | 65.28 seconds |
| Started | Jul 03 07:27:27 PM PDT 24 |
| Finished | Jul 03 07:28:33 PM PDT 24 |
| Peak memory | 573148 kb |
| Host | smart-ed63f20f-ea12-4a91-b728-db0de7bf0700 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2337429223 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_slow_rsp.2337429223 |
| Directory | /workspace/28.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_smoke_zero_delays.3283521577 |
| Short name | T2290 |
| Test name | |
| Test status | |
| Simulation time | 44310046 ps |
| CPU time | 6.33 seconds |
| Started | Jul 03 07:27:27 PM PDT 24 |
| Finished | Jul 03 07:27:35 PM PDT 24 |
| Peak memory | 573164 kb |
| Host | smart-0cbd1e08-1106-4666-a426-4922c38c67a4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3283521577 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_zero_delay s.3283521577 |
| Directory | /workspace/28.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_stress_all.878763143 |
| Short name | T2146 |
| Test name | |
| Test status | |
| Simulation time | 1417231834 ps |
| CPU time | 51.99 seconds |
| Started | Jul 03 07:27:31 PM PDT 24 |
| Finished | Jul 03 07:28:26 PM PDT 24 |
| Peak memory | 574260 kb |
| Host | smart-e7768644-256e-461b-95d1-61169c60e4a8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=878763143 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all.878763143 |
| Directory | /workspace/28.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_stress_all_with_error.2541063932 |
| Short name | T2696 |
| Test name | |
| Test status | |
| Simulation time | 1330048693 ps |
| CPU time | 85.93 seconds |
| Started | Jul 03 07:27:31 PM PDT 24 |
| Finished | Jul 03 07:28:59 PM PDT 24 |
| Peak memory | 574100 kb |
| Host | smart-7cd45834-7084-4f4f-8984-f51cd0c7380e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2541063932 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_error.2541063932 |
| Directory | /workspace/28.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_stress_all_with_reset_error.1016936812 |
| Short name | T2249 |
| Test name | |
| Test status | |
| Simulation time | 3755731515 ps |
| CPU time | 385.39 seconds |
| Started | Jul 03 07:27:30 PM PDT 24 |
| Finished | Jul 03 07:33:58 PM PDT 24 |
| Peak memory | 574708 kb |
| Host | smart-b9b2d8d2-7ec2-4c39-88d1-9393bca327b5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1016936812 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_stress_al l_with_reset_error.1016936812 |
| Directory | /workspace/28.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_unmapped_addr.161980482 |
| Short name | T2205 |
| Test name | |
| Test status | |
| Simulation time | 108505985 ps |
| CPU time | 14.84 seconds |
| Started | Jul 03 07:27:31 PM PDT 24 |
| Finished | Jul 03 07:27:48 PM PDT 24 |
| Peak memory | 574256 kb |
| Host | smart-399c8063-10ca-476d-ba29-dcc82b292930 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=161980482 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_unmapped_addr.161980482 |
| Directory | /workspace/28.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/29.chip_tl_errors.1594440437 |
| Short name | T1409 |
| Test name | |
| Test status | |
| Simulation time | 2841122313 ps |
| CPU time | 105.58 seconds |
| Started | Jul 03 07:27:32 PM PDT 24 |
| Finished | Jul 03 07:29:21 PM PDT 24 |
| Peak memory | 595988 kb |
| Host | smart-a46e10fb-2f06-48b4-a512-fac2d9d906bb |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1594440437 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.chip_tl_errors.1594440437 |
| Directory | /workspace/29.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_access_same_device.2213862449 |
| Short name | T2884 |
| Test name | |
| Test status | |
| Simulation time | 2084253226 ps |
| CPU time | 87.72 seconds |
| Started | Jul 03 07:27:41 PM PDT 24 |
| Finished | Jul 03 07:29:10 PM PDT 24 |
| Peak memory | 574160 kb |
| Host | smart-d0a9944b-3d3a-46a8-979a-e9802be7c022 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2213862449 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_access_same_device .2213862449 |
| Directory | /workspace/29.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_access_same_device_slow_rsp.2167494381 |
| Short name | T2765 |
| Test name | |
| Test status | |
| Simulation time | 23617935098 ps |
| CPU time | 426.66 seconds |
| Started | Jul 03 07:27:41 PM PDT 24 |
| Finished | Jul 03 07:34:50 PM PDT 24 |
| Peak memory | 574196 kb |
| Host | smart-349463bc-e515-4aa3-998f-351a539f5f7a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2167494381 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_access_same_ device_slow_rsp.2167494381 |
| Directory | /workspace/29.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_error_and_unmapped_addr.2325097815 |
| Short name | T2691 |
| Test name | |
| Test status | |
| Simulation time | 329557160 ps |
| CPU time | 33.87 seconds |
| Started | Jul 03 07:27:43 PM PDT 24 |
| Finished | Jul 03 07:28:18 PM PDT 24 |
| Peak memory | 574052 kb |
| Host | smart-58ad4ee5-af26-42b6-a9dd-2b358da8ea60 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2325097815 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_error_and_unmapped_add r.2325097815 |
| Directory | /workspace/29.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_error_random.948717905 |
| Short name | T1951 |
| Test name | |
| Test status | |
| Simulation time | 253539559 ps |
| CPU time | 22.87 seconds |
| Started | Jul 03 07:27:40 PM PDT 24 |
| Finished | Jul 03 07:28:04 PM PDT 24 |
| Peak memory | 574480 kb |
| Host | smart-b6acd059-167a-4858-bcce-2e23a051b9b9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=948717905 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_error_random.948717905 |
| Directory | /workspace/29.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_random.1409795179 |
| Short name | T1531 |
| Test name | |
| Test status | |
| Simulation time | 1075715572 ps |
| CPU time | 45.97 seconds |
| Started | Jul 03 07:27:35 PM PDT 24 |
| Finished | Jul 03 07:28:22 PM PDT 24 |
| Peak memory | 574220 kb |
| Host | smart-abb97df0-b73c-4243-a50f-d8c37407272f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1409795179 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_random.1409795179 |
| Directory | /workspace/29.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_random_large_delays.3757438054 |
| Short name | T2032 |
| Test name | |
| Test status | |
| Simulation time | 48777788267 ps |
| CPU time | 501.77 seconds |
| Started | Jul 03 07:27:42 PM PDT 24 |
| Finished | Jul 03 07:36:05 PM PDT 24 |
| Peak memory | 574240 kb |
| Host | smart-100ed8c5-9112-4c13-a595-7c9118a12af7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3757438054 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_random_large_delays.3757438054 |
| Directory | /workspace/29.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_random_slow_rsp.2689729191 |
| Short name | T1412 |
| Test name | |
| Test status | |
| Simulation time | 17726595127 ps |
| CPU time | 296.19 seconds |
| Started | Jul 03 07:27:41 PM PDT 24 |
| Finished | Jul 03 07:32:39 PM PDT 24 |
| Peak memory | 574080 kb |
| Host | smart-16f95b09-bee1-4f09-8f4d-1cd556f1bdd1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2689729191 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_random_slow_rsp.2689729191 |
| Directory | /workspace/29.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_random_zero_delays.1314890404 |
| Short name | T1917 |
| Test name | |
| Test status | |
| Simulation time | 525547467 ps |
| CPU time | 46.56 seconds |
| Started | Jul 03 07:27:37 PM PDT 24 |
| Finished | Jul 03 07:28:25 PM PDT 24 |
| Peak memory | 574240 kb |
| Host | smart-4684a945-b3c2-486d-9f1c-1e7589fa7abe |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1314890404 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_random_zero_del ays.1314890404 |
| Directory | /workspace/29.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_same_source.1104162182 |
| Short name | T2272 |
| Test name | |
| Test status | |
| Simulation time | 103685140 ps |
| CPU time | 10.04 seconds |
| Started | Jul 03 07:27:42 PM PDT 24 |
| Finished | Jul 03 07:27:54 PM PDT 24 |
| Peak memory | 574192 kb |
| Host | smart-75de1f18-3e69-449f-ac79-b13d5dc833c8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1104162182 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_same_source.1104162182 |
| Directory | /workspace/29.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_smoke.3989659713 |
| Short name | T2590 |
| Test name | |
| Test status | |
| Simulation time | 261331936 ps |
| CPU time | 11.52 seconds |
| Started | Jul 03 07:27:38 PM PDT 24 |
| Finished | Jul 03 07:27:50 PM PDT 24 |
| Peak memory | 573036 kb |
| Host | smart-b32ffa3c-2937-45e1-acc6-038085f642cd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3989659713 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_smoke.3989659713 |
| Directory | /workspace/29.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_smoke_large_delays.1405481373 |
| Short name | T2110 |
| Test name | |
| Test status | |
| Simulation time | 5628759688 ps |
| CPU time | 57.21 seconds |
| Started | Jul 03 07:27:37 PM PDT 24 |
| Finished | Jul 03 07:28:35 PM PDT 24 |
| Peak memory | 574172 kb |
| Host | smart-4fa48f0c-a701-46f3-a0bb-1d98a3936ba9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1405481373 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_large_delays.1405481373 |
| Directory | /workspace/29.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_smoke_slow_rsp.533001333 |
| Short name | T2307 |
| Test name | |
| Test status | |
| Simulation time | 4643266086 ps |
| CPU time | 80.77 seconds |
| Started | Jul 03 07:27:35 PM PDT 24 |
| Finished | Jul 03 07:28:57 PM PDT 24 |
| Peak memory | 573028 kb |
| Host | smart-15fd17dc-52a6-4dc6-aa7f-62f463e6e972 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=533001333 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_slow_rsp.533001333 |
| Directory | /workspace/29.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_smoke_zero_delays.2359436426 |
| Short name | T1673 |
| Test name | |
| Test status | |
| Simulation time | 41999595 ps |
| CPU time | 6.27 seconds |
| Started | Jul 03 07:27:38 PM PDT 24 |
| Finished | Jul 03 07:27:45 PM PDT 24 |
| Peak memory | 574204 kb |
| Host | smart-c43cfa88-9a79-4e3a-af47-7296c656b568 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2359436426 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_zero_delay s.2359436426 |
| Directory | /workspace/29.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_stress_all.3624113378 |
| Short name | T1679 |
| Test name | |
| Test status | |
| Simulation time | 3427782575 ps |
| CPU time | 295.8 seconds |
| Started | Jul 03 07:27:42 PM PDT 24 |
| Finished | Jul 03 07:32:40 PM PDT 24 |
| Peak memory | 574720 kb |
| Host | smart-ce0e1ea4-0d49-4653-9e58-88095957f9ff |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3624113378 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all.3624113378 |
| Directory | /workspace/29.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_stress_all_with_error.3962229488 |
| Short name | T2191 |
| Test name | |
| Test status | |
| Simulation time | 13987058243 ps |
| CPU time | 453.51 seconds |
| Started | Jul 03 07:27:46 PM PDT 24 |
| Finished | Jul 03 07:35:22 PM PDT 24 |
| Peak memory | 574676 kb |
| Host | smart-7a331203-145f-4adc-8a77-e063ea53e09c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3962229488 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_error.3962229488 |
| Directory | /workspace/29.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_stress_all_with_rand_reset.3326545886 |
| Short name | T1443 |
| Test name | |
| Test status | |
| Simulation time | 8403131678 ps |
| CPU time | 486.4 seconds |
| Started | Jul 03 07:27:47 PM PDT 24 |
| Finished | Jul 03 07:35:56 PM PDT 24 |
| Peak memory | 574732 kb |
| Host | smart-40d7850d-d66a-484c-8d13-eb876331cbd0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3326545886 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all _with_rand_reset.3326545886 |
| Directory | /workspace/29.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_stress_all_with_reset_error.3733930772 |
| Short name | T2742 |
| Test name | |
| Test status | |
| Simulation time | 154233848 ps |
| CPU time | 25.46 seconds |
| Started | Jul 03 07:27:47 PM PDT 24 |
| Finished | Jul 03 07:28:15 PM PDT 24 |
| Peak memory | 574504 kb |
| Host | smart-d519da66-726d-4ba3-bba5-0e29f849e851 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3733930772 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_stress_al l_with_reset_error.3733930772 |
| Directory | /workspace/29.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_unmapped_addr.1090742368 |
| Short name | T1667 |
| Test name | |
| Test status | |
| Simulation time | 1513834818 ps |
| CPU time | 61.59 seconds |
| Started | Jul 03 07:27:43 PM PDT 24 |
| Finished | Jul 03 07:28:47 PM PDT 24 |
| Peak memory | 574280 kb |
| Host | smart-74425e3f-2fb6-47be-a48e-3a8914846a17 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1090742368 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_unmapped_addr.1090742368 |
| Directory | /workspace/29.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/3.chip_csr_aliasing.3299137303 |
| Short name | T390 |
| Test name | |
| Test status | |
| Simulation time | 35086937758 ps |
| CPU time | 5405.65 seconds |
| Started | Jul 03 07:22:27 PM PDT 24 |
| Finished | Jul 03 08:52:35 PM PDT 24 |
| Peak memory | 592776 kb |
| Host | smart-470317e5-f317-42cc-9182-c819853256de |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +csr_aliasing +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3299137303 -assert nopostproc +UVM_TESTNAME=chip_ base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 3.chip_csr_aliasing.3299137303 |
| Directory | /workspace/3.chip_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/3.chip_csr_bit_bash.3632130049 |
| Short name | T2613 |
| Test name | |
| Test status | |
| Simulation time | 11457366724 ps |
| CPU time | 1041.68 seconds |
| Started | Jul 03 07:22:27 PM PDT 24 |
| Finished | Jul 03 07:39:50 PM PDT 24 |
| Peak memory | 590876 kb |
| Host | smart-cb691344-5d1c-4640-89f3-e39b3776e171 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +num_test_csrs=200 +csr_bit_bash +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3632130049 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 3.chip_csr_bit_bash.3632130049 |
| Directory | /workspace/3.chip_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/3.chip_csr_hw_reset.2488207182 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 5594779064 ps |
| CPU time | 399.6 seconds |
| Started | Jul 03 07:22:38 PM PDT 24 |
| Finished | Jul 03 07:29:20 PM PDT 24 |
| Peak memory | 660920 kb |
| Host | smart-700515b5-7747-41fc-a91c-2586656776b2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2488207182 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.chip_csr_hw_r eset.2488207182 |
| Directory | /workspace/3.chip_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/3.chip_csr_rw.4245223195 |
| Short name | T1628 |
| Test name | |
| Test status | |
| Simulation time | 4101782465 ps |
| CPU time | 377.98 seconds |
| Started | Jul 03 07:22:45 PM PDT 24 |
| Finished | Jul 03 07:29:04 PM PDT 24 |
| Peak memory | 596656 kb |
| Host | smart-8187d698-cddd-43fb-87c8-7be39d0c41ed |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4245223195 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.chip_csr_rw.4245223195 |
| Directory | /workspace/3.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_access_same_device.2403678614 |
| Short name | T2464 |
| Test name | |
| Test status | |
| Simulation time | 416590818 ps |
| CPU time | 30.25 seconds |
| Started | Jul 03 07:22:33 PM PDT 24 |
| Finished | Jul 03 07:23:05 PM PDT 24 |
| Peak memory | 574192 kb |
| Host | smart-2c7c5929-cd9e-4869-a533-93f70c89bc2c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2403678614 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_access_same_device. 2403678614 |
| Directory | /workspace/3.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_access_same_device_slow_rsp.2307666946 |
| Short name | T789 |
| Test name | |
| Test status | |
| Simulation time | 33343249308 ps |
| CPU time | 546.2 seconds |
| Started | Jul 03 07:22:34 PM PDT 24 |
| Finished | Jul 03 07:31:43 PM PDT 24 |
| Peak memory | 574220 kb |
| Host | smart-2a3cb1e9-dcdc-4686-be0b-70f7f6543b89 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2307666946 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_access_same_d evice_slow_rsp.2307666946 |
| Directory | /workspace/3.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_error_and_unmapped_addr.3814479216 |
| Short name | T1939 |
| Test name | |
| Test status | |
| Simulation time | 537695035 ps |
| CPU time | 23.3 seconds |
| Started | Jul 03 07:22:36 PM PDT 24 |
| Finished | Jul 03 07:23:02 PM PDT 24 |
| Peak memory | 574496 kb |
| Host | smart-62bdf122-5aa5-4c84-8e06-63db44fc073b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3814479216 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_error_and_unmapped_addr .3814479216 |
| Directory | /workspace/3.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_error_random.3259450214 |
| Short name | T2621 |
| Test name | |
| Test status | |
| Simulation time | 139001279 ps |
| CPU time | 15.23 seconds |
| Started | Jul 03 07:22:31 PM PDT 24 |
| Finished | Jul 03 07:22:48 PM PDT 24 |
| Peak memory | 574528 kb |
| Host | smart-45c3d062-c801-44e8-b1dd-0f262ed834ce |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3259450214 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_error_random.3259450214 |
| Directory | /workspace/3.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_random.4072192694 |
| Short name | T2397 |
| Test name | |
| Test status | |
| Simulation time | 105848164 ps |
| CPU time | 13.53 seconds |
| Started | Jul 03 07:22:26 PM PDT 24 |
| Finished | Jul 03 07:22:41 PM PDT 24 |
| Peak memory | 574020 kb |
| Host | smart-680b43a7-2331-41d5-9641-6aeb68e36a21 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4072192694 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_random.4072192694 |
| Directory | /workspace/3.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_random_large_delays.1855693821 |
| Short name | T2461 |
| Test name | |
| Test status | |
| Simulation time | 84737566763 ps |
| CPU time | 887.38 seconds |
| Started | Jul 03 07:22:26 PM PDT 24 |
| Finished | Jul 03 07:37:15 PM PDT 24 |
| Peak memory | 574120 kb |
| Host | smart-9cf968f1-e378-4415-962f-084f76b0d305 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1855693821 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_random_large_delays.1855693821 |
| Directory | /workspace/3.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_random_slow_rsp.435721310 |
| Short name | T2414 |
| Test name | |
| Test status | |
| Simulation time | 62996348173 ps |
| CPU time | 1139 seconds |
| Started | Jul 03 07:22:28 PM PDT 24 |
| Finished | Jul 03 07:41:29 PM PDT 24 |
| Peak memory | 574272 kb |
| Host | smart-c6bd9a82-b21e-4707-a076-427c36145952 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=435721310 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_random_slow_rsp.435721310 |
| Directory | /workspace/3.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_random_zero_delays.851072917 |
| Short name | T2117 |
| Test name | |
| Test status | |
| Simulation time | 206238913 ps |
| CPU time | 19.4 seconds |
| Started | Jul 03 07:22:34 PM PDT 24 |
| Finished | Jul 03 07:22:56 PM PDT 24 |
| Peak memory | 573968 kb |
| Host | smart-0b49a1da-3eb9-4769-b02a-ce82cb53ab2f |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=851072917 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_random_zero_delay s.851072917 |
| Directory | /workspace/3.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_same_source.1197026853 |
| Short name | T2735 |
| Test name | |
| Test status | |
| Simulation time | 237711184 ps |
| CPU time | 9.95 seconds |
| Started | Jul 03 07:22:32 PM PDT 24 |
| Finished | Jul 03 07:22:44 PM PDT 24 |
| Peak memory | 573144 kb |
| Host | smart-90e492ff-e087-4d88-8bc4-d9e74ab9be46 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1197026853 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_same_source.1197026853 |
| Directory | /workspace/3.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_smoke.1150786935 |
| Short name | T2849 |
| Test name | |
| Test status | |
| Simulation time | 191053733 ps |
| CPU time | 7.66 seconds |
| Started | Jul 03 07:22:26 PM PDT 24 |
| Finished | Jul 03 07:22:35 PM PDT 24 |
| Peak memory | 573932 kb |
| Host | smart-5e9f41cf-3a8b-4ee1-840e-d9615b8fac9d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1150786935 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_smoke.1150786935 |
| Directory | /workspace/3.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_smoke_large_delays.2141051258 |
| Short name | T2173 |
| Test name | |
| Test status | |
| Simulation time | 7764003043 ps |
| CPU time | 84.26 seconds |
| Started | Jul 03 07:22:28 PM PDT 24 |
| Finished | Jul 03 07:23:54 PM PDT 24 |
| Peak memory | 573200 kb |
| Host | smart-21f9fb9e-78f2-4060-a24d-0340d2b5fa42 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2141051258 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_large_delays.2141051258 |
| Directory | /workspace/3.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_smoke_slow_rsp.2859348290 |
| Short name | T1307 |
| Test name | |
| Test status | |
| Simulation time | 2862501575 ps |
| CPU time | 51.72 seconds |
| Started | Jul 03 07:22:26 PM PDT 24 |
| Finished | Jul 03 07:23:19 PM PDT 24 |
| Peak memory | 573212 kb |
| Host | smart-059cd655-efb5-4f87-9db2-deb889847251 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2859348290 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_slow_rsp.2859348290 |
| Directory | /workspace/3.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_smoke_zero_delays.2835357486 |
| Short name | T2264 |
| Test name | |
| Test status | |
| Simulation time | 47266855 ps |
| CPU time | 6.08 seconds |
| Started | Jul 03 07:22:34 PM PDT 24 |
| Finished | Jul 03 07:22:43 PM PDT 24 |
| Peak memory | 573120 kb |
| Host | smart-f4e895e1-e8a3-49a4-a575-1c33fb4815f1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2835357486 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_zero_delays .2835357486 |
| Directory | /workspace/3.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_stress_all.3260744909 |
| Short name | T2538 |
| Test name | |
| Test status | |
| Simulation time | 2310414198 ps |
| CPU time | 78.49 seconds |
| Started | Jul 03 07:22:33 PM PDT 24 |
| Finished | Jul 03 07:23:54 PM PDT 24 |
| Peak memory | 574064 kb |
| Host | smart-61a4e52e-2a44-428a-957b-d117a5c6a541 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260744909 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all.3260744909 |
| Directory | /workspace/3.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_stress_all_with_error.456948987 |
| Short name | T2437 |
| Test name | |
| Test status | |
| Simulation time | 13901342429 ps |
| CPU time | 517.87 seconds |
| Started | Jul 03 07:22:42 PM PDT 24 |
| Finished | Jul 03 07:31:22 PM PDT 24 |
| Peak memory | 574212 kb |
| Host | smart-48fa3029-148b-414d-8099-2560725c6344 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456948987 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_error.456948987 |
| Directory | /workspace/3.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_stress_all_with_rand_reset.593375195 |
| Short name | T441 |
| Test name | |
| Test status | |
| Simulation time | 3626597940 ps |
| CPU time | 483.34 seconds |
| Started | Jul 03 07:22:33 PM PDT 24 |
| Finished | Jul 03 07:30:40 PM PDT 24 |
| Peak memory | 574728 kb |
| Host | smart-1592f0a5-f55b-4658-9d0e-1d33ee3b31c6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=593375195 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_w ith_rand_reset.593375195 |
| Directory | /workspace/3.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_unmapped_addr.2581933695 |
| Short name | T1760 |
| Test name | |
| Test status | |
| Simulation time | 838634161 ps |
| CPU time | 38.63 seconds |
| Started | Jul 03 07:22:32 PM PDT 24 |
| Finished | Jul 03 07:23:12 PM PDT 24 |
| Peak memory | 574292 kb |
| Host | smart-3ba9ddee-e6cb-4ef1-b835-3da7dfc9b786 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581933695 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_unmapped_addr.2581933695 |
| Directory | /workspace/3.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_access_same_device.2431823334 |
| Short name | T2394 |
| Test name | |
| Test status | |
| Simulation time | 2138929268 ps |
| CPU time | 88.62 seconds |
| Started | Jul 03 07:27:59 PM PDT 24 |
| Finished | Jul 03 07:29:29 PM PDT 24 |
| Peak memory | 574216 kb |
| Host | smart-0b181d29-1231-46d3-8aea-855ad347e243 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2431823334 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_access_same_device .2431823334 |
| Directory | /workspace/30.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_access_same_device_slow_rsp.2453622214 |
| Short name | T1766 |
| Test name | |
| Test status | |
| Simulation time | 100808485754 ps |
| CPU time | 1870.64 seconds |
| Started | Jul 03 07:27:58 PM PDT 24 |
| Finished | Jul 03 07:59:11 PM PDT 24 |
| Peak memory | 574196 kb |
| Host | smart-0cd35541-5372-4077-956c-8d15ff96ba4e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2453622214 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_access_same_ device_slow_rsp.2453622214 |
| Directory | /workspace/30.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_error_and_unmapped_addr.4163639235 |
| Short name | T1552 |
| Test name | |
| Test status | |
| Simulation time | 335734336 ps |
| CPU time | 32.8 seconds |
| Started | Jul 03 07:28:03 PM PDT 24 |
| Finished | Jul 03 07:28:38 PM PDT 24 |
| Peak memory | 574528 kb |
| Host | smart-40a247eb-5df5-4678-8b02-7225452a52f0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4163639235 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_error_and_unmapped_add r.4163639235 |
| Directory | /workspace/30.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_error_random.2168003424 |
| Short name | T1433 |
| Test name | |
| Test status | |
| Simulation time | 1198906617 ps |
| CPU time | 42.69 seconds |
| Started | Jul 03 07:27:58 PM PDT 24 |
| Finished | Jul 03 07:28:43 PM PDT 24 |
| Peak memory | 574544 kb |
| Host | smart-2acfc02a-c0c0-4969-816a-760a09df3c15 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2168003424 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_error_random.2168003424 |
| Directory | /workspace/30.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_random.942174347 |
| Short name | T2871 |
| Test name | |
| Test status | |
| Simulation time | 824537759 ps |
| CPU time | 32.52 seconds |
| Started | Jul 03 07:27:54 PM PDT 24 |
| Finished | Jul 03 07:28:30 PM PDT 24 |
| Peak memory | 574000 kb |
| Host | smart-071751c7-9551-410f-95cd-7e72689fcd39 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=942174347 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_random.942174347 |
| Directory | /workspace/30.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_random_large_delays.2179306278 |
| Short name | T2747 |
| Test name | |
| Test status | |
| Simulation time | 37724174542 ps |
| CPU time | 423.32 seconds |
| Started | Jul 03 07:27:57 PM PDT 24 |
| Finished | Jul 03 07:35:03 PM PDT 24 |
| Peak memory | 574264 kb |
| Host | smart-d1b34099-2cc1-43fd-837b-57e66202b06f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179306278 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_random_large_delays.2179306278 |
| Directory | /workspace/30.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_random_slow_rsp.1810698559 |
| Short name | T2417 |
| Test name | |
| Test status | |
| Simulation time | 16999496016 ps |
| CPU time | 305.02 seconds |
| Started | Jul 03 07:27:57 PM PDT 24 |
| Finished | Jul 03 07:33:05 PM PDT 24 |
| Peak memory | 574076 kb |
| Host | smart-ab2dc769-4790-4d99-ac50-7551b33ce47b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1810698559 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_random_slow_rsp.1810698559 |
| Directory | /workspace/30.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_random_zero_delays.2951492245 |
| Short name | T2622 |
| Test name | |
| Test status | |
| Simulation time | 388179049 ps |
| CPU time | 32.57 seconds |
| Started | Jul 03 07:27:55 PM PDT 24 |
| Finished | Jul 03 07:28:31 PM PDT 24 |
| Peak memory | 574228 kb |
| Host | smart-6a940032-89b6-4f53-8045-c4db0b0e4da1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2951492245 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_random_zero_del ays.2951492245 |
| Directory | /workspace/30.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_same_source.930387862 |
| Short name | T534 |
| Test name | |
| Test status | |
| Simulation time | 996763372 ps |
| CPU time | 27.1 seconds |
| Started | Jul 03 07:27:56 PM PDT 24 |
| Finished | Jul 03 07:28:27 PM PDT 24 |
| Peak memory | 573944 kb |
| Host | smart-b765878f-8fa1-47be-a172-d55e2e23a8a1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=930387862 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_same_source.930387862 |
| Directory | /workspace/30.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_smoke.1144451950 |
| Short name | T2518 |
| Test name | |
| Test status | |
| Simulation time | 55454268 ps |
| CPU time | 6.6 seconds |
| Started | Jul 03 07:27:47 PM PDT 24 |
| Finished | Jul 03 07:27:56 PM PDT 24 |
| Peak memory | 573156 kb |
| Host | smart-b8fd367c-4552-4e36-929d-f22995baf9ac |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1144451950 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_smoke.1144451950 |
| Directory | /workspace/30.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_smoke_large_delays.4064254004 |
| Short name | T1821 |
| Test name | |
| Test status | |
| Simulation time | 7128218340 ps |
| CPU time | 76.58 seconds |
| Started | Jul 03 07:27:53 PM PDT 24 |
| Finished | Jul 03 07:29:13 PM PDT 24 |
| Peak memory | 573260 kb |
| Host | smart-48a26da4-f62e-4612-8b80-d5d43b263728 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4064254004 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_large_delays.4064254004 |
| Directory | /workspace/30.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_smoke_slow_rsp.3139298548 |
| Short name | T1585 |
| Test name | |
| Test status | |
| Simulation time | 5372062912 ps |
| CPU time | 89.31 seconds |
| Started | Jul 03 07:27:54 PM PDT 24 |
| Finished | Jul 03 07:29:27 PM PDT 24 |
| Peak memory | 574208 kb |
| Host | smart-3b132942-438b-4ad4-bb6b-18ae9a87e554 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3139298548 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_slow_rsp.3139298548 |
| Directory | /workspace/30.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_smoke_zero_delays.1905535969 |
| Short name | T2090 |
| Test name | |
| Test status | |
| Simulation time | 40419910 ps |
| CPU time | 6.3 seconds |
| Started | Jul 03 07:27:52 PM PDT 24 |
| Finished | Jul 03 07:28:01 PM PDT 24 |
| Peak memory | 573916 kb |
| Host | smart-97106cbe-d544-4f77-9e58-e7cd3bced46d |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1905535969 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_zero_delay s.1905535969 |
| Directory | /workspace/30.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_stress_all.2131572183 |
| Short name | T2852 |
| Test name | |
| Test status | |
| Simulation time | 1936962638 ps |
| CPU time | 173.15 seconds |
| Started | Jul 03 07:28:02 PM PDT 24 |
| Finished | Jul 03 07:30:56 PM PDT 24 |
| Peak memory | 574632 kb |
| Host | smart-182c0fbe-1ef6-46fe-bfa6-41f9ec165c18 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2131572183 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all.2131572183 |
| Directory | /workspace/30.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_stress_all_with_rand_reset.3178738717 |
| Short name | T415 |
| Test name | |
| Test status | |
| Simulation time | 6667943411 ps |
| CPU time | 440.29 seconds |
| Started | Jul 03 07:28:02 PM PDT 24 |
| Finished | Jul 03 07:35:23 PM PDT 24 |
| Peak memory | 574768 kb |
| Host | smart-afb0ae03-1992-4e51-97de-971a436d3fb1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3178738717 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all _with_rand_reset.3178738717 |
| Directory | /workspace/30.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_stress_all_with_reset_error.434903912 |
| Short name | T2263 |
| Test name | |
| Test status | |
| Simulation time | 473468074 ps |
| CPU time | 101.49 seconds |
| Started | Jul 03 07:28:03 PM PDT 24 |
| Finished | Jul 03 07:29:46 PM PDT 24 |
| Peak memory | 574680 kb |
| Host | smart-689fba23-7520-41ed-bebb-ba47dd653525 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=434903912 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all _with_reset_error.434903912 |
| Directory | /workspace/30.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_unmapped_addr.1014834444 |
| Short name | T2323 |
| Test name | |
| Test status | |
| Simulation time | 85887219 ps |
| CPU time | 6.95 seconds |
| Started | Jul 03 07:28:00 PM PDT 24 |
| Finished | Jul 03 07:28:08 PM PDT 24 |
| Peak memory | 573144 kb |
| Host | smart-2535beaa-9398-495e-80a1-ea7f2d710fd0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014834444 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_unmapped_addr.1014834444 |
| Directory | /workspace/30.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_access_same_device.722018259 |
| Short name | T1791 |
| Test name | |
| Test status | |
| Simulation time | 4127941621 ps |
| CPU time | 155.24 seconds |
| Started | Jul 03 07:28:08 PM PDT 24 |
| Finished | Jul 03 07:30:45 PM PDT 24 |
| Peak memory | 574356 kb |
| Host | smart-4d816007-e8c4-4f87-9260-038dbc0e90df |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=722018259 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_access_same_device. 722018259 |
| Directory | /workspace/31.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_access_same_device_slow_rsp.2918385004 |
| Short name | T2316 |
| Test name | |
| Test status | |
| Simulation time | 50070062126 ps |
| CPU time | 911.41 seconds |
| Started | Jul 03 07:28:08 PM PDT 24 |
| Finished | Jul 03 07:43:22 PM PDT 24 |
| Peak memory | 574148 kb |
| Host | smart-ce1389d6-3035-4ef4-b37b-9043bb5b8d24 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2918385004 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_access_same_ device_slow_rsp.2918385004 |
| Directory | /workspace/31.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_error_and_unmapped_addr.3991124762 |
| Short name | T1400 |
| Test name | |
| Test status | |
| Simulation time | 53911022 ps |
| CPU time | 5.78 seconds |
| Started | Jul 03 07:28:14 PM PDT 24 |
| Finished | Jul 03 07:28:22 PM PDT 24 |
| Peak memory | 574440 kb |
| Host | smart-5717c1a7-e154-4fdd-8d8d-073ae5131c97 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3991124762 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_error_and_unmapped_add r.3991124762 |
| Directory | /workspace/31.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_error_random.3320365017 |
| Short name | T1744 |
| Test name | |
| Test status | |
| Simulation time | 1976549027 ps |
| CPU time | 60.15 seconds |
| Started | Jul 03 07:28:12 PM PDT 24 |
| Finished | Jul 03 07:29:15 PM PDT 24 |
| Peak memory | 574400 kb |
| Host | smart-8257393c-128a-451e-a51e-7fce530b4037 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3320365017 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_error_random.3320365017 |
| Directory | /workspace/31.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_random.138052943 |
| Short name | T545 |
| Test name | |
| Test status | |
| Simulation time | 1349488861 ps |
| CPU time | 51.99 seconds |
| Started | Jul 03 07:28:06 PM PDT 24 |
| Finished | Jul 03 07:29:01 PM PDT 24 |
| Peak memory | 574180 kb |
| Host | smart-922b2f0b-9cf4-4a37-b680-1913aa79d9f0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=138052943 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_random.138052943 |
| Directory | /workspace/31.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_random_large_delays.1107463602 |
| Short name | T2858 |
| Test name | |
| Test status | |
| Simulation time | 96611600981 ps |
| CPU time | 988.4 seconds |
| Started | Jul 03 07:28:08 PM PDT 24 |
| Finished | Jul 03 07:44:39 PM PDT 24 |
| Peak memory | 574300 kb |
| Host | smart-7e9a565f-ee33-45c0-ba6b-075732dc8570 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1107463602 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_random_large_delays.1107463602 |
| Directory | /workspace/31.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_random_slow_rsp.2198217980 |
| Short name | T2395 |
| Test name | |
| Test status | |
| Simulation time | 41506119840 ps |
| CPU time | 778.76 seconds |
| Started | Jul 03 07:28:08 PM PDT 24 |
| Finished | Jul 03 07:41:09 PM PDT 24 |
| Peak memory | 574260 kb |
| Host | smart-fb3011f9-0508-43a4-af38-cca0f91fe9f5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198217980 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_random_slow_rsp.2198217980 |
| Directory | /workspace/31.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_random_zero_delays.3742783195 |
| Short name | T2593 |
| Test name | |
| Test status | |
| Simulation time | 456862784 ps |
| CPU time | 41.86 seconds |
| Started | Jul 03 07:28:08 PM PDT 24 |
| Finished | Jul 03 07:28:52 PM PDT 24 |
| Peak memory | 574020 kb |
| Host | smart-c54719ab-bde0-4ef3-a159-343b3fc73e53 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3742783195 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_random_zero_del ays.3742783195 |
| Directory | /workspace/31.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_same_source.2072305860 |
| Short name | T2275 |
| Test name | |
| Test status | |
| Simulation time | 1629404104 ps |
| CPU time | 50.43 seconds |
| Started | Jul 03 07:28:12 PM PDT 24 |
| Finished | Jul 03 07:29:05 PM PDT 24 |
| Peak memory | 574124 kb |
| Host | smart-d476451d-687c-424e-adcd-33949b4d77c2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2072305860 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_same_source.2072305860 |
| Directory | /workspace/31.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_smoke.4098718263 |
| Short name | T2833 |
| Test name | |
| Test status | |
| Simulation time | 177942852 ps |
| CPU time | 7.86 seconds |
| Started | Jul 03 07:28:06 PM PDT 24 |
| Finished | Jul 03 07:28:16 PM PDT 24 |
| Peak memory | 573164 kb |
| Host | smart-19bed015-be61-4b77-ac49-b017811e92b1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4098718263 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_smoke.4098718263 |
| Directory | /workspace/31.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_smoke_large_delays.3126009002 |
| Short name | T568 |
| Test name | |
| Test status | |
| Simulation time | 7520067534 ps |
| CPU time | 78.11 seconds |
| Started | Jul 03 07:28:10 PM PDT 24 |
| Finished | Jul 03 07:29:30 PM PDT 24 |
| Peak memory | 574244 kb |
| Host | smart-6e4ad2ba-be5b-47f6-8154-c1fbf82b2622 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126009002 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_large_delays.3126009002 |
| Directory | /workspace/31.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_smoke_slow_rsp.51600911 |
| Short name | T1855 |
| Test name | |
| Test status | |
| Simulation time | 5747114553 ps |
| CPU time | 99.57 seconds |
| Started | Jul 03 07:28:08 PM PDT 24 |
| Finished | Jul 03 07:29:50 PM PDT 24 |
| Peak memory | 573052 kb |
| Host | smart-fcedb707-a682-43c3-a3d5-842f242e84f9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51600911 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_slow_rsp.51600911 |
| Directory | /workspace/31.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_smoke_zero_delays.296460462 |
| Short name | T2017 |
| Test name | |
| Test status | |
| Simulation time | 39515604 ps |
| CPU time | 6.14 seconds |
| Started | Jul 03 07:28:07 PM PDT 24 |
| Finished | Jul 03 07:28:16 PM PDT 24 |
| Peak memory | 573184 kb |
| Host | smart-94d258e8-ea48-4a3c-acb9-eb1b1dc31126 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=296460462 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_zero_delays .296460462 |
| Directory | /workspace/31.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_stress_all.711799970 |
| Short name | T2339 |
| Test name | |
| Test status | |
| Simulation time | 14429394314 ps |
| CPU time | 544.4 seconds |
| Started | Jul 03 07:28:14 PM PDT 24 |
| Finished | Jul 03 07:37:22 PM PDT 24 |
| Peak memory | 574704 kb |
| Host | smart-033c6f16-5345-4064-beac-b4971bf0ec43 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=711799970 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all.711799970 |
| Directory | /workspace/31.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_stress_all_with_error.920867185 |
| Short name | T1853 |
| Test name | |
| Test status | |
| Simulation time | 1382169119 ps |
| CPU time | 111.84 seconds |
| Started | Jul 03 07:28:13 PM PDT 24 |
| Finished | Jul 03 07:30:07 PM PDT 24 |
| Peak memory | 574596 kb |
| Host | smart-53236090-e32f-4ded-8cd0-8d586bf0d5e4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=920867185 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_error.920867185 |
| Directory | /workspace/31.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_stress_all_with_reset_error.1381269404 |
| Short name | T2560 |
| Test name | |
| Test status | |
| Simulation time | 3261141691 ps |
| CPU time | 573.36 seconds |
| Started | Jul 03 07:28:16 PM PDT 24 |
| Finished | Jul 03 07:37:52 PM PDT 24 |
| Peak memory | 578040 kb |
| Host | smart-47bfc07f-d63e-491f-bfc2-7e4609a755a7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1381269404 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_stress_al l_with_reset_error.1381269404 |
| Directory | /workspace/31.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_unmapped_addr.1297911795 |
| Short name | T1639 |
| Test name | |
| Test status | |
| Simulation time | 85443393 ps |
| CPU time | 10.91 seconds |
| Started | Jul 03 07:28:14 PM PDT 24 |
| Finished | Jul 03 07:28:27 PM PDT 24 |
| Peak memory | 574252 kb |
| Host | smart-3833ac09-3043-4b3a-bb10-37cb1a121b12 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1297911795 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_unmapped_addr.1297911795 |
| Directory | /workspace/31.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_access_same_device.3639379880 |
| Short name | T2320 |
| Test name | |
| Test status | |
| Simulation time | 635535778 ps |
| CPU time | 60.53 seconds |
| Started | Jul 03 07:28:25 PM PDT 24 |
| Finished | Jul 03 07:29:27 PM PDT 24 |
| Peak memory | 574124 kb |
| Host | smart-8aa6f36e-813c-4681-9629-bd066e25e51f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3639379880 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_access_same_device .3639379880 |
| Directory | /workspace/32.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_access_same_device_slow_rsp.3722415458 |
| Short name | T1697 |
| Test name | |
| Test status | |
| Simulation time | 98152470991 ps |
| CPU time | 1681.76 seconds |
| Started | Jul 03 07:28:23 PM PDT 24 |
| Finished | Jul 03 07:56:26 PM PDT 24 |
| Peak memory | 574508 kb |
| Host | smart-e7470537-92f1-44f5-96c2-c62209c1751c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3722415458 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_access_same_ device_slow_rsp.3722415458 |
| Directory | /workspace/32.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_error_and_unmapped_addr.3796850918 |
| Short name | T1517 |
| Test name | |
| Test status | |
| Simulation time | 216831173 ps |
| CPU time | 27.04 seconds |
| Started | Jul 03 07:28:26 PM PDT 24 |
| Finished | Jul 03 07:28:54 PM PDT 24 |
| Peak memory | 574476 kb |
| Host | smart-b694a55a-9b9b-4f07-b59e-a084b462e7c9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3796850918 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_error_and_unmapped_add r.3796850918 |
| Directory | /workspace/32.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_error_random.2568644385 |
| Short name | T2203 |
| Test name | |
| Test status | |
| Simulation time | 575274228 ps |
| CPU time | 42.95 seconds |
| Started | Jul 03 07:28:26 PM PDT 24 |
| Finished | Jul 03 07:29:10 PM PDT 24 |
| Peak memory | 574012 kb |
| Host | smart-2674596c-2b8f-4da5-b295-24ce1ef2c58e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568644385 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_error_random.2568644385 |
| Directory | /workspace/32.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_random.500648034 |
| Short name | T2644 |
| Test name | |
| Test status | |
| Simulation time | 488820590 ps |
| CPU time | 39.02 seconds |
| Started | Jul 03 07:28:22 PM PDT 24 |
| Finished | Jul 03 07:29:03 PM PDT 24 |
| Peak memory | 574000 kb |
| Host | smart-bc1942bc-6362-4fab-aa3e-bb7c49fbe2f1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=500648034 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_random.500648034 |
| Directory | /workspace/32.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_random_slow_rsp.3267922605 |
| Short name | T1704 |
| Test name | |
| Test status | |
| Simulation time | 17103034546 ps |
| CPU time | 298.16 seconds |
| Started | Jul 03 07:28:20 PM PDT 24 |
| Finished | Jul 03 07:33:20 PM PDT 24 |
| Peak memory | 574268 kb |
| Host | smart-fb8be806-032e-4af8-8d43-507d0c9c6e52 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267922605 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_random_slow_rsp.3267922605 |
| Directory | /workspace/32.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_random_zero_delays.265644845 |
| Short name | T2601 |
| Test name | |
| Test status | |
| Simulation time | 340315722 ps |
| CPU time | 28.75 seconds |
| Started | Jul 03 07:28:20 PM PDT 24 |
| Finished | Jul 03 07:28:51 PM PDT 24 |
| Peak memory | 573912 kb |
| Host | smart-a5811fc2-2ef0-449d-b4e3-a467f90b08f0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=265644845 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_random_zero_dela ys.265644845 |
| Directory | /workspace/32.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_same_source.1936786832 |
| Short name | T2236 |
| Test name | |
| Test status | |
| Simulation time | 1437996907 ps |
| CPU time | 45.92 seconds |
| Started | Jul 03 07:28:25 PM PDT 24 |
| Finished | Jul 03 07:29:12 PM PDT 24 |
| Peak memory | 574188 kb |
| Host | smart-42c96071-cf76-44da-b32a-b96a296ad3d2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1936786832 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_same_source.1936786832 |
| Directory | /workspace/32.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_smoke.3064207489 |
| Short name | T1602 |
| Test name | |
| Test status | |
| Simulation time | 51227218 ps |
| CPU time | 6.23 seconds |
| Started | Jul 03 07:28:13 PM PDT 24 |
| Finished | Jul 03 07:28:22 PM PDT 24 |
| Peak memory | 573096 kb |
| Host | smart-4e198d80-6f2c-484e-b356-3c1ee8637331 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3064207489 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_smoke.3064207489 |
| Directory | /workspace/32.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_smoke_large_delays.2162992537 |
| Short name | T1688 |
| Test name | |
| Test status | |
| Simulation time | 7777239283 ps |
| CPU time | 76.37 seconds |
| Started | Jul 03 07:28:18 PM PDT 24 |
| Finished | Jul 03 07:29:37 PM PDT 24 |
| Peak memory | 574216 kb |
| Host | smart-59f9c0fd-fe0d-45fc-85c3-e81c71c04985 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162992537 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_large_delays.2162992537 |
| Directory | /workspace/32.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_smoke_slow_rsp.2176418572 |
| Short name | T1337 |
| Test name | |
| Test status | |
| Simulation time | 5350803127 ps |
| CPU time | 90.02 seconds |
| Started | Jul 03 07:28:22 PM PDT 24 |
| Finished | Jul 03 07:29:54 PM PDT 24 |
| Peak memory | 573236 kb |
| Host | smart-f1c1a970-0af2-4f19-ab3f-d24b495f7ed7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2176418572 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_slow_rsp.2176418572 |
| Directory | /workspace/32.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_smoke_zero_delays.3385260639 |
| Short name | T1804 |
| Test name | |
| Test status | |
| Simulation time | 43469444 ps |
| CPU time | 6.16 seconds |
| Started | Jul 03 07:28:15 PM PDT 24 |
| Finished | Jul 03 07:28:24 PM PDT 24 |
| Peak memory | 572900 kb |
| Host | smart-e6a38bc7-6aeb-43a2-a3ae-ad3e1615951a |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3385260639 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_zero_delay s.3385260639 |
| Directory | /workspace/32.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_stress_all.154198238 |
| Short name | T1755 |
| Test name | |
| Test status | |
| Simulation time | 4032076845 ps |
| CPU time | 297.39 seconds |
| Started | Jul 03 07:28:25 PM PDT 24 |
| Finished | Jul 03 07:33:23 PM PDT 24 |
| Peak memory | 574584 kb |
| Host | smart-dd826d45-86e1-436d-b633-aeb964b31ac5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=154198238 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all.154198238 |
| Directory | /workspace/32.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_stress_all_with_error.262720400 |
| Short name | T1459 |
| Test name | |
| Test status | |
| Simulation time | 2042662154 ps |
| CPU time | 162.59 seconds |
| Started | Jul 03 07:28:24 PM PDT 24 |
| Finished | Jul 03 07:31:08 PM PDT 24 |
| Peak memory | 574636 kb |
| Host | smart-69d3f3ac-8cde-401a-9b46-9682b509d191 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=262720400 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_error.262720400 |
| Directory | /workspace/32.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_stress_all_with_rand_reset.3768466083 |
| Short name | T1595 |
| Test name | |
| Test status | |
| Simulation time | 602979658 ps |
| CPU time | 301.52 seconds |
| Started | Jul 03 07:28:25 PM PDT 24 |
| Finished | Jul 03 07:33:28 PM PDT 24 |
| Peak memory | 574604 kb |
| Host | smart-1929eba3-e263-498a-aebe-d473ca642567 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3768466083 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all _with_rand_reset.3768466083 |
| Directory | /workspace/32.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_stress_all_with_reset_error.1366306008 |
| Short name | T501 |
| Test name | |
| Test status | |
| Simulation time | 8304595066 ps |
| CPU time | 379.4 seconds |
| Started | Jul 03 07:28:25 PM PDT 24 |
| Finished | Jul 03 07:34:45 PM PDT 24 |
| Peak memory | 574716 kb |
| Host | smart-7fc0f38b-15cf-49db-9fb4-7812f91593c1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1366306008 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_stress_al l_with_reset_error.1366306008 |
| Directory | /workspace/32.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_unmapped_addr.435681629 |
| Short name | T1479 |
| Test name | |
| Test status | |
| Simulation time | 121606584 ps |
| CPU time | 15.01 seconds |
| Started | Jul 03 07:28:24 PM PDT 24 |
| Finished | Jul 03 07:28:40 PM PDT 24 |
| Peak memory | 574244 kb |
| Host | smart-1e91cc63-dfbf-4403-9062-2584c1d14bfe |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=435681629 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_unmapped_addr.435681629 |
| Directory | /workspace/32.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_access_same_device.768825538 |
| Short name | T2035 |
| Test name | |
| Test status | |
| Simulation time | 1671977196 ps |
| CPU time | 76.38 seconds |
| Started | Jul 03 07:28:29 PM PDT 24 |
| Finished | Jul 03 07:29:47 PM PDT 24 |
| Peak memory | 574196 kb |
| Host | smart-9601f4cd-adcd-4fcb-aa9d-4d24ea6963fa |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768825538 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_access_same_device. 768825538 |
| Directory | /workspace/33.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_access_same_device_slow_rsp.2164718733 |
| Short name | T1692 |
| Test name | |
| Test status | |
| Simulation time | 58453088388 ps |
| CPU time | 1120.78 seconds |
| Started | Jul 03 07:28:28 PM PDT 24 |
| Finished | Jul 03 07:47:11 PM PDT 24 |
| Peak memory | 574300 kb |
| Host | smart-8e8fb002-cbc9-4b89-b236-c23d91b68944 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164718733 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_access_same_ device_slow_rsp.2164718733 |
| Directory | /workspace/33.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_error_and_unmapped_addr.1888162068 |
| Short name | T2444 |
| Test name | |
| Test status | |
| Simulation time | 1306182668 ps |
| CPU time | 51.43 seconds |
| Started | Jul 03 07:28:37 PM PDT 24 |
| Finished | Jul 03 07:29:32 PM PDT 24 |
| Peak memory | 574448 kb |
| Host | smart-0522b2e6-29e3-46f4-b06c-edf03392c210 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1888162068 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_error_and_unmapped_add r.1888162068 |
| Directory | /workspace/33.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_error_random.1054663598 |
| Short name | T2467 |
| Test name | |
| Test status | |
| Simulation time | 344466730 ps |
| CPU time | 29.1 seconds |
| Started | Jul 03 07:28:32 PM PDT 24 |
| Finished | Jul 03 07:29:04 PM PDT 24 |
| Peak memory | 574084 kb |
| Host | smart-84aeaed5-053c-4378-9cc3-fc2fbd92a680 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1054663598 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_error_random.1054663598 |
| Directory | /workspace/33.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_random.2624516912 |
| Short name | T2194 |
| Test name | |
| Test status | |
| Simulation time | 803540934 ps |
| CPU time | 26.89 seconds |
| Started | Jul 03 07:28:28 PM PDT 24 |
| Finished | Jul 03 07:28:57 PM PDT 24 |
| Peak memory | 573976 kb |
| Host | smart-642b8fa1-5cd1-4d45-a903-1d2d6b7ca3e9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2624516912 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_random.2624516912 |
| Directory | /workspace/33.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_random_large_delays.2652659073 |
| Short name | T2443 |
| Test name | |
| Test status | |
| Simulation time | 7629459411 ps |
| CPU time | 75.42 seconds |
| Started | Jul 03 07:28:29 PM PDT 24 |
| Finished | Jul 03 07:29:47 PM PDT 24 |
| Peak memory | 574028 kb |
| Host | smart-ccf636ab-5186-4bbb-80f3-3e9aec157060 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652659073 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_random_large_delays.2652659073 |
| Directory | /workspace/33.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_random_slow_rsp.2425371148 |
| Short name | T2207 |
| Test name | |
| Test status | |
| Simulation time | 57190103060 ps |
| CPU time | 1026.75 seconds |
| Started | Jul 03 07:28:33 PM PDT 24 |
| Finished | Jul 03 07:45:43 PM PDT 24 |
| Peak memory | 574296 kb |
| Host | smart-eb92634b-5a58-435d-8944-98991e86c513 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2425371148 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_random_slow_rsp.2425371148 |
| Directory | /workspace/33.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_random_zero_delays.3261298225 |
| Short name | T1873 |
| Test name | |
| Test status | |
| Simulation time | 526947007 ps |
| CPU time | 54.29 seconds |
| Started | Jul 03 07:28:28 PM PDT 24 |
| Finished | Jul 03 07:29:24 PM PDT 24 |
| Peak memory | 574256 kb |
| Host | smart-4252cb3e-6d1b-4dc4-a5ed-9d59a48b7325 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3261298225 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_random_zero_del ays.3261298225 |
| Directory | /workspace/33.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_same_source.797258052 |
| Short name | T2358 |
| Test name | |
| Test status | |
| Simulation time | 2759168821 ps |
| CPU time | 70.94 seconds |
| Started | Jul 03 07:28:30 PM PDT 24 |
| Finished | Jul 03 07:29:43 PM PDT 24 |
| Peak memory | 574016 kb |
| Host | smart-41cb7dae-c99b-44b9-92d4-abe97b55f803 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=797258052 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_same_source.797258052 |
| Directory | /workspace/33.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_smoke.1433784074 |
| Short name | T2356 |
| Test name | |
| Test status | |
| Simulation time | 151885234 ps |
| CPU time | 7.19 seconds |
| Started | Jul 03 07:28:25 PM PDT 24 |
| Finished | Jul 03 07:28:33 PM PDT 24 |
| Peak memory | 573156 kb |
| Host | smart-4f1d265f-bf86-45d5-bf39-e9d5035035de |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1433784074 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_smoke.1433784074 |
| Directory | /workspace/33.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_smoke_large_delays.1166877185 |
| Short name | T1823 |
| Test name | |
| Test status | |
| Simulation time | 6108309759 ps |
| CPU time | 68.11 seconds |
| Started | Jul 03 07:28:27 PM PDT 24 |
| Finished | Jul 03 07:29:36 PM PDT 24 |
| Peak memory | 574012 kb |
| Host | smart-514104f1-8334-4dfe-adbb-2be0a3f2bb55 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1166877185 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_large_delays.1166877185 |
| Directory | /workspace/33.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_smoke_slow_rsp.1989732383 |
| Short name | T1509 |
| Test name | |
| Test status | |
| Simulation time | 6173713855 ps |
| CPU time | 102.72 seconds |
| Started | Jul 03 07:28:28 PM PDT 24 |
| Finished | Jul 03 07:30:12 PM PDT 24 |
| Peak memory | 574024 kb |
| Host | smart-eed0f324-3848-4069-a616-debaa7891a63 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1989732383 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_slow_rsp.1989732383 |
| Directory | /workspace/33.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_smoke_zero_delays.3492509705 |
| Short name | T2335 |
| Test name | |
| Test status | |
| Simulation time | 40342234 ps |
| CPU time | 5.99 seconds |
| Started | Jul 03 07:28:24 PM PDT 24 |
| Finished | Jul 03 07:28:31 PM PDT 24 |
| Peak memory | 573108 kb |
| Host | smart-162f7924-3e56-4ccd-9eec-e7c1e5853bab |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492509705 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_zero_delay s.3492509705 |
| Directory | /workspace/33.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_stress_all.5714106 |
| Short name | T2625 |
| Test name | |
| Test status | |
| Simulation time | 20762269863 ps |
| CPU time | 832.04 seconds |
| Started | Jul 03 07:28:36 PM PDT 24 |
| Finished | Jul 03 07:42:32 PM PDT 24 |
| Peak memory | 574740 kb |
| Host | smart-ca4ac424-4102-4bc0-9796-f9e8829d3f0d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5714106 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all.5714106 |
| Directory | /workspace/33.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_stress_all_with_error.3771213794 |
| Short name | T1731 |
| Test name | |
| Test status | |
| Simulation time | 766404746 ps |
| CPU time | 57.76 seconds |
| Started | Jul 03 07:28:36 PM PDT 24 |
| Finished | Jul 03 07:29:37 PM PDT 24 |
| Peak memory | 574476 kb |
| Host | smart-432adead-241a-4f34-9d91-e767294d2c68 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3771213794 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_error.3771213794 |
| Directory | /workspace/33.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_stress_all_with_rand_reset.3224092156 |
| Short name | T2003 |
| Test name | |
| Test status | |
| Simulation time | 4221778257 ps |
| CPU time | 533.24 seconds |
| Started | Jul 03 07:28:41 PM PDT 24 |
| Finished | Jul 03 07:37:36 PM PDT 24 |
| Peak memory | 574764 kb |
| Host | smart-2e078ddd-2034-4fcd-b283-a330aa5e3f0c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224092156 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all _with_rand_reset.3224092156 |
| Directory | /workspace/33.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_stress_all_with_reset_error.4165261257 |
| Short name | T2789 |
| Test name | |
| Test status | |
| Simulation time | 567655434 ps |
| CPU time | 132.2 seconds |
| Started | Jul 03 07:28:33 PM PDT 24 |
| Finished | Jul 03 07:30:49 PM PDT 24 |
| Peak memory | 574664 kb |
| Host | smart-2190b976-1d7a-40ed-a52c-4f5d84a9a7eb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4165261257 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_stress_al l_with_reset_error.4165261257 |
| Directory | /workspace/33.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_unmapped_addr.172978476 |
| Short name | T2809 |
| Test name | |
| Test status | |
| Simulation time | 1066962727 ps |
| CPU time | 46.92 seconds |
| Started | Jul 03 07:28:29 PM PDT 24 |
| Finished | Jul 03 07:29:18 PM PDT 24 |
| Peak memory | 574228 kb |
| Host | smart-857170a5-f520-4e09-9472-e0219909eb6d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172978476 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_unmapped_addr.172978476 |
| Directory | /workspace/33.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_access_same_device.1016146627 |
| Short name | T1588 |
| Test name | |
| Test status | |
| Simulation time | 1820492371 ps |
| CPU time | 72.35 seconds |
| Started | Jul 03 07:28:40 PM PDT 24 |
| Finished | Jul 03 07:29:55 PM PDT 24 |
| Peak memory | 574248 kb |
| Host | smart-97cae538-f5cd-4fdc-94d0-be3d788648fa |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1016146627 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_access_same_device .1016146627 |
| Directory | /workspace/34.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_access_same_device_slow_rsp.1342703503 |
| Short name | T2012 |
| Test name | |
| Test status | |
| Simulation time | 10411776056 ps |
| CPU time | 183.24 seconds |
| Started | Jul 03 07:28:41 PM PDT 24 |
| Finished | Jul 03 07:31:47 PM PDT 24 |
| Peak memory | 573260 kb |
| Host | smart-b87d85d5-b3cb-40fc-aa28-b3a86c304ad2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1342703503 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_access_same_ device_slow_rsp.1342703503 |
| Directory | /workspace/34.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_error_and_unmapped_addr.3251901120 |
| Short name | T2867 |
| Test name | |
| Test status | |
| Simulation time | 98420785 ps |
| CPU time | 6.87 seconds |
| Started | Jul 03 07:28:42 PM PDT 24 |
| Finished | Jul 03 07:28:51 PM PDT 24 |
| Peak memory | 573432 kb |
| Host | smart-326274f3-38a6-498b-9198-5962eaa141b7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3251901120 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_error_and_unmapped_add r.3251901120 |
| Directory | /workspace/34.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_error_random.3661853350 |
| Short name | T1869 |
| Test name | |
| Test status | |
| Simulation time | 657383475 ps |
| CPU time | 24.22 seconds |
| Started | Jul 03 07:28:49 PM PDT 24 |
| Finished | Jul 03 07:29:16 PM PDT 24 |
| Peak memory | 574424 kb |
| Host | smart-d149cc71-7bae-48c2-ac90-a3b6437c505e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3661853350 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_error_random.3661853350 |
| Directory | /workspace/34.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_random.2084324350 |
| Short name | T2362 |
| Test name | |
| Test status | |
| Simulation time | 1906332601 ps |
| CPU time | 62.8 seconds |
| Started | Jul 03 07:28:37 PM PDT 24 |
| Finished | Jul 03 07:29:44 PM PDT 24 |
| Peak memory | 574188 kb |
| Host | smart-cd472d0e-9b66-43fd-88c9-64ba1917c21f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2084324350 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_random.2084324350 |
| Directory | /workspace/34.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_random_large_delays.1106297608 |
| Short name | T492 |
| Test name | |
| Test status | |
| Simulation time | 106668565360 ps |
| CPU time | 1150.19 seconds |
| Started | Jul 03 07:28:41 PM PDT 24 |
| Finished | Jul 03 07:47:54 PM PDT 24 |
| Peak memory | 574228 kb |
| Host | smart-b7f1ca7f-22fa-4fb5-81b2-c6c219dcc324 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1106297608 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_random_large_delays.1106297608 |
| Directory | /workspace/34.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_random_slow_rsp.3487598135 |
| Short name | T1565 |
| Test name | |
| Test status | |
| Simulation time | 27816306940 ps |
| CPU time | 410.33 seconds |
| Started | Jul 03 07:28:42 PM PDT 24 |
| Finished | Jul 03 07:35:35 PM PDT 24 |
| Peak memory | 574300 kb |
| Host | smart-a6d44d5a-4e70-4059-ba9f-883bfe14add2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3487598135 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_random_slow_rsp.3487598135 |
| Directory | /workspace/34.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_random_zero_delays.1205642730 |
| Short name | T2533 |
| Test name | |
| Test status | |
| Simulation time | 348696465 ps |
| CPU time | 33.28 seconds |
| Started | Jul 03 07:28:42 PM PDT 24 |
| Finished | Jul 03 07:29:18 PM PDT 24 |
| Peak memory | 574060 kb |
| Host | smart-8e285665-faf6-4230-a93b-06464593acaa |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1205642730 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_random_zero_del ays.1205642730 |
| Directory | /workspace/34.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_same_source.131651522 |
| Short name | T466 |
| Test name | |
| Test status | |
| Simulation time | 1694155219 ps |
| CPU time | 48.66 seconds |
| Started | Jul 03 07:28:39 PM PDT 24 |
| Finished | Jul 03 07:29:30 PM PDT 24 |
| Peak memory | 574144 kb |
| Host | smart-c7fa3ed8-6f10-4e2c-bbd3-213db05c7da9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=131651522 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_same_source.131651522 |
| Directory | /workspace/34.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_smoke.719557813 |
| Short name | T1864 |
| Test name | |
| Test status | |
| Simulation time | 233945254 ps |
| CPU time | 9.85 seconds |
| Started | Jul 03 07:28:40 PM PDT 24 |
| Finished | Jul 03 07:28:52 PM PDT 24 |
| Peak memory | 572912 kb |
| Host | smart-eace669c-c4b8-4962-8cd7-c2bd6bdbcc78 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=719557813 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_smoke.719557813 |
| Directory | /workspace/34.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_smoke_large_delays.296955147 |
| Short name | T1500 |
| Test name | |
| Test status | |
| Simulation time | 8805475990 ps |
| CPU time | 100.12 seconds |
| Started | Jul 03 07:28:36 PM PDT 24 |
| Finished | Jul 03 07:30:20 PM PDT 24 |
| Peak memory | 573232 kb |
| Host | smart-ad3c9ef0-60e4-4fa0-85a2-369eecf5e4f6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=296955147 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_large_delays.296955147 |
| Directory | /workspace/34.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_smoke_slow_rsp.2947815144 |
| Short name | T2230 |
| Test name | |
| Test status | |
| Simulation time | 4699288721 ps |
| CPU time | 76.35 seconds |
| Started | Jul 03 07:28:34 PM PDT 24 |
| Finished | Jul 03 07:29:55 PM PDT 24 |
| Peak memory | 574220 kb |
| Host | smart-cecd1427-2878-4c10-a6a0-c4ea98334e1c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2947815144 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_slow_rsp.2947815144 |
| Directory | /workspace/34.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_smoke_zero_delays.3113172709 |
| Short name | T1711 |
| Test name | |
| Test status | |
| Simulation time | 48904146 ps |
| CPU time | 6.49 seconds |
| Started | Jul 03 07:28:35 PM PDT 24 |
| Finished | Jul 03 07:28:45 PM PDT 24 |
| Peak memory | 573084 kb |
| Host | smart-bf27fd1f-c8f3-4948-994e-5a7179040eda |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3113172709 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_zero_delay s.3113172709 |
| Directory | /workspace/34.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_stress_all.130126201 |
| Short name | T2686 |
| Test name | |
| Test status | |
| Simulation time | 11829939286 ps |
| CPU time | 468.93 seconds |
| Started | Jul 03 07:28:41 PM PDT 24 |
| Finished | Jul 03 07:36:32 PM PDT 24 |
| Peak memory | 574816 kb |
| Host | smart-0b2ec0b1-4ec9-48b5-ae25-1c851cc60389 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=130126201 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all.130126201 |
| Directory | /workspace/34.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_stress_all_with_rand_reset.3191942375 |
| Short name | T1660 |
| Test name | |
| Test status | |
| Simulation time | 4292560699 ps |
| CPU time | 603.84 seconds |
| Started | Jul 03 07:28:41 PM PDT 24 |
| Finished | Jul 03 07:38:47 PM PDT 24 |
| Peak memory | 574704 kb |
| Host | smart-3076e9d4-83bf-4a99-8b5f-9575fd7dee7b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3191942375 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all _with_rand_reset.3191942375 |
| Directory | /workspace/34.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_stress_all_with_reset_error.425890463 |
| Short name | T1613 |
| Test name | |
| Test status | |
| Simulation time | 222759766 ps |
| CPU time | 50.62 seconds |
| Started | Jul 03 07:28:41 PM PDT 24 |
| Finished | Jul 03 07:29:33 PM PDT 24 |
| Peak memory | 574652 kb |
| Host | smart-931feb56-ad9f-4af0-8c78-66d48b385bbb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425890463 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all _with_reset_error.425890463 |
| Directory | /workspace/34.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_unmapped_addr.3063642146 |
| Short name | T1636 |
| Test name | |
| Test status | |
| Simulation time | 201120340 ps |
| CPU time | 23.44 seconds |
| Started | Jul 03 07:28:43 PM PDT 24 |
| Finished | Jul 03 07:29:08 PM PDT 24 |
| Peak memory | 574228 kb |
| Host | smart-23f3b480-f696-4ce6-8dff-5723777d5f39 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3063642146 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_unmapped_addr.3063642146 |
| Directory | /workspace/34.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_access_same_device.2117419077 |
| Short name | T2703 |
| Test name | |
| Test status | |
| Simulation time | 1140583293 ps |
| CPU time | 41.93 seconds |
| Started | Jul 03 07:28:54 PM PDT 24 |
| Finished | Jul 03 07:29:41 PM PDT 24 |
| Peak memory | 574180 kb |
| Host | smart-1cb6455a-d8ab-438d-b284-047c9e2a568f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2117419077 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_access_same_device .2117419077 |
| Directory | /workspace/35.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_access_same_device_slow_rsp.125627659 |
| Short name | T2315 |
| Test name | |
| Test status | |
| Simulation time | 33641344011 ps |
| CPU time | 563.38 seconds |
| Started | Jul 03 07:28:55 PM PDT 24 |
| Finished | Jul 03 07:38:24 PM PDT 24 |
| Peak memory | 574076 kb |
| Host | smart-f6b0f449-e8a4-4ecb-99ee-cc669d784e2e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125627659 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_access_same_d evice_slow_rsp.125627659 |
| Directory | /workspace/35.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_error_and_unmapped_addr.1729338300 |
| Short name | T2024 |
| Test name | |
| Test status | |
| Simulation time | 824343906 ps |
| CPU time | 30.79 seconds |
| Started | Jul 03 07:28:52 PM PDT 24 |
| Finished | Jul 03 07:29:27 PM PDT 24 |
| Peak memory | 574468 kb |
| Host | smart-2e05b5db-14ce-47aa-b896-1676361b05f7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729338300 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_error_and_unmapped_add r.1729338300 |
| Directory | /workspace/35.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_error_random.2166506340 |
| Short name | T1330 |
| Test name | |
| Test status | |
| Simulation time | 1467728223 ps |
| CPU time | 51.29 seconds |
| Started | Jul 03 07:28:56 PM PDT 24 |
| Finished | Jul 03 07:29:52 PM PDT 24 |
| Peak memory | 574440 kb |
| Host | smart-1792931e-539b-4331-b8d5-1c9c6162e1f9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2166506340 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_error_random.2166506340 |
| Directory | /workspace/35.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_random.1794732189 |
| Short name | T1889 |
| Test name | |
| Test status | |
| Simulation time | 2236972955 ps |
| CPU time | 81.47 seconds |
| Started | Jul 03 07:28:47 PM PDT 24 |
| Finished | Jul 03 07:30:12 PM PDT 24 |
| Peak memory | 574316 kb |
| Host | smart-a709c26c-f2b6-49b5-993b-1440d19a9108 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1794732189 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_random.1794732189 |
| Directory | /workspace/35.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_random_large_delays.3932291464 |
| Short name | T2773 |
| Test name | |
| Test status | |
| Simulation time | 41343476386 ps |
| CPU time | 401.02 seconds |
| Started | Jul 03 07:28:54 PM PDT 24 |
| Finished | Jul 03 07:35:41 PM PDT 24 |
| Peak memory | 574020 kb |
| Host | smart-4d37b68b-d5a1-43db-9b87-4fdaca339e50 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3932291464 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_random_large_delays.3932291464 |
| Directory | /workspace/35.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_random_slow_rsp.3110127705 |
| Short name | T2748 |
| Test name | |
| Test status | |
| Simulation time | 51985243757 ps |
| CPU time | 871.38 seconds |
| Started | Jul 03 07:28:47 PM PDT 24 |
| Finished | Jul 03 07:43:22 PM PDT 24 |
| Peak memory | 574272 kb |
| Host | smart-0e99cbfc-8eef-45c0-b2fc-4e7c7b83c745 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3110127705 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_random_slow_rsp.3110127705 |
| Directory | /workspace/35.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_random_zero_delays.832489213 |
| Short name | T2761 |
| Test name | |
| Test status | |
| Simulation time | 62114739 ps |
| CPU time | 7.71 seconds |
| Started | Jul 03 07:28:44 PM PDT 24 |
| Finished | Jul 03 07:28:54 PM PDT 24 |
| Peak memory | 574184 kb |
| Host | smart-80662850-bec0-4582-ad32-eaceef7a61ed |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=832489213 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_random_zero_dela ys.832489213 |
| Directory | /workspace/35.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_same_source.4209823961 |
| Short name | T1353 |
| Test name | |
| Test status | |
| Simulation time | 533387161 ps |
| CPU time | 37.04 seconds |
| Started | Jul 03 07:28:47 PM PDT 24 |
| Finished | Jul 03 07:29:27 PM PDT 24 |
| Peak memory | 574172 kb |
| Host | smart-8a4efce3-469d-4880-a5bd-993e93c57af8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4209823961 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_same_source.4209823961 |
| Directory | /workspace/35.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_smoke.3485988036 |
| Short name | T1312 |
| Test name | |
| Test status | |
| Simulation time | 51487935 ps |
| CPU time | 6.69 seconds |
| Started | Jul 03 07:28:46 PM PDT 24 |
| Finished | Jul 03 07:28:56 PM PDT 24 |
| Peak memory | 574068 kb |
| Host | smart-949b2260-f906-49c7-8c73-8506b0a419f6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3485988036 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_smoke.3485988036 |
| Directory | /workspace/35.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_smoke_large_delays.1158050129 |
| Short name | T1982 |
| Test name | |
| Test status | |
| Simulation time | 6747079504 ps |
| CPU time | 67.5 seconds |
| Started | Jul 03 07:28:45 PM PDT 24 |
| Finished | Jul 03 07:29:56 PM PDT 24 |
| Peak memory | 573228 kb |
| Host | smart-14276693-17a6-41b9-9dec-ab8ccc9c78bf |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1158050129 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_large_delays.1158050129 |
| Directory | /workspace/35.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_smoke_slow_rsp.1718343502 |
| Short name | T2845 |
| Test name | |
| Test status | |
| Simulation time | 4961268618 ps |
| CPU time | 82.43 seconds |
| Started | Jul 03 07:28:55 PM PDT 24 |
| Finished | Jul 03 07:30:23 PM PDT 24 |
| Peak memory | 573188 kb |
| Host | smart-9b59c2d3-4df9-4693-841b-2b717290408a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1718343502 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_slow_rsp.1718343502 |
| Directory | /workspace/35.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_smoke_zero_delays.2181846186 |
| Short name | T2511 |
| Test name | |
| Test status | |
| Simulation time | 51584020 ps |
| CPU time | 7.07 seconds |
| Started | Jul 03 07:28:54 PM PDT 24 |
| Finished | Jul 03 07:29:07 PM PDT 24 |
| Peak memory | 573052 kb |
| Host | smart-4b3625a8-5a7e-47e2-abc5-3bff69a142ae |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2181846186 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_zero_delay s.2181846186 |
| Directory | /workspace/35.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_stress_all.3330017331 |
| Short name | T2239 |
| Test name | |
| Test status | |
| Simulation time | 8661411973 ps |
| CPU time | 321.49 seconds |
| Started | Jul 03 07:28:50 PM PDT 24 |
| Finished | Jul 03 07:34:16 PM PDT 24 |
| Peak memory | 574672 kb |
| Host | smart-239a4cfd-682b-4f6b-bba6-af2dcf996577 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3330017331 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all.3330017331 |
| Directory | /workspace/35.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_stress_all_with_rand_reset.3591840946 |
| Short name | T2584 |
| Test name | |
| Test status | |
| Simulation time | 4203075456 ps |
| CPU time | 270.8 seconds |
| Started | Jul 03 07:28:58 PM PDT 24 |
| Finished | Jul 03 07:33:35 PM PDT 24 |
| Peak memory | 574716 kb |
| Host | smart-b1f57d72-13db-4c58-b035-ece8cdf9b97d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591840946 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all _with_rand_reset.3591840946 |
| Directory | /workspace/35.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_stress_all_with_reset_error.3400177363 |
| Short name | T1978 |
| Test name | |
| Test status | |
| Simulation time | 11713291930 ps |
| CPU time | 575.13 seconds |
| Started | Jul 03 07:28:53 PM PDT 24 |
| Finished | Jul 03 07:38:32 PM PDT 24 |
| Peak memory | 574780 kb |
| Host | smart-dc3791bb-627a-4c1a-9605-28efc8990ee0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3400177363 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_stress_al l_with_reset_error.3400177363 |
| Directory | /workspace/35.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_unmapped_addr.3802816665 |
| Short name | T2694 |
| Test name | |
| Test status | |
| Simulation time | 432534625 ps |
| CPU time | 21.5 seconds |
| Started | Jul 03 07:28:51 PM PDT 24 |
| Finished | Jul 03 07:29:17 PM PDT 24 |
| Peak memory | 574196 kb |
| Host | smart-cf68ac39-02a2-42a1-990a-17d51a60577a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3802816665 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_unmapped_addr.3802816665 |
| Directory | /workspace/35.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_access_same_device_slow_rsp.2429212775 |
| Short name | T1606 |
| Test name | |
| Test status | |
| Simulation time | 81249481421 ps |
| CPU time | 1395.66 seconds |
| Started | Jul 03 07:28:58 PM PDT 24 |
| Finished | Jul 03 07:52:20 PM PDT 24 |
| Peak memory | 574240 kb |
| Host | smart-203b18cd-2e6b-413b-8329-1992bba39553 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2429212775 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_access_same_ device_slow_rsp.2429212775 |
| Directory | /workspace/36.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_error_and_unmapped_addr.3969708597 |
| Short name | T2029 |
| Test name | |
| Test status | |
| Simulation time | 1102629108 ps |
| CPU time | 41.86 seconds |
| Started | Jul 03 07:29:02 PM PDT 24 |
| Finished | Jul 03 07:29:51 PM PDT 24 |
| Peak memory | 574468 kb |
| Host | smart-ed2eedff-f080-4392-a6c8-443882436569 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3969708597 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_error_and_unmapped_add r.3969708597 |
| Directory | /workspace/36.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_error_random.4216761165 |
| Short name | T1621 |
| Test name | |
| Test status | |
| Simulation time | 657631895 ps |
| CPU time | 22.53 seconds |
| Started | Jul 03 07:29:03 PM PDT 24 |
| Finished | Jul 03 07:29:32 PM PDT 24 |
| Peak memory | 574432 kb |
| Host | smart-f818920e-b9b5-4982-8a7c-900fbbdb2868 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216761165 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_error_random.4216761165 |
| Directory | /workspace/36.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_random.503081303 |
| Short name | T1749 |
| Test name | |
| Test status | |
| Simulation time | 306431716 ps |
| CPU time | 26.71 seconds |
| Started | Jul 03 07:28:49 PM PDT 24 |
| Finished | Jul 03 07:29:20 PM PDT 24 |
| Peak memory | 574176 kb |
| Host | smart-1d547a0f-c1a2-48b0-a403-fd271a64afa2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=503081303 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_random.503081303 |
| Directory | /workspace/36.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_random_large_delays.1725665264 |
| Short name | T2519 |
| Test name | |
| Test status | |
| Simulation time | 85900953905 ps |
| CPU time | 923.02 seconds |
| Started | Jul 03 07:28:57 PM PDT 24 |
| Finished | Jul 03 07:44:26 PM PDT 24 |
| Peak memory | 574300 kb |
| Host | smart-f06aea38-1e03-418c-9a6a-7f9ac38aac87 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1725665264 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_random_large_delays.1725665264 |
| Directory | /workspace/36.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_random_slow_rsp.1020423006 |
| Short name | T1975 |
| Test name | |
| Test status | |
| Simulation time | 50459223603 ps |
| CPU time | 868.75 seconds |
| Started | Jul 03 07:28:55 PM PDT 24 |
| Finished | Jul 03 07:43:30 PM PDT 24 |
| Peak memory | 574200 kb |
| Host | smart-d2ed67a1-669f-41a3-9b86-70bd53b7ab56 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1020423006 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_random_slow_rsp.1020423006 |
| Directory | /workspace/36.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_random_zero_delays.2527757478 |
| Short name | T2523 |
| Test name | |
| Test status | |
| Simulation time | 511527597 ps |
| CPU time | 43.59 seconds |
| Started | Jul 03 07:28:58 PM PDT 24 |
| Finished | Jul 03 07:29:48 PM PDT 24 |
| Peak memory | 574028 kb |
| Host | smart-4c2a147a-ea6a-420d-a78a-3cb3353d1733 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2527757478 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_random_zero_del ays.2527757478 |
| Directory | /workspace/36.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_same_source.2816135064 |
| Short name | T2148 |
| Test name | |
| Test status | |
| Simulation time | 384546090 ps |
| CPU time | 30.03 seconds |
| Started | Jul 03 07:29:00 PM PDT 24 |
| Finished | Jul 03 07:29:37 PM PDT 24 |
| Peak memory | 574080 kb |
| Host | smart-08c33182-c585-4759-9202-10e9449b0486 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2816135064 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_same_source.2816135064 |
| Directory | /workspace/36.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_smoke.3339443539 |
| Short name | T1956 |
| Test name | |
| Test status | |
| Simulation time | 219746399 ps |
| CPU time | 9.41 seconds |
| Started | Jul 03 07:28:59 PM PDT 24 |
| Finished | Jul 03 07:29:15 PM PDT 24 |
| Peak memory | 573952 kb |
| Host | smart-52db1474-4e90-4372-ad39-66e652c3dc92 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3339443539 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_smoke.3339443539 |
| Directory | /workspace/36.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_smoke_large_delays.3514509537 |
| Short name | T2197 |
| Test name | |
| Test status | |
| Simulation time | 7925974731 ps |
| CPU time | 83.9 seconds |
| Started | Jul 03 07:28:51 PM PDT 24 |
| Finished | Jul 03 07:30:19 PM PDT 24 |
| Peak memory | 573228 kb |
| Host | smart-9a5f727a-0edc-4ea6-8a41-12e58b638f35 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3514509537 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_large_delays.3514509537 |
| Directory | /workspace/36.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_smoke_slow_rsp.2613814238 |
| Short name | T2258 |
| Test name | |
| Test status | |
| Simulation time | 5967594139 ps |
| CPU time | 90.78 seconds |
| Started | Jul 03 07:28:59 PM PDT 24 |
| Finished | Jul 03 07:30:36 PM PDT 24 |
| Peak memory | 573196 kb |
| Host | smart-6229e7dd-d7ce-42e8-99eb-4b44ed6a3e0a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2613814238 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_slow_rsp.2613814238 |
| Directory | /workspace/36.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_smoke_zero_delays.1717578155 |
| Short name | T2366 |
| Test name | |
| Test status | |
| Simulation time | 52586034 ps |
| CPU time | 7.22 seconds |
| Started | Jul 03 07:28:52 PM PDT 24 |
| Finished | Jul 03 07:29:04 PM PDT 24 |
| Peak memory | 573076 kb |
| Host | smart-406a981c-962a-431b-92f9-ab08cd6fa2d1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1717578155 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_zero_delay s.1717578155 |
| Directory | /workspace/36.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_stress_all.2447946992 |
| Short name | T471 |
| Test name | |
| Test status | |
| Simulation time | 1106147499 ps |
| CPU time | 87.3 seconds |
| Started | Jul 03 07:29:02 PM PDT 24 |
| Finished | Jul 03 07:30:36 PM PDT 24 |
| Peak memory | 574076 kb |
| Host | smart-3be7f4e7-cfee-4118-8e05-6898aa3db277 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2447946992 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all.2447946992 |
| Directory | /workspace/36.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_stress_all_with_error.179520932 |
| Short name | T2594 |
| Test name | |
| Test status | |
| Simulation time | 1574388861 ps |
| CPU time | 100.63 seconds |
| Started | Jul 03 07:29:00 PM PDT 24 |
| Finished | Jul 03 07:30:47 PM PDT 24 |
| Peak memory | 574508 kb |
| Host | smart-c080ba50-612a-4e8a-9e2c-5b0a8a0bb74e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=179520932 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_error.179520932 |
| Directory | /workspace/36.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_stress_all_with_rand_reset.1902857876 |
| Short name | T477 |
| Test name | |
| Test status | |
| Simulation time | 685919993 ps |
| CPU time | 283.67 seconds |
| Started | Jul 03 07:29:00 PM PDT 24 |
| Finished | Jul 03 07:33:50 PM PDT 24 |
| Peak memory | 574616 kb |
| Host | smart-4a9861ae-c621-4f15-8a6d-636c83cf875d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1902857876 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all _with_rand_reset.1902857876 |
| Directory | /workspace/36.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_stress_all_with_reset_error.3803596069 |
| Short name | T2022 |
| Test name | |
| Test status | |
| Simulation time | 832144914 ps |
| CPU time | 159.19 seconds |
| Started | Jul 03 07:29:08 PM PDT 24 |
| Finished | Jul 03 07:31:53 PM PDT 24 |
| Peak memory | 574668 kb |
| Host | smart-6d4c7b5e-d1ad-4033-9d53-355097f399f8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3803596069 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_stress_al l_with_reset_error.3803596069 |
| Directory | /workspace/36.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_unmapped_addr.229528491 |
| Short name | T1893 |
| Test name | |
| Test status | |
| Simulation time | 524157957 ps |
| CPU time | 23.94 seconds |
| Started | Jul 03 07:29:02 PM PDT 24 |
| Finished | Jul 03 07:29:33 PM PDT 24 |
| Peak memory | 574264 kb |
| Host | smart-d95a0685-72a7-4db6-888a-43fe21df2c80 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=229528491 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_unmapped_addr.229528491 |
| Directory | /workspace/36.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_access_same_device.3195437480 |
| Short name | T2462 |
| Test name | |
| Test status | |
| Simulation time | 3541826704 ps |
| CPU time | 137.75 seconds |
| Started | Jul 03 07:29:07 PM PDT 24 |
| Finished | Jul 03 07:31:30 PM PDT 24 |
| Peak memory | 574304 kb |
| Host | smart-68cedd29-be85-4f37-870b-9581ec760730 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3195437480 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_access_same_device .3195437480 |
| Directory | /workspace/37.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_access_same_device_slow_rsp.807539851 |
| Short name | T2104 |
| Test name | |
| Test status | |
| Simulation time | 113775243851 ps |
| CPU time | 1989.35 seconds |
| Started | Jul 03 07:29:11 PM PDT 24 |
| Finished | Jul 03 08:02:28 PM PDT 24 |
| Peak memory | 574332 kb |
| Host | smart-400dbd94-3c5b-4f6a-ac83-cdd0413f3280 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=807539851 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_access_same_d evice_slow_rsp.807539851 |
| Directory | /workspace/37.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_error_and_unmapped_addr.1545559391 |
| Short name | T1947 |
| Test name | |
| Test status | |
| Simulation time | 1399312507 ps |
| CPU time | 55.56 seconds |
| Started | Jul 03 07:29:17 PM PDT 24 |
| Finished | Jul 03 07:30:18 PM PDT 24 |
| Peak memory | 574108 kb |
| Host | smart-28e448ad-0a93-4bde-b087-141c1c3beaa7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545559391 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_error_and_unmapped_add r.1545559391 |
| Directory | /workspace/37.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_error_random.2869464293 |
| Short name | T2026 |
| Test name | |
| Test status | |
| Simulation time | 2053907073 ps |
| CPU time | 68.32 seconds |
| Started | Jul 03 07:29:17 PM PDT 24 |
| Finished | Jul 03 07:30:32 PM PDT 24 |
| Peak memory | 574080 kb |
| Host | smart-da776a23-72d8-4e8e-8e9a-b03673f8c643 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2869464293 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_error_random.2869464293 |
| Directory | /workspace/37.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_random.2020780201 |
| Short name | T2810 |
| Test name | |
| Test status | |
| Simulation time | 1455594515 ps |
| CPU time | 50.26 seconds |
| Started | Jul 03 07:29:07 PM PDT 24 |
| Finished | Jul 03 07:30:03 PM PDT 24 |
| Peak memory | 574084 kb |
| Host | smart-3e711ae1-8692-4b4a-82e3-d47664dbc796 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2020780201 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_random.2020780201 |
| Directory | /workspace/37.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_random_large_delays.1089502585 |
| Short name | T2596 |
| Test name | |
| Test status | |
| Simulation time | 53903798035 ps |
| CPU time | 555.36 seconds |
| Started | Jul 03 07:29:08 PM PDT 24 |
| Finished | Jul 03 07:38:30 PM PDT 24 |
| Peak memory | 574268 kb |
| Host | smart-bbe23bdb-1e81-4d41-a952-befa079f0b7b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1089502585 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_random_large_delays.1089502585 |
| Directory | /workspace/37.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_random_slow_rsp.3813843804 |
| Short name | T2195 |
| Test name | |
| Test status | |
| Simulation time | 10175609619 ps |
| CPU time | 173.93 seconds |
| Started | Jul 03 07:29:09 PM PDT 24 |
| Finished | Jul 03 07:32:10 PM PDT 24 |
| Peak memory | 574264 kb |
| Host | smart-3611bddb-8338-4a66-a33a-086db69bcc68 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3813843804 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_random_slow_rsp.3813843804 |
| Directory | /workspace/37.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_random_zero_delays.1007004606 |
| Short name | T444 |
| Test name | |
| Test status | |
| Simulation time | 632008644 ps |
| CPU time | 54.32 seconds |
| Started | Jul 03 07:29:08 PM PDT 24 |
| Finished | Jul 03 07:30:09 PM PDT 24 |
| Peak memory | 574224 kb |
| Host | smart-c89c037b-5803-4f1b-a08e-bd2744f0d4a2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007004606 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_random_zero_del ays.1007004606 |
| Directory | /workspace/37.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_same_source.3016202169 |
| Short name | T1596 |
| Test name | |
| Test status | |
| Simulation time | 466254339 ps |
| CPU time | 32.81 seconds |
| Started | Jul 03 07:29:14 PM PDT 24 |
| Finished | Jul 03 07:29:53 PM PDT 24 |
| Peak memory | 574160 kb |
| Host | smart-fbc57d3f-b95e-4b8a-baad-31019f4473cf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3016202169 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_same_source.3016202169 |
| Directory | /workspace/37.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_smoke.2198534394 |
| Short name | T2293 |
| Test name | |
| Test status | |
| Simulation time | 213194402 ps |
| CPU time | 9.67 seconds |
| Started | Jul 03 07:29:12 PM PDT 24 |
| Finished | Jul 03 07:29:28 PM PDT 24 |
| Peak memory | 573140 kb |
| Host | smart-f08183e2-7a99-43f3-b991-c22db48f45fd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198534394 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_smoke.2198534394 |
| Directory | /workspace/37.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_smoke_large_delays.3487711380 |
| Short name | T2803 |
| Test name | |
| Test status | |
| Simulation time | 8872152335 ps |
| CPU time | 99.02 seconds |
| Started | Jul 03 07:29:08 PM PDT 24 |
| Finished | Jul 03 07:30:53 PM PDT 24 |
| Peak memory | 574076 kb |
| Host | smart-e757ef83-3a42-4fd7-9e02-94e34e7272c0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3487711380 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_large_delays.3487711380 |
| Directory | /workspace/37.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_smoke_slow_rsp.1086084908 |
| Short name | T2736 |
| Test name | |
| Test status | |
| Simulation time | 5290238708 ps |
| CPU time | 83.53 seconds |
| Started | Jul 03 07:29:12 PM PDT 24 |
| Finished | Jul 03 07:30:42 PM PDT 24 |
| Peak memory | 574260 kb |
| Host | smart-7969402a-58ec-4cb6-b0fc-6497f646d841 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1086084908 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_slow_rsp.1086084908 |
| Directory | /workspace/37.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_smoke_zero_delays.3697107879 |
| Short name | T2268 |
| Test name | |
| Test status | |
| Simulation time | 41970033 ps |
| CPU time | 5.89 seconds |
| Started | Jul 03 07:29:09 PM PDT 24 |
| Finished | Jul 03 07:29:22 PM PDT 24 |
| Peak memory | 573992 kb |
| Host | smart-166dbb07-25ec-465f-bc33-194091cf646e |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3697107879 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_zero_delay s.3697107879 |
| Directory | /workspace/37.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_stress_all.1062891241 |
| Short name | T478 |
| Test name | |
| Test status | |
| Simulation time | 1496079289 ps |
| CPU time | 127.91 seconds |
| Started | Jul 03 07:29:17 PM PDT 24 |
| Finished | Jul 03 07:31:31 PM PDT 24 |
| Peak memory | 574084 kb |
| Host | smart-380ee06d-a4de-4273-817b-2a5f0cfd98ba |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062891241 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all.1062891241 |
| Directory | /workspace/37.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_stress_all_with_error.3856263659 |
| Short name | T1710 |
| Test name | |
| Test status | |
| Simulation time | 5794658646 ps |
| CPU time | 201.31 seconds |
| Started | Jul 03 07:29:17 PM PDT 24 |
| Finished | Jul 03 07:32:44 PM PDT 24 |
| Peak memory | 574240 kb |
| Host | smart-0beb925e-6bcf-4205-a289-4f97786e6624 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3856263659 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_error.3856263659 |
| Directory | /workspace/37.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_stress_all_with_rand_reset.1812778691 |
| Short name | T2455 |
| Test name | |
| Test status | |
| Simulation time | 107631808 ps |
| CPU time | 55.76 seconds |
| Started | Jul 03 07:29:17 PM PDT 24 |
| Finished | Jul 03 07:30:19 PM PDT 24 |
| Peak memory | 574644 kb |
| Host | smart-80342a71-8607-49ff-9146-465e1f423bee |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1812778691 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all _with_rand_reset.1812778691 |
| Directory | /workspace/37.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_stress_all_with_reset_error.324780170 |
| Short name | T822 |
| Test name | |
| Test status | |
| Simulation time | 6013779200 ps |
| CPU time | 404.19 seconds |
| Started | Jul 03 07:29:25 PM PDT 24 |
| Finished | Jul 03 07:36:13 PM PDT 24 |
| Peak memory | 574732 kb |
| Host | smart-54aeabde-86dc-4284-a3a9-6dd0d89ce7b0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=324780170 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all _with_reset_error.324780170 |
| Directory | /workspace/37.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_unmapped_addr.3237214673 |
| Short name | T2025 |
| Test name | |
| Test status | |
| Simulation time | 289031569 ps |
| CPU time | 15.26 seconds |
| Started | Jul 03 07:29:19 PM PDT 24 |
| Finished | Jul 03 07:29:40 PM PDT 24 |
| Peak memory | 574216 kb |
| Host | smart-55d0e832-8866-402f-9ae8-416669f9b586 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3237214673 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_unmapped_addr.3237214673 |
| Directory | /workspace/37.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_access_same_device.1007700262 |
| Short name | T2359 |
| Test name | |
| Test status | |
| Simulation time | 49030599 ps |
| CPU time | 6.86 seconds |
| Started | Jul 03 07:29:27 PM PDT 24 |
| Finished | Jul 03 07:29:37 PM PDT 24 |
| Peak memory | 574184 kb |
| Host | smart-dbc29275-830f-45c7-9390-1d6a00850cf7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007700262 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_access_same_device .1007700262 |
| Directory | /workspace/38.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_access_same_device_slow_rsp.29363925 |
| Short name | T1693 |
| Test name | |
| Test status | |
| Simulation time | 157306544558 ps |
| CPU time | 3115.74 seconds |
| Started | Jul 03 07:29:25 PM PDT 24 |
| Finished | Jul 03 08:21:25 PM PDT 24 |
| Peak memory | 574316 kb |
| Host | smart-c983d4ce-6122-44ca-b64b-c8162c410319 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29363925 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_access_same_de vice_slow_rsp.29363925 |
| Directory | /workspace/38.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_error_and_unmapped_addr.902871278 |
| Short name | T2526 |
| Test name | |
| Test status | |
| Simulation time | 654209139 ps |
| CPU time | 28.2 seconds |
| Started | Jul 03 07:29:27 PM PDT 24 |
| Finished | Jul 03 07:29:58 PM PDT 24 |
| Peak memory | 574536 kb |
| Host | smart-3f76578c-d0de-49f6-a6bc-1cbe94524fa3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902871278 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_error_and_unmapped_addr .902871278 |
| Directory | /workspace/38.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_error_random.686730436 |
| Short name | T2062 |
| Test name | |
| Test status | |
| Simulation time | 553322694 ps |
| CPU time | 45.85 seconds |
| Started | Jul 03 07:29:20 PM PDT 24 |
| Finished | Jul 03 07:30:11 PM PDT 24 |
| Peak memory | 574428 kb |
| Host | smart-16218164-2518-47a1-a0d2-cb0c8aa3eb93 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=686730436 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_error_random.686730436 |
| Directory | /workspace/38.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_random.2698636704 |
| Short name | T1469 |
| Test name | |
| Test status | |
| Simulation time | 1607706589 ps |
| CPU time | 60.94 seconds |
| Started | Jul 03 07:29:24 PM PDT 24 |
| Finished | Jul 03 07:30:29 PM PDT 24 |
| Peak memory | 574036 kb |
| Host | smart-1caa19e8-72e1-4837-845e-e8fd276a757c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2698636704 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_random.2698636704 |
| Directory | /workspace/38.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_random_large_delays.814069548 |
| Short name | T2446 |
| Test name | |
| Test status | |
| Simulation time | 17152915357 ps |
| CPU time | 179.8 seconds |
| Started | Jul 03 07:29:25 PM PDT 24 |
| Finished | Jul 03 07:32:28 PM PDT 24 |
| Peak memory | 574288 kb |
| Host | smart-6618c337-81a6-4799-8845-90082214e783 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=814069548 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_random_large_delays.814069548 |
| Directory | /workspace/38.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_random_slow_rsp.3713020388 |
| Short name | T1854 |
| Test name | |
| Test status | |
| Simulation time | 21338982992 ps |
| CPU time | 355.72 seconds |
| Started | Jul 03 07:29:22 PM PDT 24 |
| Finished | Jul 03 07:35:22 PM PDT 24 |
| Peak memory | 574244 kb |
| Host | smart-c3aa539c-4f6a-44ca-a36a-f393bb8385a4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713020388 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_random_slow_rsp.3713020388 |
| Directory | /workspace/38.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_random_zero_delays.982302485 |
| Short name | T2118 |
| Test name | |
| Test status | |
| Simulation time | 135206999 ps |
| CPU time | 13.38 seconds |
| Started | Jul 03 07:29:23 PM PDT 24 |
| Finished | Jul 03 07:29:41 PM PDT 24 |
| Peak memory | 574240 kb |
| Host | smart-26739f19-c47b-4c15-928e-3570ec8aa2d6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=982302485 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_random_zero_dela ys.982302485 |
| Directory | /workspace/38.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_same_source.1454580484 |
| Short name | T1599 |
| Test name | |
| Test status | |
| Simulation time | 1445632684 ps |
| CPU time | 43.05 seconds |
| Started | Jul 03 07:29:26 PM PDT 24 |
| Finished | Jul 03 07:30:12 PM PDT 24 |
| Peak memory | 574196 kb |
| Host | smart-f47e42f0-f5fc-4cca-97c6-b5ccd9e8d9e4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1454580484 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_same_source.1454580484 |
| Directory | /workspace/38.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_smoke.3805456650 |
| Short name | T1425 |
| Test name | |
| Test status | |
| Simulation time | 38290502 ps |
| CPU time | 6.43 seconds |
| Started | Jul 03 07:29:22 PM PDT 24 |
| Finished | Jul 03 07:29:33 PM PDT 24 |
| Peak memory | 573060 kb |
| Host | smart-815cd0fb-8dce-4230-8c45-e8524f26f24e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3805456650 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_smoke.3805456650 |
| Directory | /workspace/38.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_smoke_large_delays.1279140241 |
| Short name | T1659 |
| Test name | |
| Test status | |
| Simulation time | 6853488557 ps |
| CPU time | 68.69 seconds |
| Started | Jul 03 07:29:25 PM PDT 24 |
| Finished | Jul 03 07:30:37 PM PDT 24 |
| Peak memory | 573004 kb |
| Host | smart-c32a64d9-218c-42a9-8a4a-9390a1210891 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1279140241 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_large_delays.1279140241 |
| Directory | /workspace/38.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_smoke_slow_rsp.3479489748 |
| Short name | T1647 |
| Test name | |
| Test status | |
| Simulation time | 5055016333 ps |
| CPU time | 83.28 seconds |
| Started | Jul 03 07:29:24 PM PDT 24 |
| Finished | Jul 03 07:30:51 PM PDT 24 |
| Peak memory | 574192 kb |
| Host | smart-cb077b57-88c7-4777-a30d-3e4d28c522f8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3479489748 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_slow_rsp.3479489748 |
| Directory | /workspace/38.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_smoke_zero_delays.2063490084 |
| Short name | T1432 |
| Test name | |
| Test status | |
| Simulation time | 48107802 ps |
| CPU time | 6.43 seconds |
| Started | Jul 03 07:29:27 PM PDT 24 |
| Finished | Jul 03 07:29:36 PM PDT 24 |
| Peak memory | 572920 kb |
| Host | smart-83d2f09a-eef1-4313-a96e-355aeb81a6b0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2063490084 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_zero_delay s.2063490084 |
| Directory | /workspace/38.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_stress_all.1150756150 |
| Short name | T487 |
| Test name | |
| Test status | |
| Simulation time | 1454173258 ps |
| CPU time | 89.41 seconds |
| Started | Jul 03 07:29:28 PM PDT 24 |
| Finished | Jul 03 07:31:00 PM PDT 24 |
| Peak memory | 574228 kb |
| Host | smart-b64ce275-9dfa-4e31-b274-0632e91b7300 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1150756150 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all.1150756150 |
| Directory | /workspace/38.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_stress_all_with_error.1614000268 |
| Short name | T2070 |
| Test name | |
| Test status | |
| Simulation time | 383404146 ps |
| CPU time | 29.69 seconds |
| Started | Jul 03 07:29:28 PM PDT 24 |
| Finished | Jul 03 07:30:00 PM PDT 24 |
| Peak memory | 574468 kb |
| Host | smart-aa9cd9c3-aa92-433d-bdf4-aa1e73790502 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1614000268 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_error.1614000268 |
| Directory | /workspace/38.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_stress_all_with_rand_reset.252045646 |
| Short name | T420 |
| Test name | |
| Test status | |
| Simulation time | 2731732001 ps |
| CPU time | 322.99 seconds |
| Started | Jul 03 07:29:30 PM PDT 24 |
| Finished | Jul 03 07:34:55 PM PDT 24 |
| Peak memory | 574700 kb |
| Host | smart-9dd3ea92-bbb3-4e62-9bb3-a792e25631fd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=252045646 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_ with_rand_reset.252045646 |
| Directory | /workspace/38.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_stress_all_with_reset_error.2466168191 |
| Short name | T2164 |
| Test name | |
| Test status | |
| Simulation time | 196328083 ps |
| CPU time | 35.32 seconds |
| Started | Jul 03 07:29:29 PM PDT 24 |
| Finished | Jul 03 07:30:07 PM PDT 24 |
| Peak memory | 574652 kb |
| Host | smart-4865fb5e-6d5d-41a5-93fb-1b017e851f52 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2466168191 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_stress_al l_with_reset_error.2466168191 |
| Directory | /workspace/38.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_unmapped_addr.3806623719 |
| Short name | T2102 |
| Test name | |
| Test status | |
| Simulation time | 407441876 ps |
| CPU time | 17.39 seconds |
| Started | Jul 03 07:29:25 PM PDT 24 |
| Finished | Jul 03 07:29:46 PM PDT 24 |
| Peak memory | 574300 kb |
| Host | smart-190a3a01-4b96-4b3b-89b4-afc3dce14ada |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3806623719 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_unmapped_addr.3806623719 |
| Directory | /workspace/38.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_access_same_device.3781991642 |
| Short name | T2235 |
| Test name | |
| Test status | |
| Simulation time | 1461660591 ps |
| CPU time | 67.81 seconds |
| Started | Jul 03 07:29:32 PM PDT 24 |
| Finished | Jul 03 07:30:41 PM PDT 24 |
| Peak memory | 574024 kb |
| Host | smart-00036f05-6f50-42cb-a0be-e6960c6281c7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3781991642 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_access_same_device .3781991642 |
| Directory | /workspace/39.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_access_same_device_slow_rsp.1297172464 |
| Short name | T1844 |
| Test name | |
| Test status | |
| Simulation time | 49432063229 ps |
| CPU time | 741.05 seconds |
| Started | Jul 03 07:29:34 PM PDT 24 |
| Finished | Jul 03 07:41:56 PM PDT 24 |
| Peak memory | 574380 kb |
| Host | smart-06ea9d0b-65e4-4ca8-ac7b-58ba4ba6a380 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1297172464 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_access_same_ device_slow_rsp.1297172464 |
| Directory | /workspace/39.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_error_and_unmapped_addr.882165544 |
| Short name | T1332 |
| Test name | |
| Test status | |
| Simulation time | 1283501373 ps |
| CPU time | 50.65 seconds |
| Started | Jul 03 07:29:40 PM PDT 24 |
| Finished | Jul 03 07:30:31 PM PDT 24 |
| Peak memory | 574456 kb |
| Host | smart-635b6902-b9df-4083-a3aa-dff4ed06a114 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=882165544 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_error_and_unmapped_addr .882165544 |
| Directory | /workspace/39.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_error_random.3658214251 |
| Short name | T2488 |
| Test name | |
| Test status | |
| Simulation time | 676564397 ps |
| CPU time | 27 seconds |
| Started | Jul 03 07:29:33 PM PDT 24 |
| Finished | Jul 03 07:30:01 PM PDT 24 |
| Peak memory | 574428 kb |
| Host | smart-e85b912c-ced8-4762-96f7-0c20253b06b4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3658214251 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_error_random.3658214251 |
| Directory | /workspace/39.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_random.1213612214 |
| Short name | T1597 |
| Test name | |
| Test status | |
| Simulation time | 2955955054 ps |
| CPU time | 93.4 seconds |
| Started | Jul 03 07:29:27 PM PDT 24 |
| Finished | Jul 03 07:31:03 PM PDT 24 |
| Peak memory | 574224 kb |
| Host | smart-840fd5a4-1c78-4c4e-ba04-d544341d86cc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1213612214 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_random.1213612214 |
| Directory | /workspace/39.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_random_large_delays.3381786231 |
| Short name | T1909 |
| Test name | |
| Test status | |
| Simulation time | 107126254035 ps |
| CPU time | 1143.6 seconds |
| Started | Jul 03 07:29:31 PM PDT 24 |
| Finished | Jul 03 07:48:37 PM PDT 24 |
| Peak memory | 574344 kb |
| Host | smart-67dad22c-5f73-4720-aae1-5ea097213f42 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381786231 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_random_large_delays.3381786231 |
| Directory | /workspace/39.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_random_slow_rsp.3004002723 |
| Short name | T2196 |
| Test name | |
| Test status | |
| Simulation time | 62484728959 ps |
| CPU time | 1063.86 seconds |
| Started | Jul 03 07:29:31 PM PDT 24 |
| Finished | Jul 03 07:47:17 PM PDT 24 |
| Peak memory | 574272 kb |
| Host | smart-67cceedf-d8d3-462a-b6a3-8cbd88e451cd |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3004002723 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_random_slow_rsp.3004002723 |
| Directory | /workspace/39.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_random_zero_delays.1858912533 |
| Short name | T1890 |
| Test name | |
| Test status | |
| Simulation time | 311539351 ps |
| CPU time | 27.99 seconds |
| Started | Jul 03 07:29:29 PM PDT 24 |
| Finished | Jul 03 07:29:59 PM PDT 24 |
| Peak memory | 574136 kb |
| Host | smart-75d2c8e0-cc0f-4130-9be8-7793d2e4b42a |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1858912533 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_random_zero_del ays.1858912533 |
| Directory | /workspace/39.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_same_source.3425863689 |
| Short name | T2799 |
| Test name | |
| Test status | |
| Simulation time | 302639603 ps |
| CPU time | 23.28 seconds |
| Started | Jul 03 07:29:31 PM PDT 24 |
| Finished | Jul 03 07:29:57 PM PDT 24 |
| Peak memory | 573952 kb |
| Host | smart-d7893379-eff1-4d94-8c85-15f54b082710 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425863689 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_same_source.3425863689 |
| Directory | /workspace/39.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_smoke.1840918802 |
| Short name | T1309 |
| Test name | |
| Test status | |
| Simulation time | 40302978 ps |
| CPU time | 6.34 seconds |
| Started | Jul 03 07:29:25 PM PDT 24 |
| Finished | Jul 03 07:29:35 PM PDT 24 |
| Peak memory | 574160 kb |
| Host | smart-b2d66512-b11d-4fda-92af-6f26961b25b4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1840918802 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_smoke.1840918802 |
| Directory | /workspace/39.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_smoke_large_delays.704293133 |
| Short name | T2815 |
| Test name | |
| Test status | |
| Simulation time | 8657369649 ps |
| CPU time | 95.57 seconds |
| Started | Jul 03 07:29:31 PM PDT 24 |
| Finished | Jul 03 07:31:08 PM PDT 24 |
| Peak memory | 573196 kb |
| Host | smart-33049de5-2e04-4cba-acad-36ea1b991696 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=704293133 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_large_delays.704293133 |
| Directory | /workspace/39.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_smoke_slow_rsp.1095179060 |
| Short name | T1676 |
| Test name | |
| Test status | |
| Simulation time | 6163593606 ps |
| CPU time | 107.16 seconds |
| Started | Jul 03 07:29:31 PM PDT 24 |
| Finished | Jul 03 07:31:20 PM PDT 24 |
| Peak memory | 573012 kb |
| Host | smart-8a1e3ab3-dd80-47e9-b78a-46c7523ffe70 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1095179060 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_slow_rsp.1095179060 |
| Directory | /workspace/39.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_smoke_zero_delays.2553666006 |
| Short name | T2413 |
| Test name | |
| Test status | |
| Simulation time | 48827536 ps |
| CPU time | 6.64 seconds |
| Started | Jul 03 07:29:30 PM PDT 24 |
| Finished | Jul 03 07:29:39 PM PDT 24 |
| Peak memory | 574020 kb |
| Host | smart-a38e25b6-c558-41f4-886e-4fb0c56d255c |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2553666006 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_zero_delay s.2553666006 |
| Directory | /workspace/39.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_stress_all.1321360133 |
| Short name | T598 |
| Test name | |
| Test status | |
| Simulation time | 6001629841 ps |
| CPU time | 466.18 seconds |
| Started | Jul 03 07:29:38 PM PDT 24 |
| Finished | Jul 03 07:37:25 PM PDT 24 |
| Peak memory | 574472 kb |
| Host | smart-3de3f04d-c50d-431c-b429-74d90984e6b8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1321360133 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all.1321360133 |
| Directory | /workspace/39.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_stress_all_with_error.3485486158 |
| Short name | T769 |
| Test name | |
| Test status | |
| Simulation time | 1792136827 ps |
| CPU time | 159.73 seconds |
| Started | Jul 03 07:29:43 PM PDT 24 |
| Finished | Jul 03 07:32:23 PM PDT 24 |
| Peak memory | 574144 kb |
| Host | smart-d1f72e7a-2481-4a64-bc26-5025ee824e07 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3485486158 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_error.3485486158 |
| Directory | /workspace/39.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_stress_all_with_rand_reset.3423745544 |
| Short name | T808 |
| Test name | |
| Test status | |
| Simulation time | 1447209493 ps |
| CPU time | 229.88 seconds |
| Started | Jul 03 07:29:39 PM PDT 24 |
| Finished | Jul 03 07:33:30 PM PDT 24 |
| Peak memory | 574728 kb |
| Host | smart-94146550-e222-4ace-b9fd-f049094a2bae |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3423745544 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all _with_rand_reset.3423745544 |
| Directory | /workspace/39.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_stress_all_with_reset_error.65497303 |
| Short name | T1967 |
| Test name | |
| Test status | |
| Simulation time | 199169749 ps |
| CPU time | 65.82 seconds |
| Started | Jul 03 07:29:41 PM PDT 24 |
| Finished | Jul 03 07:30:48 PM PDT 24 |
| Peak memory | 574644 kb |
| Host | smart-e5fd67b3-76ba-4128-a105-5ba632ff4970 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65497303 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_ with_reset_error.65497303 |
| Directory | /workspace/39.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_unmapped_addr.698214040 |
| Short name | T1654 |
| Test name | |
| Test status | |
| Simulation time | 1218882917 ps |
| CPU time | 52.18 seconds |
| Started | Jul 03 07:29:37 PM PDT 24 |
| Finished | Jul 03 07:30:30 PM PDT 24 |
| Peak memory | 573988 kb |
| Host | smart-50edacf1-af3c-4655-803b-c5bb126899fa |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=698214040 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_unmapped_addr.698214040 |
| Directory | /workspace/39.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/4.chip_csr_aliasing.1851519400 |
| Short name | T2869 |
| Test name | |
| Test status | |
| Simulation time | 36644893979 ps |
| CPU time | 6375.54 seconds |
| Started | Jul 03 07:22:44 PM PDT 24 |
| Finished | Jul 03 09:09:02 PM PDT 24 |
| Peak memory | 592660 kb |
| Host | smart-9256a2e1-1b81-4571-8085-ee192203181f |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +csr_aliasing +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1851519400 -assert nopostproc +UVM_TESTNAME=chip_ base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 4.chip_csr_aliasing.1851519400 |
| Directory | /workspace/4.chip_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/4.chip_csr_bit_bash.2549183949 |
| Short name | T2120 |
| Test name | |
| Test status | |
| Simulation time | 6171444520 ps |
| CPU time | 502.8 seconds |
| Started | Jul 03 07:22:38 PM PDT 24 |
| Finished | Jul 03 07:31:03 PM PDT 24 |
| Peak memory | 590904 kb |
| Host | smart-242fe036-3f02-4d95-94a2-affec39c5cdd |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +num_test_csrs=200 +csr_bit_bash +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2549183949 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 4.chip_csr_bit_bash.2549183949 |
| Directory | /workspace/4.chip_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/4.chip_csr_rw.3816926077 |
| Short name | T1929 |
| Test name | |
| Test status | |
| Simulation time | 5914385818 ps |
| CPU time | 627.8 seconds |
| Started | Jul 03 07:22:47 PM PDT 24 |
| Finished | Jul 03 07:33:15 PM PDT 24 |
| Peak memory | 598268 kb |
| Host | smart-a39ccef0-49ae-417b-bd22-0f6f766dc4a8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3816926077 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.chip_csr_rw.3816926077 |
| Directory | /workspace/4.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/4.chip_same_csr_outstanding.2774902971 |
| Short name | T391 |
| Test name | |
| Test status | |
| Simulation time | 15544978072 ps |
| CPU time | 1867.14 seconds |
| Started | Jul 03 07:22:39 PM PDT 24 |
| Finished | Jul 03 07:53:48 PM PDT 24 |
| Peak memory | 592196 kb |
| Host | smart-67a7cc9a-56ec-4724-ac8d-550237216195 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2774902971 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 4.chip_same_csr_outstanding.2774902971 |
| Directory | /workspace/4.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/4.chip_tl_errors.802377579 |
| Short name | T521 |
| Test name | |
| Test status | |
| Simulation time | 3237227840 ps |
| CPU time | 223.87 seconds |
| Started | Jul 03 07:22:36 PM PDT 24 |
| Finished | Jul 03 07:26:23 PM PDT 24 |
| Peak memory | 595996 kb |
| Host | smart-31a86687-1002-487e-9e0a-3fe7d32fcf67 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=802377579 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.chip_tl_errors.802377579 |
| Directory | /workspace/4.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_access_same_device.3241078828 |
| Short name | T2278 |
| Test name | |
| Test status | |
| Simulation time | 523413654 ps |
| CPU time | 40.03 seconds |
| Started | Jul 03 07:22:37 PM PDT 24 |
| Finished | Jul 03 07:23:19 PM PDT 24 |
| Peak memory | 574048 kb |
| Host | smart-a6d450ae-c36f-49b6-aa3f-d7c8a956004f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3241078828 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_access_same_device. 3241078828 |
| Directory | /workspace/4.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_access_same_device_slow_rsp.320117448 |
| Short name | T468 |
| Test name | |
| Test status | |
| Simulation time | 153851305808 ps |
| CPU time | 2660.71 seconds |
| Started | Jul 03 07:22:44 PM PDT 24 |
| Finished | Jul 03 08:07:06 PM PDT 24 |
| Peak memory | 574304 kb |
| Host | smart-83c19381-0ae6-4398-adb3-caed591862c9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=320117448 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_access_same_de vice_slow_rsp.320117448 |
| Directory | /workspace/4.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_error_and_unmapped_addr.574444422 |
| Short name | T2557 |
| Test name | |
| Test status | |
| Simulation time | 121702676 ps |
| CPU time | 16.13 seconds |
| Started | Jul 03 07:22:44 PM PDT 24 |
| Finished | Jul 03 07:23:02 PM PDT 24 |
| Peak memory | 574456 kb |
| Host | smart-33d37ee4-7980-443c-a382-904190115729 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=574444422 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_error_and_unmapped_addr. 574444422 |
| Directory | /workspace/4.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_error_random.228667298 |
| Short name | T2053 |
| Test name | |
| Test status | |
| Simulation time | 602491605 ps |
| CPU time | 49.69 seconds |
| Started | Jul 03 07:22:45 PM PDT 24 |
| Finished | Jul 03 07:23:36 PM PDT 24 |
| Peak memory | 574524 kb |
| Host | smart-e7941b1d-7596-4809-9fbd-eeef1741e104 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228667298 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_error_random.228667298 |
| Directory | /workspace/4.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_random.2202711443 |
| Short name | T2004 |
| Test name | |
| Test status | |
| Simulation time | 1611189193 ps |
| CPU time | 51.71 seconds |
| Started | Jul 03 07:22:39 PM PDT 24 |
| Finished | Jul 03 07:23:33 PM PDT 24 |
| Peak memory | 574248 kb |
| Host | smart-af608497-db4b-4df9-b8c0-c72a314ce8f1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202711443 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_random.2202711443 |
| Directory | /workspace/4.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_random_large_delays.3615203074 |
| Short name | T1566 |
| Test name | |
| Test status | |
| Simulation time | 56062737400 ps |
| CPU time | 597.05 seconds |
| Started | Jul 03 07:22:39 PM PDT 24 |
| Finished | Jul 03 07:32:39 PM PDT 24 |
| Peak memory | 574232 kb |
| Host | smart-6a03aac0-0bb8-40c6-9bdd-7edfd5d659b4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3615203074 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_random_large_delays.3615203074 |
| Directory | /workspace/4.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_random_slow_rsp.3593148763 |
| Short name | T1990 |
| Test name | |
| Test status | |
| Simulation time | 11188803844 ps |
| CPU time | 177.14 seconds |
| Started | Jul 03 07:22:40 PM PDT 24 |
| Finished | Jul 03 07:25:39 PM PDT 24 |
| Peak memory | 574308 kb |
| Host | smart-57f4a4bb-b59e-4182-b7e5-3a6c94285f11 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3593148763 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_random_slow_rsp.3593148763 |
| Directory | /workspace/4.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_random_zero_delays.746285581 |
| Short name | T484 |
| Test name | |
| Test status | |
| Simulation time | 543801655 ps |
| CPU time | 50.09 seconds |
| Started | Jul 03 07:22:37 PM PDT 24 |
| Finished | Jul 03 07:23:30 PM PDT 24 |
| Peak memory | 574124 kb |
| Host | smart-e2830fb0-27b4-457a-b364-b5ec28c35077 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=746285581 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_random_zero_delay s.746285581 |
| Directory | /workspace/4.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_same_source.3640792519 |
| Short name | T2745 |
| Test name | |
| Test status | |
| Simulation time | 689611265 ps |
| CPU time | 24.34 seconds |
| Started | Jul 03 07:22:45 PM PDT 24 |
| Finished | Jul 03 07:23:11 PM PDT 24 |
| Peak memory | 574080 kb |
| Host | smart-b91315f9-eeae-4c06-8ad5-da405f4089e8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3640792519 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_same_source.3640792519 |
| Directory | /workspace/4.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_smoke.1299624246 |
| Short name | T1317 |
| Test name | |
| Test status | |
| Simulation time | 226243609 ps |
| CPU time | 8.86 seconds |
| Started | Jul 03 07:22:38 PM PDT 24 |
| Finished | Jul 03 07:22:49 PM PDT 24 |
| Peak memory | 574128 kb |
| Host | smart-98f9b63f-4b49-45b4-86ec-a651ae756f11 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1299624246 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_smoke.1299624246 |
| Directory | /workspace/4.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_smoke_large_delays.406712120 |
| Short name | T2039 |
| Test name | |
| Test status | |
| Simulation time | 8322774569 ps |
| CPU time | 86.11 seconds |
| Started | Jul 03 07:22:37 PM PDT 24 |
| Finished | Jul 03 07:24:05 PM PDT 24 |
| Peak memory | 573236 kb |
| Host | smart-a22ae293-6410-43f5-a112-02596204328d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=406712120 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_large_delays.406712120 |
| Directory | /workspace/4.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_smoke_slow_rsp.4176749558 |
| Short name | T653 |
| Test name | |
| Test status | |
| Simulation time | 4769461399 ps |
| CPU time | 83.6 seconds |
| Started | Jul 03 07:22:40 PM PDT 24 |
| Finished | Jul 03 07:24:05 PM PDT 24 |
| Peak memory | 572996 kb |
| Host | smart-64a7df0b-2d56-4f3c-9542-05be4429091f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176749558 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_slow_rsp.4176749558 |
| Directory | /workspace/4.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_smoke_zero_delays.2239453941 |
| Short name | T2702 |
| Test name | |
| Test status | |
| Simulation time | 44107844 ps |
| CPU time | 6.36 seconds |
| Started | Jul 03 07:22:42 PM PDT 24 |
| Finished | Jul 03 07:22:50 PM PDT 24 |
| Peak memory | 573096 kb |
| Host | smart-e7d75ff0-59f6-4dbc-88e2-4e2b27089e95 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239453941 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_zero_delays .2239453941 |
| Directory | /workspace/4.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_stress_all.3198882950 |
| Short name | T457 |
| Test name | |
| Test status | |
| Simulation time | 1412337753 ps |
| CPU time | 103.04 seconds |
| Started | Jul 03 07:22:43 PM PDT 24 |
| Finished | Jul 03 07:24:28 PM PDT 24 |
| Peak memory | 574584 kb |
| Host | smart-c9f2fd1f-d362-44d7-8fb4-fd8c0c7bf272 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198882950 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all.3198882950 |
| Directory | /workspace/4.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_stress_all_with_error.3427598688 |
| Short name | T580 |
| Test name | |
| Test status | |
| Simulation time | 3773906411 ps |
| CPU time | 135.99 seconds |
| Started | Jul 03 07:22:44 PM PDT 24 |
| Finished | Jul 03 07:25:02 PM PDT 24 |
| Peak memory | 574188 kb |
| Host | smart-65fc6da6-524b-4b71-9798-87b7f16268dc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3427598688 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_error.3427598688 |
| Directory | /workspace/4.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_stress_all_with_rand_reset.1929226364 |
| Short name | T2798 |
| Test name | |
| Test status | |
| Simulation time | 9387627282 ps |
| CPU time | 484.8 seconds |
| Started | Jul 03 07:22:44 PM PDT 24 |
| Finished | Jul 03 07:30:51 PM PDT 24 |
| Peak memory | 574680 kb |
| Host | smart-0936f051-7f1d-4557-8bb8-7f1c99237ae5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1929226364 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_ with_rand_reset.1929226364 |
| Directory | /workspace/4.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_stress_all_with_reset_error.79585334 |
| Short name | T1346 |
| Test name | |
| Test status | |
| Simulation time | 146169302 ps |
| CPU time | 51.91 seconds |
| Started | Jul 03 07:22:45 PM PDT 24 |
| Finished | Jul 03 07:23:38 PM PDT 24 |
| Peak memory | 574624 kb |
| Host | smart-78cbe3d5-70e8-4e6c-ac2f-9b8eb8af06da |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79585334 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_w ith_reset_error.79585334 |
| Directory | /workspace/4.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_unmapped_addr.3924973238 |
| Short name | T2369 |
| Test name | |
| Test status | |
| Simulation time | 169185402 ps |
| CPU time | 18.89 seconds |
| Started | Jul 03 07:22:44 PM PDT 24 |
| Finished | Jul 03 07:23:05 PM PDT 24 |
| Peak memory | 574280 kb |
| Host | smart-7707985e-b8cb-4508-b7d8-233858bb66d5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3924973238 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_unmapped_addr.3924973238 |
| Directory | /workspace/4.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_access_same_device.615481184 |
| Short name | T2619 |
| Test name | |
| Test status | |
| Simulation time | 16785565 ps |
| CPU time | 6.13 seconds |
| Started | Jul 03 07:29:55 PM PDT 24 |
| Finished | Jul 03 07:30:03 PM PDT 24 |
| Peak memory | 572968 kb |
| Host | smart-2ae6ff58-2e6d-4a52-8a6e-a2b999a2f095 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=615481184 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_access_same_device. 615481184 |
| Directory | /workspace/40.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_access_same_device_slow_rsp.620725684 |
| Short name | T1989 |
| Test name | |
| Test status | |
| Simulation time | 99778943716 ps |
| CPU time | 1814.73 seconds |
| Started | Jul 03 07:29:54 PM PDT 24 |
| Finished | Jul 03 08:00:11 PM PDT 24 |
| Peak memory | 574556 kb |
| Host | smart-6e2f3d92-3d71-4469-9469-056c4578af34 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620725684 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_access_same_d evice_slow_rsp.620725684 |
| Directory | /workspace/40.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_error_and_unmapped_addr.983901717 |
| Short name | T1454 |
| Test name | |
| Test status | |
| Simulation time | 122296851 ps |
| CPU time | 15.72 seconds |
| Started | Jul 03 07:29:53 PM PDT 24 |
| Finished | Jul 03 07:30:12 PM PDT 24 |
| Peak memory | 574056 kb |
| Host | smart-9a5e4397-cdea-4181-914b-06894ee2e233 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=983901717 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_error_and_unmapped_addr .983901717 |
| Directory | /workspace/40.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_error_random.1739888325 |
| Short name | T2224 |
| Test name | |
| Test status | |
| Simulation time | 2082321541 ps |
| CPU time | 76.37 seconds |
| Started | Jul 03 07:29:52 PM PDT 24 |
| Finished | Jul 03 07:31:11 PM PDT 24 |
| Peak memory | 574468 kb |
| Host | smart-f6232809-6d8c-4271-acef-0f6f7c21423a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1739888325 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_error_random.1739888325 |
| Directory | /workspace/40.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_random.2955856595 |
| Short name | T2649 |
| Test name | |
| Test status | |
| Simulation time | 479493256 ps |
| CPU time | 45.87 seconds |
| Started | Jul 03 07:29:47 PM PDT 24 |
| Finished | Jul 03 07:30:35 PM PDT 24 |
| Peak memory | 574116 kb |
| Host | smart-20f9f3a1-5ee0-4ef1-810c-b5d9056334da |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2955856595 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_random.2955856595 |
| Directory | /workspace/40.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_random_large_delays.2711106649 |
| Short name | T2868 |
| Test name | |
| Test status | |
| Simulation time | 56472542199 ps |
| CPU time | 575.74 seconds |
| Started | Jul 03 07:29:53 PM PDT 24 |
| Finished | Jul 03 07:39:31 PM PDT 24 |
| Peak memory | 574208 kb |
| Host | smart-d26b334e-2c6f-4ebc-8b89-9b54cb6fa573 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2711106649 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_random_large_delays.2711106649 |
| Directory | /workspace/40.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_random_slow_rsp.2368328479 |
| Short name | T2163 |
| Test name | |
| Test status | |
| Simulation time | 38141681578 ps |
| CPU time | 652.13 seconds |
| Started | Jul 03 07:29:54 PM PDT 24 |
| Finished | Jul 03 07:40:48 PM PDT 24 |
| Peak memory | 574308 kb |
| Host | smart-827cce4f-d254-4c11-93ce-a39ef78cb1fb |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2368328479 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_random_slow_rsp.2368328479 |
| Directory | /workspace/40.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_random_zero_delays.2518016602 |
| Short name | T1780 |
| Test name | |
| Test status | |
| Simulation time | 298268254 ps |
| CPU time | 25.73 seconds |
| Started | Jul 03 07:29:49 PM PDT 24 |
| Finished | Jul 03 07:30:16 PM PDT 24 |
| Peak memory | 574160 kb |
| Host | smart-00ed99e9-1834-442c-b9ee-c58cbca4fc93 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2518016602 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_random_zero_del ays.2518016602 |
| Directory | /workspace/40.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_same_source.1126576036 |
| Short name | T1511 |
| Test name | |
| Test status | |
| Simulation time | 401746109 ps |
| CPU time | 30.54 seconds |
| Started | Jul 03 07:29:53 PM PDT 24 |
| Finished | Jul 03 07:30:26 PM PDT 24 |
| Peak memory | 574120 kb |
| Host | smart-ae32c5ba-fef3-4ac9-aaa7-65653fefeb37 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1126576036 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_same_source.1126576036 |
| Directory | /workspace/40.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_smoke.3602909470 |
| Short name | T1995 |
| Test name | |
| Test status | |
| Simulation time | 46881595 ps |
| CPU time | 5.74 seconds |
| Started | Jul 03 07:29:44 PM PDT 24 |
| Finished | Jul 03 07:29:51 PM PDT 24 |
| Peak memory | 573980 kb |
| Host | smart-869f6666-b23c-4690-99e4-6a6910c9dbe1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602909470 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_smoke.3602909470 |
| Directory | /workspace/40.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_smoke_large_delays.284371593 |
| Short name | T1836 |
| Test name | |
| Test status | |
| Simulation time | 7424002619 ps |
| CPU time | 78.92 seconds |
| Started | Jul 03 07:29:50 PM PDT 24 |
| Finished | Jul 03 07:31:10 PM PDT 24 |
| Peak memory | 573256 kb |
| Host | smart-8272b3a9-2948-42c5-b316-67537e0e515b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=284371593 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_large_delays.284371593 |
| Directory | /workspace/40.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_smoke_slow_rsp.4003784730 |
| Short name | T2425 |
| Test name | |
| Test status | |
| Simulation time | 3745897770 ps |
| CPU time | 65.88 seconds |
| Started | Jul 03 07:29:49 PM PDT 24 |
| Finished | Jul 03 07:30:57 PM PDT 24 |
| Peak memory | 573132 kb |
| Host | smart-f9e9b68d-7aa6-4986-9496-bc1aad359e3a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4003784730 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_slow_rsp.4003784730 |
| Directory | /workspace/40.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_smoke_zero_delays.435838992 |
| Short name | T2470 |
| Test name | |
| Test status | |
| Simulation time | 47993001 ps |
| CPU time | 6.48 seconds |
| Started | Jul 03 07:29:41 PM PDT 24 |
| Finished | Jul 03 07:29:48 PM PDT 24 |
| Peak memory | 573152 kb |
| Host | smart-e643e154-1eb5-488b-89be-b87bde7879b5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=435838992 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_zero_delays .435838992 |
| Directory | /workspace/40.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_stress_all.1984122054 |
| Short name | T502 |
| Test name | |
| Test status | |
| Simulation time | 7740605703 ps |
| CPU time | 273.01 seconds |
| Started | Jul 03 07:29:53 PM PDT 24 |
| Finished | Jul 03 07:34:29 PM PDT 24 |
| Peak memory | 574704 kb |
| Host | smart-0bc14fe5-c5d4-480d-9bfc-379071621967 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984122054 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all.1984122054 |
| Directory | /workspace/40.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_stress_all_with_error.4280024852 |
| Short name | T1527 |
| Test name | |
| Test status | |
| Simulation time | 5455297047 ps |
| CPU time | 206.82 seconds |
| Started | Jul 03 07:29:59 PM PDT 24 |
| Finished | Jul 03 07:33:27 PM PDT 24 |
| Peak memory | 574792 kb |
| Host | smart-5ce78566-9b2d-4fea-8820-f9736659a4e0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4280024852 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_error.4280024852 |
| Directory | /workspace/40.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_stress_all_with_rand_reset.496909238 |
| Short name | T2068 |
| Test name | |
| Test status | |
| Simulation time | 7851453359 ps |
| CPU time | 825.02 seconds |
| Started | Jul 03 07:29:58 PM PDT 24 |
| Finished | Jul 03 07:43:45 PM PDT 24 |
| Peak memory | 574724 kb |
| Host | smart-51d236b3-e7f0-4a2b-9cf6-0b43cff7eadc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=496909238 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_ with_rand_reset.496909238 |
| Directory | /workspace/40.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_stress_all_with_reset_error.3593316387 |
| Short name | T772 |
| Test name | |
| Test status | |
| Simulation time | 9665019308 ps |
| CPU time | 446.89 seconds |
| Started | Jul 03 07:29:58 PM PDT 24 |
| Finished | Jul 03 07:37:26 PM PDT 24 |
| Peak memory | 574768 kb |
| Host | smart-7704ce66-92bc-4ba5-ba67-557a4f7e64e3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3593316387 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_stress_al l_with_reset_error.3593316387 |
| Directory | /workspace/40.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_unmapped_addr.878149735 |
| Short name | T474 |
| Test name | |
| Test status | |
| Simulation time | 509346927 ps |
| CPU time | 23.93 seconds |
| Started | Jul 03 07:29:53 PM PDT 24 |
| Finished | Jul 03 07:30:19 PM PDT 24 |
| Peak memory | 574024 kb |
| Host | smart-2ed0d22f-7316-4069-8a05-86813c7479ba |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=878149735 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_unmapped_addr.878149735 |
| Directory | /workspace/40.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_access_same_device.1857525232 |
| Short name | T2507 |
| Test name | |
| Test status | |
| Simulation time | 944366537 ps |
| CPU time | 42.35 seconds |
| Started | Jul 03 07:30:05 PM PDT 24 |
| Finished | Jul 03 07:30:49 PM PDT 24 |
| Peak memory | 574168 kb |
| Host | smart-0aeb19eb-0b99-44bf-ab54-22068f935617 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1857525232 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_access_same_device .1857525232 |
| Directory | /workspace/41.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_access_same_device_slow_rsp.4217798309 |
| Short name | T2155 |
| Test name | |
| Test status | |
| Simulation time | 66287411325 ps |
| CPU time | 1223.41 seconds |
| Started | Jul 03 07:30:05 PM PDT 24 |
| Finished | Jul 03 07:50:30 PM PDT 24 |
| Peak memory | 574356 kb |
| Host | smart-c976997c-71e9-4e73-83ae-ac8a0c6bf526 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4217798309 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_access_same_ device_slow_rsp.4217798309 |
| Directory | /workspace/41.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_error_and_unmapped_addr.3851442626 |
| Short name | T1701 |
| Test name | |
| Test status | |
| Simulation time | 426275398 ps |
| CPU time | 19.98 seconds |
| Started | Jul 03 07:30:08 PM PDT 24 |
| Finished | Jul 03 07:30:29 PM PDT 24 |
| Peak memory | 574552 kb |
| Host | smart-f643be12-920b-4e36-baeb-9dee87205390 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3851442626 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_error_and_unmapped_add r.3851442626 |
| Directory | /workspace/41.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_error_random.756056284 |
| Short name | T2185 |
| Test name | |
| Test status | |
| Simulation time | 1371297482 ps |
| CPU time | 45.55 seconds |
| Started | Jul 03 07:30:02 PM PDT 24 |
| Finished | Jul 03 07:30:49 PM PDT 24 |
| Peak memory | 574084 kb |
| Host | smart-b47d3462-86e9-4e2c-8e4f-a6d8f6d8014c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=756056284 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_error_random.756056284 |
| Directory | /workspace/41.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_random.183700737 |
| Short name | T1393 |
| Test name | |
| Test status | |
| Simulation time | 439075490 ps |
| CPU time | 34.51 seconds |
| Started | Jul 03 07:30:05 PM PDT 24 |
| Finished | Jul 03 07:30:41 PM PDT 24 |
| Peak memory | 574156 kb |
| Host | smart-f9b57316-07f8-4893-aff1-40b48d2585ad |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=183700737 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_random.183700737 |
| Directory | /workspace/41.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_random_large_delays.1915206959 |
| Short name | T2006 |
| Test name | |
| Test status | |
| Simulation time | 77855825044 ps |
| CPU time | 929.23 seconds |
| Started | Jul 03 07:30:02 PM PDT 24 |
| Finished | Jul 03 07:45:32 PM PDT 24 |
| Peak memory | 574368 kb |
| Host | smart-6a3819a6-0f16-4053-beb1-2be0faede60c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915206959 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_random_large_delays.1915206959 |
| Directory | /workspace/41.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_random_slow_rsp.829153280 |
| Short name | T2031 |
| Test name | |
| Test status | |
| Simulation time | 31781541345 ps |
| CPU time | 545.22 seconds |
| Started | Jul 03 07:30:02 PM PDT 24 |
| Finished | Jul 03 07:39:09 PM PDT 24 |
| Peak memory | 574092 kb |
| Host | smart-75a3a83f-c8da-4954-af40-d83e57e533c0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=829153280 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_random_slow_rsp.829153280 |
| Directory | /workspace/41.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_random_zero_delays.2573350873 |
| Short name | T1548 |
| Test name | |
| Test status | |
| Simulation time | 352961973 ps |
| CPU time | 30.91 seconds |
| Started | Jul 03 07:30:03 PM PDT 24 |
| Finished | Jul 03 07:30:35 PM PDT 24 |
| Peak memory | 574308 kb |
| Host | smart-f3ee3386-c1c3-4e31-a556-002817abece0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2573350873 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_random_zero_del ays.2573350873 |
| Directory | /workspace/41.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_same_source.1728007690 |
| Short name | T2829 |
| Test name | |
| Test status | |
| Simulation time | 384210212 ps |
| CPU time | 33.49 seconds |
| Started | Jul 03 07:30:03 PM PDT 24 |
| Finished | Jul 03 07:30:38 PM PDT 24 |
| Peak memory | 573940 kb |
| Host | smart-b4ce11cd-11ce-47c2-aceb-d593f92128ce |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1728007690 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_same_source.1728007690 |
| Directory | /workspace/41.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_smoke.1979742179 |
| Short name | T2797 |
| Test name | |
| Test status | |
| Simulation time | 210193579 ps |
| CPU time | 8.71 seconds |
| Started | Jul 03 07:29:57 PM PDT 24 |
| Finished | Jul 03 07:30:07 PM PDT 24 |
| Peak memory | 573072 kb |
| Host | smart-a7cacbf4-ffd5-4c11-874a-0537b42c793f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1979742179 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_smoke.1979742179 |
| Directory | /workspace/41.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_smoke_large_delays.1603215650 |
| Short name | T2430 |
| Test name | |
| Test status | |
| Simulation time | 5338882843 ps |
| CPU time | 53.03 seconds |
| Started | Jul 03 07:30:02 PM PDT 24 |
| Finished | Jul 03 07:30:56 PM PDT 24 |
| Peak memory | 573184 kb |
| Host | smart-f9820647-4a0a-49dd-b9b9-3f9cb1ed8637 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1603215650 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_large_delays.1603215650 |
| Directory | /workspace/41.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_smoke_slow_rsp.696124424 |
| Short name | T2041 |
| Test name | |
| Test status | |
| Simulation time | 5568967575 ps |
| CPU time | 99.35 seconds |
| Started | Jul 03 07:30:03 PM PDT 24 |
| Finished | Jul 03 07:31:44 PM PDT 24 |
| Peak memory | 573076 kb |
| Host | smart-8b04d18d-a5a1-4b5b-b2d0-55d56f6f04a1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=696124424 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_slow_rsp.696124424 |
| Directory | /workspace/41.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_smoke_zero_delays.3804794254 |
| Short name | T2669 |
| Test name | |
| Test status | |
| Simulation time | 48666915 ps |
| CPU time | 6.57 seconds |
| Started | Jul 03 07:30:00 PM PDT 24 |
| Finished | Jul 03 07:30:08 PM PDT 24 |
| Peak memory | 572972 kb |
| Host | smart-99634748-8be4-4558-b734-3aac2be7ea8e |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3804794254 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_zero_delay s.3804794254 |
| Directory | /workspace/41.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_stress_all.1654223655 |
| Short name | T2190 |
| Test name | |
| Test status | |
| Simulation time | 6497286988 ps |
| CPU time | 285.45 seconds |
| Started | Jul 03 07:30:09 PM PDT 24 |
| Finished | Jul 03 07:34:56 PM PDT 24 |
| Peak memory | 574344 kb |
| Host | smart-a0ac9dd2-fbf0-4825-ba45-9c6c604b87ae |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1654223655 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all.1654223655 |
| Directory | /workspace/41.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_stress_all_with_error.2453050984 |
| Short name | T2069 |
| Test name | |
| Test status | |
| Simulation time | 202359691 ps |
| CPU time | 19.79 seconds |
| Started | Jul 03 07:30:08 PM PDT 24 |
| Finished | Jul 03 07:30:30 PM PDT 24 |
| Peak memory | 574476 kb |
| Host | smart-fc4fd7d1-e7ae-4a6e-a220-f0b164a21183 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2453050984 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_error.2453050984 |
| Directory | /workspace/41.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_stress_all_with_rand_reset.1648118939 |
| Short name | T2672 |
| Test name | |
| Test status | |
| Simulation time | 115640321 ps |
| CPU time | 32.37 seconds |
| Started | Jul 03 07:30:09 PM PDT 24 |
| Finished | Jul 03 07:30:43 PM PDT 24 |
| Peak memory | 574648 kb |
| Host | smart-ffa6c211-669b-436b-9184-3ccb00e339cf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1648118939 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all _with_rand_reset.1648118939 |
| Directory | /workspace/41.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_unmapped_addr.551934733 |
| Short name | T2208 |
| Test name | |
| Test status | |
| Simulation time | 1224733560 ps |
| CPU time | 43.97 seconds |
| Started | Jul 03 07:30:05 PM PDT 24 |
| Finished | Jul 03 07:30:50 PM PDT 24 |
| Peak memory | 574272 kb |
| Host | smart-b9cdbb9d-a53d-4871-9636-13e57f9f3a98 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=551934733 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_unmapped_addr.551934733 |
| Directory | /workspace/41.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_access_same_device.463314544 |
| Short name | T1782 |
| Test name | |
| Test status | |
| Simulation time | 1224552383 ps |
| CPU time | 46.98 seconds |
| Started | Jul 03 07:30:25 PM PDT 24 |
| Finished | Jul 03 07:31:15 PM PDT 24 |
| Peak memory | 574180 kb |
| Host | smart-0a0c1157-4442-460b-b999-2a27ee06c22b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=463314544 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_access_same_device. 463314544 |
| Directory | /workspace/42.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_access_same_device_slow_rsp.1986944579 |
| Short name | T1614 |
| Test name | |
| Test status | |
| Simulation time | 129283706439 ps |
| CPU time | 2373.47 seconds |
| Started | Jul 03 07:30:21 PM PDT 24 |
| Finished | Jul 03 08:09:56 PM PDT 24 |
| Peak memory | 574288 kb |
| Host | smart-f89b1ffd-c4bb-4b31-bf3b-70e6c25c8870 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1986944579 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_access_same_ device_slow_rsp.1986944579 |
| Directory | /workspace/42.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_error_and_unmapped_addr.1344659665 |
| Short name | T1562 |
| Test name | |
| Test status | |
| Simulation time | 689242993 ps |
| CPU time | 26.71 seconds |
| Started | Jul 03 07:30:19 PM PDT 24 |
| Finished | Jul 03 07:30:48 PM PDT 24 |
| Peak memory | 574076 kb |
| Host | smart-a6b92f51-091b-4365-9cb1-faebcb126e06 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1344659665 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_error_and_unmapped_add r.1344659665 |
| Directory | /workspace/42.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_error_random.1484977160 |
| Short name | T2434 |
| Test name | |
| Test status | |
| Simulation time | 1842629691 ps |
| CPU time | 74.6 seconds |
| Started | Jul 03 07:30:18 PM PDT 24 |
| Finished | Jul 03 07:31:36 PM PDT 24 |
| Peak memory | 574504 kb |
| Host | smart-89d939d6-787b-4ab8-987f-6c23819a6ed2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1484977160 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_error_random.1484977160 |
| Directory | /workspace/42.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_random.700899248 |
| Short name | T573 |
| Test name | |
| Test status | |
| Simulation time | 88898812 ps |
| CPU time | 9.6 seconds |
| Started | Jul 03 07:30:11 PM PDT 24 |
| Finished | Jul 03 07:30:25 PM PDT 24 |
| Peak memory | 574180 kb |
| Host | smart-7eb3a023-7355-493e-98e7-ca914a8ae63d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=700899248 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_random.700899248 |
| Directory | /workspace/42.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_random_large_delays.3571962870 |
| Short name | T1490 |
| Test name | |
| Test status | |
| Simulation time | 96355482413 ps |
| CPU time | 1006.04 seconds |
| Started | Jul 03 07:30:16 PM PDT 24 |
| Finished | Jul 03 07:47:07 PM PDT 24 |
| Peak memory | 574428 kb |
| Host | smart-490158db-544d-4391-9fee-2b3ab700646e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3571962870 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_random_large_delays.3571962870 |
| Directory | /workspace/42.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_random_slow_rsp.406986859 |
| Short name | T1696 |
| Test name | |
| Test status | |
| Simulation time | 11046071214 ps |
| CPU time | 193.29 seconds |
| Started | Jul 03 07:30:16 PM PDT 24 |
| Finished | Jul 03 07:33:33 PM PDT 24 |
| Peak memory | 574220 kb |
| Host | smart-4e274d2c-503b-4904-9ae0-9bc42b536a47 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=406986859 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_random_slow_rsp.406986859 |
| Directory | /workspace/42.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_random_zero_delays.3258692552 |
| Short name | T2855 |
| Test name | |
| Test status | |
| Simulation time | 369769254 ps |
| CPU time | 29.89 seconds |
| Started | Jul 03 07:30:16 PM PDT 24 |
| Finished | Jul 03 07:30:50 PM PDT 24 |
| Peak memory | 574232 kb |
| Host | smart-79154979-bfba-4710-a138-09a73cb07ed0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3258692552 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_random_zero_del ays.3258692552 |
| Directory | /workspace/42.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_same_source.4064939549 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 379115449 ps |
| CPU time | 28.36 seconds |
| Started | Jul 03 07:30:25 PM PDT 24 |
| Finished | Jul 03 07:30:55 PM PDT 24 |
| Peak memory | 573980 kb |
| Host | smart-b202f624-dab7-457a-a891-c1b35247af17 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4064939549 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_same_source.4064939549 |
| Directory | /workspace/42.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_smoke.2990113920 |
| Short name | T1974 |
| Test name | |
| Test status | |
| Simulation time | 33030689 ps |
| CPU time | 5.67 seconds |
| Started | Jul 03 07:30:08 PM PDT 24 |
| Finished | Jul 03 07:30:15 PM PDT 24 |
| Peak memory | 573148 kb |
| Host | smart-64ff00e8-d588-4580-81ee-ed469553afb3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2990113920 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_smoke.2990113920 |
| Directory | /workspace/42.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_smoke_large_delays.2698657633 |
| Short name | T2154 |
| Test name | |
| Test status | |
| Simulation time | 7421564400 ps |
| CPU time | 77.4 seconds |
| Started | Jul 03 07:30:15 PM PDT 24 |
| Finished | Jul 03 07:31:37 PM PDT 24 |
| Peak memory | 574184 kb |
| Host | smart-ce899cfe-7511-4751-9fd2-1b63b26740d2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2698657633 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_large_delays.2698657633 |
| Directory | /workspace/42.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_smoke_slow_rsp.1063666402 |
| Short name | T1396 |
| Test name | |
| Test status | |
| Simulation time | 4107004290 ps |
| CPU time | 76.79 seconds |
| Started | Jul 03 07:30:14 PM PDT 24 |
| Finished | Jul 03 07:31:35 PM PDT 24 |
| Peak memory | 572944 kb |
| Host | smart-4c1ec849-1668-4aa6-adbb-50710a342ec8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1063666402 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_slow_rsp.1063666402 |
| Directory | /workspace/42.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_smoke_zero_delays.678619513 |
| Short name | T2640 |
| Test name | |
| Test status | |
| Simulation time | 47076689 ps |
| CPU time | 6.69 seconds |
| Started | Jul 03 07:30:14 PM PDT 24 |
| Finished | Jul 03 07:30:25 PM PDT 24 |
| Peak memory | 573168 kb |
| Host | smart-9a66f0b3-bba3-4d64-9bb4-4298c73fd0a1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=678619513 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_zero_delays .678619513 |
| Directory | /workspace/42.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_stress_all.3230279015 |
| Short name | T479 |
| Test name | |
| Test status | |
| Simulation time | 4455032882 ps |
| CPU time | 164.06 seconds |
| Started | Jul 03 07:30:19 PM PDT 24 |
| Finished | Jul 03 07:33:06 PM PDT 24 |
| Peak memory | 574668 kb |
| Host | smart-1db4432e-f97b-4760-a129-6a5dc27618ab |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3230279015 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all.3230279015 |
| Directory | /workspace/42.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_stress_all_with_error.549952736 |
| Short name | T762 |
| Test name | |
| Test status | |
| Simulation time | 8468534912 ps |
| CPU time | 259.33 seconds |
| Started | Jul 03 07:30:25 PM PDT 24 |
| Finished | Jul 03 07:34:47 PM PDT 24 |
| Peak memory | 574688 kb |
| Host | smart-217d22e9-652c-4157-b94b-00be47bbb987 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=549952736 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_error.549952736 |
| Directory | /workspace/42.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_stress_all_with_rand_reset.2290298218 |
| Short name | T2636 |
| Test name | |
| Test status | |
| Simulation time | 61611486 ps |
| CPU time | 13.24 seconds |
| Started | Jul 03 07:30:17 PM PDT 24 |
| Finished | Jul 03 07:30:34 PM PDT 24 |
| Peak memory | 573576 kb |
| Host | smart-70c43831-40fb-40c8-83f1-fff23f80f2d5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2290298218 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all _with_rand_reset.2290298218 |
| Directory | /workspace/42.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_stress_all_with_reset_error.861002259 |
| Short name | T1662 |
| Test name | |
| Test status | |
| Simulation time | 1774379723 ps |
| CPU time | 212.46 seconds |
| Started | Jul 03 07:30:20 PM PDT 24 |
| Finished | Jul 03 07:33:54 PM PDT 24 |
| Peak memory | 574592 kb |
| Host | smart-476a943d-3888-4429-a67e-e4cb7afa18b0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=861002259 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all _with_reset_error.861002259 |
| Directory | /workspace/42.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_unmapped_addr.2386263279 |
| Short name | T1580 |
| Test name | |
| Test status | |
| Simulation time | 1008347161 ps |
| CPU time | 39.59 seconds |
| Started | Jul 03 07:30:19 PM PDT 24 |
| Finished | Jul 03 07:31:01 PM PDT 24 |
| Peak memory | 574240 kb |
| Host | smart-b2c0d566-28cd-43a8-ab20-2163e4fe572d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386263279 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_unmapped_addr.2386263279 |
| Directory | /workspace/42.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_access_same_device.1499918046 |
| Short name | T2743 |
| Test name | |
| Test status | |
| Simulation time | 70378594 ps |
| CPU time | 7.95 seconds |
| Started | Jul 03 07:30:26 PM PDT 24 |
| Finished | Jul 03 07:30:36 PM PDT 24 |
| Peak memory | 572948 kb |
| Host | smart-ae1029d0-2587-429d-8e32-9e8ff06dcec7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1499918046 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_access_same_device .1499918046 |
| Directory | /workspace/43.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_error_and_unmapped_addr.2428482357 |
| Short name | T2854 |
| Test name | |
| Test status | |
| Simulation time | 23232740 ps |
| CPU time | 5.71 seconds |
| Started | Jul 03 07:30:31 PM PDT 24 |
| Finished | Jul 03 07:30:38 PM PDT 24 |
| Peak memory | 573408 kb |
| Host | smart-1b445f91-83d5-402b-b7cb-a16e2dc6fc33 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2428482357 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_error_and_unmapped_add r.2428482357 |
| Directory | /workspace/43.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_error_random.2011901628 |
| Short name | T1327 |
| Test name | |
| Test status | |
| Simulation time | 515111393 ps |
| CPU time | 47.55 seconds |
| Started | Jul 03 07:30:29 PM PDT 24 |
| Finished | Jul 03 07:31:18 PM PDT 24 |
| Peak memory | 574448 kb |
| Host | smart-b511a4c3-3ba7-4d83-9e92-900c7fc6c213 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2011901628 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_error_random.2011901628 |
| Directory | /workspace/43.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_random.1677080041 |
| Short name | T527 |
| Test name | |
| Test status | |
| Simulation time | 1898766615 ps |
| CPU time | 74.03 seconds |
| Started | Jul 03 07:30:23 PM PDT 24 |
| Finished | Jul 03 07:31:39 PM PDT 24 |
| Peak memory | 574200 kb |
| Host | smart-83d73161-a99f-4794-9a4c-f6eb682cf3f8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1677080041 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_random.1677080041 |
| Directory | /workspace/43.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_random_large_delays.2037507119 |
| Short name | T2057 |
| Test name | |
| Test status | |
| Simulation time | 15812827537 ps |
| CPU time | 173.23 seconds |
| Started | Jul 03 07:30:26 PM PDT 24 |
| Finished | Jul 03 07:33:21 PM PDT 24 |
| Peak memory | 574068 kb |
| Host | smart-3e719e15-cac5-43e6-b579-e2328c719841 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037507119 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_random_large_delays.2037507119 |
| Directory | /workspace/43.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_random_slow_rsp.1659288892 |
| Short name | T2808 |
| Test name | |
| Test status | |
| Simulation time | 52808544474 ps |
| CPU time | 926.07 seconds |
| Started | Jul 03 07:30:23 PM PDT 24 |
| Finished | Jul 03 07:45:50 PM PDT 24 |
| Peak memory | 574252 kb |
| Host | smart-2bc21ffe-78cb-4c4b-9591-d398667de4fd |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1659288892 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_random_slow_rsp.1659288892 |
| Directory | /workspace/43.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_random_zero_delays.2896117594 |
| Short name | T1903 |
| Test name | |
| Test status | |
| Simulation time | 341643190 ps |
| CPU time | 29.05 seconds |
| Started | Jul 03 07:30:25 PM PDT 24 |
| Finished | Jul 03 07:30:56 PM PDT 24 |
| Peak memory | 573972 kb |
| Host | smart-c56fd3cd-1d9b-4f3d-a4ea-8792bb7384a9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896117594 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_random_zero_del ays.2896117594 |
| Directory | /workspace/43.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_same_source.3956612722 |
| Short name | T1407 |
| Test name | |
| Test status | |
| Simulation time | 45094797 ps |
| CPU time | 6.37 seconds |
| Started | Jul 03 07:30:23 PM PDT 24 |
| Finished | Jul 03 07:30:32 PM PDT 24 |
| Peak memory | 573172 kb |
| Host | smart-544bb8b1-e8f3-40f6-b724-c7c2f7214ff0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3956612722 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_same_source.3956612722 |
| Directory | /workspace/43.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_smoke.1908857248 |
| Short name | T2095 |
| Test name | |
| Test status | |
| Simulation time | 56508663 ps |
| CPU time | 6.48 seconds |
| Started | Jul 03 07:30:24 PM PDT 24 |
| Finished | Jul 03 07:30:33 PM PDT 24 |
| Peak memory | 573104 kb |
| Host | smart-7236d039-3d12-4f7b-b511-88eb596fa00c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908857248 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_smoke.1908857248 |
| Directory | /workspace/43.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_smoke_large_delays.2581462343 |
| Short name | T2674 |
| Test name | |
| Test status | |
| Simulation time | 9899798716 ps |
| CPU time | 100.73 seconds |
| Started | Jul 03 07:30:24 PM PDT 24 |
| Finished | Jul 03 07:32:07 PM PDT 24 |
| Peak memory | 573248 kb |
| Host | smart-7592c028-7827-49d3-8049-d695bdca7260 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581462343 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_large_delays.2581462343 |
| Directory | /workspace/43.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_smoke_slow_rsp.3297872215 |
| Short name | T1423 |
| Test name | |
| Test status | |
| Simulation time | 4135027818 ps |
| CPU time | 77.25 seconds |
| Started | Jul 03 07:30:23 PM PDT 24 |
| Finished | Jul 03 07:31:42 PM PDT 24 |
| Peak memory | 574000 kb |
| Host | smart-aa57d5ef-ed39-45ac-8bf8-93f28c49ae40 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3297872215 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_slow_rsp.3297872215 |
| Directory | /workspace/43.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_smoke_zero_delays.3474060593 |
| Short name | T2552 |
| Test name | |
| Test status | |
| Simulation time | 41211428 ps |
| CPU time | 5.72 seconds |
| Started | Jul 03 07:30:22 PM PDT 24 |
| Finished | Jul 03 07:30:29 PM PDT 24 |
| Peak memory | 573264 kb |
| Host | smart-dc674370-daaa-4e2e-b46f-26d4eeb88789 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3474060593 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_zero_delay s.3474060593 |
| Directory | /workspace/43.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_stress_all.2284851903 |
| Short name | T1735 |
| Test name | |
| Test status | |
| Simulation time | 1174763881 ps |
| CPU time | 49.82 seconds |
| Started | Jul 03 07:30:30 PM PDT 24 |
| Finished | Jul 03 07:31:21 PM PDT 24 |
| Peak memory | 574036 kb |
| Host | smart-e0814c0f-34b5-4e4d-904d-a69e7c0a441c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2284851903 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all.2284851903 |
| Directory | /workspace/43.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_stress_all_with_error.2168191132 |
| Short name | T2318 |
| Test name | |
| Test status | |
| Simulation time | 5050688821 ps |
| CPU time | 175.1 seconds |
| Started | Jul 03 07:30:28 PM PDT 24 |
| Finished | Jul 03 07:33:25 PM PDT 24 |
| Peak memory | 574236 kb |
| Host | smart-29a93e15-eb1e-4cd8-9b4b-19180cd121de |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2168191132 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_error.2168191132 |
| Directory | /workspace/43.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_stress_all_with_reset_error.1216260610 |
| Short name | T799 |
| Test name | |
| Test status | |
| Simulation time | 6998905 ps |
| CPU time | 4 seconds |
| Started | Jul 03 07:30:29 PM PDT 24 |
| Finished | Jul 03 07:30:35 PM PDT 24 |
| Peak memory | 564668 kb |
| Host | smart-14ebd965-bc9c-4347-a6d9-625caf1fa014 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1216260610 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_stress_al l_with_reset_error.1216260610 |
| Directory | /workspace/43.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_unmapped_addr.128659405 |
| Short name | T2441 |
| Test name | |
| Test status | |
| Simulation time | 40268561 ps |
| CPU time | 7.75 seconds |
| Started | Jul 03 07:30:29 PM PDT 24 |
| Finished | Jul 03 07:30:39 PM PDT 24 |
| Peak memory | 573220 kb |
| Host | smart-a9857f58-3a62-4e48-8c31-4bb9c6e490d3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=128659405 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_unmapped_addr.128659405 |
| Directory | /workspace/43.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_access_same_device.641822985 |
| Short name | T1858 |
| Test name | |
| Test status | |
| Simulation time | 537421951 ps |
| CPU time | 35.86 seconds |
| Started | Jul 03 07:30:34 PM PDT 24 |
| Finished | Jul 03 07:31:12 PM PDT 24 |
| Peak memory | 573908 kb |
| Host | smart-a15047d4-07fa-4910-a2d4-9aaf952b411b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=641822985 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_access_same_device. 641822985 |
| Directory | /workspace/44.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_access_same_device_slow_rsp.50267126 |
| Short name | T2788 |
| Test name | |
| Test status | |
| Simulation time | 24348051661 ps |
| CPU time | 437.61 seconds |
| Started | Jul 03 07:30:35 PM PDT 24 |
| Finished | Jul 03 07:37:54 PM PDT 24 |
| Peak memory | 574224 kb |
| Host | smart-cf3ba8e0-5458-4a81-b874-b313899db18e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50267126 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_access_same_de vice_slow_rsp.50267126 |
| Directory | /workspace/44.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_error_and_unmapped_addr.1575611854 |
| Short name | T1534 |
| Test name | |
| Test status | |
| Simulation time | 231293587 ps |
| CPU time | 24.47 seconds |
| Started | Jul 03 07:30:43 PM PDT 24 |
| Finished | Jul 03 07:31:08 PM PDT 24 |
| Peak memory | 574468 kb |
| Host | smart-ff9e3c6c-bd8d-41d7-856b-caab8dcd9eb7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1575611854 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_error_and_unmapped_add r.1575611854 |
| Directory | /workspace/44.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_error_random.3989613266 |
| Short name | T2888 |
| Test name | |
| Test status | |
| Simulation time | 141316028 ps |
| CPU time | 8.23 seconds |
| Started | Jul 03 07:30:40 PM PDT 24 |
| Finished | Jul 03 07:30:50 PM PDT 24 |
| Peak memory | 573032 kb |
| Host | smart-e0df2f50-afb2-4862-85f5-6a46306fc46f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3989613266 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_error_random.3989613266 |
| Directory | /workspace/44.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_random.537486131 |
| Short name | T2459 |
| Test name | |
| Test status | |
| Simulation time | 220012355 ps |
| CPU time | 11.06 seconds |
| Started | Jul 03 07:30:33 PM PDT 24 |
| Finished | Jul 03 07:30:46 PM PDT 24 |
| Peak memory | 573052 kb |
| Host | smart-ba1a60f3-a098-4aa0-af88-187b38bba5aa |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=537486131 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_random.537486131 |
| Directory | /workspace/44.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_random_large_delays.1632615256 |
| Short name | T2704 |
| Test name | |
| Test status | |
| Simulation time | 36000481521 ps |
| CPU time | 379.56 seconds |
| Started | Jul 03 07:30:34 PM PDT 24 |
| Finished | Jul 03 07:36:55 PM PDT 24 |
| Peak memory | 574296 kb |
| Host | smart-1d64fee6-48e4-4866-ad9f-13e734e7e169 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1632615256 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_random_large_delays.1632615256 |
| Directory | /workspace/44.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_random_slow_rsp.2065745676 |
| Short name | T1740 |
| Test name | |
| Test status | |
| Simulation time | 8802540775 ps |
| CPU time | 152.35 seconds |
| Started | Jul 03 07:30:33 PM PDT 24 |
| Finished | Jul 03 07:33:07 PM PDT 24 |
| Peak memory | 574236 kb |
| Host | smart-44d8d63b-36eb-4c53-a4a1-641310e0ecf7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065745676 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_random_slow_rsp.2065745676 |
| Directory | /workspace/44.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_random_zero_delays.3449513918 |
| Short name | T2276 |
| Test name | |
| Test status | |
| Simulation time | 492176847 ps |
| CPU time | 45.49 seconds |
| Started | Jul 03 07:30:35 PM PDT 24 |
| Finished | Jul 03 07:31:22 PM PDT 24 |
| Peak memory | 574292 kb |
| Host | smart-265b8548-34ec-45ec-8524-2938c39bee30 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3449513918 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_random_zero_del ays.3449513918 |
| Directory | /workspace/44.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_same_source.2832794813 |
| Short name | T589 |
| Test name | |
| Test status | |
| Simulation time | 879809829 ps |
| CPU time | 26.74 seconds |
| Started | Jul 03 07:30:33 PM PDT 24 |
| Finished | Jul 03 07:31:01 PM PDT 24 |
| Peak memory | 574120 kb |
| Host | smart-4e3ff0ac-de4a-476d-8dfd-e47fbe8fb5a0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2832794813 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_same_source.2832794813 |
| Directory | /workspace/44.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_smoke.2686053759 |
| Short name | T2060 |
| Test name | |
| Test status | |
| Simulation time | 179857244 ps |
| CPU time | 8.54 seconds |
| Started | Jul 03 07:30:26 PM PDT 24 |
| Finished | Jul 03 07:30:37 PM PDT 24 |
| Peak memory | 573140 kb |
| Host | smart-1beca1de-8756-48e9-a198-c8335cb3723c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2686053759 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_smoke.2686053759 |
| Directory | /workspace/44.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_smoke_large_delays.364824489 |
| Short name | T1322 |
| Test name | |
| Test status | |
| Simulation time | 4925617429 ps |
| CPU time | 48.7 seconds |
| Started | Jul 03 07:30:30 PM PDT 24 |
| Finished | Jul 03 07:31:20 PM PDT 24 |
| Peak memory | 573216 kb |
| Host | smart-b93a9f44-d807-4304-9ac7-4d0dc5173d1d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=364824489 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_large_delays.364824489 |
| Directory | /workspace/44.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_smoke_slow_rsp.2214262690 |
| Short name | T1745 |
| Test name | |
| Test status | |
| Simulation time | 4921179350 ps |
| CPU time | 89.48 seconds |
| Started | Jul 03 07:30:34 PM PDT 24 |
| Finished | Jul 03 07:32:04 PM PDT 24 |
| Peak memory | 573028 kb |
| Host | smart-54f77edf-094e-4f4f-84a1-679350ca29c5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2214262690 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_slow_rsp.2214262690 |
| Directory | /workspace/44.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_smoke_zero_delays.3001513812 |
| Short name | T1983 |
| Test name | |
| Test status | |
| Simulation time | 48733231 ps |
| CPU time | 6.75 seconds |
| Started | Jul 03 07:30:29 PM PDT 24 |
| Finished | Jul 03 07:30:37 PM PDT 24 |
| Peak memory | 574148 kb |
| Host | smart-f163aa89-ef2b-4710-b837-4df3e8c1af08 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3001513812 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_zero_delay s.3001513812 |
| Directory | /workspace/44.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_stress_all.389006151 |
| Short name | T2819 |
| Test name | |
| Test status | |
| Simulation time | 9598474183 ps |
| CPU time | 375.3 seconds |
| Started | Jul 03 07:30:42 PM PDT 24 |
| Finished | Jul 03 07:36:59 PM PDT 24 |
| Peak memory | 574552 kb |
| Host | smart-68e32ecf-cee9-4187-b9e3-bf1c2bb5943a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=389006151 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all.389006151 |
| Directory | /workspace/44.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_stress_all_with_error.1357717862 |
| Short name | T1430 |
| Test name | |
| Test status | |
| Simulation time | 4322894206 ps |
| CPU time | 145.92 seconds |
| Started | Jul 03 07:30:40 PM PDT 24 |
| Finished | Jul 03 07:33:07 PM PDT 24 |
| Peak memory | 574112 kb |
| Host | smart-1d9c435a-462f-4319-91c7-c7a25aa8d40f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1357717862 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_error.1357717862 |
| Directory | /workspace/44.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_stress_all_with_reset_error.3264371199 |
| Short name | T780 |
| Test name | |
| Test status | |
| Simulation time | 18767742981 ps |
| CPU time | 717.9 seconds |
| Started | Jul 03 07:30:39 PM PDT 24 |
| Finished | Jul 03 07:42:39 PM PDT 24 |
| Peak memory | 574704 kb |
| Host | smart-24c53cfa-2a0a-4075-ad9c-1f081c8f7deb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3264371199 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_stress_al l_with_reset_error.3264371199 |
| Directory | /workspace/44.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_unmapped_addr.4137170083 |
| Short name | T2564 |
| Test name | |
| Test status | |
| Simulation time | 298622147 ps |
| CPU time | 34.92 seconds |
| Started | Jul 03 07:30:39 PM PDT 24 |
| Finished | Jul 03 07:31:15 PM PDT 24 |
| Peak memory | 574256 kb |
| Host | smart-8e75f6ea-fe34-4ae7-baf0-b05149647bbb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4137170083 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_unmapped_addr.4137170083 |
| Directory | /workspace/44.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_access_same_device.1326437980 |
| Short name | T2764 |
| Test name | |
| Test status | |
| Simulation time | 649261957 ps |
| CPU time | 61.31 seconds |
| Started | Jul 03 07:30:45 PM PDT 24 |
| Finished | Jul 03 07:31:47 PM PDT 24 |
| Peak memory | 574172 kb |
| Host | smart-4c48c57b-a100-4bce-82c6-98543c536797 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1326437980 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_access_same_device .1326437980 |
| Directory | /workspace/45.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_access_same_device_slow_rsp.1949429108 |
| Short name | T1834 |
| Test name | |
| Test status | |
| Simulation time | 85021485001 ps |
| CPU time | 1544.98 seconds |
| Started | Jul 03 07:30:45 PM PDT 24 |
| Finished | Jul 03 07:56:31 PM PDT 24 |
| Peak memory | 574328 kb |
| Host | smart-1e576911-1d90-4350-8ced-7c9c4ed7e7f7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1949429108 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_access_same_ device_slow_rsp.1949429108 |
| Directory | /workspace/45.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_error_and_unmapped_addr.4182120968 |
| Short name | T1658 |
| Test name | |
| Test status | |
| Simulation time | 159550415 ps |
| CPU time | 17.56 seconds |
| Started | Jul 03 07:30:50 PM PDT 24 |
| Finished | Jul 03 07:31:08 PM PDT 24 |
| Peak memory | 574444 kb |
| Host | smart-1d68aa5f-6800-4f60-ae06-54a6be337148 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4182120968 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_error_and_unmapped_add r.4182120968 |
| Directory | /workspace/45.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_error_random.934437315 |
| Short name | T1932 |
| Test name | |
| Test status | |
| Simulation time | 1649114379 ps |
| CPU time | 60.79 seconds |
| Started | Jul 03 07:30:50 PM PDT 24 |
| Finished | Jul 03 07:31:51 PM PDT 24 |
| Peak memory | 574596 kb |
| Host | smart-ba6434fd-91cc-4d6e-b068-9186486f4919 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=934437315 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_error_random.934437315 |
| Directory | /workspace/45.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_random.2470667178 |
| Short name | T1772 |
| Test name | |
| Test status | |
| Simulation time | 1568806906 ps |
| CPU time | 54.41 seconds |
| Started | Jul 03 07:30:45 PM PDT 24 |
| Finished | Jul 03 07:31:40 PM PDT 24 |
| Peak memory | 574156 kb |
| Host | smart-3be597b2-bd53-4f5c-980a-14bd870fce2c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2470667178 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_random.2470667178 |
| Directory | /workspace/45.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_random_large_delays.469654360 |
| Short name | T1470 |
| Test name | |
| Test status | |
| Simulation time | 15121056679 ps |
| CPU time | 161.94 seconds |
| Started | Jul 03 07:30:44 PM PDT 24 |
| Finished | Jul 03 07:33:27 PM PDT 24 |
| Peak memory | 574284 kb |
| Host | smart-8f3e9028-eb04-48ce-bbdb-c4d6cf91ae36 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=469654360 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_random_large_delays.469654360 |
| Directory | /workspace/45.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_random_slow_rsp.248469950 |
| Short name | T2287 |
| Test name | |
| Test status | |
| Simulation time | 32016992264 ps |
| CPU time | 560.54 seconds |
| Started | Jul 03 07:30:45 PM PDT 24 |
| Finished | Jul 03 07:40:07 PM PDT 24 |
| Peak memory | 574312 kb |
| Host | smart-2745b31e-de47-4629-af56-3ddc51bf08b4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=248469950 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_random_slow_rsp.248469950 |
| Directory | /workspace/45.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_random_zero_delays.1370129482 |
| Short name | T2581 |
| Test name | |
| Test status | |
| Simulation time | 121823055 ps |
| CPU time | 12.57 seconds |
| Started | Jul 03 07:30:45 PM PDT 24 |
| Finished | Jul 03 07:30:59 PM PDT 24 |
| Peak memory | 574176 kb |
| Host | smart-ce5d939f-6f63-434e-b2b6-36941db3fd98 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1370129482 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_random_zero_del ays.1370129482 |
| Directory | /workspace/45.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_same_source.1169364210 |
| Short name | T2114 |
| Test name | |
| Test status | |
| Simulation time | 2251886361 ps |
| CPU time | 66.94 seconds |
| Started | Jul 03 07:30:50 PM PDT 24 |
| Finished | Jul 03 07:31:57 PM PDT 24 |
| Peak memory | 574244 kb |
| Host | smart-917162ff-334d-4a2b-bafc-26bb89d30c66 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1169364210 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_same_source.1169364210 |
| Directory | /workspace/45.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_smoke.2613815793 |
| Short name | T2331 |
| Test name | |
| Test status | |
| Simulation time | 238203511 ps |
| CPU time | 9.9 seconds |
| Started | Jul 03 07:30:40 PM PDT 24 |
| Finished | Jul 03 07:30:52 PM PDT 24 |
| Peak memory | 574140 kb |
| Host | smart-ac1221d9-c8df-4026-b122-7a54dbfee70f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2613815793 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_smoke.2613815793 |
| Directory | /workspace/45.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_smoke_large_delays.1120779860 |
| Short name | T2675 |
| Test name | |
| Test status | |
| Simulation time | 6447412727 ps |
| CPU time | 70.7 seconds |
| Started | Jul 03 07:30:44 PM PDT 24 |
| Finished | Jul 03 07:31:56 PM PDT 24 |
| Peak memory | 574044 kb |
| Host | smart-d0434958-1232-4397-a302-7d4ae2d833cf |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120779860 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_large_delays.1120779860 |
| Directory | /workspace/45.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_smoke_slow_rsp.1980191996 |
| Short name | T1860 |
| Test name | |
| Test status | |
| Simulation time | 5439481167 ps |
| CPU time | 89.04 seconds |
| Started | Jul 03 07:30:44 PM PDT 24 |
| Finished | Jul 03 07:32:14 PM PDT 24 |
| Peak memory | 573188 kb |
| Host | smart-822c8b90-7c0d-45b6-88b5-3d7e3539205d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1980191996 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_slow_rsp.1980191996 |
| Directory | /workspace/45.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_smoke_zero_delays.934701311 |
| Short name | T2324 |
| Test name | |
| Test status | |
| Simulation time | 47095559 ps |
| CPU time | 6.77 seconds |
| Started | Jul 03 07:30:39 PM PDT 24 |
| Finished | Jul 03 07:30:47 PM PDT 24 |
| Peak memory | 574000 kb |
| Host | smart-7c366ebe-056c-4b87-96eb-24fc688886a8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=934701311 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_zero_delays .934701311 |
| Directory | /workspace/45.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_stress_all.3702164860 |
| Short name | T2391 |
| Test name | |
| Test status | |
| Simulation time | 15731625055 ps |
| CPU time | 724.56 seconds |
| Started | Jul 03 07:30:48 PM PDT 24 |
| Finished | Jul 03 07:42:54 PM PDT 24 |
| Peak memory | 574736 kb |
| Host | smart-b789796e-9e00-4403-96a9-69fd9c6eb796 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3702164860 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all.3702164860 |
| Directory | /workspace/45.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_stress_all_with_error.1529099254 |
| Short name | T1783 |
| Test name | |
| Test status | |
| Simulation time | 3454030122 ps |
| CPU time | 138.04 seconds |
| Started | Jul 03 07:30:59 PM PDT 24 |
| Finished | Jul 03 07:33:18 PM PDT 24 |
| Peak memory | 574584 kb |
| Host | smart-b08fad7d-23ce-43fd-88f6-a7bd7918ff54 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1529099254 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_error.1529099254 |
| Directory | /workspace/45.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_stress_all_with_rand_reset.1989292918 |
| Short name | T810 |
| Test name | |
| Test status | |
| Simulation time | 5976175643 ps |
| CPU time | 438.29 seconds |
| Started | Jul 03 07:30:47 PM PDT 24 |
| Finished | Jul 03 07:38:06 PM PDT 24 |
| Peak memory | 574740 kb |
| Host | smart-0b8c31d6-cd06-419d-a55b-387e4204ee12 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1989292918 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all _with_rand_reset.1989292918 |
| Directory | /workspace/45.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_stress_all_with_reset_error.3015209716 |
| Short name | T817 |
| Test name | |
| Test status | |
| Simulation time | 431257626 ps |
| CPU time | 116.04 seconds |
| Started | Jul 03 07:30:58 PM PDT 24 |
| Finished | Jul 03 07:32:56 PM PDT 24 |
| Peak memory | 574628 kb |
| Host | smart-39c517b6-2c1c-41b1-9d9d-938b0eb933b1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3015209716 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_stress_al l_with_reset_error.3015209716 |
| Directory | /workspace/45.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_unmapped_addr.3034409660 |
| Short name | T2183 |
| Test name | |
| Test status | |
| Simulation time | 320621723 ps |
| CPU time | 35.24 seconds |
| Started | Jul 03 07:30:48 PM PDT 24 |
| Finished | Jul 03 07:31:24 PM PDT 24 |
| Peak memory | 574208 kb |
| Host | smart-82412709-c743-4d89-a92f-71db6aba4e53 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034409660 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_unmapped_addr.3034409660 |
| Directory | /workspace/45.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_access_same_device.4184484557 |
| Short name | T1620 |
| Test name | |
| Test status | |
| Simulation time | 675766646 ps |
| CPU time | 46.95 seconds |
| Started | Jul 03 07:30:57 PM PDT 24 |
| Finished | Jul 03 07:31:45 PM PDT 24 |
| Peak memory | 574168 kb |
| Host | smart-5a358988-635d-41c0-9e63-ffa66e1eef04 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4184484557 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_access_same_device .4184484557 |
| Directory | /workspace/46.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_access_same_device_slow_rsp.366841757 |
| Short name | T2100 |
| Test name | |
| Test status | |
| Simulation time | 96441241777 ps |
| CPU time | 1747.04 seconds |
| Started | Jul 03 07:30:58 PM PDT 24 |
| Finished | Jul 03 08:00:07 PM PDT 24 |
| Peak memory | 574096 kb |
| Host | smart-fc213c65-8318-47dd-a823-8ef073d1e698 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=366841757 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_access_same_d evice_slow_rsp.366841757 |
| Directory | /workspace/46.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_error_and_unmapped_addr.4088500824 |
| Short name | T2418 |
| Test name | |
| Test status | |
| Simulation time | 1301462040 ps |
| CPU time | 48.7 seconds |
| Started | Jul 03 07:31:03 PM PDT 24 |
| Finished | Jul 03 07:31:52 PM PDT 24 |
| Peak memory | 574440 kb |
| Host | smart-e3e1f89e-d1f2-4c8f-9a10-738a60c0ed0f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4088500824 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_error_and_unmapped_add r.4088500824 |
| Directory | /workspace/46.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_error_random.433847507 |
| Short name | T2711 |
| Test name | |
| Test status | |
| Simulation time | 1866789376 ps |
| CPU time | 64.31 seconds |
| Started | Jul 03 07:30:57 PM PDT 24 |
| Finished | Jul 03 07:32:02 PM PDT 24 |
| Peak memory | 574408 kb |
| Host | smart-d37787d3-c506-4439-9981-a5413b6c41e4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=433847507 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_error_random.433847507 |
| Directory | /workspace/46.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_random.2119114667 |
| Short name | T1626 |
| Test name | |
| Test status | |
| Simulation time | 1978134648 ps |
| CPU time | 73.19 seconds |
| Started | Jul 03 07:30:57 PM PDT 24 |
| Finished | Jul 03 07:32:10 PM PDT 24 |
| Peak memory | 574264 kb |
| Host | smart-b1bc5a90-19c2-4ef8-a396-1fa016b4610b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2119114667 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_random.2119114667 |
| Directory | /workspace/46.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_random_large_delays.2133436132 |
| Short name | T1498 |
| Test name | |
| Test status | |
| Simulation time | 17577334173 ps |
| CPU time | 194.72 seconds |
| Started | Jul 03 07:30:55 PM PDT 24 |
| Finished | Jul 03 07:34:11 PM PDT 24 |
| Peak memory | 574088 kb |
| Host | smart-1973e04a-bf3b-46ed-bf4d-5ce7c325e545 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2133436132 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_random_large_delays.2133436132 |
| Directory | /workspace/46.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_random_slow_rsp.1397195924 |
| Short name | T2385 |
| Test name | |
| Test status | |
| Simulation time | 47970085589 ps |
| CPU time | 824.56 seconds |
| Started | Jul 03 07:30:58 PM PDT 24 |
| Finished | Jul 03 07:44:45 PM PDT 24 |
| Peak memory | 574272 kb |
| Host | smart-f8200a77-835b-4cab-8587-4fc7c82568d5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1397195924 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_random_slow_rsp.1397195924 |
| Directory | /workspace/46.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_random_zero_delays.1351310178 |
| Short name | T2380 |
| Test name | |
| Test status | |
| Simulation time | 536528766 ps |
| CPU time | 48.01 seconds |
| Started | Jul 03 07:30:59 PM PDT 24 |
| Finished | Jul 03 07:31:49 PM PDT 24 |
| Peak memory | 574184 kb |
| Host | smart-0d46fe04-ca22-4327-93d3-15857f2b35da |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1351310178 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_random_zero_del ays.1351310178 |
| Directory | /workspace/46.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_same_source.1403709751 |
| Short name | T1590 |
| Test name | |
| Test status | |
| Simulation time | 2461461570 ps |
| CPU time | 74.07 seconds |
| Started | Jul 03 07:30:55 PM PDT 24 |
| Finished | Jul 03 07:32:10 PM PDT 24 |
| Peak memory | 574092 kb |
| Host | smart-c4aec1ff-efb4-4559-a1b3-2abbdfdf503a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1403709751 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_same_source.1403709751 |
| Directory | /workspace/46.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_smoke.1904120391 |
| Short name | T1848 |
| Test name | |
| Test status | |
| Simulation time | 196119831 ps |
| CPU time | 8.82 seconds |
| Started | Jul 03 07:30:57 PM PDT 24 |
| Finished | Jul 03 07:31:07 PM PDT 24 |
| Peak memory | 574144 kb |
| Host | smart-350de94a-4b5f-40bf-9ec9-f29082beb562 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904120391 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_smoke.1904120391 |
| Directory | /workspace/46.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_smoke_large_delays.1562601336 |
| Short name | T1729 |
| Test name | |
| Test status | |
| Simulation time | 7505065637 ps |
| CPU time | 79.7 seconds |
| Started | Jul 03 07:30:59 PM PDT 24 |
| Finished | Jul 03 07:32:20 PM PDT 24 |
| Peak memory | 573244 kb |
| Host | smart-14ca3b46-da72-455d-9cf9-fa7c054b3432 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1562601336 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_large_delays.1562601336 |
| Directory | /workspace/46.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_smoke_slow_rsp.217341069 |
| Short name | T2083 |
| Test name | |
| Test status | |
| Simulation time | 3919487380 ps |
| CPU time | 64.55 seconds |
| Started | Jul 03 07:30:56 PM PDT 24 |
| Finished | Jul 03 07:32:01 PM PDT 24 |
| Peak memory | 572992 kb |
| Host | smart-a7d01ab0-e7f4-448e-8cd2-f506d888d165 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=217341069 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_slow_rsp.217341069 |
| Directory | /workspace/46.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_smoke_zero_delays.3332855668 |
| Short name | T2289 |
| Test name | |
| Test status | |
| Simulation time | 43553408 ps |
| CPU time | 6.11 seconds |
| Started | Jul 03 07:31:04 PM PDT 24 |
| Finished | Jul 03 07:31:11 PM PDT 24 |
| Peak memory | 572908 kb |
| Host | smart-19c712b6-567a-404c-9a7f-f983e82a4a6a |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3332855668 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_zero_delay s.3332855668 |
| Directory | /workspace/46.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_stress_all.1764190642 |
| Short name | T2348 |
| Test name | |
| Test status | |
| Simulation time | 8336885494 ps |
| CPU time | 254.58 seconds |
| Started | Jul 03 07:31:03 PM PDT 24 |
| Finished | Jul 03 07:35:19 PM PDT 24 |
| Peak memory | 574704 kb |
| Host | smart-4c90c11d-f4b3-402f-b24b-3529fbfb92cd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1764190642 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all.1764190642 |
| Directory | /workspace/46.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_stress_all_with_error.954453009 |
| Short name | T775 |
| Test name | |
| Test status | |
| Simulation time | 7064019475 ps |
| CPU time | 232.14 seconds |
| Started | Jul 03 07:31:05 PM PDT 24 |
| Finished | Jul 03 07:34:58 PM PDT 24 |
| Peak memory | 574676 kb |
| Host | smart-f615b8f0-626f-4f4d-a73c-c4fb8f55f57f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=954453009 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_error.954453009 |
| Directory | /workspace/46.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_stress_all_with_rand_reset.1722140561 |
| Short name | T802 |
| Test name | |
| Test status | |
| Simulation time | 34558272 ps |
| CPU time | 51.37 seconds |
| Started | Jul 03 07:30:59 PM PDT 24 |
| Finished | Jul 03 07:31:52 PM PDT 24 |
| Peak memory | 574644 kb |
| Host | smart-71c6fb5b-4151-434f-9da3-31b51f7d804f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1722140561 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all _with_rand_reset.1722140561 |
| Directory | /workspace/46.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_stress_all_with_reset_error.3956066803 |
| Short name | T2267 |
| Test name | |
| Test status | |
| Simulation time | 332892409 ps |
| CPU time | 83.7 seconds |
| Started | Jul 03 07:31:07 PM PDT 24 |
| Finished | Jul 03 07:32:31 PM PDT 24 |
| Peak memory | 574640 kb |
| Host | smart-9c1c6eb9-3285-48d2-9ffa-816df2c2c78d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3956066803 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_stress_al l_with_reset_error.3956066803 |
| Directory | /workspace/46.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_unmapped_addr.3593900921 |
| Short name | T2749 |
| Test name | |
| Test status | |
| Simulation time | 412242259 ps |
| CPU time | 18.89 seconds |
| Started | Jul 03 07:31:02 PM PDT 24 |
| Finished | Jul 03 07:31:22 PM PDT 24 |
| Peak memory | 574224 kb |
| Host | smart-5c77f711-d64f-495b-a3c2-b7940060e5ac |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3593900921 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_unmapped_addr.3593900921 |
| Directory | /workspace/46.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_access_same_device.2625169716 |
| Short name | T2091 |
| Test name | |
| Test status | |
| Simulation time | 102415500 ps |
| CPU time | 9.75 seconds |
| Started | Jul 03 07:31:11 PM PDT 24 |
| Finished | Jul 03 07:31:23 PM PDT 24 |
| Peak memory | 572992 kb |
| Host | smart-3c4e2ced-8b1e-4ffa-a166-f55d544a5903 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2625169716 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_access_same_device .2625169716 |
| Directory | /workspace/47.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_access_same_device_slow_rsp.3554447058 |
| Short name | T2051 |
| Test name | |
| Test status | |
| Simulation time | 43268915610 ps |
| CPU time | 741.14 seconds |
| Started | Jul 03 07:31:12 PM PDT 24 |
| Finished | Jul 03 07:43:36 PM PDT 24 |
| Peak memory | 574316 kb |
| Host | smart-f0852e8d-2871-4edc-ba98-f146ec885281 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3554447058 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_access_same_ device_slow_rsp.3554447058 |
| Directory | /workspace/47.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_error_and_unmapped_addr.1484369170 |
| Short name | T1785 |
| Test name | |
| Test status | |
| Simulation time | 215891509 ps |
| CPU time | 10.71 seconds |
| Started | Jul 03 07:31:11 PM PDT 24 |
| Finished | Jul 03 07:31:24 PM PDT 24 |
| Peak memory | 574520 kb |
| Host | smart-7d968cc9-38a4-468b-a23f-9b96f0f3a551 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1484369170 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_error_and_unmapped_add r.1484369170 |
| Directory | /workspace/47.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_error_random.1166587924 |
| Short name | T2125 |
| Test name | |
| Test status | |
| Simulation time | 2620404385 ps |
| CPU time | 84.78 seconds |
| Started | Jul 03 07:31:11 PM PDT 24 |
| Finished | Jul 03 07:32:38 PM PDT 24 |
| Peak memory | 574108 kb |
| Host | smart-e88112dc-0234-4a31-a1e0-2f8076ca4bdd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1166587924 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_error_random.1166587924 |
| Directory | /workspace/47.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_random.1160513216 |
| Short name | T482 |
| Test name | |
| Test status | |
| Simulation time | 1123433759 ps |
| CPU time | 40.98 seconds |
| Started | Jul 03 07:31:04 PM PDT 24 |
| Finished | Jul 03 07:31:46 PM PDT 24 |
| Peak memory | 574184 kb |
| Host | smart-751b1fa8-6066-4ed5-bc4d-594d17d79c14 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1160513216 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_random.1160513216 |
| Directory | /workspace/47.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_random_large_delays.1516847832 |
| Short name | T2294 |
| Test name | |
| Test status | |
| Simulation time | 4322484221 ps |
| CPU time | 46.3 seconds |
| Started | Jul 03 07:31:09 PM PDT 24 |
| Finished | Jul 03 07:31:58 PM PDT 24 |
| Peak memory | 573316 kb |
| Host | smart-1580ad60-b449-48cf-a0f4-e705e3e07e29 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1516847832 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_random_large_delays.1516847832 |
| Directory | /workspace/47.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_random_slow_rsp.1312089186 |
| Short name | T1558 |
| Test name | |
| Test status | |
| Simulation time | 20770467171 ps |
| CPU time | 368.05 seconds |
| Started | Jul 03 07:31:12 PM PDT 24 |
| Finished | Jul 03 07:37:22 PM PDT 24 |
| Peak memory | 574292 kb |
| Host | smart-ebe42bcc-a0c0-4b9f-9595-a0f6284b65b1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1312089186 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_random_slow_rsp.1312089186 |
| Directory | /workspace/47.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_random_zero_delays.1237857615 |
| Short name | T1564 |
| Test name | |
| Test status | |
| Simulation time | 94795522 ps |
| CPU time | 11.07 seconds |
| Started | Jul 03 07:31:06 PM PDT 24 |
| Finished | Jul 03 07:31:18 PM PDT 24 |
| Peak memory | 574184 kb |
| Host | smart-b5a126f5-cf70-46ad-b921-7e00070d34a0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1237857615 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_random_zero_del ays.1237857615 |
| Directory | /workspace/47.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_same_source.4235923193 |
| Short name | T2712 |
| Test name | |
| Test status | |
| Simulation time | 2585532818 ps |
| CPU time | 76 seconds |
| Started | Jul 03 07:31:15 PM PDT 24 |
| Finished | Jul 03 07:32:32 PM PDT 24 |
| Peak memory | 574040 kb |
| Host | smart-6efaad78-07a8-4022-8b1f-97e70bc86ad7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4235923193 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_same_source.4235923193 |
| Directory | /workspace/47.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_smoke.1822438028 |
| Short name | T1674 |
| Test name | |
| Test status | |
| Simulation time | 221725339 ps |
| CPU time | 9.23 seconds |
| Started | Jul 03 07:31:01 PM PDT 24 |
| Finished | Jul 03 07:31:11 PM PDT 24 |
| Peak memory | 574080 kb |
| Host | smart-525765b8-b884-4a4b-bcb8-7ab62cffafeb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1822438028 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_smoke.1822438028 |
| Directory | /workspace/47.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_smoke_large_delays.585961724 |
| Short name | T1313 |
| Test name | |
| Test status | |
| Simulation time | 8930105644 ps |
| CPU time | 91.72 seconds |
| Started | Jul 03 07:31:05 PM PDT 24 |
| Finished | Jul 03 07:32:37 PM PDT 24 |
| Peak memory | 573144 kb |
| Host | smart-7b340053-cd27-4101-ace3-38695e18bc3f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=585961724 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_large_delays.585961724 |
| Directory | /workspace/47.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_smoke_slow_rsp.1045318772 |
| Short name | T588 |
| Test name | |
| Test status | |
| Simulation time | 5420985305 ps |
| CPU time | 97.04 seconds |
| Started | Jul 03 07:31:06 PM PDT 24 |
| Finished | Jul 03 07:32:44 PM PDT 24 |
| Peak memory | 573052 kb |
| Host | smart-d7ff779b-607b-4314-a9e9-8f99a6812418 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1045318772 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_slow_rsp.1045318772 |
| Directory | /workspace/47.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_smoke_zero_delays.660774916 |
| Short name | T1996 |
| Test name | |
| Test status | |
| Simulation time | 44211908 ps |
| CPU time | 6.31 seconds |
| Started | Jul 03 07:31:09 PM PDT 24 |
| Finished | Jul 03 07:31:17 PM PDT 24 |
| Peak memory | 573232 kb |
| Host | smart-144aa2fa-2d1c-4f05-aded-7d13309e6a32 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=660774916 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_zero_delays .660774916 |
| Directory | /workspace/47.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_stress_all.1263846230 |
| Short name | T2633 |
| Test name | |
| Test status | |
| Simulation time | 13902696851 ps |
| CPU time | 507.08 seconds |
| Started | Jul 03 07:31:09 PM PDT 24 |
| Finished | Jul 03 07:39:39 PM PDT 24 |
| Peak memory | 574704 kb |
| Host | smart-e1df3e56-45d4-4ac9-a26a-eebfaf26bd8a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1263846230 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all.1263846230 |
| Directory | /workspace/47.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_stress_all_with_error.2321475899 |
| Short name | T1520 |
| Test name | |
| Test status | |
| Simulation time | 10529394832 ps |
| CPU time | 415.64 seconds |
| Started | Jul 03 07:31:11 PM PDT 24 |
| Finished | Jul 03 07:38:08 PM PDT 24 |
| Peak memory | 574664 kb |
| Host | smart-0af2f9b5-4418-4271-93b0-289d45527172 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2321475899 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_error.2321475899 |
| Directory | /workspace/47.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_stress_all_with_rand_reset.2883878229 |
| Short name | T2767 |
| Test name | |
| Test status | |
| Simulation time | 4581870514 ps |
| CPU time | 545.31 seconds |
| Started | Jul 03 07:31:16 PM PDT 24 |
| Finished | Jul 03 07:40:22 PM PDT 24 |
| Peak memory | 574696 kb |
| Host | smart-1e65fda4-b440-4515-82d1-b500d03f8766 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2883878229 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all _with_rand_reset.2883878229 |
| Directory | /workspace/47.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_stress_all_with_reset_error.2886836297 |
| Short name | T1528 |
| Test name | |
| Test status | |
| Simulation time | 549339163 ps |
| CPU time | 169.52 seconds |
| Started | Jul 03 07:31:10 PM PDT 24 |
| Finished | Jul 03 07:34:02 PM PDT 24 |
| Peak memory | 574680 kb |
| Host | smart-01e2145b-19cd-4749-a122-e7a6b5204afc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2886836297 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_stress_al l_with_reset_error.2886836297 |
| Directory | /workspace/47.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_unmapped_addr.898940113 |
| Short name | T1391 |
| Test name | |
| Test status | |
| Simulation time | 180711991 ps |
| CPU time | 22.75 seconds |
| Started | Jul 03 07:31:09 PM PDT 24 |
| Finished | Jul 03 07:31:34 PM PDT 24 |
| Peak memory | 574040 kb |
| Host | smart-b88e903b-5b07-45ee-a7d8-ed1200da3974 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=898940113 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_unmapped_addr.898940113 |
| Directory | /workspace/47.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_access_same_device.4148472053 |
| Short name | T1382 |
| Test name | |
| Test status | |
| Simulation time | 254486604 ps |
| CPU time | 25.39 seconds |
| Started | Jul 03 07:31:17 PM PDT 24 |
| Finished | Jul 03 07:31:43 PM PDT 24 |
| Peak memory | 574160 kb |
| Host | smart-75fb7db3-8ebc-43bd-bd00-6565c18d27b3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4148472053 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_access_same_device .4148472053 |
| Directory | /workspace/48.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_access_same_device_slow_rsp.3086621465 |
| Short name | T2144 |
| Test name | |
| Test status | |
| Simulation time | 92690336907 ps |
| CPU time | 1710.41 seconds |
| Started | Jul 03 07:31:17 PM PDT 24 |
| Finished | Jul 03 07:59:48 PM PDT 24 |
| Peak memory | 574128 kb |
| Host | smart-f722679a-414a-4c1d-9dd0-6ecbfc63e68f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3086621465 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_access_same_ device_slow_rsp.3086621465 |
| Directory | /workspace/48.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_error_and_unmapped_addr.3798331682 |
| Short name | T2226 |
| Test name | |
| Test status | |
| Simulation time | 266284594 ps |
| CPU time | 25.53 seconds |
| Started | Jul 03 07:31:20 PM PDT 24 |
| Finished | Jul 03 07:31:46 PM PDT 24 |
| Peak memory | 574436 kb |
| Host | smart-38db6a7d-9e8c-47c9-adad-23aaa346341e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3798331682 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_error_and_unmapped_add r.3798331682 |
| Directory | /workspace/48.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_error_random.3387436786 |
| Short name | T2572 |
| Test name | |
| Test status | |
| Simulation time | 253453716 ps |
| CPU time | 11.12 seconds |
| Started | Jul 03 07:31:16 PM PDT 24 |
| Finished | Jul 03 07:31:27 PM PDT 24 |
| Peak memory | 574024 kb |
| Host | smart-acaa9912-7bb0-4ac0-8364-e3355dfc2680 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387436786 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_error_random.3387436786 |
| Directory | /workspace/48.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_random.1157047862 |
| Short name | T2242 |
| Test name | |
| Test status | |
| Simulation time | 971228211 ps |
| CPU time | 33.99 seconds |
| Started | Jul 03 07:31:15 PM PDT 24 |
| Finished | Jul 03 07:31:50 PM PDT 24 |
| Peak memory | 574124 kb |
| Host | smart-eba64d26-6d5e-44f6-8017-cbcbf6940067 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1157047862 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_random.1157047862 |
| Directory | /workspace/48.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_random_large_delays.1946234459 |
| Short name | T434 |
| Test name | |
| Test status | |
| Simulation time | 52257400835 ps |
| CPU time | 522.25 seconds |
| Started | Jul 03 07:31:17 PM PDT 24 |
| Finished | Jul 03 07:40:00 PM PDT 24 |
| Peak memory | 574248 kb |
| Host | smart-857b1aff-aaf6-4d19-8f5a-46461f6a0dd8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1946234459 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_random_large_delays.1946234459 |
| Directory | /workspace/48.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_random_slow_rsp.3124788429 |
| Short name | T2019 |
| Test name | |
| Test status | |
| Simulation time | 51434898526 ps |
| CPU time | 983.25 seconds |
| Started | Jul 03 07:31:16 PM PDT 24 |
| Finished | Jul 03 07:47:40 PM PDT 24 |
| Peak memory | 574064 kb |
| Host | smart-6332998b-2f8a-4e76-9ab2-ef654f9383ab |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3124788429 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_random_slow_rsp.3124788429 |
| Directory | /workspace/48.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_random_zero_delays.3225375068 |
| Short name | T1538 |
| Test name | |
| Test status | |
| Simulation time | 115513842 ps |
| CPU time | 13.08 seconds |
| Started | Jul 03 07:31:17 PM PDT 24 |
| Finished | Jul 03 07:31:31 PM PDT 24 |
| Peak memory | 574128 kb |
| Host | smart-530338f0-a6ee-4985-b1f3-54c44565668c |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3225375068 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_random_zero_del ays.3225375068 |
| Directory | /workspace/48.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_same_source.4246898863 |
| Short name | T2571 |
| Test name | |
| Test status | |
| Simulation time | 1077844414 ps |
| CPU time | 33.46 seconds |
| Started | Jul 03 07:31:17 PM PDT 24 |
| Finished | Jul 03 07:31:51 PM PDT 24 |
| Peak memory | 573972 kb |
| Host | smart-bf97419b-be0d-46c8-afad-ee8882debc43 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4246898863 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_same_source.4246898863 |
| Directory | /workspace/48.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_smoke.3730655106 |
| Short name | T1841 |
| Test name | |
| Test status | |
| Simulation time | 136356537 ps |
| CPU time | 6.93 seconds |
| Started | Jul 03 07:31:18 PM PDT 24 |
| Finished | Jul 03 07:31:25 PM PDT 24 |
| Peak memory | 573148 kb |
| Host | smart-15d09e77-3bb3-49fd-9647-3fd379cb9c70 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3730655106 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_smoke.3730655106 |
| Directory | /workspace/48.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_smoke_large_delays.1447856680 |
| Short name | T2555 |
| Test name | |
| Test status | |
| Simulation time | 5756297311 ps |
| CPU time | 59.92 seconds |
| Started | Jul 03 07:31:15 PM PDT 24 |
| Finished | Jul 03 07:32:16 PM PDT 24 |
| Peak memory | 574200 kb |
| Host | smart-b5a5d49b-4e48-4c40-b41f-1306868a6fe2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1447856680 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_large_delays.1447856680 |
| Directory | /workspace/48.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_smoke_slow_rsp.1364114095 |
| Short name | T2739 |
| Test name | |
| Test status | |
| Simulation time | 5462638161 ps |
| CPU time | 86.53 seconds |
| Started | Jul 03 07:31:14 PM PDT 24 |
| Finished | Jul 03 07:32:42 PM PDT 24 |
| Peak memory | 574208 kb |
| Host | smart-5c380eb9-dcd7-4dba-bb70-3d06539a3310 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1364114095 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_slow_rsp.1364114095 |
| Directory | /workspace/48.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_smoke_zero_delays.3312805414 |
| Short name | T2720 |
| Test name | |
| Test status | |
| Simulation time | 48935783 ps |
| CPU time | 6.42 seconds |
| Started | Jul 03 07:31:16 PM PDT 24 |
| Finished | Jul 03 07:31:23 PM PDT 24 |
| Peak memory | 574148 kb |
| Host | smart-d4b17e30-8175-420a-aa87-215b137dea03 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312805414 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_zero_delay s.3312805414 |
| Directory | /workspace/48.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_stress_all.1320331000 |
| Short name | T2036 |
| Test name | |
| Test status | |
| Simulation time | 2650018722 ps |
| CPU time | 209.61 seconds |
| Started | Jul 03 07:31:21 PM PDT 24 |
| Finished | Jul 03 07:34:52 PM PDT 24 |
| Peak memory | 574288 kb |
| Host | smart-133e4f68-91d4-4f8d-80e5-9bc498e553fb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1320331000 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all.1320331000 |
| Directory | /workspace/48.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_stress_all_with_error.2746929207 |
| Short name | T2379 |
| Test name | |
| Test status | |
| Simulation time | 1330635912 ps |
| CPU time | 98.15 seconds |
| Started | Jul 03 07:31:20 PM PDT 24 |
| Finished | Jul 03 07:32:59 PM PDT 24 |
| Peak memory | 574520 kb |
| Host | smart-21da7f06-3ac8-4ac4-a1ba-d21098d9fdc7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746929207 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_error.2746929207 |
| Directory | /workspace/48.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_stress_all_with_rand_reset.2251117276 |
| Short name | T1986 |
| Test name | |
| Test status | |
| Simulation time | 10636316346 ps |
| CPU time | 759.44 seconds |
| Started | Jul 03 07:31:21 PM PDT 24 |
| Finished | Jul 03 07:44:02 PM PDT 24 |
| Peak memory | 574704 kb |
| Host | smart-a7d216c8-2418-407f-aeaf-b7f8d5cba189 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2251117276 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all _with_rand_reset.2251117276 |
| Directory | /workspace/48.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_stress_all_with_reset_error.4099001134 |
| Short name | T1805 |
| Test name | |
| Test status | |
| Simulation time | 4591028071 ps |
| CPU time | 234.3 seconds |
| Started | Jul 03 07:31:21 PM PDT 24 |
| Finished | Jul 03 07:35:17 PM PDT 24 |
| Peak memory | 574728 kb |
| Host | smart-7cb3796c-06d5-4f71-823c-abf21294e290 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4099001134 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_stress_al l_with_reset_error.4099001134 |
| Directory | /workspace/48.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_unmapped_addr.1660162523 |
| Short name | T2112 |
| Test name | |
| Test status | |
| Simulation time | 357313754 ps |
| CPU time | 16.12 seconds |
| Started | Jul 03 07:31:22 PM PDT 24 |
| Finished | Jul 03 07:31:39 PM PDT 24 |
| Peak memory | 574340 kb |
| Host | smart-c175017c-83f3-49af-8ed7-aaef5f47d505 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1660162523 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_unmapped_addr.1660162523 |
| Directory | /workspace/48.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_access_same_device.1204660579 |
| Short name | T783 |
| Test name | |
| Test status | |
| Simulation time | 432895691 ps |
| CPU time | 38.54 seconds |
| Started | Jul 03 07:31:35 PM PDT 24 |
| Finished | Jul 03 07:32:14 PM PDT 24 |
| Peak memory | 574140 kb |
| Host | smart-a5c6c313-5c2d-4384-af78-182b50885764 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204660579 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_access_same_device .1204660579 |
| Directory | /workspace/49.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_access_same_device_slow_rsp.2666190764 |
| Short name | T1813 |
| Test name | |
| Test status | |
| Simulation time | 69444251878 ps |
| CPU time | 1152.72 seconds |
| Started | Jul 03 07:31:33 PM PDT 24 |
| Finished | Jul 03 07:50:46 PM PDT 24 |
| Peak memory | 574384 kb |
| Host | smart-7002a1a4-0491-44d4-bf05-9937fe5e152c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2666190764 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_access_same_ device_slow_rsp.2666190764 |
| Directory | /workspace/49.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_error_and_unmapped_addr.1255036015 |
| Short name | T2456 |
| Test name | |
| Test status | |
| Simulation time | 580880547 ps |
| CPU time | 25.6 seconds |
| Started | Jul 03 07:31:32 PM PDT 24 |
| Finished | Jul 03 07:31:58 PM PDT 24 |
| Peak memory | 574436 kb |
| Host | smart-e274f2e4-9c4d-4a53-9001-801f471ae550 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1255036015 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_error_and_unmapped_add r.1255036015 |
| Directory | /workspace/49.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_error_random.2728541746 |
| Short name | T1736 |
| Test name | |
| Test status | |
| Simulation time | 344115392 ps |
| CPU time | 15.32 seconds |
| Started | Jul 03 07:31:33 PM PDT 24 |
| Finished | Jul 03 07:31:49 PM PDT 24 |
| Peak memory | 574464 kb |
| Host | smart-ae281da0-0f12-4b90-8c7c-84def08a24b2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728541746 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_error_random.2728541746 |
| Directory | /workspace/49.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_random.3005142537 |
| Short name | T562 |
| Test name | |
| Test status | |
| Simulation time | 2600710337 ps |
| CPU time | 94.29 seconds |
| Started | Jul 03 07:31:35 PM PDT 24 |
| Finished | Jul 03 07:33:09 PM PDT 24 |
| Peak memory | 574252 kb |
| Host | smart-9701470c-e2db-40cc-8a54-af0c109c75cd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3005142537 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_random.3005142537 |
| Directory | /workspace/49.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_random_large_delays.2761896130 |
| Short name | T2527 |
| Test name | |
| Test status | |
| Simulation time | 89417274447 ps |
| CPU time | 959.79 seconds |
| Started | Jul 03 07:31:32 PM PDT 24 |
| Finished | Jul 03 07:47:33 PM PDT 24 |
| Peak memory | 574036 kb |
| Host | smart-b4332abb-ae6f-43df-abce-7dfee551b71f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761896130 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_random_large_delays.2761896130 |
| Directory | /workspace/49.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_random_slow_rsp.3526449788 |
| Short name | T1826 |
| Test name | |
| Test status | |
| Simulation time | 53998128672 ps |
| CPU time | 970.86 seconds |
| Started | Jul 03 07:31:32 PM PDT 24 |
| Finished | Jul 03 07:47:44 PM PDT 24 |
| Peak memory | 574228 kb |
| Host | smart-a95817fd-911f-4ebb-977c-c8d8e38a2418 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3526449788 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_random_slow_rsp.3526449788 |
| Directory | /workspace/49.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_random_zero_delays.1625004957 |
| Short name | T2648 |
| Test name | |
| Test status | |
| Simulation time | 349076676 ps |
| CPU time | 29.62 seconds |
| Started | Jul 03 07:31:32 PM PDT 24 |
| Finished | Jul 03 07:32:03 PM PDT 24 |
| Peak memory | 574220 kb |
| Host | smart-88cc9cfa-e493-4c68-9dff-93bf75b6382f |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1625004957 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_random_zero_del ays.1625004957 |
| Directory | /workspace/49.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_same_source.844521140 |
| Short name | T2824 |
| Test name | |
| Test status | |
| Simulation time | 2091692368 ps |
| CPU time | 65.88 seconds |
| Started | Jul 03 07:31:34 PM PDT 24 |
| Finished | Jul 03 07:32:40 PM PDT 24 |
| Peak memory | 574000 kb |
| Host | smart-c2c6a964-3bac-4896-86c0-080bb6c95cdd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=844521140 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_same_source.844521140 |
| Directory | /workspace/49.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_smoke.1427513991 |
| Short name | T2668 |
| Test name | |
| Test status | |
| Simulation time | 190506503 ps |
| CPU time | 8.69 seconds |
| Started | Jul 03 07:31:35 PM PDT 24 |
| Finished | Jul 03 07:31:44 PM PDT 24 |
| Peak memory | 573144 kb |
| Host | smart-c867c77f-400f-4cf7-9bb9-133017eb5d65 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1427513991 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_smoke.1427513991 |
| Directory | /workspace/49.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_smoke_large_delays.1762525517 |
| Short name | T2679 |
| Test name | |
| Test status | |
| Simulation time | 9790424777 ps |
| CPU time | 98.2 seconds |
| Started | Jul 03 07:31:26 PM PDT 24 |
| Finished | Jul 03 07:33:05 PM PDT 24 |
| Peak memory | 573224 kb |
| Host | smart-b2890d6c-d5cd-48d7-96ea-3c388b7d5c50 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1762525517 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_large_delays.1762525517 |
| Directory | /workspace/49.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_smoke_slow_rsp.2411890436 |
| Short name | T1567 |
| Test name | |
| Test status | |
| Simulation time | 5331437552 ps |
| CPU time | 92.93 seconds |
| Started | Jul 03 07:31:34 PM PDT 24 |
| Finished | Jul 03 07:33:07 PM PDT 24 |
| Peak memory | 574232 kb |
| Host | smart-a22270e8-1a70-447f-9699-0fb84e9565b9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2411890436 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_slow_rsp.2411890436 |
| Directory | /workspace/49.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_smoke_zero_delays.410147705 |
| Short name | T1302 |
| Test name | |
| Test status | |
| Simulation time | 36576782 ps |
| CPU time | 5.5 seconds |
| Started | Jul 03 07:31:27 PM PDT 24 |
| Finished | Jul 03 07:31:33 PM PDT 24 |
| Peak memory | 573896 kb |
| Host | smart-a3e1f012-b0de-48bc-b218-07cc9fb867e1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=410147705 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_zero_delays .410147705 |
| Directory | /workspace/49.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_stress_all.939840707 |
| Short name | T532 |
| Test name | |
| Test status | |
| Simulation time | 11904976071 ps |
| CPU time | 433.29 seconds |
| Started | Jul 03 07:31:32 PM PDT 24 |
| Finished | Jul 03 07:38:47 PM PDT 24 |
| Peak memory | 574748 kb |
| Host | smart-92f41daf-272b-46e8-9e96-bf9dd91f402f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=939840707 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all.939840707 |
| Directory | /workspace/49.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_stress_all_with_error.1128175265 |
| Short name | T2005 |
| Test name | |
| Test status | |
| Simulation time | 3005373753 ps |
| CPU time | 236.91 seconds |
| Started | Jul 03 07:31:39 PM PDT 24 |
| Finished | Jul 03 07:35:37 PM PDT 24 |
| Peak memory | 574696 kb |
| Host | smart-d512b75c-3918-4421-9cc7-80589eda4fac |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1128175265 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_error.1128175265 |
| Directory | /workspace/49.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_stress_all_with_rand_reset.1601441997 |
| Short name | T2405 |
| Test name | |
| Test status | |
| Simulation time | 226703395 ps |
| CPU time | 63.48 seconds |
| Started | Jul 03 07:31:32 PM PDT 24 |
| Finished | Jul 03 07:32:36 PM PDT 24 |
| Peak memory | 574680 kb |
| Host | smart-14c87f30-6a9d-42cb-a9b9-45104036bc37 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1601441997 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all _with_rand_reset.1601441997 |
| Directory | /workspace/49.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_stress_all_with_reset_error.3975317942 |
| Short name | T1930 |
| Test name | |
| Test status | |
| Simulation time | 1751983859 ps |
| CPU time | 313.73 seconds |
| Started | Jul 03 07:31:41 PM PDT 24 |
| Finished | Jul 03 07:36:56 PM PDT 24 |
| Peak memory | 574668 kb |
| Host | smart-4734644d-3422-4654-8e6c-6a17d6f38938 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3975317942 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_stress_al l_with_reset_error.3975317942 |
| Directory | /workspace/49.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_unmapped_addr.3302463571 |
| Short name | T1458 |
| Test name | |
| Test status | |
| Simulation time | 265272889 ps |
| CPU time | 16.19 seconds |
| Started | Jul 03 07:31:31 PM PDT 24 |
| Finished | Jul 03 07:31:48 PM PDT 24 |
| Peak memory | 573992 kb |
| Host | smart-97062762-afb5-48ad-b118-5e754cb06592 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3302463571 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_unmapped_addr.3302463571 |
| Directory | /workspace/49.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/5.chip_csr_rw.108365275 |
| Short name | T1556 |
| Test name | |
| Test status | |
| Simulation time | 6007343760 ps |
| CPU time | 485.11 seconds |
| Started | Jul 03 07:22:57 PM PDT 24 |
| Finished | Jul 03 07:31:04 PM PDT 24 |
| Peak memory | 597304 kb |
| Host | smart-83ff86cd-17c1-4ddd-8ad7-7c9dc3463099 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108365275 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.chip_csr_rw.108365275 |
| Directory | /workspace/5.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/5.chip_same_csr_outstanding.940982734 |
| Short name | T380 |
| Test name | |
| Test status | |
| Simulation time | 32135600442 ps |
| CPU time | 4250.74 seconds |
| Started | Jul 03 07:22:44 PM PDT 24 |
| Finished | Jul 03 08:33:37 PM PDT 24 |
| Peak memory | 592428 kb |
| Host | smart-2742355e-039f-42c4-ac83-9afa28df83c1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=940982734 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 5.chip_same_csr_outstanding.940982734 |
| Directory | /workspace/5.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/5.chip_tl_errors.1893340342 |
| Short name | T2334 |
| Test name | |
| Test status | |
| Simulation time | 2526209564 ps |
| CPU time | 103.34 seconds |
| Started | Jul 03 07:22:45 PM PDT 24 |
| Finished | Jul 03 07:24:30 PM PDT 24 |
| Peak memory | 599024 kb |
| Host | smart-90093702-0e83-40f8-9cc3-954f7806d8d3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1893340342 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.chip_tl_errors.1893340342 |
| Directory | /workspace/5.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_access_same_device.2517337084 |
| Short name | T2589 |
| Test name | |
| Test status | |
| Simulation time | 782552459 ps |
| CPU time | 64.92 seconds |
| Started | Jul 03 07:22:51 PM PDT 24 |
| Finished | Jul 03 07:23:57 PM PDT 24 |
| Peak memory | 574200 kb |
| Host | smart-94fadf87-4511-4b0f-b8cb-49b9911239d2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2517337084 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_access_same_device. 2517337084 |
| Directory | /workspace/5.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_access_same_device_slow_rsp.1418281581 |
| Short name | T770 |
| Test name | |
| Test status | |
| Simulation time | 45683519593 ps |
| CPU time | 796.4 seconds |
| Started | Jul 03 07:22:49 PM PDT 24 |
| Finished | Jul 03 07:36:06 PM PDT 24 |
| Peak memory | 574348 kb |
| Host | smart-4f8b8620-c256-4baa-8187-22edba64e3c3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1418281581 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_access_same_d evice_slow_rsp.1418281581 |
| Directory | /workspace/5.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_error_and_unmapped_addr.2369339704 |
| Short name | T2730 |
| Test name | |
| Test status | |
| Simulation time | 36152660 ps |
| CPU time | 6.42 seconds |
| Started | Jul 03 07:22:48 PM PDT 24 |
| Finished | Jul 03 07:22:56 PM PDT 24 |
| Peak memory | 573380 kb |
| Host | smart-d2e3b1c4-af2f-4e36-be36-657835d51418 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369339704 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_error_and_unmapped_addr .2369339704 |
| Directory | /workspace/5.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_error_random.1196849299 |
| Short name | T2384 |
| Test name | |
| Test status | |
| Simulation time | 2200585861 ps |
| CPU time | 75.59 seconds |
| Started | Jul 03 07:22:50 PM PDT 24 |
| Finished | Jul 03 07:24:06 PM PDT 24 |
| Peak memory | 574156 kb |
| Host | smart-e45f8eb4-43ef-485e-8404-e08c4161711e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1196849299 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_error_random.1196849299 |
| Directory | /workspace/5.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_random.3872476313 |
| Short name | T1544 |
| Test name | |
| Test status | |
| Simulation time | 1083031230 ps |
| CPU time | 36.21 seconds |
| Started | Jul 03 07:22:52 PM PDT 24 |
| Finished | Jul 03 07:23:29 PM PDT 24 |
| Peak memory | 574144 kb |
| Host | smart-2f9e036f-e51b-40f6-b3d1-c6462dddf5b2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3872476313 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_random.3872476313 |
| Directory | /workspace/5.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_random_large_delays.1738725668 |
| Short name | T551 |
| Test name | |
| Test status | |
| Simulation time | 52414380325 ps |
| CPU time | 510.56 seconds |
| Started | Jul 03 07:22:52 PM PDT 24 |
| Finished | Jul 03 07:31:24 PM PDT 24 |
| Peak memory | 574288 kb |
| Host | smart-80ebf229-bee8-4cd9-a349-625d3d16d50d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1738725668 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_random_large_delays.1738725668 |
| Directory | /workspace/5.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_random_slow_rsp.4231221839 |
| Short name | T2228 |
| Test name | |
| Test status | |
| Simulation time | 35590116626 ps |
| CPU time | 547.41 seconds |
| Started | Jul 03 07:22:53 PM PDT 24 |
| Finished | Jul 03 07:32:01 PM PDT 24 |
| Peak memory | 574068 kb |
| Host | smart-e18b391a-61ec-4ac9-b0d9-a46d14fc2fd7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4231221839 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_random_slow_rsp.4231221839 |
| Directory | /workspace/5.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_random_zero_delays.1312249575 |
| Short name | T607 |
| Test name | |
| Test status | |
| Simulation time | 181073378 ps |
| CPU time | 18.37 seconds |
| Started | Jul 03 07:22:47 PM PDT 24 |
| Finished | Jul 03 07:23:06 PM PDT 24 |
| Peak memory | 574188 kb |
| Host | smart-ed56ece5-4c55-4907-9a50-eac4d918a41f |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1312249575 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_random_zero_dela ys.1312249575 |
| Directory | /workspace/5.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_same_source.3901672575 |
| Short name | T1719 |
| Test name | |
| Test status | |
| Simulation time | 1943330539 ps |
| CPU time | 62.01 seconds |
| Started | Jul 03 07:22:54 PM PDT 24 |
| Finished | Jul 03 07:23:57 PM PDT 24 |
| Peak memory | 573960 kb |
| Host | smart-0e8c5fdd-2e8b-4a8d-a86b-3bc5655594a6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3901672575 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_same_source.3901672575 |
| Directory | /workspace/5.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_smoke.2778391714 |
| Short name | T1911 |
| Test name | |
| Test status | |
| Simulation time | 184668342 ps |
| CPU time | 8 seconds |
| Started | Jul 03 07:22:43 PM PDT 24 |
| Finished | Jul 03 07:22:53 PM PDT 24 |
| Peak memory | 572932 kb |
| Host | smart-1d4f780f-4482-45c5-b9c1-e2c7dae469c5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2778391714 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_smoke.2778391714 |
| Directory | /workspace/5.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_smoke_large_delays.827751663 |
| Short name | T2189 |
| Test name | |
| Test status | |
| Simulation time | 7905216025 ps |
| CPU time | 79.88 seconds |
| Started | Jul 03 07:22:49 PM PDT 24 |
| Finished | Jul 03 07:24:10 PM PDT 24 |
| Peak memory | 573040 kb |
| Host | smart-96c639f3-e609-499c-8141-eac7a53342cb |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=827751663 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_large_delays.827751663 |
| Directory | /workspace/5.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_smoke_slow_rsp.4249740820 |
| Short name | T509 |
| Test name | |
| Test status | |
| Simulation time | 5818484865 ps |
| CPU time | 100.18 seconds |
| Started | Jul 03 07:22:49 PM PDT 24 |
| Finished | Jul 03 07:24:30 PM PDT 24 |
| Peak memory | 574064 kb |
| Host | smart-ddfc84d7-dcfa-4870-99cf-17fd4f5d1936 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4249740820 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_slow_rsp.4249740820 |
| Directory | /workspace/5.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_smoke_zero_delays.3414256272 |
| Short name | T2618 |
| Test name | |
| Test status | |
| Simulation time | 35228468 ps |
| CPU time | 5.8 seconds |
| Started | Jul 03 07:22:49 PM PDT 24 |
| Finished | Jul 03 07:22:56 PM PDT 24 |
| Peak memory | 574192 kb |
| Host | smart-b9c0fb85-6b30-4ae3-bc49-c5e4c619d0d2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3414256272 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_zero_delays .3414256272 |
| Directory | /workspace/5.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_stress_all.244461797 |
| Short name | T1699 |
| Test name | |
| Test status | |
| Simulation time | 3240596508 ps |
| CPU time | 290.2 seconds |
| Started | Jul 03 07:22:49 PM PDT 24 |
| Finished | Jul 03 07:27:41 PM PDT 24 |
| Peak memory | 574700 kb |
| Host | smart-0329273f-2e09-42f0-bef2-4c02775db6ca |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=244461797 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all.244461797 |
| Directory | /workspace/5.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_stress_all_with_error.549372317 |
| Short name | T2762 |
| Test name | |
| Test status | |
| Simulation time | 11470043468 ps |
| CPU time | 423.76 seconds |
| Started | Jul 03 07:22:50 PM PDT 24 |
| Finished | Jul 03 07:29:55 PM PDT 24 |
| Peak memory | 574224 kb |
| Host | smart-2bee47d3-77e3-4a5b-8a4a-307482130314 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=549372317 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_error.549372317 |
| Directory | /workspace/5.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_stress_all_with_rand_reset.4292766524 |
| Short name | T575 |
| Test name | |
| Test status | |
| Simulation time | 561233539 ps |
| CPU time | 206.9 seconds |
| Started | Jul 03 07:22:49 PM PDT 24 |
| Finished | Jul 03 07:26:17 PM PDT 24 |
| Peak memory | 574656 kb |
| Host | smart-56a2454f-59fb-4fb8-95a2-3e177d59903c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4292766524 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_ with_rand_reset.4292766524 |
| Directory | /workspace/5.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_stress_all_with_reset_error.2172133344 |
| Short name | T2008 |
| Test name | |
| Test status | |
| Simulation time | 295629499 ps |
| CPU time | 85.21 seconds |
| Started | Jul 03 07:22:50 PM PDT 24 |
| Finished | Jul 03 07:24:16 PM PDT 24 |
| Peak memory | 574604 kb |
| Host | smart-d1148ce4-e59b-4758-94c5-a6c5a9bc430a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2172133344 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all _with_reset_error.2172133344 |
| Directory | /workspace/5.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_unmapped_addr.939764470 |
| Short name | T2515 |
| Test name | |
| Test status | |
| Simulation time | 1232194833 ps |
| CPU time | 52.08 seconds |
| Started | Jul 03 07:22:49 PM PDT 24 |
| Finished | Jul 03 07:23:41 PM PDT 24 |
| Peak memory | 574288 kb |
| Host | smart-f60236b3-240b-456b-9b12-e736870495d1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=939764470 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_unmapped_addr.939764470 |
| Directory | /workspace/5.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_access_same_device.1295324400 |
| Short name | T2337 |
| Test name | |
| Test status | |
| Simulation time | 256880467 ps |
| CPU time | 11.94 seconds |
| Started | Jul 03 07:31:39 PM PDT 24 |
| Finished | Jul 03 07:31:52 PM PDT 24 |
| Peak memory | 573000 kb |
| Host | smart-b485b9f9-3fe2-4304-9e40-431ed9fb1d31 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1295324400 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_access_same_device .1295324400 |
| Directory | /workspace/50.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_access_same_device_slow_rsp.2342705703 |
| Short name | T2047 |
| Test name | |
| Test status | |
| Simulation time | 20576269117 ps |
| CPU time | 343.25 seconds |
| Started | Jul 03 07:31:40 PM PDT 24 |
| Finished | Jul 03 07:37:24 PM PDT 24 |
| Peak memory | 574340 kb |
| Host | smart-d3a6bf25-ea74-4495-a31d-a9e7cf9a8985 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2342705703 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_access_same_ device_slow_rsp.2342705703 |
| Directory | /workspace/50.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_error_and_unmapped_addr.1016622071 |
| Short name | T2862 |
| Test name | |
| Test status | |
| Simulation time | 93236379 ps |
| CPU time | 6.89 seconds |
| Started | Jul 03 07:31:46 PM PDT 24 |
| Finished | Jul 03 07:31:55 PM PDT 24 |
| Peak memory | 573024 kb |
| Host | smart-4ec1fed2-b6b3-421f-be49-01157f462e1a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1016622071 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_error_and_unmapped_add r.1016622071 |
| Directory | /workspace/50.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_error_random.1101364683 |
| Short name | T1703 |
| Test name | |
| Test status | |
| Simulation time | 141120473 ps |
| CPU time | 12.71 seconds |
| Started | Jul 03 07:31:42 PM PDT 24 |
| Finished | Jul 03 07:31:55 PM PDT 24 |
| Peak memory | 574452 kb |
| Host | smart-3d75cd22-801b-4723-b724-8a7719b1af42 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1101364683 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_error_random.1101364683 |
| Directory | /workspace/50.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_random.3722250531 |
| Short name | T2399 |
| Test name | |
| Test status | |
| Simulation time | 484117121 ps |
| CPU time | 51.18 seconds |
| Started | Jul 03 07:31:43 PM PDT 24 |
| Finished | Jul 03 07:32:35 PM PDT 24 |
| Peak memory | 574076 kb |
| Host | smart-75ade878-0ed6-455e-ad3b-3f5113f98956 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3722250531 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_random.3722250531 |
| Directory | /workspace/50.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_random_large_delays.3988339157 |
| Short name | T2301 |
| Test name | |
| Test status | |
| Simulation time | 68265637164 ps |
| CPU time | 709.54 seconds |
| Started | Jul 03 07:31:41 PM PDT 24 |
| Finished | Jul 03 07:43:31 PM PDT 24 |
| Peak memory | 574104 kb |
| Host | smart-e09c0f46-ce4a-45aa-9a1d-c3edd313f940 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3988339157 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_random_large_delays.3988339157 |
| Directory | /workspace/50.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_random_slow_rsp.2353199710 |
| Short name | T1940 |
| Test name | |
| Test status | |
| Simulation time | 40951652100 ps |
| CPU time | 785.68 seconds |
| Started | Jul 03 07:31:40 PM PDT 24 |
| Finished | Jul 03 07:44:46 PM PDT 24 |
| Peak memory | 574276 kb |
| Host | smart-e8f874f8-e316-4158-8b44-95270d439ca7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2353199710 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_random_slow_rsp.2353199710 |
| Directory | /workspace/50.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_random_zero_delays.1887929098 |
| Short name | T2774 |
| Test name | |
| Test status | |
| Simulation time | 532010504 ps |
| CPU time | 49.41 seconds |
| Started | Jul 03 07:31:39 PM PDT 24 |
| Finished | Jul 03 07:32:29 PM PDT 24 |
| Peak memory | 574232 kb |
| Host | smart-527fe07b-d281-4e9a-b185-719e7d0666c4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1887929098 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_random_zero_del ays.1887929098 |
| Directory | /workspace/50.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_same_source.1686085638 |
| Short name | T2587 |
| Test name | |
| Test status | |
| Simulation time | 831215168 ps |
| CPU time | 27.38 seconds |
| Started | Jul 03 07:31:39 PM PDT 24 |
| Finished | Jul 03 07:32:07 PM PDT 24 |
| Peak memory | 574092 kb |
| Host | smart-bdd28a54-8bef-4c5f-b5b7-d4dcf41b1ffe |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1686085638 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_same_source.1686085638 |
| Directory | /workspace/50.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_smoke.916263600 |
| Short name | T2656 |
| Test name | |
| Test status | |
| Simulation time | 51818609 ps |
| CPU time | 6.27 seconds |
| Started | Jul 03 07:31:38 PM PDT 24 |
| Finished | Jul 03 07:31:45 PM PDT 24 |
| Peak memory | 574088 kb |
| Host | smart-b93f7461-064a-4125-b593-018d8ccd84b4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=916263600 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_smoke.916263600 |
| Directory | /workspace/50.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_smoke_large_delays.4220642368 |
| Short name | T1404 |
| Test name | |
| Test status | |
| Simulation time | 6986426770 ps |
| CPU time | 74.86 seconds |
| Started | Jul 03 07:31:40 PM PDT 24 |
| Finished | Jul 03 07:32:56 PM PDT 24 |
| Peak memory | 573000 kb |
| Host | smart-250dac72-6334-454e-b754-eaea2ecc7ae8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4220642368 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_smoke_large_delays.4220642368 |
| Directory | /workspace/50.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_smoke_slow_rsp.4147740767 |
| Short name | T249 |
| Test name | |
| Test status | |
| Simulation time | 5540213316 ps |
| CPU time | 90.76 seconds |
| Started | Jul 03 07:31:39 PM PDT 24 |
| Finished | Jul 03 07:33:10 PM PDT 24 |
| Peak memory | 573196 kb |
| Host | smart-bfea46f4-01de-4189-a953-8659aa381142 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4147740767 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_smoke_slow_rsp.4147740767 |
| Directory | /workspace/50.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_smoke_zero_delays.979256745 |
| Short name | T574 |
| Test name | |
| Test status | |
| Simulation time | 42324129 ps |
| CPU time | 6.13 seconds |
| Started | Jul 03 07:31:41 PM PDT 24 |
| Finished | Jul 03 07:31:48 PM PDT 24 |
| Peak memory | 574140 kb |
| Host | smart-ce40ad2e-aef1-443f-ba3e-58929f0c548b |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=979256745 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_smoke_zero_delays .979256745 |
| Directory | /workspace/50.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_stress_all.1193433591 |
| Short name | T1717 |
| Test name | |
| Test status | |
| Simulation time | 2404537312 ps |
| CPU time | 74.57 seconds |
| Started | Jul 03 07:31:43 PM PDT 24 |
| Finished | Jul 03 07:32:58 PM PDT 24 |
| Peak memory | 574228 kb |
| Host | smart-7dfb1280-73c0-4e32-8589-06ebb8579b2f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1193433591 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_stress_all.1193433591 |
| Directory | /workspace/50.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_stress_all_with_error.2741271982 |
| Short name | T2516 |
| Test name | |
| Test status | |
| Simulation time | 675138806 ps |
| CPU time | 55.68 seconds |
| Started | Jul 03 07:31:43 PM PDT 24 |
| Finished | Jul 03 07:32:40 PM PDT 24 |
| Peak memory | 574464 kb |
| Host | smart-b4b5c8de-a78b-4fbb-87f5-622bc6eedc5a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2741271982 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_stress_all_with_error.2741271982 |
| Directory | /workspace/50.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_stress_all_with_rand_reset.1318670672 |
| Short name | T564 |
| Test name | |
| Test status | |
| Simulation time | 1216516415 ps |
| CPU time | 167.17 seconds |
| Started | Jul 03 07:31:46 PM PDT 24 |
| Finished | Jul 03 07:34:34 PM PDT 24 |
| Peak memory | 574668 kb |
| Host | smart-c9da1667-119c-4d94-a1a2-727b48e3ad57 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1318670672 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_stress_all _with_rand_reset.1318670672 |
| Directory | /workspace/50.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_stress_all_with_reset_error.1962579057 |
| Short name | T2658 |
| Test name | |
| Test status | |
| Simulation time | 3270359673 ps |
| CPU time | 176.8 seconds |
| Started | Jul 03 07:31:47 PM PDT 24 |
| Finished | Jul 03 07:34:45 PM PDT 24 |
| Peak memory | 574728 kb |
| Host | smart-89327c6c-21c9-435e-84a9-81f775aa5974 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1962579057 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_stress_al l_with_reset_error.1962579057 |
| Directory | /workspace/50.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_unmapped_addr.1340480850 |
| Short name | T1816 |
| Test name | |
| Test status | |
| Simulation time | 296750579 ps |
| CPU time | 33.37 seconds |
| Started | Jul 03 07:31:43 PM PDT 24 |
| Finished | Jul 03 07:32:17 PM PDT 24 |
| Peak memory | 574196 kb |
| Host | smart-4de49925-40ba-480b-8e72-a90f931544f8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1340480850 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_unmapped_addr.1340480850 |
| Directory | /workspace/50.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_access_same_device.1177830923 |
| Short name | T2387 |
| Test name | |
| Test status | |
| Simulation time | 1034367346 ps |
| CPU time | 73.71 seconds |
| Started | Jul 03 07:31:50 PM PDT 24 |
| Finished | Jul 03 07:33:05 PM PDT 24 |
| Peak memory | 574188 kb |
| Host | smart-553c8662-f537-49e5-a48b-55e25b464a78 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1177830923 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_access_same_device .1177830923 |
| Directory | /workspace/51.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_access_same_device_slow_rsp.4219351438 |
| Short name | T2583 |
| Test name | |
| Test status | |
| Simulation time | 47970833533 ps |
| CPU time | 832.52 seconds |
| Started | Jul 03 07:31:54 PM PDT 24 |
| Finished | Jul 03 07:45:48 PM PDT 24 |
| Peak memory | 574052 kb |
| Host | smart-e92d5f22-25d5-4625-b762-6d921ad4fcdd |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4219351438 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_access_same_ device_slow_rsp.4219351438 |
| Directory | /workspace/51.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_error_and_unmapped_addr.1362423384 |
| Short name | T1881 |
| Test name | |
| Test status | |
| Simulation time | 112894787 ps |
| CPU time | 13.82 seconds |
| Started | Jul 03 07:31:49 PM PDT 24 |
| Finished | Jul 03 07:32:04 PM PDT 24 |
| Peak memory | 573972 kb |
| Host | smart-b2eaedf4-18ae-4f89-8bc7-811f41dedbfb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1362423384 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_error_and_unmapped_add r.1362423384 |
| Directory | /workspace/51.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_error_random.3900810670 |
| Short name | T1489 |
| Test name | |
| Test status | |
| Simulation time | 1693512139 ps |
| CPU time | 56.29 seconds |
| Started | Jul 03 07:31:48 PM PDT 24 |
| Finished | Jul 03 07:32:46 PM PDT 24 |
| Peak memory | 574504 kb |
| Host | smart-fa3e0345-4ffc-404f-a5de-f33c65a9ebdd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3900810670 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_error_random.3900810670 |
| Directory | /workspace/51.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_random.4271778770 |
| Short name | T587 |
| Test name | |
| Test status | |
| Simulation time | 190656391 ps |
| CPU time | 20.68 seconds |
| Started | Jul 03 07:31:44 PM PDT 24 |
| Finished | Jul 03 07:32:07 PM PDT 24 |
| Peak memory | 574116 kb |
| Host | smart-77526d4e-0326-4989-a63a-5a444efc593d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4271778770 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_random.4271778770 |
| Directory | /workspace/51.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_random_large_delays.762745659 |
| Short name | T1549 |
| Test name | |
| Test status | |
| Simulation time | 82685711842 ps |
| CPU time | 808.16 seconds |
| Started | Jul 03 07:31:51 PM PDT 24 |
| Finished | Jul 03 07:45:22 PM PDT 24 |
| Peak memory | 574288 kb |
| Host | smart-edbb8183-c263-42bc-ba0e-aae0ed75f889 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=762745659 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_random_large_delays.762745659 |
| Directory | /workspace/51.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_random_slow_rsp.2572834283 |
| Short name | T2341 |
| Test name | |
| Test status | |
| Simulation time | 48623274393 ps |
| CPU time | 926.56 seconds |
| Started | Jul 03 07:31:47 PM PDT 24 |
| Finished | Jul 03 07:47:15 PM PDT 24 |
| Peak memory | 574312 kb |
| Host | smart-8969c38b-8125-4bc4-893a-5d4117d5af14 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2572834283 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_random_slow_rsp.2572834283 |
| Directory | /workspace/51.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_random_zero_delays.2555975997 |
| Short name | T1838 |
| Test name | |
| Test status | |
| Simulation time | 510635383 ps |
| CPU time | 46.44 seconds |
| Started | Jul 03 07:31:50 PM PDT 24 |
| Finished | Jul 03 07:32:37 PM PDT 24 |
| Peak memory | 574252 kb |
| Host | smart-5b435657-fea5-4240-8d23-06b58135e743 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2555975997 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_random_zero_del ays.2555975997 |
| Directory | /workspace/51.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_same_source.2157611308 |
| Short name | T1642 |
| Test name | |
| Test status | |
| Simulation time | 1898397073 ps |
| CPU time | 60.46 seconds |
| Started | Jul 03 07:31:54 PM PDT 24 |
| Finished | Jul 03 07:32:56 PM PDT 24 |
| Peak memory | 574124 kb |
| Host | smart-3cc13dbd-85ca-43a0-a81d-df02ec19899d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2157611308 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_same_source.2157611308 |
| Directory | /workspace/51.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_smoke.1158740557 |
| Short name | T2751 |
| Test name | |
| Test status | |
| Simulation time | 204519814 ps |
| CPU time | 9.17 seconds |
| Started | Jul 03 07:31:43 PM PDT 24 |
| Finished | Jul 03 07:31:52 PM PDT 24 |
| Peak memory | 573168 kb |
| Host | smart-960ff182-275a-4e3f-b1e8-83572b30c0df |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1158740557 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_smoke.1158740557 |
| Directory | /workspace/51.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_smoke_large_delays.2672202570 |
| Short name | T504 |
| Test name | |
| Test status | |
| Simulation time | 7899697419 ps |
| CPU time | 81.71 seconds |
| Started | Jul 03 07:31:44 PM PDT 24 |
| Finished | Jul 03 07:33:06 PM PDT 24 |
| Peak memory | 573204 kb |
| Host | smart-dad9776f-1730-44f9-94c6-abd196127bcb |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2672202570 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_smoke_large_delays.2672202570 |
| Directory | /workspace/51.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_smoke_slow_rsp.1921679335 |
| Short name | T654 |
| Test name | |
| Test status | |
| Simulation time | 5664829295 ps |
| CPU time | 101.29 seconds |
| Started | Jul 03 07:31:42 PM PDT 24 |
| Finished | Jul 03 07:33:24 PM PDT 24 |
| Peak memory | 573216 kb |
| Host | smart-1d8ccae5-7ca4-44ae-ace2-4bb9c8fe2865 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921679335 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_smoke_slow_rsp.1921679335 |
| Directory | /workspace/51.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_smoke_zero_delays.3693912558 |
| Short name | T1315 |
| Test name | |
| Test status | |
| Simulation time | 57878531 ps |
| CPU time | 7.25 seconds |
| Started | Jul 03 07:31:42 PM PDT 24 |
| Finished | Jul 03 07:31:50 PM PDT 24 |
| Peak memory | 573104 kb |
| Host | smart-c77bf0ec-01a1-4b9c-aefb-a4c3b939cb21 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693912558 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_smoke_zero_delay s.3693912558 |
| Directory | /workspace/51.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_stress_all.2981413306 |
| Short name | T2628 |
| Test name | |
| Test status | |
| Simulation time | 2349020410 ps |
| CPU time | 107.77 seconds |
| Started | Jul 03 07:31:54 PM PDT 24 |
| Finished | Jul 03 07:33:44 PM PDT 24 |
| Peak memory | 574236 kb |
| Host | smart-b48e703e-f440-460f-98dd-d850d18f8848 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2981413306 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_stress_all.2981413306 |
| Directory | /workspace/51.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_stress_all_with_error.3219955232 |
| Short name | T1762 |
| Test name | |
| Test status | |
| Simulation time | 2170774598 ps |
| CPU time | 162.85 seconds |
| Started | Jul 03 07:31:48 PM PDT 24 |
| Finished | Jul 03 07:34:33 PM PDT 24 |
| Peak memory | 574588 kb |
| Host | smart-57d0b3d2-986d-4655-9e52-7c9a50561e81 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219955232 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_stress_all_with_error.3219955232 |
| Directory | /workspace/51.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_stress_all_with_rand_reset.2891432787 |
| Short name | T473 |
| Test name | |
| Test status | |
| Simulation time | 2797177729 ps |
| CPU time | 437.35 seconds |
| Started | Jul 03 07:31:52 PM PDT 24 |
| Finished | Jul 03 07:39:12 PM PDT 24 |
| Peak memory | 574700 kb |
| Host | smart-b95d2568-a1db-4b05-a05f-ec99b4d0363f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2891432787 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_stress_all _with_rand_reset.2891432787 |
| Directory | /workspace/51.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_stress_all_with_reset_error.461488007 |
| Short name | T1796 |
| Test name | |
| Test status | |
| Simulation time | 7051832401 ps |
| CPU time | 325.06 seconds |
| Started | Jul 03 07:31:53 PM PDT 24 |
| Finished | Jul 03 07:37:20 PM PDT 24 |
| Peak memory | 574760 kb |
| Host | smart-23e6cc91-2748-46c8-910f-f9e940007474 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=461488007 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_stress_all _with_reset_error.461488007 |
| Directory | /workspace/51.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_unmapped_addr.4147638672 |
| Short name | T2237 |
| Test name | |
| Test status | |
| Simulation time | 251917695 ps |
| CPU time | 30.76 seconds |
| Started | Jul 03 07:31:47 PM PDT 24 |
| Finished | Jul 03 07:32:19 PM PDT 24 |
| Peak memory | 574328 kb |
| Host | smart-c29d2eba-de48-45e9-84b0-63d15d213e5f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4147638672 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_unmapped_addr.4147638672 |
| Directory | /workspace/51.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_access_same_device.1019876357 |
| Short name | T1863 |
| Test name | |
| Test status | |
| Simulation time | 2729056740 ps |
| CPU time | 114.05 seconds |
| Started | Jul 03 07:32:08 PM PDT 24 |
| Finished | Jul 03 07:34:03 PM PDT 24 |
| Peak memory | 574076 kb |
| Host | smart-00666904-9231-45e6-96c4-83978ee01951 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1019876357 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_access_same_device .1019876357 |
| Directory | /workspace/52.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_access_same_device_slow_rsp.3439291374 |
| Short name | T2531 |
| Test name | |
| Test status | |
| Simulation time | 65896302460 ps |
| CPU time | 1251.65 seconds |
| Started | Jul 03 07:32:00 PM PDT 24 |
| Finished | Jul 03 07:52:52 PM PDT 24 |
| Peak memory | 574080 kb |
| Host | smart-644ecb15-d44a-4e47-9696-335843bad6be |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3439291374 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_access_same_ device_slow_rsp.3439291374 |
| Directory | /workspace/52.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_error_and_unmapped_addr.2348801232 |
| Short name | T1640 |
| Test name | |
| Test status | |
| Simulation time | 1233936696 ps |
| CPU time | 51.01 seconds |
| Started | Jul 03 07:32:01 PM PDT 24 |
| Finished | Jul 03 07:32:53 PM PDT 24 |
| Peak memory | 574072 kb |
| Host | smart-078a9752-8702-4000-bb6c-3e0e597a280e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2348801232 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_error_and_unmapped_add r.2348801232 |
| Directory | /workspace/52.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_error_random.980011673 |
| Short name | T2791 |
| Test name | |
| Test status | |
| Simulation time | 186883019 ps |
| CPU time | 9.65 seconds |
| Started | Jul 03 07:32:08 PM PDT 24 |
| Finished | Jul 03 07:32:18 PM PDT 24 |
| Peak memory | 572956 kb |
| Host | smart-e9ffd817-c708-475a-b683-0579fccc36f2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=980011673 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_error_random.980011673 |
| Directory | /workspace/52.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_random.758799001 |
| Short name | T1545 |
| Test name | |
| Test status | |
| Simulation time | 1069523949 ps |
| CPU time | 40.43 seconds |
| Started | Jul 03 07:31:56 PM PDT 24 |
| Finished | Jul 03 07:32:37 PM PDT 24 |
| Peak memory | 573916 kb |
| Host | smart-d817ebc8-a139-4cc0-ae90-5555a3a20137 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=758799001 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_random.758799001 |
| Directory | /workspace/52.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_random_large_delays.1296880433 |
| Short name | T1483 |
| Test name | |
| Test status | |
| Simulation time | 59528831378 ps |
| CPU time | 630.7 seconds |
| Started | Jul 03 07:31:53 PM PDT 24 |
| Finished | Jul 03 07:42:26 PM PDT 24 |
| Peak memory | 574244 kb |
| Host | smart-a9a0089e-e69e-4575-b9ee-fd9e3299a687 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1296880433 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_random_large_delays.1296880433 |
| Directory | /workspace/52.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_random_slow_rsp.3894681719 |
| Short name | T2179 |
| Test name | |
| Test status | |
| Simulation time | 27932290501 ps |
| CPU time | 451.88 seconds |
| Started | Jul 03 07:32:08 PM PDT 24 |
| Finished | Jul 03 07:39:41 PM PDT 24 |
| Peak memory | 574032 kb |
| Host | smart-4ed8a8e9-eec4-4e72-98b7-584fd770948a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3894681719 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_random_slow_rsp.3894681719 |
| Directory | /workspace/52.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_random_zero_delays.4006031614 |
| Short name | T1753 |
| Test name | |
| Test status | |
| Simulation time | 619530346 ps |
| CPU time | 48.77 seconds |
| Started | Jul 03 07:31:51 PM PDT 24 |
| Finished | Jul 03 07:32:43 PM PDT 24 |
| Peak memory | 574268 kb |
| Host | smart-8929550d-827f-423a-9faf-774787dd34b5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4006031614 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_random_zero_del ays.4006031614 |
| Directory | /workspace/52.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_same_source.57988443 |
| Short name | T529 |
| Test name | |
| Test status | |
| Simulation time | 163636208 ps |
| CPU time | 14.46 seconds |
| Started | Jul 03 07:32:08 PM PDT 24 |
| Finished | Jul 03 07:32:24 PM PDT 24 |
| Peak memory | 574140 kb |
| Host | smart-55db62b1-28fc-4cfb-b0a3-b9cef14c4dd6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57988443 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_same_source.57988443 |
| Directory | /workspace/52.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_smoke.3313680582 |
| Short name | T2746 |
| Test name | |
| Test status | |
| Simulation time | 184482307 ps |
| CPU time | 8.6 seconds |
| Started | Jul 03 07:31:54 PM PDT 24 |
| Finished | Jul 03 07:32:04 PM PDT 24 |
| Peak memory | 572932 kb |
| Host | smart-bab3260c-e8df-4666-bd04-c5e184bc90bf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3313680582 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_smoke.3313680582 |
| Directory | /workspace/52.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_smoke_large_delays.3269318634 |
| Short name | T2043 |
| Test name | |
| Test status | |
| Simulation time | 7477807147 ps |
| CPU time | 81.42 seconds |
| Started | Jul 03 07:31:52 PM PDT 24 |
| Finished | Jul 03 07:33:16 PM PDT 24 |
| Peak memory | 572992 kb |
| Host | smart-c148d356-901c-4bb0-a69f-702877703d1c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3269318634 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_smoke_large_delays.3269318634 |
| Directory | /workspace/52.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_smoke_slow_rsp.333223166 |
| Short name | T2220 |
| Test name | |
| Test status | |
| Simulation time | 6105493653 ps |
| CPU time | 107.67 seconds |
| Started | Jul 03 07:31:55 PM PDT 24 |
| Finished | Jul 03 07:33:44 PM PDT 24 |
| Peak memory | 573156 kb |
| Host | smart-d216493a-0b83-4054-9a56-334ee74e3369 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=333223166 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_smoke_slow_rsp.333223166 |
| Directory | /workspace/52.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_smoke_zero_delays.3882021003 |
| Short name | T1384 |
| Test name | |
| Test status | |
| Simulation time | 42917351 ps |
| CPU time | 5.86 seconds |
| Started | Jul 03 07:31:55 PM PDT 24 |
| Finished | Jul 03 07:32:02 PM PDT 24 |
| Peak memory | 573956 kb |
| Host | smart-346efccc-c812-4a21-9925-8eb44eed0503 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3882021003 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_smoke_zero_delay s.3882021003 |
| Directory | /workspace/52.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_stress_all.1134840343 |
| Short name | T2804 |
| Test name | |
| Test status | |
| Simulation time | 11978550291 ps |
| CPU time | 419.88 seconds |
| Started | Jul 03 07:32:10 PM PDT 24 |
| Finished | Jul 03 07:39:11 PM PDT 24 |
| Peak memory | 574744 kb |
| Host | smart-0821642b-78c5-44b5-ab7d-f06e4e3ce37a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1134840343 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_stress_all.1134840343 |
| Directory | /workspace/52.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_stress_all_with_error.2685446417 |
| Short name | T2336 |
| Test name | |
| Test status | |
| Simulation time | 1275891952 ps |
| CPU time | 97.56 seconds |
| Started | Jul 03 07:32:02 PM PDT 24 |
| Finished | Jul 03 07:33:41 PM PDT 24 |
| Peak memory | 574092 kb |
| Host | smart-b3b4e737-f2c0-42f9-8cf7-70bec953214b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2685446417 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_stress_all_with_error.2685446417 |
| Directory | /workspace/52.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_stress_all_with_rand_reset.3955603246 |
| Short name | T2719 |
| Test name | |
| Test status | |
| Simulation time | 92818739 ps |
| CPU time | 29.63 seconds |
| Started | Jul 03 07:32:03 PM PDT 24 |
| Finished | Jul 03 07:32:34 PM PDT 24 |
| Peak memory | 574572 kb |
| Host | smart-a2346967-e812-4b59-a1af-12411edb5d78 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3955603246 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_stress_all _with_rand_reset.3955603246 |
| Directory | /workspace/52.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_unmapped_addr.1783469882 |
| Short name | T606 |
| Test name | |
| Test status | |
| Simulation time | 213358812 ps |
| CPU time | 28.73 seconds |
| Started | Jul 03 07:31:58 PM PDT 24 |
| Finished | Jul 03 07:32:27 PM PDT 24 |
| Peak memory | 574244 kb |
| Host | smart-32b787e0-15c0-47e3-95a1-84a9e720b397 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1783469882 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_unmapped_addr.1783469882 |
| Directory | /workspace/52.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_access_same_device.2173126100 |
| Short name | T781 |
| Test name | |
| Test status | |
| Simulation time | 2606699385 ps |
| CPU time | 115.41 seconds |
| Started | Jul 03 07:32:07 PM PDT 24 |
| Finished | Jul 03 07:34:03 PM PDT 24 |
| Peak memory | 574064 kb |
| Host | smart-2006f6d6-3688-4a04-83a5-69f15519a52c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2173126100 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_access_same_device .2173126100 |
| Directory | /workspace/53.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_access_same_device_slow_rsp.1903563960 |
| Short name | T2077 |
| Test name | |
| Test status | |
| Simulation time | 102249809175 ps |
| CPU time | 1773.71 seconds |
| Started | Jul 03 07:32:11 PM PDT 24 |
| Finished | Jul 03 08:01:46 PM PDT 24 |
| Peak memory | 574604 kb |
| Host | smart-0a138fd8-7ed8-406d-9075-d59e0990b16a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1903563960 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_access_same_ device_slow_rsp.1903563960 |
| Directory | /workspace/53.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_error_and_unmapped_addr.3321300644 |
| Short name | T2825 |
| Test name | |
| Test status | |
| Simulation time | 1030025225 ps |
| CPU time | 40.44 seconds |
| Started | Jul 03 07:32:12 PM PDT 24 |
| Finished | Jul 03 07:32:53 PM PDT 24 |
| Peak memory | 574444 kb |
| Host | smart-17fd27fc-ac5b-4ca3-8738-0b37b7468af3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3321300644 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_error_and_unmapped_add r.3321300644 |
| Directory | /workspace/53.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_error_random.2759828563 |
| Short name | T1426 |
| Test name | |
| Test status | |
| Simulation time | 240751315 ps |
| CPU time | 12.1 seconds |
| Started | Jul 03 07:32:07 PM PDT 24 |
| Finished | Jul 03 07:32:20 PM PDT 24 |
| Peak memory | 574040 kb |
| Host | smart-2fc5a463-ec54-4bde-8108-ff93d03acec2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2759828563 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_error_random.2759828563 |
| Directory | /workspace/53.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_random.2469391269 |
| Short name | T1732 |
| Test name | |
| Test status | |
| Simulation time | 1196864167 ps |
| CPU time | 43.57 seconds |
| Started | Jul 03 07:32:04 PM PDT 24 |
| Finished | Jul 03 07:32:49 PM PDT 24 |
| Peak memory | 574140 kb |
| Host | smart-a22b4d01-615f-4966-809f-84bdcd8f9a67 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2469391269 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_random.2469391269 |
| Directory | /workspace/53.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_random_large_delays.2451883046 |
| Short name | T2811 |
| Test name | |
| Test status | |
| Simulation time | 105666110823 ps |
| CPU time | 1113.1 seconds |
| Started | Jul 03 07:32:08 PM PDT 24 |
| Finished | Jul 03 07:50:42 PM PDT 24 |
| Peak memory | 574344 kb |
| Host | smart-339e32c1-daa1-4c02-ae9b-4b154afa2526 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2451883046 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_random_large_delays.2451883046 |
| Directory | /workspace/53.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_random_slow_rsp.2213634516 |
| Short name | T1541 |
| Test name | |
| Test status | |
| Simulation time | 32158299476 ps |
| CPU time | 577.13 seconds |
| Started | Jul 03 07:32:09 PM PDT 24 |
| Finished | Jul 03 07:41:47 PM PDT 24 |
| Peak memory | 573992 kb |
| Host | smart-5d95d535-610e-45e5-b255-74e9bfbc634e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2213634516 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_random_slow_rsp.2213634516 |
| Directory | /workspace/53.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_random_zero_delays.3746195835 |
| Short name | T2101 |
| Test name | |
| Test status | |
| Simulation time | 491554621 ps |
| CPU time | 41.1 seconds |
| Started | Jul 03 07:32:07 PM PDT 24 |
| Finished | Jul 03 07:32:49 PM PDT 24 |
| Peak memory | 574036 kb |
| Host | smart-9a939f25-4160-410a-bf91-99e48449961a |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3746195835 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_random_zero_del ays.3746195835 |
| Directory | /workspace/53.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_same_source.2450038403 |
| Short name | T472 |
| Test name | |
| Test status | |
| Simulation time | 163908010 ps |
| CPU time | 13.81 seconds |
| Started | Jul 03 07:32:08 PM PDT 24 |
| Finished | Jul 03 07:32:23 PM PDT 24 |
| Peak memory | 574220 kb |
| Host | smart-f2f635db-e584-4bf4-951e-58bf2470baac |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2450038403 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_same_source.2450038403 |
| Directory | /workspace/53.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_smoke.3576446984 |
| Short name | T1867 |
| Test name | |
| Test status | |
| Simulation time | 199151933 ps |
| CPU time | 8.84 seconds |
| Started | Jul 03 07:32:11 PM PDT 24 |
| Finished | Jul 03 07:32:21 PM PDT 24 |
| Peak memory | 572900 kb |
| Host | smart-9268ab63-68de-4fb4-94ec-1a35fce7d9fd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3576446984 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_smoke.3576446984 |
| Directory | /workspace/53.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_smoke_large_delays.3472167919 |
| Short name | T2286 |
| Test name | |
| Test status | |
| Simulation time | 6436435589 ps |
| CPU time | 70.46 seconds |
| Started | Jul 03 07:32:02 PM PDT 24 |
| Finished | Jul 03 07:33:13 PM PDT 24 |
| Peak memory | 574260 kb |
| Host | smart-3cccf4c4-5780-4e42-aa6e-c3027fc5c3f4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3472167919 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_smoke_large_delays.3472167919 |
| Directory | /workspace/53.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_smoke_slow_rsp.336413436 |
| Short name | T2458 |
| Test name | |
| Test status | |
| Simulation time | 6503835618 ps |
| CPU time | 105.62 seconds |
| Started | Jul 03 07:32:10 PM PDT 24 |
| Finished | Jul 03 07:33:56 PM PDT 24 |
| Peak memory | 573060 kb |
| Host | smart-71ebb4bf-4eab-4dec-8a4a-a1af311c6b5f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=336413436 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_smoke_slow_rsp.336413436 |
| Directory | /workspace/53.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_smoke_zero_delays.3294934142 |
| Short name | T1524 |
| Test name | |
| Test status | |
| Simulation time | 41659865 ps |
| CPU time | 6.08 seconds |
| Started | Jul 03 07:32:02 PM PDT 24 |
| Finished | Jul 03 07:32:09 PM PDT 24 |
| Peak memory | 573996 kb |
| Host | smart-24f91d2a-7489-4703-b60b-b51a55dec9ef |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294934142 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_smoke_zero_delay s.3294934142 |
| Directory | /workspace/53.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_stress_all.3115128084 |
| Short name | T2592 |
| Test name | |
| Test status | |
| Simulation time | 1259525339 ps |
| CPU time | 104.88 seconds |
| Started | Jul 03 07:32:13 PM PDT 24 |
| Finished | Jul 03 07:33:59 PM PDT 24 |
| Peak memory | 574636 kb |
| Host | smart-777ab82d-77b1-4df5-a40c-eeff79bf1af7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115128084 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_stress_all.3115128084 |
| Directory | /workspace/53.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_stress_all_with_error.4185381977 |
| Short name | T1493 |
| Test name | |
| Test status | |
| Simulation time | 4901486840 ps |
| CPU time | 369.66 seconds |
| Started | Jul 03 07:32:11 PM PDT 24 |
| Finished | Jul 03 07:38:22 PM PDT 24 |
| Peak memory | 574652 kb |
| Host | smart-6302f2d9-e5fb-4ab8-8f5d-94eccb6df6fe |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4185381977 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_stress_all_with_error.4185381977 |
| Directory | /workspace/53.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_stress_all_with_rand_reset.1526475123 |
| Short name | T2882 |
| Test name | |
| Test status | |
| Simulation time | 9431794441 ps |
| CPU time | 413.36 seconds |
| Started | Jul 03 07:32:14 PM PDT 24 |
| Finished | Jul 03 07:39:08 PM PDT 24 |
| Peak memory | 574756 kb |
| Host | smart-22146a92-e8f1-4c4d-b41e-5d77df86ed53 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1526475123 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_stress_all _with_rand_reset.1526475123 |
| Directory | /workspace/53.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_stress_all_with_reset_error.893231449 |
| Short name | T1695 |
| Test name | |
| Test status | |
| Simulation time | 9659091739 ps |
| CPU time | 927.98 seconds |
| Started | Jul 03 07:32:12 PM PDT 24 |
| Finished | Jul 03 07:47:41 PM PDT 24 |
| Peak memory | 574748 kb |
| Host | smart-16c472e8-48a5-4db6-b689-e8f20030f7ae |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=893231449 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_stress_all _with_reset_error.893231449 |
| Directory | /workspace/53.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_unmapped_addr.2327262357 |
| Short name | T2818 |
| Test name | |
| Test status | |
| Simulation time | 261681843 ps |
| CPU time | 32.62 seconds |
| Started | Jul 03 07:32:18 PM PDT 24 |
| Finished | Jul 03 07:32:51 PM PDT 24 |
| Peak memory | 574256 kb |
| Host | smart-8cef8329-5149-4d7f-8078-ac0383524d21 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2327262357 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_unmapped_addr.2327262357 |
| Directory | /workspace/53.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_access_same_device.3465203816 |
| Short name | T2367 |
| Test name | |
| Test status | |
| Simulation time | 649678496 ps |
| CPU time | 53.66 seconds |
| Started | Jul 03 07:32:26 PM PDT 24 |
| Finished | Jul 03 07:33:21 PM PDT 24 |
| Peak memory | 574248 kb |
| Host | smart-a8812b9d-82ea-47c6-89bd-800a731b6da2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465203816 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_access_same_device .3465203816 |
| Directory | /workspace/54.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_access_same_device_slow_rsp.1280748917 |
| Short name | T1700 |
| Test name | |
| Test status | |
| Simulation time | 23929615677 ps |
| CPU time | 399.49 seconds |
| Started | Jul 03 07:32:20 PM PDT 24 |
| Finished | Jul 03 07:39:01 PM PDT 24 |
| Peak memory | 574292 kb |
| Host | smart-394f20df-8c47-4782-a63a-0dab045088e1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1280748917 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_access_same_ device_slow_rsp.1280748917 |
| Directory | /workspace/54.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_error_and_unmapped_addr.107013700 |
| Short name | T1518 |
| Test name | |
| Test status | |
| Simulation time | 369692115 ps |
| CPU time | 17.14 seconds |
| Started | Jul 03 07:32:21 PM PDT 24 |
| Finished | Jul 03 07:32:39 PM PDT 24 |
| Peak memory | 574636 kb |
| Host | smart-31a45abb-62c4-45e0-af8e-ccc31430fd98 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107013700 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_error_and_unmapped_addr .107013700 |
| Directory | /workspace/54.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_error_random.4100025761 |
| Short name | T2620 |
| Test name | |
| Test status | |
| Simulation time | 1968446047 ps |
| CPU time | 70.37 seconds |
| Started | Jul 03 07:32:22 PM PDT 24 |
| Finished | Jul 03 07:33:33 PM PDT 24 |
| Peak memory | 574464 kb |
| Host | smart-b6bafd09-b4f1-4838-876a-e08f5d658e17 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4100025761 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_error_random.4100025761 |
| Directory | /workspace/54.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_random.1763308955 |
| Short name | T2277 |
| Test name | |
| Test status | |
| Simulation time | 805595251 ps |
| CPU time | 27.75 seconds |
| Started | Jul 03 07:32:20 PM PDT 24 |
| Finished | Jul 03 07:32:48 PM PDT 24 |
| Peak memory | 574144 kb |
| Host | smart-5cac0518-d751-43e8-b772-cc520b406018 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763308955 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_random.1763308955 |
| Directory | /workspace/54.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_random_large_delays.4274036951 |
| Short name | T1958 |
| Test name | |
| Test status | |
| Simulation time | 104126424754 ps |
| CPU time | 1110.32 seconds |
| Started | Jul 03 07:32:17 PM PDT 24 |
| Finished | Jul 03 07:50:48 PM PDT 24 |
| Peak memory | 574308 kb |
| Host | smart-ea1b0939-6d76-440d-8f2c-c83772b57f33 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4274036951 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_random_large_delays.4274036951 |
| Directory | /workspace/54.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_random_slow_rsp.1125874956 |
| Short name | T583 |
| Test name | |
| Test status | |
| Simulation time | 47815946661 ps |
| CPU time | 807.53 seconds |
| Started | Jul 03 07:32:17 PM PDT 24 |
| Finished | Jul 03 07:45:46 PM PDT 24 |
| Peak memory | 574224 kb |
| Host | smart-d2708a25-018b-4163-a0dd-5c149a80a3db |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1125874956 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_random_slow_rsp.1125874956 |
| Directory | /workspace/54.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_random_zero_delays.36137656 |
| Short name | T1554 |
| Test name | |
| Test status | |
| Simulation time | 451134540 ps |
| CPU time | 35.52 seconds |
| Started | Jul 03 07:32:22 PM PDT 24 |
| Finished | Jul 03 07:32:58 PM PDT 24 |
| Peak memory | 574156 kb |
| Host | smart-45af8afe-62d1-4e9f-a718-64bbd8239736 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36137656 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_random_zero_delay s.36137656 |
| Directory | /workspace/54.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_same_source.3261136596 |
| Short name | T2271 |
| Test name | |
| Test status | |
| Simulation time | 902480937 ps |
| CPU time | 24.53 seconds |
| Started | Jul 03 07:32:22 PM PDT 24 |
| Finished | Jul 03 07:32:48 PM PDT 24 |
| Peak memory | 574132 kb |
| Host | smart-850a3d6a-841b-4252-bfda-592977f3b3c3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3261136596 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_same_source.3261136596 |
| Directory | /workspace/54.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_smoke.1385851835 |
| Short name | T2145 |
| Test name | |
| Test status | |
| Simulation time | 148040094 ps |
| CPU time | 7.9 seconds |
| Started | Jul 03 07:32:12 PM PDT 24 |
| Finished | Jul 03 07:32:21 PM PDT 24 |
| Peak memory | 573160 kb |
| Host | smart-2b9b0385-88c8-4036-bec3-b9355fe09a19 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385851835 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_smoke.1385851835 |
| Directory | /workspace/54.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_smoke_large_delays.4027419623 |
| Short name | T1830 |
| Test name | |
| Test status | |
| Simulation time | 9427578027 ps |
| CPU time | 97.99 seconds |
| Started | Jul 03 07:32:17 PM PDT 24 |
| Finished | Jul 03 07:33:56 PM PDT 24 |
| Peak memory | 574280 kb |
| Host | smart-35f45508-f188-4878-8407-74cc58dc5429 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4027419623 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_smoke_large_delays.4027419623 |
| Directory | /workspace/54.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_smoke_slow_rsp.287062128 |
| Short name | T1905 |
| Test name | |
| Test status | |
| Simulation time | 3267852434 ps |
| CPU time | 55.09 seconds |
| Started | Jul 03 07:32:22 PM PDT 24 |
| Finished | Jul 03 07:33:18 PM PDT 24 |
| Peak memory | 574072 kb |
| Host | smart-60cc0598-c0cd-4355-bf79-beb50d7a38ad |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=287062128 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_smoke_slow_rsp.287062128 |
| Directory | /workspace/54.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_smoke_zero_delays.757225020 |
| Short name | T1428 |
| Test name | |
| Test status | |
| Simulation time | 52944441 ps |
| CPU time | 6.88 seconds |
| Started | Jul 03 07:32:19 PM PDT 24 |
| Finished | Jul 03 07:32:26 PM PDT 24 |
| Peak memory | 572936 kb |
| Host | smart-51ce239f-c48d-48d3-8323-8833a9e2d444 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=757225020 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_smoke_zero_delays .757225020 |
| Directory | /workspace/54.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_stress_all.1559356405 |
| Short name | T1814 |
| Test name | |
| Test status | |
| Simulation time | 10589536433 ps |
| CPU time | 382.94 seconds |
| Started | Jul 03 07:32:32 PM PDT 24 |
| Finished | Jul 03 07:38:56 PM PDT 24 |
| Peak memory | 574732 kb |
| Host | smart-6b9ecb4f-beb2-4c6c-85f3-7c24e205a4ea |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1559356405 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_stress_all.1559356405 |
| Directory | /workspace/54.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_stress_all_with_error.2161680532 |
| Short name | T2416 |
| Test name | |
| Test status | |
| Simulation time | 612783253 ps |
| CPU time | 47.49 seconds |
| Started | Jul 03 07:32:24 PM PDT 24 |
| Finished | Jul 03 07:33:12 PM PDT 24 |
| Peak memory | 574460 kb |
| Host | smart-cf613796-4d05-451e-bf0a-167817b4b630 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2161680532 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_stress_all_with_error.2161680532 |
| Directory | /workspace/54.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_stress_all_with_rand_reset.261095397 |
| Short name | T2273 |
| Test name | |
| Test status | |
| Simulation time | 9547866720 ps |
| CPU time | 524.89 seconds |
| Started | Jul 03 07:32:26 PM PDT 24 |
| Finished | Jul 03 07:41:12 PM PDT 24 |
| Peak memory | 574688 kb |
| Host | smart-7bd84b6f-edc6-4779-967a-d3049237a95e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=261095397 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_stress_all_ with_rand_reset.261095397 |
| Directory | /workspace/54.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_stress_all_with_reset_error.1637648761 |
| Short name | T2054 |
| Test name | |
| Test status | |
| Simulation time | 3102339315 ps |
| CPU time | 184.67 seconds |
| Started | Jul 03 07:32:23 PM PDT 24 |
| Finished | Jul 03 07:35:29 PM PDT 24 |
| Peak memory | 574796 kb |
| Host | smart-86e3cf08-b4ce-460a-bb64-99c7cbfc50de |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1637648761 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_stress_al l_with_reset_error.1637648761 |
| Directory | /workspace/54.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_unmapped_addr.864249826 |
| Short name | T1338 |
| Test name | |
| Test status | |
| Simulation time | 355814470 ps |
| CPU time | 16.88 seconds |
| Started | Jul 03 07:32:24 PM PDT 24 |
| Finished | Jul 03 07:32:41 PM PDT 24 |
| Peak memory | 574224 kb |
| Host | smart-8847af92-72d4-44d0-803e-38ddadf806ae |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=864249826 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_unmapped_addr.864249826 |
| Directory | /workspace/54.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_access_same_device.2927928146 |
| Short name | T779 |
| Test name | |
| Test status | |
| Simulation time | 2540111832 ps |
| CPU time | 105.91 seconds |
| Started | Jul 03 07:32:31 PM PDT 24 |
| Finished | Jul 03 07:34:18 PM PDT 24 |
| Peak memory | 574104 kb |
| Host | smart-1c460ad8-39fe-4e56-8747-29bab8d4c950 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927928146 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_access_same_device .2927928146 |
| Directory | /workspace/55.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_error_and_unmapped_addr.185656312 |
| Short name | T1301 |
| Test name | |
| Test status | |
| Simulation time | 197201480 ps |
| CPU time | 21.77 seconds |
| Started | Jul 03 07:32:33 PM PDT 24 |
| Finished | Jul 03 07:32:56 PM PDT 24 |
| Peak memory | 574064 kb |
| Host | smart-e134262c-d360-45ec-b51d-1ad10acf4ef6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=185656312 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_error_and_unmapped_addr .185656312 |
| Directory | /workspace/55.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_error_random.4029716826 |
| Short name | T1875 |
| Test name | |
| Test status | |
| Simulation time | 59394916 ps |
| CPU time | 8.31 seconds |
| Started | Jul 03 07:32:33 PM PDT 24 |
| Finished | Jul 03 07:32:42 PM PDT 24 |
| Peak memory | 574028 kb |
| Host | smart-0b7c6c79-fcd0-4903-a573-2a1a1765e48e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029716826 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_error_random.4029716826 |
| Directory | /workspace/55.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_random.1613916596 |
| Short name | T1435 |
| Test name | |
| Test status | |
| Simulation time | 496328475 ps |
| CPU time | 48.15 seconds |
| Started | Jul 03 07:32:26 PM PDT 24 |
| Finished | Jul 03 07:33:16 PM PDT 24 |
| Peak memory | 574224 kb |
| Host | smart-c2917c87-8fd9-4cac-9abb-1882f382ac36 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1613916596 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_random.1613916596 |
| Directory | /workspace/55.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_random_large_delays.3279323085 |
| Short name | T1465 |
| Test name | |
| Test status | |
| Simulation time | 75721090409 ps |
| CPU time | 778.72 seconds |
| Started | Jul 03 07:32:33 PM PDT 24 |
| Finished | Jul 03 07:45:33 PM PDT 24 |
| Peak memory | 574140 kb |
| Host | smart-28fef2f6-ca1d-4ac6-9356-700718871c2e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3279323085 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_random_large_delays.3279323085 |
| Directory | /workspace/55.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_random_slow_rsp.3767313051 |
| Short name | T2427 |
| Test name | |
| Test status | |
| Simulation time | 36816303319 ps |
| CPU time | 588.53 seconds |
| Started | Jul 03 07:32:27 PM PDT 24 |
| Finished | Jul 03 07:42:16 PM PDT 24 |
| Peak memory | 574212 kb |
| Host | smart-1702b02c-8b4c-44ea-acd9-0b3283db839b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3767313051 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_random_slow_rsp.3767313051 |
| Directory | /workspace/55.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_random_zero_delays.2469729278 |
| Short name | T464 |
| Test name | |
| Test status | |
| Simulation time | 568096757 ps |
| CPU time | 52.7 seconds |
| Started | Jul 03 07:32:26 PM PDT 24 |
| Finished | Jul 03 07:33:20 PM PDT 24 |
| Peak memory | 574036 kb |
| Host | smart-da2a5597-4617-4d19-907c-1791d02adce4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2469729278 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_random_zero_del ays.2469729278 |
| Directory | /workspace/55.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_same_source.1700903629 |
| Short name | T2087 |
| Test name | |
| Test status | |
| Simulation time | 1291041503 ps |
| CPU time | 37.12 seconds |
| Started | Jul 03 07:32:31 PM PDT 24 |
| Finished | Jul 03 07:33:09 PM PDT 24 |
| Peak memory | 574064 kb |
| Host | smart-5faec5ae-68f5-4012-b20e-f062545ff774 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1700903629 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_same_source.1700903629 |
| Directory | /workspace/55.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_smoke.3272800661 |
| Short name | T1730 |
| Test name | |
| Test status | |
| Simulation time | 35238906 ps |
| CPU time | 5.76 seconds |
| Started | Jul 03 07:32:27 PM PDT 24 |
| Finished | Jul 03 07:32:33 PM PDT 24 |
| Peak memory | 573088 kb |
| Host | smart-33464d98-07ab-4376-b7ff-e97f04e9c34c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3272800661 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_smoke.3272800661 |
| Directory | /workspace/55.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_smoke_large_delays.2503027736 |
| Short name | T2851 |
| Test name | |
| Test status | |
| Simulation time | 9341645827 ps |
| CPU time | 91.14 seconds |
| Started | Jul 03 07:32:29 PM PDT 24 |
| Finished | Jul 03 07:34:01 PM PDT 24 |
| Peak memory | 573320 kb |
| Host | smart-e5963729-84a4-44f0-aa83-f0fdf49ed02b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2503027736 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_smoke_large_delays.2503027736 |
| Directory | /workspace/55.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_smoke_slow_rsp.639108908 |
| Short name | T2844 |
| Test name | |
| Test status | |
| Simulation time | 6289655752 ps |
| CPU time | 95.17 seconds |
| Started | Jul 03 07:32:28 PM PDT 24 |
| Finished | Jul 03 07:34:04 PM PDT 24 |
| Peak memory | 573200 kb |
| Host | smart-07944ae1-5461-4497-82e6-c4b5a1c8393b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=639108908 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_smoke_slow_rsp.639108908 |
| Directory | /workspace/55.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_smoke_zero_delays.3017026665 |
| Short name | T1880 |
| Test name | |
| Test status | |
| Simulation time | 49707146 ps |
| CPU time | 5.97 seconds |
| Started | Jul 03 07:32:25 PM PDT 24 |
| Finished | Jul 03 07:32:31 PM PDT 24 |
| Peak memory | 573068 kb |
| Host | smart-bec572e4-508e-4fc4-9fbe-282a614d1d47 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3017026665 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_smoke_zero_delay s.3017026665 |
| Directory | /workspace/55.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_stress_all.429834534 |
| Short name | T437 |
| Test name | |
| Test status | |
| Simulation time | 2880108911 ps |
| CPU time | 246.59 seconds |
| Started | Jul 03 07:32:37 PM PDT 24 |
| Finished | Jul 03 07:36:45 PM PDT 24 |
| Peak memory | 574704 kb |
| Host | smart-47a60a27-9456-461a-96dc-fd1c1c0a7dd9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=429834534 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_stress_all.429834534 |
| Directory | /workspace/55.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_stress_all_with_error.1187251196 |
| Short name | T2086 |
| Test name | |
| Test status | |
| Simulation time | 17733304609 ps |
| CPU time | 556.66 seconds |
| Started | Jul 03 07:32:45 PM PDT 24 |
| Finished | Jul 03 07:42:03 PM PDT 24 |
| Peak memory | 574728 kb |
| Host | smart-cf719d2f-a6f2-4462-9543-43195c791f05 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187251196 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_stress_all_with_error.1187251196 |
| Directory | /workspace/55.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_stress_all_with_rand_reset.219023453 |
| Short name | T2241 |
| Test name | |
| Test status | |
| Simulation time | 2407550176 ps |
| CPU time | 210.96 seconds |
| Started | Jul 03 07:32:37 PM PDT 24 |
| Finished | Jul 03 07:36:09 PM PDT 24 |
| Peak memory | 574708 kb |
| Host | smart-2fb3e399-2404-4e91-b729-ee8f80a8d71f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219023453 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_stress_all_ with_rand_reset.219023453 |
| Directory | /workspace/55.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_stress_all_with_reset_error.1658774934 |
| Short name | T2304 |
| Test name | |
| Test status | |
| Simulation time | 203247765 ps |
| CPU time | 79.5 seconds |
| Started | Jul 03 07:32:37 PM PDT 24 |
| Finished | Jul 03 07:33:57 PM PDT 24 |
| Peak memory | 574668 kb |
| Host | smart-149fe60d-1005-4c89-a182-b6aee55f0d83 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1658774934 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_stress_al l_with_reset_error.1658774934 |
| Directory | /workspace/55.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_unmapped_addr.458815989 |
| Short name | T1897 |
| Test name | |
| Test status | |
| Simulation time | 918532877 ps |
| CPU time | 35.16 seconds |
| Started | Jul 03 07:32:32 PM PDT 24 |
| Finished | Jul 03 07:33:08 PM PDT 24 |
| Peak memory | 574192 kb |
| Host | smart-feba2f64-3263-4876-85fc-fcb72b5f653d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=458815989 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_unmapped_addr.458815989 |
| Directory | /workspace/55.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_access_same_device.1226522270 |
| Short name | T630 |
| Test name | |
| Test status | |
| Simulation time | 262175199 ps |
| CPU time | 23.99 seconds |
| Started | Jul 03 07:32:42 PM PDT 24 |
| Finished | Jul 03 07:33:07 PM PDT 24 |
| Peak memory | 573976 kb |
| Host | smart-701102d6-a50e-438d-b34e-2b7cd5d63173 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1226522270 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_access_same_device .1226522270 |
| Directory | /workspace/56.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_access_same_device_slow_rsp.3738963752 |
| Short name | T796 |
| Test name | |
| Test status | |
| Simulation time | 34931364502 ps |
| CPU time | 578.73 seconds |
| Started | Jul 03 07:32:46 PM PDT 24 |
| Finished | Jul 03 07:42:26 PM PDT 24 |
| Peak memory | 574256 kb |
| Host | smart-673620da-28e0-4caf-ba06-2ce254cc39b1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3738963752 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_access_same_ device_slow_rsp.3738963752 |
| Directory | /workspace/56.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_error_and_unmapped_addr.1339720812 |
| Short name | T1308 |
| Test name | |
| Test status | |
| Simulation time | 205675252 ps |
| CPU time | 10.99 seconds |
| Started | Jul 03 07:32:49 PM PDT 24 |
| Finished | Jul 03 07:33:01 PM PDT 24 |
| Peak memory | 574044 kb |
| Host | smart-5335b824-15e2-4dc0-ba03-d19644d09877 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1339720812 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_error_and_unmapped_add r.1339720812 |
| Directory | /workspace/56.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_error_random.69519132 |
| Short name | T2795 |
| Test name | |
| Test status | |
| Simulation time | 360813350 ps |
| CPU time | 13.74 seconds |
| Started | Jul 03 07:32:47 PM PDT 24 |
| Finished | Jul 03 07:33:01 PM PDT 24 |
| Peak memory | 574528 kb |
| Host | smart-294bd4e4-4065-4164-b0b7-6c485c9f4eff |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69519132 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_error_random.69519132 |
| Directory | /workspace/56.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_random.3076973258 |
| Short name | T1592 |
| Test name | |
| Test status | |
| Simulation time | 1067068690 ps |
| CPU time | 37.97 seconds |
| Started | Jul 03 07:32:41 PM PDT 24 |
| Finished | Jul 03 07:33:20 PM PDT 24 |
| Peak memory | 574236 kb |
| Host | smart-2f9e983d-33ee-4e00-b307-dd51db7ce4ef |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3076973258 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_random.3076973258 |
| Directory | /workspace/56.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_random_large_delays.1702484593 |
| Short name | T2419 |
| Test name | |
| Test status | |
| Simulation time | 4353101700 ps |
| CPU time | 45.4 seconds |
| Started | Jul 03 07:32:49 PM PDT 24 |
| Finished | Jul 03 07:33:35 PM PDT 24 |
| Peak memory | 573172 kb |
| Host | smart-d31ec5d4-0d0b-4865-bfc6-5b02cfa1fb1f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702484593 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_random_large_delays.1702484593 |
| Directory | /workspace/56.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_random_slow_rsp.858681265 |
| Short name | T2403 |
| Test name | |
| Test status | |
| Simulation time | 19961020625 ps |
| CPU time | 320.92 seconds |
| Started | Jul 03 07:32:49 PM PDT 24 |
| Finished | Jul 03 07:38:11 PM PDT 24 |
| Peak memory | 574252 kb |
| Host | smart-b6a0d77f-01be-4c64-9ef5-7bb715dc20e7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=858681265 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_random_slow_rsp.858681265 |
| Directory | /workspace/56.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_random_zero_delays.3266769422 |
| Short name | T1959 |
| Test name | |
| Test status | |
| Simulation time | 220919844 ps |
| CPU time | 22.15 seconds |
| Started | Jul 03 07:32:43 PM PDT 24 |
| Finished | Jul 03 07:33:06 PM PDT 24 |
| Peak memory | 574200 kb |
| Host | smart-9190d3b4-735d-4d44-a5be-9c4c5596acdd |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3266769422 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_random_zero_del ays.3266769422 |
| Directory | /workspace/56.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_same_source.2284638501 |
| Short name | T1572 |
| Test name | |
| Test status | |
| Simulation time | 1216835184 ps |
| CPU time | 41.41 seconds |
| Started | Jul 03 07:32:47 PM PDT 24 |
| Finished | Jul 03 07:33:29 PM PDT 24 |
| Peak memory | 574276 kb |
| Host | smart-189496df-8a0e-416e-814e-1ebcd420a6b5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2284638501 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_same_source.2284638501 |
| Directory | /workspace/56.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_smoke.3927121837 |
| Short name | T2066 |
| Test name | |
| Test status | |
| Simulation time | 211535171 ps |
| CPU time | 9.01 seconds |
| Started | Jul 03 07:32:38 PM PDT 24 |
| Finished | Jul 03 07:32:48 PM PDT 24 |
| Peak memory | 572896 kb |
| Host | smart-9869699f-235c-424b-b946-8e549d51ca9b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3927121837 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_smoke.3927121837 |
| Directory | /workspace/56.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_smoke_large_delays.3851550298 |
| Short name | T2687 |
| Test name | |
| Test status | |
| Simulation time | 7777562248 ps |
| CPU time | 74.97 seconds |
| Started | Jul 03 07:32:41 PM PDT 24 |
| Finished | Jul 03 07:33:57 PM PDT 24 |
| Peak memory | 573240 kb |
| Host | smart-c4afd5ca-615e-4847-9e0f-a49008ae416a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3851550298 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_smoke_large_delays.3851550298 |
| Directory | /workspace/56.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_smoke_slow_rsp.1368784355 |
| Short name | T2351 |
| Test name | |
| Test status | |
| Simulation time | 4653604536 ps |
| CPU time | 83.86 seconds |
| Started | Jul 03 07:32:42 PM PDT 24 |
| Finished | Jul 03 07:34:07 PM PDT 24 |
| Peak memory | 573156 kb |
| Host | smart-5172c9e6-1eae-47ea-bf21-c6bcd6310c44 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1368784355 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_smoke_slow_rsp.1368784355 |
| Directory | /workspace/56.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_smoke_zero_delays.2067996783 |
| Short name | T511 |
| Test name | |
| Test status | |
| Simulation time | 35995079 ps |
| CPU time | 5.76 seconds |
| Started | Jul 03 07:32:42 PM PDT 24 |
| Finished | Jul 03 07:32:49 PM PDT 24 |
| Peak memory | 573116 kb |
| Host | smart-cf5de670-52d8-463e-96e6-e2dad6de9338 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2067996783 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_smoke_zero_delay s.2067996783 |
| Directory | /workspace/56.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_stress_all.198538777 |
| Short name | T1325 |
| Test name | |
| Test status | |
| Simulation time | 6652955 ps |
| CPU time | 3.97 seconds |
| Started | Jul 03 07:32:48 PM PDT 24 |
| Finished | Jul 03 07:32:52 PM PDT 24 |
| Peak memory | 564736 kb |
| Host | smart-91523725-14bf-4f6b-b9c0-a158056a1942 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=198538777 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_stress_all.198538777 |
| Directory | /workspace/56.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_stress_all_with_error.1311433235 |
| Short name | T600 |
| Test name | |
| Test status | |
| Simulation time | 11371988260 ps |
| CPU time | 357.41 seconds |
| Started | Jul 03 07:32:49 PM PDT 24 |
| Finished | Jul 03 07:38:47 PM PDT 24 |
| Peak memory | 574644 kb |
| Host | smart-e88f1f2d-6e0e-4df5-a5d7-70b8a4410f0b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1311433235 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_stress_all_with_error.1311433235 |
| Directory | /workspace/56.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_stress_all_with_rand_reset.2395414880 |
| Short name | T2634 |
| Test name | |
| Test status | |
| Simulation time | 635364497 ps |
| CPU time | 63.4 seconds |
| Started | Jul 03 07:32:53 PM PDT 24 |
| Finished | Jul 03 07:33:59 PM PDT 24 |
| Peak memory | 574636 kb |
| Host | smart-6b502d58-eab7-4fa4-b53c-39e1d6073499 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2395414880 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_stress_all _with_rand_reset.2395414880 |
| Directory | /workspace/56.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_stress_all_with_reset_error.426136431 |
| Short name | T774 |
| Test name | |
| Test status | |
| Simulation time | 4905036181 ps |
| CPU time | 216.88 seconds |
| Started | Jul 03 07:32:53 PM PDT 24 |
| Finished | Jul 03 07:36:32 PM PDT 24 |
| Peak memory | 574720 kb |
| Host | smart-235372ad-d4c9-4267-8bbf-aa6c1da1b358 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=426136431 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_stress_all _with_reset_error.426136431 |
| Directory | /workspace/56.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_unmapped_addr.3825805178 |
| Short name | T2508 |
| Test name | |
| Test status | |
| Simulation time | 102562032 ps |
| CPU time | 14.37 seconds |
| Started | Jul 03 07:32:45 PM PDT 24 |
| Finished | Jul 03 07:33:00 PM PDT 24 |
| Peak memory | 574068 kb |
| Host | smart-8e149d25-bb08-4cfe-b25e-c80af530e556 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3825805178 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_unmapped_addr.3825805178 |
| Directory | /workspace/56.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_access_same_device.3799117977 |
| Short name | T1563 |
| Test name | |
| Test status | |
| Simulation time | 647378513 ps |
| CPU time | 26.91 seconds |
| Started | Jul 03 07:32:51 PM PDT 24 |
| Finished | Jul 03 07:33:20 PM PDT 24 |
| Peak memory | 573956 kb |
| Host | smart-9b7f4aa8-1d8f-4b38-b3b1-70a75b3866c3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3799117977 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_access_same_device .3799117977 |
| Directory | /workspace/57.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_access_same_device_slow_rsp.2318499042 |
| Short name | T1779 |
| Test name | |
| Test status | |
| Simulation time | 32895876255 ps |
| CPU time | 616.76 seconds |
| Started | Jul 03 07:32:51 PM PDT 24 |
| Finished | Jul 03 07:43:11 PM PDT 24 |
| Peak memory | 574364 kb |
| Host | smart-bf722f77-2999-4657-9ef7-2c06a0b32f90 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318499042 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_access_same_ device_slow_rsp.2318499042 |
| Directory | /workspace/57.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_error_and_unmapped_addr.3431802420 |
| Short name | T2238 |
| Test name | |
| Test status | |
| Simulation time | 1187905928 ps |
| CPU time | 47.24 seconds |
| Started | Jul 03 07:32:53 PM PDT 24 |
| Finished | Jul 03 07:33:43 PM PDT 24 |
| Peak memory | 574476 kb |
| Host | smart-5c93ad80-1f09-447e-9138-82a2ab1d7771 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3431802420 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_error_and_unmapped_add r.3431802420 |
| Directory | /workspace/57.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_error_random.1634829413 |
| Short name | T1510 |
| Test name | |
| Test status | |
| Simulation time | 333462385 ps |
| CPU time | 28.88 seconds |
| Started | Jul 03 07:32:52 PM PDT 24 |
| Finished | Jul 03 07:33:24 PM PDT 24 |
| Peak memory | 574020 kb |
| Host | smart-abfe8357-5327-4b4b-9481-1c4eb1195da5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1634829413 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_error_random.1634829413 |
| Directory | /workspace/57.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_random.4152887795 |
| Short name | T2480 |
| Test name | |
| Test status | |
| Simulation time | 330156507 ps |
| CPU time | 31.74 seconds |
| Started | Jul 03 07:32:48 PM PDT 24 |
| Finished | Jul 03 07:33:20 PM PDT 24 |
| Peak memory | 574096 kb |
| Host | smart-8dc16d7c-b41f-4809-993b-ceb9cb7d81f3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4152887795 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_random.4152887795 |
| Directory | /workspace/57.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_random_large_delays.3056636680 |
| Short name | T496 |
| Test name | |
| Test status | |
| Simulation time | 60144218132 ps |
| CPU time | 667.86 seconds |
| Started | Jul 03 07:32:55 PM PDT 24 |
| Finished | Jul 03 07:44:04 PM PDT 24 |
| Peak memory | 574316 kb |
| Host | smart-f7029480-64bd-4735-b85e-17179611813c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3056636680 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_random_large_delays.3056636680 |
| Directory | /workspace/57.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_random_slow_rsp.312748143 |
| Short name | T2089 |
| Test name | |
| Test status | |
| Simulation time | 11048309429 ps |
| CPU time | 190.06 seconds |
| Started | Jul 03 07:32:53 PM PDT 24 |
| Finished | Jul 03 07:36:05 PM PDT 24 |
| Peak memory | 574104 kb |
| Host | smart-d6ab9ed8-7aee-4186-900f-ea2ed27c64a9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=312748143 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_random_slow_rsp.312748143 |
| Directory | /workspace/57.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_random_zero_delays.371284546 |
| Short name | T1884 |
| Test name | |
| Test status | |
| Simulation time | 268581419 ps |
| CPU time | 28.08 seconds |
| Started | Jul 03 07:32:53 PM PDT 24 |
| Finished | Jul 03 07:33:23 PM PDT 24 |
| Peak memory | 574132 kb |
| Host | smart-4d022438-e46a-470c-8439-38945da71892 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=371284546 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_random_zero_dela ys.371284546 |
| Directory | /workspace/57.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_same_source.3700797747 |
| Short name | T2495 |
| Test name | |
| Test status | |
| Simulation time | 1309904091 ps |
| CPU time | 35.99 seconds |
| Started | Jul 03 07:32:50 PM PDT 24 |
| Finished | Jul 03 07:33:28 PM PDT 24 |
| Peak memory | 574196 kb |
| Host | smart-b7355734-aa7e-4f30-813c-86a2ac2297e0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3700797747 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_same_source.3700797747 |
| Directory | /workspace/57.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_smoke.3891764599 |
| Short name | T2708 |
| Test name | |
| Test status | |
| Simulation time | 48707483 ps |
| CPU time | 6.23 seconds |
| Started | Jul 03 07:32:47 PM PDT 24 |
| Finished | Jul 03 07:32:54 PM PDT 24 |
| Peak memory | 574072 kb |
| Host | smart-03094d2f-c1b7-4ab1-a15e-c738f6d17777 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3891764599 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_smoke.3891764599 |
| Directory | /workspace/57.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_smoke_large_delays.4192038052 |
| Short name | T2481 |
| Test name | |
| Test status | |
| Simulation time | 8658171999 ps |
| CPU time | 95.62 seconds |
| Started | Jul 03 07:32:48 PM PDT 24 |
| Finished | Jul 03 07:34:24 PM PDT 24 |
| Peak memory | 573156 kb |
| Host | smart-52950716-a8f0-4db7-9501-3c5beb4792c5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4192038052 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_smoke_large_delays.4192038052 |
| Directory | /workspace/57.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_smoke_slow_rsp.2396886497 |
| Short name | T2215 |
| Test name | |
| Test status | |
| Simulation time | 3820200686 ps |
| CPU time | 65.03 seconds |
| Started | Jul 03 07:32:48 PM PDT 24 |
| Finished | Jul 03 07:33:54 PM PDT 24 |
| Peak memory | 574332 kb |
| Host | smart-adc4b3ed-54eb-41b8-b6dc-4756cadac3c9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2396886497 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_smoke_slow_rsp.2396886497 |
| Directory | /workspace/57.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_smoke_zero_delays.3443203551 |
| Short name | T2448 |
| Test name | |
| Test status | |
| Simulation time | 52817917 ps |
| CPU time | 6.25 seconds |
| Started | Jul 03 07:32:47 PM PDT 24 |
| Finished | Jul 03 07:32:54 PM PDT 24 |
| Peak memory | 573176 kb |
| Host | smart-58b426ff-49d3-417e-b988-d495763f0348 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3443203551 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_smoke_zero_delay s.3443203551 |
| Directory | /workspace/57.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_stress_all.220968509 |
| Short name | T538 |
| Test name | |
| Test status | |
| Simulation time | 1642582495 ps |
| CPU time | 68.04 seconds |
| Started | Jul 03 07:32:50 PM PDT 24 |
| Finished | Jul 03 07:34:00 PM PDT 24 |
| Peak memory | 574272 kb |
| Host | smart-38a89dd9-a14b-4125-ac7e-b8d2661894be |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220968509 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_stress_all.220968509 |
| Directory | /workspace/57.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_stress_all_with_error.148815901 |
| Short name | T2136 |
| Test name | |
| Test status | |
| Simulation time | 4268793331 ps |
| CPU time | 146.6 seconds |
| Started | Jul 03 07:32:56 PM PDT 24 |
| Finished | Jul 03 07:35:24 PM PDT 24 |
| Peak memory | 574544 kb |
| Host | smart-5e6f2f00-cf77-4ef4-a555-ab65084c8ede |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=148815901 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_stress_all_with_error.148815901 |
| Directory | /workspace/57.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_stress_all_with_rand_reset.3469564166 |
| Short name | T557 |
| Test name | |
| Test status | |
| Simulation time | 2627776447 ps |
| CPU time | 199.81 seconds |
| Started | Jul 03 07:32:52 PM PDT 24 |
| Finished | Jul 03 07:36:14 PM PDT 24 |
| Peak memory | 574676 kb |
| Host | smart-1b5fb212-7409-4a01-a2a1-b6f69212059b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3469564166 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_stress_all _with_rand_reset.3469564166 |
| Directory | /workspace/57.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_stress_all_with_reset_error.1281316201 |
| Short name | T1795 |
| Test name | |
| Test status | |
| Simulation time | 42837816 ps |
| CPU time | 17.15 seconds |
| Started | Jul 03 07:32:57 PM PDT 24 |
| Finished | Jul 03 07:33:15 PM PDT 24 |
| Peak memory | 574504 kb |
| Host | smart-bac93c42-afa3-419e-8902-f9bd366f5f89 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1281316201 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_stress_al l_with_reset_error.1281316201 |
| Directory | /workspace/57.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_unmapped_addr.4255384729 |
| Short name | T1850 |
| Test name | |
| Test status | |
| Simulation time | 278320403 ps |
| CPU time | 31.39 seconds |
| Started | Jul 03 07:32:53 PM PDT 24 |
| Finished | Jul 03 07:33:27 PM PDT 24 |
| Peak memory | 574268 kb |
| Host | smart-27bb4d86-355e-42f9-b051-e02f4ee22340 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4255384729 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_unmapped_addr.4255384729 |
| Directory | /workspace/57.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_access_same_device.3552224139 |
| Short name | T2075 |
| Test name | |
| Test status | |
| Simulation time | 751724665 ps |
| CPU time | 37.28 seconds |
| Started | Jul 03 07:32:56 PM PDT 24 |
| Finished | Jul 03 07:33:35 PM PDT 24 |
| Peak memory | 574224 kb |
| Host | smart-5d9a4365-8dfe-4538-b9ef-478066f18d94 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3552224139 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_access_same_device .3552224139 |
| Directory | /workspace/58.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_access_same_device_slow_rsp.4234534261 |
| Short name | T2253 |
| Test name | |
| Test status | |
| Simulation time | 85210111693 ps |
| CPU time | 1454.78 seconds |
| Started | Jul 03 07:33:03 PM PDT 24 |
| Finished | Jul 03 07:57:19 PM PDT 24 |
| Peak memory | 574440 kb |
| Host | smart-a4390a1c-7b92-4d8b-b1ba-e93c8760f4f4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4234534261 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_access_same_ device_slow_rsp.4234534261 |
| Directory | /workspace/58.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_error_and_unmapped_addr.3122624417 |
| Short name | T1444 |
| Test name | |
| Test status | |
| Simulation time | 1013544311 ps |
| CPU time | 36.73 seconds |
| Started | Jul 03 07:33:01 PM PDT 24 |
| Finished | Jul 03 07:33:39 PM PDT 24 |
| Peak memory | 574040 kb |
| Host | smart-9f73a600-5cb1-42d4-9a79-7db1f52b26c2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3122624417 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_error_and_unmapped_add r.3122624417 |
| Directory | /workspace/58.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_error_random.481014549 |
| Short name | T1874 |
| Test name | |
| Test status | |
| Simulation time | 146700240 ps |
| CPU time | 14.65 seconds |
| Started | Jul 03 07:33:01 PM PDT 24 |
| Finished | Jul 03 07:33:16 PM PDT 24 |
| Peak memory | 574056 kb |
| Host | smart-73363a15-e692-4136-a6a1-be325b2b2069 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=481014549 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_error_random.481014549 |
| Directory | /workspace/58.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_random.2974894905 |
| Short name | T544 |
| Test name | |
| Test status | |
| Simulation time | 304947742 ps |
| CPU time | 27.8 seconds |
| Started | Jul 03 07:32:59 PM PDT 24 |
| Finished | Jul 03 07:33:27 PM PDT 24 |
| Peak memory | 574208 kb |
| Host | smart-36ca1141-23cd-4e07-952c-4513ec48f89c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974894905 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_random.2974894905 |
| Directory | /workspace/58.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_random_large_delays.3114511217 |
| Short name | T2308 |
| Test name | |
| Test status | |
| Simulation time | 102817620327 ps |
| CPU time | 1162.13 seconds |
| Started | Jul 03 07:32:57 PM PDT 24 |
| Finished | Jul 03 07:52:20 PM PDT 24 |
| Peak memory | 574372 kb |
| Host | smart-531e9de5-3c27-4562-9956-5c5ba4b13700 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114511217 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_random_large_delays.3114511217 |
| Directory | /workspace/58.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_random_slow_rsp.2841766938 |
| Short name | T469 |
| Test name | |
| Test status | |
| Simulation time | 40167082506 ps |
| CPU time | 696.19 seconds |
| Started | Jul 03 07:32:59 PM PDT 24 |
| Finished | Jul 03 07:44:37 PM PDT 24 |
| Peak memory | 574220 kb |
| Host | smart-aba67191-7988-4e67-b224-3c2513a20de8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841766938 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_random_slow_rsp.2841766938 |
| Directory | /workspace/58.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_random_zero_delays.491019485 |
| Short name | T533 |
| Test name | |
| Test status | |
| Simulation time | 311451742 ps |
| CPU time | 26.48 seconds |
| Started | Jul 03 07:32:57 PM PDT 24 |
| Finished | Jul 03 07:33:24 PM PDT 24 |
| Peak memory | 574184 kb |
| Host | smart-ce3e30d1-3d39-4ed4-a3db-13a5ef0343d8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=491019485 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_random_zero_dela ys.491019485 |
| Directory | /workspace/58.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_same_source.3380199478 |
| Short name | T485 |
| Test name | |
| Test status | |
| Simulation time | 329751211 ps |
| CPU time | 25.69 seconds |
| Started | Jul 03 07:33:02 PM PDT 24 |
| Finished | Jul 03 07:33:29 PM PDT 24 |
| Peak memory | 574104 kb |
| Host | smart-ecdbefdc-7566-4760-b266-0c6349a829df |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3380199478 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_same_source.3380199478 |
| Directory | /workspace/58.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_smoke.1058429696 |
| Short name | T1371 |
| Test name | |
| Test status | |
| Simulation time | 52373119 ps |
| CPU time | 6.6 seconds |
| Started | Jul 03 07:32:55 PM PDT 24 |
| Finished | Jul 03 07:33:03 PM PDT 24 |
| Peak memory | 573948 kb |
| Host | smart-6a2f0eb1-68b2-4ac7-9eb9-4e979eda0bb0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1058429696 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_smoke.1058429696 |
| Directory | /workspace/58.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_smoke_large_delays.1202374211 |
| Short name | T1568 |
| Test name | |
| Test status | |
| Simulation time | 6911773521 ps |
| CPU time | 71.75 seconds |
| Started | Jul 03 07:32:55 PM PDT 24 |
| Finished | Jul 03 07:34:08 PM PDT 24 |
| Peak memory | 573028 kb |
| Host | smart-a3d8d845-ebb5-440b-9256-9841fddc481a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1202374211 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_smoke_large_delays.1202374211 |
| Directory | /workspace/58.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_smoke_slow_rsp.2188642462 |
| Short name | T2042 |
| Test name | |
| Test status | |
| Simulation time | 4320086643 ps |
| CPU time | 75.79 seconds |
| Started | Jul 03 07:32:57 PM PDT 24 |
| Finished | Jul 03 07:34:14 PM PDT 24 |
| Peak memory | 573072 kb |
| Host | smart-bba54a29-4cf3-4aa9-a324-e3582bc227a4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188642462 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_smoke_slow_rsp.2188642462 |
| Directory | /workspace/58.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_smoke_zero_delays.2639975804 |
| Short name | T2181 |
| Test name | |
| Test status | |
| Simulation time | 38563428 ps |
| CPU time | 6.22 seconds |
| Started | Jul 03 07:32:59 PM PDT 24 |
| Finished | Jul 03 07:33:05 PM PDT 24 |
| Peak memory | 574104 kb |
| Host | smart-38cd4aa2-629e-4a94-8858-5c8c7c4bf67e |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2639975804 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_smoke_zero_delay s.2639975804 |
| Directory | /workspace/58.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_stress_all.2967550038 |
| Short name | T1611 |
| Test name | |
| Test status | |
| Simulation time | 855758508 ps |
| CPU time | 71.27 seconds |
| Started | Jul 03 07:33:03 PM PDT 24 |
| Finished | Jul 03 07:34:15 PM PDT 24 |
| Peak memory | 574408 kb |
| Host | smart-38aca8db-f2ff-47e6-bf7d-f8fa1fe9dd08 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2967550038 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_stress_all.2967550038 |
| Directory | /workspace/58.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_stress_all_with_error.208957823 |
| Short name | T1601 |
| Test name | |
| Test status | |
| Simulation time | 1995400780 ps |
| CPU time | 148.31 seconds |
| Started | Jul 03 07:33:01 PM PDT 24 |
| Finished | Jul 03 07:35:31 PM PDT 24 |
| Peak memory | 574228 kb |
| Host | smart-56eeeae8-d6aa-47eb-bbdf-0beafa2c5b0a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=208957823 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_stress_all_with_error.208957823 |
| Directory | /workspace/58.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_stress_all_with_rand_reset.3733981464 |
| Short name | T2474 |
| Test name | |
| Test status | |
| Simulation time | 578218768 ps |
| CPU time | 170.28 seconds |
| Started | Jul 03 07:33:03 PM PDT 24 |
| Finished | Jul 03 07:35:54 PM PDT 24 |
| Peak memory | 574624 kb |
| Host | smart-478ef760-7c71-4ad1-963b-b233f92a3223 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3733981464 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_stress_all _with_rand_reset.3733981464 |
| Directory | /workspace/58.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_stress_all_with_reset_error.1586977769 |
| Short name | T809 |
| Test name | |
| Test status | |
| Simulation time | 10735110627 ps |
| CPU time | 560.97 seconds |
| Started | Jul 03 07:33:04 PM PDT 24 |
| Finished | Jul 03 07:42:25 PM PDT 24 |
| Peak memory | 574672 kb |
| Host | smart-96e1fcb2-4872-474e-a89d-6eea40e66852 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1586977769 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_stress_al l_with_reset_error.1586977769 |
| Directory | /workspace/58.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_unmapped_addr.1381002998 |
| Short name | T1723 |
| Test name | |
| Test status | |
| Simulation time | 791905552 ps |
| CPU time | 32.95 seconds |
| Started | Jul 03 07:33:01 PM PDT 24 |
| Finished | Jul 03 07:33:35 PM PDT 24 |
| Peak memory | 574016 kb |
| Host | smart-1e726cff-6919-4fb2-b0ba-65026d129ba3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1381002998 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_unmapped_addr.1381002998 |
| Directory | /workspace/58.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_access_same_device.3088692600 |
| Short name | T2497 |
| Test name | |
| Test status | |
| Simulation time | 415601615 ps |
| CPU time | 26.7 seconds |
| Started | Jul 03 07:33:07 PM PDT 24 |
| Finished | Jul 03 07:33:35 PM PDT 24 |
| Peak memory | 574156 kb |
| Host | smart-65beb585-5d47-4fb1-9bde-0d9bad502ace |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3088692600 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_access_same_device .3088692600 |
| Directory | /workspace/59.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_access_same_device_slow_rsp.3164609976 |
| Short name | T784 |
| Test name | |
| Test status | |
| Simulation time | 109284307568 ps |
| CPU time | 1997.64 seconds |
| Started | Jul 03 07:33:08 PM PDT 24 |
| Finished | Jul 03 08:06:27 PM PDT 24 |
| Peak memory | 574268 kb |
| Host | smart-1cb59d2f-a71f-4aaa-b5a5-c04d121fa4be |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3164609976 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_access_same_ device_slow_rsp.3164609976 |
| Directory | /workspace/59.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_error_random.1259192691 |
| Short name | T1797 |
| Test name | |
| Test status | |
| Simulation time | 1716215249 ps |
| CPU time | 52.32 seconds |
| Started | Jul 03 07:33:13 PM PDT 24 |
| Finished | Jul 03 07:34:05 PM PDT 24 |
| Peak memory | 574508 kb |
| Host | smart-8537b77e-014e-4918-a20c-5a69d8c037d2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1259192691 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_error_random.1259192691 |
| Directory | /workspace/59.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_random.2952655044 |
| Short name | T2212 |
| Test name | |
| Test status | |
| Simulation time | 299588955 ps |
| CPU time | 13.86 seconds |
| Started | Jul 03 07:33:07 PM PDT 24 |
| Finished | Jul 03 07:33:22 PM PDT 24 |
| Peak memory | 574124 kb |
| Host | smart-3390a45a-9184-4492-96c5-7e750f8e77b3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2952655044 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_random.2952655044 |
| Directory | /workspace/59.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_random_large_delays.3631862031 |
| Short name | T2471 |
| Test name | |
| Test status | |
| Simulation time | 30064627285 ps |
| CPU time | 316.05 seconds |
| Started | Jul 03 07:33:10 PM PDT 24 |
| Finished | Jul 03 07:38:27 PM PDT 24 |
| Peak memory | 574304 kb |
| Host | smart-c5897b00-d2a0-420b-ae6f-edf88c0e6d36 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3631862031 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_random_large_delays.3631862031 |
| Directory | /workspace/59.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_random_slow_rsp.4204630157 |
| Short name | T2693 |
| Test name | |
| Test status | |
| Simulation time | 31752717325 ps |
| CPU time | 540.02 seconds |
| Started | Jul 03 07:33:08 PM PDT 24 |
| Finished | Jul 03 07:42:09 PM PDT 24 |
| Peak memory | 574308 kb |
| Host | smart-1a2d8d38-82d2-4d00-acaf-71759d71240a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4204630157 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_random_slow_rsp.4204630157 |
| Directory | /workspace/59.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_random_zero_delays.915061593 |
| Short name | T1578 |
| Test name | |
| Test status | |
| Simulation time | 525518058 ps |
| CPU time | 46.92 seconds |
| Started | Jul 03 07:33:06 PM PDT 24 |
| Finished | Jul 03 07:33:55 PM PDT 24 |
| Peak memory | 574240 kb |
| Host | smart-1867171e-687c-4d6f-bee3-ecd347782c27 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=915061593 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_random_zero_dela ys.915061593 |
| Directory | /workspace/59.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_same_source.845557884 |
| Short name | T1803 |
| Test name | |
| Test status | |
| Simulation time | 2308819090 ps |
| CPU time | 68.02 seconds |
| Started | Jul 03 07:33:13 PM PDT 24 |
| Finished | Jul 03 07:34:22 PM PDT 24 |
| Peak memory | 574200 kb |
| Host | smart-49262e9e-717d-4aa7-a65f-daeaeaaadc5e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=845557884 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_same_source.845557884 |
| Directory | /workspace/59.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_smoke.4241251888 |
| Short name | T1627 |
| Test name | |
| Test status | |
| Simulation time | 44663858 ps |
| CPU time | 6.73 seconds |
| Started | Jul 03 07:33:02 PM PDT 24 |
| Finished | Jul 03 07:33:10 PM PDT 24 |
| Peak memory | 574092 kb |
| Host | smart-34c96ce1-5aaa-4f8d-b0b2-be334cc0f225 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4241251888 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_smoke.4241251888 |
| Directory | /workspace/59.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_smoke_large_delays.3029447982 |
| Short name | T1501 |
| Test name | |
| Test status | |
| Simulation time | 9761668890 ps |
| CPU time | 103.62 seconds |
| Started | Jul 03 07:33:09 PM PDT 24 |
| Finished | Jul 03 07:34:54 PM PDT 24 |
| Peak memory | 573264 kb |
| Host | smart-b735dcbe-1703-4e16-93f6-ab6f4aa56ad3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3029447982 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_smoke_large_delays.3029447982 |
| Directory | /workspace/59.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_smoke_slow_rsp.2698943218 |
| Short name | T2284 |
| Test name | |
| Test status | |
| Simulation time | 3014130107 ps |
| CPU time | 53.15 seconds |
| Started | Jul 03 07:33:07 PM PDT 24 |
| Finished | Jul 03 07:34:02 PM PDT 24 |
| Peak memory | 573152 kb |
| Host | smart-fd74ebfb-2f10-48f6-a845-4777e0b492f1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2698943218 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_smoke_slow_rsp.2698943218 |
| Directory | /workspace/59.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_smoke_zero_delays.1922548868 |
| Short name | T1892 |
| Test name | |
| Test status | |
| Simulation time | 44110627 ps |
| CPU time | 6.43 seconds |
| Started | Jul 03 07:33:07 PM PDT 24 |
| Finished | Jul 03 07:33:15 PM PDT 24 |
| Peak memory | 573164 kb |
| Host | smart-72c2a03e-d49c-4c45-a67b-07e96cae0cb3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1922548868 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_smoke_zero_delay s.1922548868 |
| Directory | /workspace/59.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_stress_all.1556382268 |
| Short name | T520 |
| Test name | |
| Test status | |
| Simulation time | 5674303531 ps |
| CPU time | 209.27 seconds |
| Started | Jul 03 07:33:13 PM PDT 24 |
| Finished | Jul 03 07:36:44 PM PDT 24 |
| Peak memory | 574644 kb |
| Host | smart-a72795fb-938c-46a6-aa28-1ae2f9928e53 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556382268 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_stress_all.1556382268 |
| Directory | /workspace/59.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_stress_all_with_error.1050623500 |
| Short name | T2147 |
| Test name | |
| Test status | |
| Simulation time | 2656808281 ps |
| CPU time | 206.27 seconds |
| Started | Jul 03 07:33:11 PM PDT 24 |
| Finished | Jul 03 07:36:38 PM PDT 24 |
| Peak memory | 574784 kb |
| Host | smart-c7059cda-83eb-459d-97f6-4e42403f20d8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1050623500 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_stress_all_with_error.1050623500 |
| Directory | /workspace/59.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_stress_all_with_rand_reset.2581491 |
| Short name | T2126 |
| Test name | |
| Test status | |
| Simulation time | 10538590806 ps |
| CPU time | 653.47 seconds |
| Started | Jul 03 07:33:13 PM PDT 24 |
| Finished | Jul 03 07:44:08 PM PDT 24 |
| Peak memory | 574708 kb |
| Host | smart-5a3bdcc5-5d75-411b-8f0e-5b15f8ea3c3a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581491 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_reset _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_stress_all_wi th_rand_reset.2581491 |
| Directory | /workspace/59.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_stress_all_with_reset_error.2831655188 |
| Short name | T1583 |
| Test name | |
| Test status | |
| Simulation time | 709813135 ps |
| CPU time | 58.02 seconds |
| Started | Jul 03 07:33:19 PM PDT 24 |
| Finished | Jul 03 07:34:18 PM PDT 24 |
| Peak memory | 574224 kb |
| Host | smart-9cc1d73d-b9a2-4d74-b51e-f481d2b13133 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2831655188 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_stress_al l_with_reset_error.2831655188 |
| Directory | /workspace/59.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_unmapped_addr.1616659517 |
| Short name | T2777 |
| Test name | |
| Test status | |
| Simulation time | 1111739820 ps |
| CPU time | 45.03 seconds |
| Started | Jul 03 07:33:13 PM PDT 24 |
| Finished | Jul 03 07:33:59 PM PDT 24 |
| Peak memory | 574260 kb |
| Host | smart-205fe201-57a8-4887-853a-bdf36bca0d99 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1616659517 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_unmapped_addr.1616659517 |
| Directory | /workspace/59.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/6.chip_csr_rw.1005590815 |
| Short name | T2741 |
| Test name | |
| Test status | |
| Simulation time | 5643140561 ps |
| CPU time | 535.67 seconds |
| Started | Jul 03 07:23:05 PM PDT 24 |
| Finished | Jul 03 07:32:02 PM PDT 24 |
| Peak memory | 596544 kb |
| Host | smart-0d27d84c-2dcb-4dad-822f-add7069399c2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1005590815 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.chip_csr_rw.1005590815 |
| Directory | /workspace/6.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/6.chip_same_csr_outstanding.367682108 |
| Short name | T2162 |
| Test name | |
| Test status | |
| Simulation time | 32446578345 ps |
| CPU time | 4211.16 seconds |
| Started | Jul 03 07:22:53 PM PDT 24 |
| Finished | Jul 03 08:33:06 PM PDT 24 |
| Peak memory | 592472 kb |
| Host | smart-db774d72-4bac-46fa-982c-5f34b4c9259e |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=367682108 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 6.chip_same_csr_outstanding.367682108 |
| Directory | /workspace/6.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_access_same_device.266462758 |
| Short name | T1843 |
| Test name | |
| Test status | |
| Simulation time | 94760174 ps |
| CPU time | 14.27 seconds |
| Started | Jul 03 07:23:00 PM PDT 24 |
| Finished | Jul 03 07:23:16 PM PDT 24 |
| Peak memory | 574108 kb |
| Host | smart-97e73fae-9004-4324-b5a0-32f07495238f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=266462758 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_access_same_device.266462758 |
| Directory | /workspace/6.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_access_same_device_slow_rsp.2012307751 |
| Short name | T2821 |
| Test name | |
| Test status | |
| Simulation time | 45882147877 ps |
| CPU time | 813.47 seconds |
| Started | Jul 03 07:23:00 PM PDT 24 |
| Finished | Jul 03 07:36:34 PM PDT 24 |
| Peak memory | 574196 kb |
| Host | smart-1bf0a291-2ef3-440d-8dc2-a43dca3ce2b4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2012307751 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_access_same_d evice_slow_rsp.2012307751 |
| Directory | /workspace/6.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_error_and_unmapped_addr.1721468041 |
| Short name | T1680 |
| Test name | |
| Test status | |
| Simulation time | 428364242 ps |
| CPU time | 18.91 seconds |
| Started | Jul 03 07:23:05 PM PDT 24 |
| Finished | Jul 03 07:23:26 PM PDT 24 |
| Peak memory | 574040 kb |
| Host | smart-d9b2c7d8-5253-4837-a25c-490985776926 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1721468041 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_error_and_unmapped_addr .1721468041 |
| Directory | /workspace/6.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_error_random.1976007563 |
| Short name | T2700 |
| Test name | |
| Test status | |
| Simulation time | 2325575586 ps |
| CPU time | 81.94 seconds |
| Started | Jul 03 07:23:00 PM PDT 24 |
| Finished | Jul 03 07:24:23 PM PDT 24 |
| Peak memory | 574096 kb |
| Host | smart-379dcfb6-66e3-41ea-b48e-e5f8b7b1b67d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976007563 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_error_random.1976007563 |
| Directory | /workspace/6.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_random.283344938 |
| Short name | T2724 |
| Test name | |
| Test status | |
| Simulation time | 285973423 ps |
| CPU time | 12.1 seconds |
| Started | Jul 03 07:22:55 PM PDT 24 |
| Finished | Jul 03 07:23:08 PM PDT 24 |
| Peak memory | 574188 kb |
| Host | smart-8c17b54f-514b-46dd-b1d2-bc3d3cde5085 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283344938 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_random.283344938 |
| Directory | /workspace/6.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_random_large_delays.2709319946 |
| Short name | T2056 |
| Test name | |
| Test status | |
| Simulation time | 19501288995 ps |
| CPU time | 205.45 seconds |
| Started | Jul 03 07:22:59 PM PDT 24 |
| Finished | Jul 03 07:26:25 PM PDT 24 |
| Peak memory | 574300 kb |
| Host | smart-0e67a0a3-3c4f-4472-91b1-1a432d416493 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2709319946 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_random_large_delays.2709319946 |
| Directory | /workspace/6.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_random_slow_rsp.2407158648 |
| Short name | T1390 |
| Test name | |
| Test status | |
| Simulation time | 36515698388 ps |
| CPU time | 628.18 seconds |
| Started | Jul 03 07:23:01 PM PDT 24 |
| Finished | Jul 03 07:33:31 PM PDT 24 |
| Peak memory | 574296 kb |
| Host | smart-0d9dd712-6b03-4c72-bbc4-c5f715d83a6d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2407158648 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_random_slow_rsp.2407158648 |
| Directory | /workspace/6.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_random_zero_delays.3910641657 |
| Short name | T1793 |
| Test name | |
| Test status | |
| Simulation time | 289710773 ps |
| CPU time | 27.61 seconds |
| Started | Jul 03 07:22:55 PM PDT 24 |
| Finished | Jul 03 07:23:24 PM PDT 24 |
| Peak memory | 574216 kb |
| Host | smart-847153db-f5a8-4d3b-9762-8cb4346ad677 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3910641657 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_random_zero_dela ys.3910641657 |
| Directory | /workspace/6.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_same_source.2762368711 |
| Short name | T1378 |
| Test name | |
| Test status | |
| Simulation time | 204155751 ps |
| CPU time | 9.01 seconds |
| Started | Jul 03 07:23:04 PM PDT 24 |
| Finished | Jul 03 07:23:14 PM PDT 24 |
| Peak memory | 573032 kb |
| Host | smart-0f99a1f9-a6e1-4a00-bb04-fb62e154fe33 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2762368711 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_same_source.2762368711 |
| Directory | /workspace/6.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_smoke.1926574725 |
| Short name | T1733 |
| Test name | |
| Test status | |
| Simulation time | 213076824 ps |
| CPU time | 8.86 seconds |
| Started | Jul 03 07:23:01 PM PDT 24 |
| Finished | Jul 03 07:23:12 PM PDT 24 |
| Peak memory | 573176 kb |
| Host | smart-c1083341-f6cb-4308-8a76-2594527ce069 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1926574725 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_smoke.1926574725 |
| Directory | /workspace/6.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_smoke_large_delays.41804624 |
| Short name | T1809 |
| Test name | |
| Test status | |
| Simulation time | 8266199404 ps |
| CPU time | 87.11 seconds |
| Started | Jul 03 07:22:55 PM PDT 24 |
| Finished | Jul 03 07:24:23 PM PDT 24 |
| Peak memory | 573032 kb |
| Host | smart-d64e4aac-9777-4096-ab70-97b6e217ecd4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41804624 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_large_delays.41804624 |
| Directory | /workspace/6.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_smoke_slow_rsp.694001722 |
| Short name | T1645 |
| Test name | |
| Test status | |
| Simulation time | 4648340715 ps |
| CPU time | 81.22 seconds |
| Started | Jul 03 07:23:02 PM PDT 24 |
| Finished | Jul 03 07:24:25 PM PDT 24 |
| Peak memory | 573232 kb |
| Host | smart-f87e79ef-dfea-40e1-bbfe-bd574e339183 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694001722 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_slow_rsp.694001722 |
| Directory | /workspace/6.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_smoke_zero_delays.2811139917 |
| Short name | T2152 |
| Test name | |
| Test status | |
| Simulation time | 52493020 ps |
| CPU time | 6.62 seconds |
| Started | Jul 03 07:23:02 PM PDT 24 |
| Finished | Jul 03 07:23:10 PM PDT 24 |
| Peak memory | 572992 kb |
| Host | smart-698b8c9b-6824-4aa7-b873-497c5f5572ee |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811139917 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_zero_delays .2811139917 |
| Directory | /workspace/6.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_stress_all.1457997351 |
| Short name | T447 |
| Test name | |
| Test status | |
| Simulation time | 2231804731 ps |
| CPU time | 204.44 seconds |
| Started | Jul 03 07:23:06 PM PDT 24 |
| Finished | Jul 03 07:26:32 PM PDT 24 |
| Peak memory | 574684 kb |
| Host | smart-43ae85ec-e627-4599-a682-65e096b2ddb4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1457997351 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all.1457997351 |
| Directory | /workspace/6.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_stress_all_with_error.2584624353 |
| Short name | T1665 |
| Test name | |
| Test status | |
| Simulation time | 953349964 ps |
| CPU time | 73.98 seconds |
| Started | Jul 03 07:23:06 PM PDT 24 |
| Finished | Jul 03 07:24:21 PM PDT 24 |
| Peak memory | 573996 kb |
| Host | smart-2c9030c4-41d8-4d94-b14c-117c98f3cb4b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2584624353 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_error.2584624353 |
| Directory | /workspace/6.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_stress_all_with_rand_reset.2813598243 |
| Short name | T2402 |
| Test name | |
| Test status | |
| Simulation time | 6688804451 ps |
| CPU time | 489.44 seconds |
| Started | Jul 03 07:23:05 PM PDT 24 |
| Finished | Jul 03 07:31:16 PM PDT 24 |
| Peak memory | 574704 kb |
| Host | smart-c69076dd-3fe6-4be9-82ce-8b8e9714aa4f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2813598243 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_ with_rand_reset.2813598243 |
| Directory | /workspace/6.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_stress_all_with_reset_error.1358667812 |
| Short name | T1742 |
| Test name | |
| Test status | |
| Simulation time | 14718418310 ps |
| CPU time | 690.62 seconds |
| Started | Jul 03 07:23:05 PM PDT 24 |
| Finished | Jul 03 07:34:37 PM PDT 24 |
| Peak memory | 577160 kb |
| Host | smart-1f6656c4-afaf-4b78-a8c0-b85f73742d33 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358667812 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all _with_reset_error.1358667812 |
| Directory | /workspace/6.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_unmapped_addr.3371691206 |
| Short name | T1777 |
| Test name | |
| Test status | |
| Simulation time | 39631471 ps |
| CPU time | 7.93 seconds |
| Started | Jul 03 07:23:01 PM PDT 24 |
| Finished | Jul 03 07:23:10 PM PDT 24 |
| Peak memory | 573168 kb |
| Host | smart-c5b2510f-08ce-4642-a589-b83142a3402d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3371691206 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_unmapped_addr.3371691206 |
| Directory | /workspace/6.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_access_same_device.1670193109 |
| Short name | T1516 |
| Test name | |
| Test status | |
| Simulation time | 1019429623 ps |
| CPU time | 70.68 seconds |
| Started | Jul 03 07:33:24 PM PDT 24 |
| Finished | Jul 03 07:34:36 PM PDT 24 |
| Peak memory | 574088 kb |
| Host | smart-976151f3-cc90-41bc-8e05-2472ffe1b4c5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1670193109 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_access_same_device .1670193109 |
| Directory | /workspace/60.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_access_same_device_slow_rsp.3265493001 |
| Short name | T2494 |
| Test name | |
| Test status | |
| Simulation time | 116445595603 ps |
| CPU time | 2204.35 seconds |
| Started | Jul 03 07:33:25 PM PDT 24 |
| Finished | Jul 03 08:10:11 PM PDT 24 |
| Peak memory | 574688 kb |
| Host | smart-32bc3d8d-aac1-4f8e-957c-258012d92987 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3265493001 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_access_same_ device_slow_rsp.3265493001 |
| Directory | /workspace/60.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_error_and_unmapped_addr.2232569470 |
| Short name | T1401 |
| Test name | |
| Test status | |
| Simulation time | 292428766 ps |
| CPU time | 33.62 seconds |
| Started | Jul 03 07:33:21 PM PDT 24 |
| Finished | Jul 03 07:33:56 PM PDT 24 |
| Peak memory | 574532 kb |
| Host | smart-4d638486-862c-4b86-b81e-2add970376b1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2232569470 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_error_and_unmapped_add r.2232569470 |
| Directory | /workspace/60.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_error_random.2377534046 |
| Short name | T1333 |
| Test name | |
| Test status | |
| Simulation time | 2554532217 ps |
| CPU time | 92.16 seconds |
| Started | Jul 03 07:33:24 PM PDT 24 |
| Finished | Jul 03 07:34:58 PM PDT 24 |
| Peak memory | 574492 kb |
| Host | smart-91c0dec4-cc60-4140-a78d-71b1599e690f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2377534046 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_error_random.2377534046 |
| Directory | /workspace/60.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_random.306066723 |
| Short name | T566 |
| Test name | |
| Test status | |
| Simulation time | 755208041 ps |
| CPU time | 30.42 seconds |
| Started | Jul 03 07:33:26 PM PDT 24 |
| Finished | Jul 03 07:33:58 PM PDT 24 |
| Peak memory | 574152 kb |
| Host | smart-82aa47b6-a008-464b-ad0f-ce23e2a9b161 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=306066723 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_random.306066723 |
| Directory | /workspace/60.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_random_large_delays.344879272 |
| Short name | T2492 |
| Test name | |
| Test status | |
| Simulation time | 110318629234 ps |
| CPU time | 1147.1 seconds |
| Started | Jul 03 07:33:25 PM PDT 24 |
| Finished | Jul 03 07:52:34 PM PDT 24 |
| Peak memory | 574104 kb |
| Host | smart-3418d111-5299-46e7-8458-3127a37454b2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344879272 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_random_large_delays.344879272 |
| Directory | /workspace/60.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_random_slow_rsp.1613106872 |
| Short name | T2775 |
| Test name | |
| Test status | |
| Simulation time | 54503952204 ps |
| CPU time | 996.49 seconds |
| Started | Jul 03 07:33:24 PM PDT 24 |
| Finished | Jul 03 07:50:02 PM PDT 24 |
| Peak memory | 574300 kb |
| Host | smart-7d835235-30d3-4453-9d1c-3f7121d8801d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1613106872 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_random_slow_rsp.1613106872 |
| Directory | /workspace/60.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_random_zero_delays.2930592974 |
| Short name | T1739 |
| Test name | |
| Test status | |
| Simulation time | 374439350 ps |
| CPU time | 37.42 seconds |
| Started | Jul 03 07:33:23 PM PDT 24 |
| Finished | Jul 03 07:34:02 PM PDT 24 |
| Peak memory | 574228 kb |
| Host | smart-0dc872a3-5090-464c-8475-b5b6f5c61cc0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2930592974 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_random_zero_del ays.2930592974 |
| Directory | /workspace/60.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_same_source.139881465 |
| Short name | T2733 |
| Test name | |
| Test status | |
| Simulation time | 2244279230 ps |
| CPU time | 68.82 seconds |
| Started | Jul 03 07:33:23 PM PDT 24 |
| Finished | Jul 03 07:34:34 PM PDT 24 |
| Peak memory | 574076 kb |
| Host | smart-ec704e5e-42ab-44fd-80c5-4ff2041af0ee |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=139881465 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_same_source.139881465 |
| Directory | /workspace/60.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_smoke.449208727 |
| Short name | T1551 |
| Test name | |
| Test status | |
| Simulation time | 220284207 ps |
| CPU time | 8.53 seconds |
| Started | Jul 03 07:33:19 PM PDT 24 |
| Finished | Jul 03 07:33:28 PM PDT 24 |
| Peak memory | 573108 kb |
| Host | smart-e4fa2a3f-f72d-4e2f-88b4-228d3623007e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=449208727 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_smoke.449208727 |
| Directory | /workspace/60.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_smoke_large_delays.3776087704 |
| Short name | T1652 |
| Test name | |
| Test status | |
| Simulation time | 7723086657 ps |
| CPU time | 82.37 seconds |
| Started | Jul 03 07:33:18 PM PDT 24 |
| Finished | Jul 03 07:34:41 PM PDT 24 |
| Peak memory | 573032 kb |
| Host | smart-6cebe23d-e65f-4a75-ba69-1b173d872540 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3776087704 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_smoke_large_delays.3776087704 |
| Directory | /workspace/60.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_smoke_slow_rsp.155589938 |
| Short name | T2132 |
| Test name | |
| Test status | |
| Simulation time | 5578602730 ps |
| CPU time | 99.11 seconds |
| Started | Jul 03 07:33:27 PM PDT 24 |
| Finished | Jul 03 07:35:07 PM PDT 24 |
| Peak memory | 573120 kb |
| Host | smart-1f9ee1ea-b888-4f69-b3e5-f5a03d103099 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=155589938 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_smoke_slow_rsp.155589938 |
| Directory | /workspace/60.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_smoke_zero_delays.2764390191 |
| Short name | T2382 |
| Test name | |
| Test status | |
| Simulation time | 53985806 ps |
| CPU time | 6.56 seconds |
| Started | Jul 03 07:33:19 PM PDT 24 |
| Finished | Jul 03 07:33:26 PM PDT 24 |
| Peak memory | 573188 kb |
| Host | smart-50fd1469-7005-42bd-8456-8339ec61af5e |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2764390191 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_smoke_zero_delay s.2764390191 |
| Directory | /workspace/60.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_stress_all.172090004 |
| Short name | T597 |
| Test name | |
| Test status | |
| Simulation time | 1517657946 ps |
| CPU time | 52.51 seconds |
| Started | Jul 03 07:33:29 PM PDT 24 |
| Finished | Jul 03 07:34:23 PM PDT 24 |
| Peak memory | 574276 kb |
| Host | smart-0d49f509-0b22-4894-b156-5d26075f6414 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172090004 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_stress_all.172090004 |
| Directory | /workspace/60.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_stress_all_with_error.2716430220 |
| Short name | T2886 |
| Test name | |
| Test status | |
| Simulation time | 6203371484 ps |
| CPU time | 224.84 seconds |
| Started | Jul 03 07:33:29 PM PDT 24 |
| Finished | Jul 03 07:37:15 PM PDT 24 |
| Peak memory | 574672 kb |
| Host | smart-a5065627-901b-4b91-86a7-fb1e699c1e1e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2716430220 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_stress_all_with_error.2716430220 |
| Directory | /workspace/60.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_stress_all_with_rand_reset.3505780282 |
| Short name | T2338 |
| Test name | |
| Test status | |
| Simulation time | 368059775 ps |
| CPU time | 181.48 seconds |
| Started | Jul 03 07:33:32 PM PDT 24 |
| Finished | Jul 03 07:36:34 PM PDT 24 |
| Peak memory | 574664 kb |
| Host | smart-f87dad7d-19c5-4442-a772-b86eda872888 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3505780282 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_stress_all _with_rand_reset.3505780282 |
| Directory | /workspace/60.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_stress_all_with_reset_error.3469595085 |
| Short name | T1868 |
| Test name | |
| Test status | |
| Simulation time | 8269861956 ps |
| CPU time | 471.05 seconds |
| Started | Jul 03 07:33:28 PM PDT 24 |
| Finished | Jul 03 07:41:20 PM PDT 24 |
| Peak memory | 574708 kb |
| Host | smart-818b5fcd-6430-4a22-a29d-00747e926ebb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3469595085 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_stress_al l_with_reset_error.3469595085 |
| Directory | /workspace/60.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_unmapped_addr.4278320836 |
| Short name | T2079 |
| Test name | |
| Test status | |
| Simulation time | 530970714 ps |
| CPU time | 24.05 seconds |
| Started | Jul 03 07:33:22 PM PDT 24 |
| Finished | Jul 03 07:33:47 PM PDT 24 |
| Peak memory | 574260 kb |
| Host | smart-88cefff0-7aba-4708-8269-301ae20ae475 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4278320836 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_unmapped_addr.4278320836 |
| Directory | /workspace/60.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_access_same_device.2643442094 |
| Short name | T1969 |
| Test name | |
| Test status | |
| Simulation time | 1026120942 ps |
| CPU time | 43.49 seconds |
| Started | Jul 03 07:33:36 PM PDT 24 |
| Finished | Jul 03 07:34:20 PM PDT 24 |
| Peak memory | 574128 kb |
| Host | smart-f4bb0e1e-a980-49ba-9015-84f37712686d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2643442094 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_access_same_device .2643442094 |
| Directory | /workspace/61.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_access_same_device_slow_rsp.943327494 |
| Short name | T1915 |
| Test name | |
| Test status | |
| Simulation time | 77326327752 ps |
| CPU time | 1399 seconds |
| Started | Jul 03 07:33:38 PM PDT 24 |
| Finished | Jul 03 07:56:58 PM PDT 24 |
| Peak memory | 574204 kb |
| Host | smart-5013f976-90e7-4fe4-a15e-b6129868f250 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=943327494 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_access_same_d evice_slow_rsp.943327494 |
| Directory | /workspace/61.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_error_and_unmapped_addr.2972297278 |
| Short name | T1600 |
| Test name | |
| Test status | |
| Simulation time | 1003415339 ps |
| CPU time | 40.55 seconds |
| Started | Jul 03 07:33:40 PM PDT 24 |
| Finished | Jul 03 07:34:22 PM PDT 24 |
| Peak memory | 574480 kb |
| Host | smart-a08b204c-9843-4b90-a895-9b23e33b97e7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2972297278 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_error_and_unmapped_add r.2972297278 |
| Directory | /workspace/61.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_error_random.2777949472 |
| Short name | T1920 |
| Test name | |
| Test status | |
| Simulation time | 1799105553 ps |
| CPU time | 65.45 seconds |
| Started | Jul 03 07:33:39 PM PDT 24 |
| Finished | Jul 03 07:34:45 PM PDT 24 |
| Peak memory | 574444 kb |
| Host | smart-147858e3-8222-4921-96ed-41d88681d7b8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777949472 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_error_random.2777949472 |
| Directory | /workspace/61.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_random.920317290 |
| Short name | T1973 |
| Test name | |
| Test status | |
| Simulation time | 551717723 ps |
| CPU time | 46.38 seconds |
| Started | Jul 03 07:33:34 PM PDT 24 |
| Finished | Jul 03 07:34:21 PM PDT 24 |
| Peak memory | 574216 kb |
| Host | smart-e1439ea9-e1d1-4439-9f80-ffba97dbbadc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=920317290 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_random.920317290 |
| Directory | /workspace/61.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_random_large_delays.2629277406 |
| Short name | T1331 |
| Test name | |
| Test status | |
| Simulation time | 28528234203 ps |
| CPU time | 302.05 seconds |
| Started | Jul 03 07:33:34 PM PDT 24 |
| Finished | Jul 03 07:38:36 PM PDT 24 |
| Peak memory | 574284 kb |
| Host | smart-b90944c9-da90-4232-a27f-523d42b427bf |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2629277406 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_random_large_delays.2629277406 |
| Directory | /workspace/61.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_random_slow_rsp.543874148 |
| Short name | T2501 |
| Test name | |
| Test status | |
| Simulation time | 13608664254 ps |
| CPU time | 237.31 seconds |
| Started | Jul 03 07:33:34 PM PDT 24 |
| Finished | Jul 03 07:37:32 PM PDT 24 |
| Peak memory | 574320 kb |
| Host | smart-1ec8da13-4cc1-4f29-8119-77c86f2019e0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=543874148 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_random_slow_rsp.543874148 |
| Directory | /workspace/61.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_random_zero_delays.4058143295 |
| Short name | T1716 |
| Test name | |
| Test status | |
| Simulation time | 166065903 ps |
| CPU time | 18.42 seconds |
| Started | Jul 03 07:33:35 PM PDT 24 |
| Finished | Jul 03 07:33:54 PM PDT 24 |
| Peak memory | 574224 kb |
| Host | smart-6241634b-7c1d-4935-a1cc-a4d71a12e082 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4058143295 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_random_zero_del ays.4058143295 |
| Directory | /workspace/61.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_same_source.2673134015 |
| Short name | T427 |
| Test name | |
| Test status | |
| Simulation time | 331808485 ps |
| CPU time | 13.37 seconds |
| Started | Jul 03 07:33:38 PM PDT 24 |
| Finished | Jul 03 07:33:53 PM PDT 24 |
| Peak memory | 573960 kb |
| Host | smart-978aaf60-b1af-4ee6-ba7c-1fc4051720e0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2673134015 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_same_source.2673134015 |
| Directory | /workspace/61.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_smoke.1106162955 |
| Short name | T2826 |
| Test name | |
| Test status | |
| Simulation time | 52665441 ps |
| CPU time | 6.9 seconds |
| Started | Jul 03 07:33:28 PM PDT 24 |
| Finished | Jul 03 07:33:36 PM PDT 24 |
| Peak memory | 573268 kb |
| Host | smart-ac4720f2-ec01-44d3-a6cf-fbde494b0faf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1106162955 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_smoke.1106162955 |
| Directory | /workspace/61.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_smoke_large_delays.500486620 |
| Short name | T2614 |
| Test name | |
| Test status | |
| Simulation time | 9376843731 ps |
| CPU time | 101.68 seconds |
| Started | Jul 03 07:33:36 PM PDT 24 |
| Finished | Jul 03 07:35:19 PM PDT 24 |
| Peak memory | 574248 kb |
| Host | smart-8d28d2ff-cc2e-415a-bb54-c7011fdfebff |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=500486620 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_smoke_large_delays.500486620 |
| Directory | /workspace/61.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_smoke_slow_rsp.37203146 |
| Short name | T578 |
| Test name | |
| Test status | |
| Simulation time | 4528879695 ps |
| CPU time | 77.23 seconds |
| Started | Jul 03 07:33:31 PM PDT 24 |
| Finished | Jul 03 07:34:50 PM PDT 24 |
| Peak memory | 574188 kb |
| Host | smart-46d94048-302d-465b-9122-89604a8b12a5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37203146 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_smoke_slow_rsp.37203146 |
| Directory | /workspace/61.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_smoke_zero_delays.4109271606 |
| Short name | T1741 |
| Test name | |
| Test status | |
| Simulation time | 53589077 ps |
| CPU time | 6.46 seconds |
| Started | Jul 03 07:33:33 PM PDT 24 |
| Finished | Jul 03 07:33:40 PM PDT 24 |
| Peak memory | 573180 kb |
| Host | smart-583cf568-a2f4-4d5e-a3e7-9afd4de96ed7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4109271606 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_smoke_zero_delay s.4109271606 |
| Directory | /workspace/61.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_stress_all.1661230103 |
| Short name | T438 |
| Test name | |
| Test status | |
| Simulation time | 3168380348 ps |
| CPU time | 111.48 seconds |
| Started | Jul 03 07:33:40 PM PDT 24 |
| Finished | Jul 03 07:35:32 PM PDT 24 |
| Peak memory | 574344 kb |
| Host | smart-ad3474f9-4e53-43a0-9e20-a32f752ee958 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1661230103 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_stress_all.1661230103 |
| Directory | /workspace/61.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_stress_all_with_error.3174006137 |
| Short name | T2229 |
| Test name | |
| Test status | |
| Simulation time | 9026317919 ps |
| CPU time | 308.71 seconds |
| Started | Jul 03 07:33:46 PM PDT 24 |
| Finished | Jul 03 07:38:56 PM PDT 24 |
| Peak memory | 574732 kb |
| Host | smart-b98b47b4-eede-41f6-88d5-7481a4fc41a8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3174006137 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_stress_all_with_error.3174006137 |
| Directory | /workspace/61.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_stress_all_with_rand_reset.1640656652 |
| Short name | T1968 |
| Test name | |
| Test status | |
| Simulation time | 226592720 ps |
| CPU time | 103.84 seconds |
| Started | Jul 03 07:33:41 PM PDT 24 |
| Finished | Jul 03 07:35:25 PM PDT 24 |
| Peak memory | 574680 kb |
| Host | smart-546bd370-36c5-4547-af88-ff50f06376da |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640656652 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_stress_all _with_rand_reset.1640656652 |
| Directory | /workspace/61.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_stress_all_with_reset_error.3101179818 |
| Short name | T767 |
| Test name | |
| Test status | |
| Simulation time | 6478640877 ps |
| CPU time | 631.06 seconds |
| Started | Jul 03 07:33:47 PM PDT 24 |
| Finished | Jul 03 07:44:19 PM PDT 24 |
| Peak memory | 574776 kb |
| Host | smart-108fa4c1-422d-48f6-b6bb-af739948392e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3101179818 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_stress_al l_with_reset_error.3101179818 |
| Directory | /workspace/61.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_unmapped_addr.1793412831 |
| Short name | T2001 |
| Test name | |
| Test status | |
| Simulation time | 1040564709 ps |
| CPU time | 43.33 seconds |
| Started | Jul 03 07:33:46 PM PDT 24 |
| Finished | Jul 03 07:34:31 PM PDT 24 |
| Peak memory | 574252 kb |
| Host | smart-50380c5a-f0bb-403c-a8a6-2d11fab15508 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1793412831 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_unmapped_addr.1793412831 |
| Directory | /workspace/61.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_access_same_device.56479367 |
| Short name | T2710 |
| Test name | |
| Test status | |
| Simulation time | 306108293 ps |
| CPU time | 25.15 seconds |
| Started | Jul 03 07:33:46 PM PDT 24 |
| Finished | Jul 03 07:34:12 PM PDT 24 |
| Peak memory | 574136 kb |
| Host | smart-fc70143b-15b4-4339-8bb5-36b294bd5d46 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56479367 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_access_same_device.56479367 |
| Directory | /workspace/62.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_access_same_device_slow_rsp.3015438280 |
| Short name | T1664 |
| Test name | |
| Test status | |
| Simulation time | 148306123113 ps |
| CPU time | 2956.77 seconds |
| Started | Jul 03 07:33:46 PM PDT 24 |
| Finished | Jul 03 08:23:04 PM PDT 24 |
| Peak memory | 574316 kb |
| Host | smart-2550f31f-f516-45ea-9a51-4143e6b4b67e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3015438280 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_access_same_ device_slow_rsp.3015438280 |
| Directory | /workspace/62.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_error_and_unmapped_addr.2841266491 |
| Short name | T1781 |
| Test name | |
| Test status | |
| Simulation time | 333160255 ps |
| CPU time | 30.59 seconds |
| Started | Jul 03 07:33:47 PM PDT 24 |
| Finished | Jul 03 07:34:18 PM PDT 24 |
| Peak memory | 574056 kb |
| Host | smart-d59d8b54-46e0-42cc-84e6-09009c42e96a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841266491 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_error_and_unmapped_add r.2841266491 |
| Directory | /workspace/62.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_error_random.2074633587 |
| Short name | T1649 |
| Test name | |
| Test status | |
| Simulation time | 310056727 ps |
| CPU time | 23.9 seconds |
| Started | Jul 03 07:33:44 PM PDT 24 |
| Finished | Jul 03 07:34:09 PM PDT 24 |
| Peak memory | 574464 kb |
| Host | smart-d10f3d28-16c6-44ba-b44e-ad61ed010b48 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074633587 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_error_random.2074633587 |
| Directory | /workspace/62.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_random.1217981487 |
| Short name | T2830 |
| Test name | |
| Test status | |
| Simulation time | 1575649709 ps |
| CPU time | 56.96 seconds |
| Started | Jul 03 07:33:38 PM PDT 24 |
| Finished | Jul 03 07:34:35 PM PDT 24 |
| Peak memory | 574088 kb |
| Host | smart-24576252-060b-470b-989f-7280ea7dafb8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1217981487 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_random.1217981487 |
| Directory | /workspace/62.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_random_large_delays.670713040 |
| Short name | T2435 |
| Test name | |
| Test status | |
| Simulation time | 21501783193 ps |
| CPU time | 212.64 seconds |
| Started | Jul 03 07:33:45 PM PDT 24 |
| Finished | Jul 03 07:37:19 PM PDT 24 |
| Peak memory | 574248 kb |
| Host | smart-597be35f-5ba5-4e9d-b990-0219d2397c1d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=670713040 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_random_large_delays.670713040 |
| Directory | /workspace/62.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_random_slow_rsp.1142761923 |
| Short name | T2537 |
| Test name | |
| Test status | |
| Simulation time | 17655836523 ps |
| CPU time | 304.99 seconds |
| Started | Jul 03 07:33:49 PM PDT 24 |
| Finished | Jul 03 07:38:56 PM PDT 24 |
| Peak memory | 574292 kb |
| Host | smart-9cb1acce-ce6f-492a-860b-0d294cd7abe6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1142761923 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_random_slow_rsp.1142761923 |
| Directory | /workspace/62.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_random_zero_delays.3384749054 |
| Short name | T1882 |
| Test name | |
| Test status | |
| Simulation time | 366476411 ps |
| CPU time | 30.88 seconds |
| Started | Jul 03 07:33:43 PM PDT 24 |
| Finished | Jul 03 07:34:14 PM PDT 24 |
| Peak memory | 574220 kb |
| Host | smart-4595419e-e170-48cc-bb89-ae6687387c22 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3384749054 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_random_zero_del ays.3384749054 |
| Directory | /workspace/62.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_same_source.2469545571 |
| Short name | T2166 |
| Test name | |
| Test status | |
| Simulation time | 1780236435 ps |
| CPU time | 58.7 seconds |
| Started | Jul 03 07:33:45 PM PDT 24 |
| Finished | Jul 03 07:34:45 PM PDT 24 |
| Peak memory | 574144 kb |
| Host | smart-887905cc-e20a-46fd-9491-2f207696080c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2469545571 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_same_source.2469545571 |
| Directory | /workspace/62.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_smoke.2616055355 |
| Short name | T1577 |
| Test name | |
| Test status | |
| Simulation time | 213810581 ps |
| CPU time | 9.02 seconds |
| Started | Jul 03 07:33:38 PM PDT 24 |
| Finished | Jul 03 07:33:48 PM PDT 24 |
| Peak memory | 572892 kb |
| Host | smart-19fcb50e-bcf0-4cd4-8b8b-a3c162870130 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2616055355 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_smoke.2616055355 |
| Directory | /workspace/62.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_smoke_large_delays.2194337834 |
| Short name | T1919 |
| Test name | |
| Test status | |
| Simulation time | 9468241819 ps |
| CPU time | 97.12 seconds |
| Started | Jul 03 07:33:43 PM PDT 24 |
| Finished | Jul 03 07:35:21 PM PDT 24 |
| Peak memory | 573032 kb |
| Host | smart-9b8c3391-8c80-4731-ad1a-1b8656311830 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2194337834 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_smoke_large_delays.2194337834 |
| Directory | /workspace/62.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_smoke_slow_rsp.2539775526 |
| Short name | T1870 |
| Test name | |
| Test status | |
| Simulation time | 3014083939 ps |
| CPU time | 53.9 seconds |
| Started | Jul 03 07:33:38 PM PDT 24 |
| Finished | Jul 03 07:34:32 PM PDT 24 |
| Peak memory | 573192 kb |
| Host | smart-78508985-b1e7-4596-8859-292fa7149982 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2539775526 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_smoke_slow_rsp.2539775526 |
| Directory | /workspace/62.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_smoke_zero_delays.2299993040 |
| Short name | T1957 |
| Test name | |
| Test status | |
| Simulation time | 50622745 ps |
| CPU time | 6.62 seconds |
| Started | Jul 03 07:33:40 PM PDT 24 |
| Finished | Jul 03 07:33:47 PM PDT 24 |
| Peak memory | 574168 kb |
| Host | smart-45b7cb8d-9a21-4c65-bc71-17f6429e08b7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2299993040 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_smoke_zero_delay s.2299993040 |
| Directory | /workspace/62.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_stress_all.1036430958 |
| Short name | T2234 |
| Test name | |
| Test status | |
| Simulation time | 601000665 ps |
| CPU time | 45.94 seconds |
| Started | Jul 03 07:33:49 PM PDT 24 |
| Finished | Jul 03 07:34:36 PM PDT 24 |
| Peak memory | 574272 kb |
| Host | smart-7cee263b-d9d3-4bb0-bc38-ef0d9800f09d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1036430958 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_stress_all.1036430958 |
| Directory | /workspace/62.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_stress_all_with_error.2132737203 |
| Short name | T2389 |
| Test name | |
| Test status | |
| Simulation time | 8139509350 ps |
| CPU time | 284.46 seconds |
| Started | Jul 03 07:33:51 PM PDT 24 |
| Finished | Jul 03 07:38:37 PM PDT 24 |
| Peak memory | 574716 kb |
| Host | smart-01a9fc5d-3774-454b-91da-6912fda90ff0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2132737203 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_stress_all_with_error.2132737203 |
| Directory | /workspace/62.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_stress_all_with_rand_reset.2816648513 |
| Short name | T2216 |
| Test name | |
| Test status | |
| Simulation time | 170250423 ps |
| CPU time | 61.42 seconds |
| Started | Jul 03 07:33:54 PM PDT 24 |
| Finished | Jul 03 07:34:57 PM PDT 24 |
| Peak memory | 574668 kb |
| Host | smart-423de273-7840-414e-81d5-da78102a4232 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2816648513 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_stress_all _with_rand_reset.2816648513 |
| Directory | /workspace/62.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_stress_all_with_reset_error.2811983624 |
| Short name | T812 |
| Test name | |
| Test status | |
| Simulation time | 463973049 ps |
| CPU time | 155.99 seconds |
| Started | Jul 03 07:33:54 PM PDT 24 |
| Finished | Jul 03 07:36:31 PM PDT 24 |
| Peak memory | 574712 kb |
| Host | smart-b568c587-7469-4295-bb0c-ada6ad114cc9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811983624 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_stress_al l_with_reset_error.2811983624 |
| Directory | /workspace/62.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_unmapped_addr.3505777402 |
| Short name | T1634 |
| Test name | |
| Test status | |
| Simulation time | 20456104 ps |
| CPU time | 5.81 seconds |
| Started | Jul 03 07:33:45 PM PDT 24 |
| Finished | Jul 03 07:33:52 PM PDT 24 |
| Peak memory | 573128 kb |
| Host | smart-e73e8c7f-064f-43bd-ab0c-aeeb1c66f115 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3505777402 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_unmapped_addr.3505777402 |
| Directory | /workspace/62.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_access_same_device.3148687026 |
| Short name | T2306 |
| Test name | |
| Test status | |
| Simulation time | 1037564207 ps |
| CPU time | 44.75 seconds |
| Started | Jul 03 07:33:55 PM PDT 24 |
| Finished | Jul 03 07:34:41 PM PDT 24 |
| Peak memory | 574184 kb |
| Host | smart-b81df045-6a7c-485c-90eb-e6dd05c619c0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3148687026 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_access_same_device .3148687026 |
| Directory | /workspace/63.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_access_same_device_slow_rsp.1919816500 |
| Short name | T1904 |
| Test name | |
| Test status | |
| Simulation time | 115933525186 ps |
| CPU time | 2168.28 seconds |
| Started | Jul 03 07:33:59 PM PDT 24 |
| Finished | Jul 03 08:10:08 PM PDT 24 |
| Peak memory | 574672 kb |
| Host | smart-69adcc2d-63ad-47e1-b98a-043aecc1c9c7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1919816500 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_access_same_ device_slow_rsp.1919816500 |
| Directory | /workspace/63.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_error_and_unmapped_addr.1561497630 |
| Short name | T1311 |
| Test name | |
| Test status | |
| Simulation time | 343826285 ps |
| CPU time | 32.23 seconds |
| Started | Jul 03 07:33:59 PM PDT 24 |
| Finished | Jul 03 07:34:32 PM PDT 24 |
| Peak memory | 574460 kb |
| Host | smart-6a7e2e8b-05c4-4393-ae11-ebb3f0d64e65 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1561497630 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_error_and_unmapped_add r.1561497630 |
| Directory | /workspace/63.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_error_random.1292582470 |
| Short name | T616 |
| Test name | |
| Test status | |
| Simulation time | 137699506 ps |
| CPU time | 14.67 seconds |
| Started | Jul 03 07:33:55 PM PDT 24 |
| Finished | Jul 03 07:34:11 PM PDT 24 |
| Peak memory | 574440 kb |
| Host | smart-eded688a-ae87-4b98-b4ca-6939ef81c53c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1292582470 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_error_random.1292582470 |
| Directory | /workspace/63.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_random.2577866450 |
| Short name | T1849 |
| Test name | |
| Test status | |
| Simulation time | 1600423668 ps |
| CPU time | 59.81 seconds |
| Started | Jul 03 07:33:58 PM PDT 24 |
| Finished | Jul 03 07:34:59 PM PDT 24 |
| Peak memory | 574056 kb |
| Host | smart-fc8b4eb0-27de-4cda-9225-e2398eded931 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577866450 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_random.2577866450 |
| Directory | /workspace/63.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_random_large_delays.3436373376 |
| Short name | T2317 |
| Test name | |
| Test status | |
| Simulation time | 81542882254 ps |
| CPU time | 896.66 seconds |
| Started | Jul 03 07:33:55 PM PDT 24 |
| Finished | Jul 03 07:48:53 PM PDT 24 |
| Peak memory | 574288 kb |
| Host | smart-24f08ced-fd66-4304-bf1c-94ecd76d8882 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3436373376 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_random_large_delays.3436373376 |
| Directory | /workspace/63.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_random_slow_rsp.1433359764 |
| Short name | T475 |
| Test name | |
| Test status | |
| Simulation time | 39040153559 ps |
| CPU time | 693.16 seconds |
| Started | Jul 03 07:33:56 PM PDT 24 |
| Finished | Jul 03 07:45:30 PM PDT 24 |
| Peak memory | 574212 kb |
| Host | smart-16818502-f1ab-4d15-a1b6-6cc4ad350c01 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1433359764 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_random_slow_rsp.1433359764 |
| Directory | /workspace/63.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_random_zero_delays.144022335 |
| Short name | T2310 |
| Test name | |
| Test status | |
| Simulation time | 300355812 ps |
| CPU time | 29.17 seconds |
| Started | Jul 03 07:33:55 PM PDT 24 |
| Finished | Jul 03 07:34:25 PM PDT 24 |
| Peak memory | 574248 kb |
| Host | smart-889f70ae-56c6-40c4-aace-c2c4865afcf1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=144022335 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_random_zero_dela ys.144022335 |
| Directory | /workspace/63.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_same_source.2930889228 |
| Short name | T2299 |
| Test name | |
| Test status | |
| Simulation time | 74064555 ps |
| CPU time | 8.75 seconds |
| Started | Jul 03 07:33:55 PM PDT 24 |
| Finished | Jul 03 07:34:05 PM PDT 24 |
| Peak memory | 573984 kb |
| Host | smart-693b3b07-bbc5-41ec-a69a-bb89e5c4ca52 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2930889228 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_same_source.2930889228 |
| Directory | /workspace/63.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_smoke.1532466294 |
| Short name | T2856 |
| Test name | |
| Test status | |
| Simulation time | 196719613 ps |
| CPU time | 9.2 seconds |
| Started | Jul 03 07:33:50 PM PDT 24 |
| Finished | Jul 03 07:34:01 PM PDT 24 |
| Peak memory | 574108 kb |
| Host | smart-e2831b77-beef-4ed1-9478-89529953ffac |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1532466294 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_smoke.1532466294 |
| Directory | /workspace/63.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_smoke_large_delays.201972288 |
| Short name | T1709 |
| Test name | |
| Test status | |
| Simulation time | 10472984403 ps |
| CPU time | 102.39 seconds |
| Started | Jul 03 07:33:50 PM PDT 24 |
| Finished | Jul 03 07:35:34 PM PDT 24 |
| Peak memory | 574152 kb |
| Host | smart-2407721c-fd3c-4e22-a795-5e4249293430 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=201972288 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_smoke_large_delays.201972288 |
| Directory | /workspace/63.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_smoke_slow_rsp.2962631233 |
| Short name | T1879 |
| Test name | |
| Test status | |
| Simulation time | 6867225300 ps |
| CPU time | 121.03 seconds |
| Started | Jul 03 07:33:49 PM PDT 24 |
| Finished | Jul 03 07:35:52 PM PDT 24 |
| Peak memory | 573136 kb |
| Host | smart-1c416edd-59ec-4265-b352-5f29a5ff08b8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2962631233 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_smoke_slow_rsp.2962631233 |
| Directory | /workspace/63.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_smoke_zero_delays.1051827729 |
| Short name | T1535 |
| Test name | |
| Test status | |
| Simulation time | 44986588 ps |
| CPU time | 6.19 seconds |
| Started | Jul 03 07:33:52 PM PDT 24 |
| Finished | Jul 03 07:34:00 PM PDT 24 |
| Peak memory | 572936 kb |
| Host | smart-590482e3-7280-475d-b55c-6661f80cb444 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051827729 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_smoke_zero_delay s.1051827729 |
| Directory | /workspace/63.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_stress_all.786675575 |
| Short name | T2600 |
| Test name | |
| Test status | |
| Simulation time | 8830316405 ps |
| CPU time | 337.82 seconds |
| Started | Jul 03 07:33:58 PM PDT 24 |
| Finished | Jul 03 07:39:36 PM PDT 24 |
| Peak memory | 574660 kb |
| Host | smart-79d755ec-b08e-46b9-aced-d21d348a23c8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=786675575 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_stress_all.786675575 |
| Directory | /workspace/63.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_stress_all_with_error.2184064654 |
| Short name | T2652 |
| Test name | |
| Test status | |
| Simulation time | 5581529205 ps |
| CPU time | 199.63 seconds |
| Started | Jul 03 07:34:02 PM PDT 24 |
| Finished | Jul 03 07:37:22 PM PDT 24 |
| Peak memory | 574604 kb |
| Host | smart-ca26e7c6-ed25-4c82-a1b9-8a010ad07221 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2184064654 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_stress_all_with_error.2184064654 |
| Directory | /workspace/63.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_stress_all_with_rand_reset.3206490319 |
| Short name | T2260 |
| Test name | |
| Test status | |
| Simulation time | 507749218 ps |
| CPU time | 178.1 seconds |
| Started | Jul 03 07:34:00 PM PDT 24 |
| Finished | Jul 03 07:36:59 PM PDT 24 |
| Peak memory | 574624 kb |
| Host | smart-298f5db6-47f3-456a-aca5-df625e715e78 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3206490319 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_stress_all _with_rand_reset.3206490319 |
| Directory | /workspace/63.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_stress_all_with_reset_error.3690596515 |
| Short name | T2646 |
| Test name | |
| Test status | |
| Simulation time | 207594407 ps |
| CPU time | 95.87 seconds |
| Started | Jul 03 07:34:00 PM PDT 24 |
| Finished | Jul 03 07:35:37 PM PDT 24 |
| Peak memory | 574644 kb |
| Host | smart-b2abdb2d-7226-4fa4-8ae2-0726d7c04cb7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3690596515 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_stress_al l_with_reset_error.3690596515 |
| Directory | /workspace/63.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_unmapped_addr.959010308 |
| Short name | T552 |
| Test name | |
| Test status | |
| Simulation time | 674834339 ps |
| CPU time | 27.13 seconds |
| Started | Jul 03 07:33:58 PM PDT 24 |
| Finished | Jul 03 07:34:26 PM PDT 24 |
| Peak memory | 574248 kb |
| Host | smart-b4f7dde2-47f2-43e5-980b-3d5c715202ab |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=959010308 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_unmapped_addr.959010308 |
| Directory | /workspace/63.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_access_same_device.2423175889 |
| Short name | T2360 |
| Test name | |
| Test status | |
| Simulation time | 3067622082 ps |
| CPU time | 118.46 seconds |
| Started | Jul 03 07:34:07 PM PDT 24 |
| Finished | Jul 03 07:36:06 PM PDT 24 |
| Peak memory | 574260 kb |
| Host | smart-c353e7ee-b4fb-4e09-add1-3a5833c1d00b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2423175889 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_access_same_device .2423175889 |
| Directory | /workspace/64.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_access_same_device_slow_rsp.3977954550 |
| Short name | T1497 |
| Test name | |
| Test status | |
| Simulation time | 49461921007 ps |
| CPU time | 939.03 seconds |
| Started | Jul 03 07:34:10 PM PDT 24 |
| Finished | Jul 03 07:49:50 PM PDT 24 |
| Peak memory | 574292 kb |
| Host | smart-3edfac7f-8f51-416e-b972-b0af845a6842 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3977954550 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_access_same_ device_slow_rsp.3977954550 |
| Directory | /workspace/64.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_error_and_unmapped_addr.3007130380 |
| Short name | T2352 |
| Test name | |
| Test status | |
| Simulation time | 609642776 ps |
| CPU time | 28.5 seconds |
| Started | Jul 03 07:34:05 PM PDT 24 |
| Finished | Jul 03 07:34:35 PM PDT 24 |
| Peak memory | 574048 kb |
| Host | smart-fb5b1200-5918-44c1-a909-f9fd68738c98 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3007130380 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_error_and_unmapped_add r.3007130380 |
| Directory | /workspace/64.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_error_random.2794313559 |
| Short name | T2243 |
| Test name | |
| Test status | |
| Simulation time | 48298505 ps |
| CPU time | 6.9 seconds |
| Started | Jul 03 07:34:07 PM PDT 24 |
| Finished | Jul 03 07:34:15 PM PDT 24 |
| Peak memory | 573044 kb |
| Host | smart-53b8d768-7d07-4aff-ac20-bb09f307c18a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2794313559 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_error_random.2794313559 |
| Directory | /workspace/64.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_random.2558483393 |
| Short name | T2666 |
| Test name | |
| Test status | |
| Simulation time | 113846865 ps |
| CPU time | 7.46 seconds |
| Started | Jul 03 07:34:03 PM PDT 24 |
| Finished | Jul 03 07:34:11 PM PDT 24 |
| Peak memory | 574088 kb |
| Host | smart-cc97955e-3d66-492f-b121-2974747a3e3d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2558483393 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_random.2558483393 |
| Directory | /workspace/64.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_random_large_delays.517020867 |
| Short name | T2259 |
| Test name | |
| Test status | |
| Simulation time | 43817763276 ps |
| CPU time | 428.2 seconds |
| Started | Jul 03 07:34:08 PM PDT 24 |
| Finished | Jul 03 07:41:16 PM PDT 24 |
| Peak memory | 574320 kb |
| Host | smart-7d69ca1c-3592-41f8-adfc-984dda3f8a70 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=517020867 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_random_large_delays.517020867 |
| Directory | /workspace/64.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_random_slow_rsp.2720846534 |
| Short name | T497 |
| Test name | |
| Test status | |
| Simulation time | 16901996193 ps |
| CPU time | 288.7 seconds |
| Started | Jul 03 07:34:05 PM PDT 24 |
| Finished | Jul 03 07:38:55 PM PDT 24 |
| Peak memory | 574120 kb |
| Host | smart-95d5be2e-ebc7-4a48-870c-c9e1abfe91f3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2720846534 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_random_slow_rsp.2720846534 |
| Directory | /workspace/64.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_random_zero_delays.321381986 |
| Short name | T2722 |
| Test name | |
| Test status | |
| Simulation time | 33101831 ps |
| CPU time | 5.97 seconds |
| Started | Jul 03 07:34:06 PM PDT 24 |
| Finished | Jul 03 07:34:13 PM PDT 24 |
| Peak memory | 574216 kb |
| Host | smart-b2281090-1569-4c21-ab93-1ff1fde19c9b |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321381986 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_random_zero_dela ys.321381986 |
| Directory | /workspace/64.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_same_source.2996771016 |
| Short name | T560 |
| Test name | |
| Test status | |
| Simulation time | 706153683 ps |
| CPU time | 22.83 seconds |
| Started | Jul 03 07:34:06 PM PDT 24 |
| Finished | Jul 03 07:34:30 PM PDT 24 |
| Peak memory | 574148 kb |
| Host | smart-b42279a0-d087-4ecd-8da7-39991d49779f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2996771016 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_same_source.2996771016 |
| Directory | /workspace/64.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_smoke.2017356964 |
| Short name | T1305 |
| Test name | |
| Test status | |
| Simulation time | 228399277 ps |
| CPU time | 9.84 seconds |
| Started | Jul 03 07:34:01 PM PDT 24 |
| Finished | Jul 03 07:34:12 PM PDT 24 |
| Peak memory | 573052 kb |
| Host | smart-15967799-3024-4bc0-8607-444ce6917d6f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2017356964 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_smoke.2017356964 |
| Directory | /workspace/64.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_smoke_large_delays.3116139042 |
| Short name | T1619 |
| Test name | |
| Test status | |
| Simulation time | 6912046854 ps |
| CPU time | 74.81 seconds |
| Started | Jul 03 07:34:00 PM PDT 24 |
| Finished | Jul 03 07:35:16 PM PDT 24 |
| Peak memory | 574152 kb |
| Host | smart-76df7ed9-1dd9-4a55-86cc-520b01b36b29 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3116139042 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_smoke_large_delays.3116139042 |
| Directory | /workspace/64.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_smoke_slow_rsp.982471434 |
| Short name | T1998 |
| Test name | |
| Test status | |
| Simulation time | 7140708759 ps |
| CPU time | 123.24 seconds |
| Started | Jul 03 07:34:02 PM PDT 24 |
| Finished | Jul 03 07:36:06 PM PDT 24 |
| Peak memory | 573212 kb |
| Host | smart-46e61ffd-fc5f-405c-be93-6358965cf2f2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=982471434 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_smoke_slow_rsp.982471434 |
| Directory | /workspace/64.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_smoke_zero_delays.1091412211 |
| Short name | T1424 |
| Test name | |
| Test status | |
| Simulation time | 41457438 ps |
| CPU time | 6.01 seconds |
| Started | Jul 03 07:33:59 PM PDT 24 |
| Finished | Jul 03 07:34:06 PM PDT 24 |
| Peak memory | 573992 kb |
| Host | smart-b41fbc7a-91ae-4b18-ab16-71480c03d550 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091412211 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_smoke_zero_delay s.1091412211 |
| Directory | /workspace/64.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_stress_all_with_error.1837693503 |
| Short name | T2661 |
| Test name | |
| Test status | |
| Simulation time | 13710096190 ps |
| CPU time | 462.89 seconds |
| Started | Jul 03 07:34:18 PM PDT 24 |
| Finished | Jul 03 07:42:02 PM PDT 24 |
| Peak memory | 574800 kb |
| Host | smart-9c853a1d-b742-4f02-b61f-d54a6941877a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1837693503 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_stress_all_with_error.1837693503 |
| Directory | /workspace/64.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_stress_all_with_rand_reset.513424525 |
| Short name | T1747 |
| Test name | |
| Test status | |
| Simulation time | 527450458 ps |
| CPU time | 209.42 seconds |
| Started | Jul 03 07:34:12 PM PDT 24 |
| Finished | Jul 03 07:37:42 PM PDT 24 |
| Peak memory | 574644 kb |
| Host | smart-9498e8db-f5b0-4919-8617-155bc45dcf73 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=513424525 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_stress_all_ with_rand_reset.513424525 |
| Directory | /workspace/64.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_stress_all_with_reset_error.356510317 |
| Short name | T2729 |
| Test name | |
| Test status | |
| Simulation time | 182632979 ps |
| CPU time | 67.5 seconds |
| Started | Jul 03 07:34:13 PM PDT 24 |
| Finished | Jul 03 07:35:21 PM PDT 24 |
| Peak memory | 574628 kb |
| Host | smart-8f61116c-79f9-40e7-a6f3-d5141e1ddc71 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=356510317 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_stress_all _with_reset_error.356510317 |
| Directory | /workspace/64.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_unmapped_addr.3558431577 |
| Short name | T2447 |
| Test name | |
| Test status | |
| Simulation time | 299996158 ps |
| CPU time | 38.79 seconds |
| Started | Jul 03 07:34:08 PM PDT 24 |
| Finished | Jul 03 07:34:48 PM PDT 24 |
| Peak memory | 574088 kb |
| Host | smart-25a425e4-f964-40fd-902a-6acd94a37de1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3558431577 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_unmapped_addr.3558431577 |
| Directory | /workspace/64.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_access_same_device.553407276 |
| Short name | T790 |
| Test name | |
| Test status | |
| Simulation time | 1249759669 ps |
| CPU time | 49.33 seconds |
| Started | Jul 03 07:34:18 PM PDT 24 |
| Finished | Jul 03 07:35:08 PM PDT 24 |
| Peak memory | 574088 kb |
| Host | smart-090df218-0703-44b7-983f-546cbd497d2f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=553407276 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_access_same_device. 553407276 |
| Directory | /workspace/65.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_access_same_device_slow_rsp.1520324102 |
| Short name | T1526 |
| Test name | |
| Test status | |
| Simulation time | 141727924550 ps |
| CPU time | 2674.42 seconds |
| Started | Jul 03 07:34:18 PM PDT 24 |
| Finished | Jul 03 08:18:54 PM PDT 24 |
| Peak memory | 574212 kb |
| Host | smart-d5cd7505-d797-4044-a474-2e44ded0b4bb |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1520324102 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_access_same_ device_slow_rsp.1520324102 |
| Directory | /workspace/65.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_error_and_unmapped_addr.9008280 |
| Short name | T1857 |
| Test name | |
| Test status | |
| Simulation time | 83215554 ps |
| CPU time | 11.82 seconds |
| Started | Jul 03 07:34:16 PM PDT 24 |
| Finished | Jul 03 07:34:28 PM PDT 24 |
| Peak memory | 574500 kb |
| Host | smart-1dcb5510-cf56-4cf4-b400-66b752e3c535 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9008280 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_error_and_unmapped_addr.9008280 |
| Directory | /workspace/65.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_error_random.244288930 |
| Short name | T2186 |
| Test name | |
| Test status | |
| Simulation time | 2413637559 ps |
| CPU time | 76.07 seconds |
| Started | Jul 03 07:34:16 PM PDT 24 |
| Finished | Jul 03 07:35:33 PM PDT 24 |
| Peak memory | 574504 kb |
| Host | smart-2b8bf356-88bf-41b4-a7fd-76f5d7d8107e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=244288930 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_error_random.244288930 |
| Directory | /workspace/65.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_random.1158820792 |
| Short name | T1705 |
| Test name | |
| Test status | |
| Simulation time | 224433539 ps |
| CPU time | 22.09 seconds |
| Started | Jul 03 07:34:10 PM PDT 24 |
| Finished | Jul 03 07:34:33 PM PDT 24 |
| Peak memory | 574104 kb |
| Host | smart-9d398c10-4cea-4a29-ae22-de60f450d28a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1158820792 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_random.1158820792 |
| Directory | /workspace/65.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_random_large_delays.596459494 |
| Short name | T2375 |
| Test name | |
| Test status | |
| Simulation time | 102907542299 ps |
| CPU time | 1058.95 seconds |
| Started | Jul 03 07:34:13 PM PDT 24 |
| Finished | Jul 03 07:51:52 PM PDT 24 |
| Peak memory | 574092 kb |
| Host | smart-7d21564a-d1a2-4f0b-9157-0b5993e6e5ca |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=596459494 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_random_large_delays.596459494 |
| Directory | /workspace/65.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_random_slow_rsp.1349600214 |
| Short name | T1584 |
| Test name | |
| Test status | |
| Simulation time | 42143009173 ps |
| CPU time | 767.78 seconds |
| Started | Jul 03 07:34:12 PM PDT 24 |
| Finished | Jul 03 07:47:01 PM PDT 24 |
| Peak memory | 574328 kb |
| Host | smart-d7b6feeb-cdf1-4ff6-8398-d5ca8e275c72 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1349600214 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_random_slow_rsp.1349600214 |
| Directory | /workspace/65.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_random_zero_delays.1039260697 |
| Short name | T2424 |
| Test name | |
| Test status | |
| Simulation time | 386552742 ps |
| CPU time | 33.13 seconds |
| Started | Jul 03 07:34:15 PM PDT 24 |
| Finished | Jul 03 07:34:49 PM PDT 24 |
| Peak memory | 574180 kb |
| Host | smart-23f35a45-8fc4-499f-a67b-bf2f7aacd246 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1039260697 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_random_zero_del ays.1039260697 |
| Directory | /workspace/65.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_same_source.3330864049 |
| Short name | T2096 |
| Test name | |
| Test status | |
| Simulation time | 95606279 ps |
| CPU time | 9.36 seconds |
| Started | Jul 03 07:34:15 PM PDT 24 |
| Finished | Jul 03 07:34:25 PM PDT 24 |
| Peak memory | 574120 kb |
| Host | smart-40bcde26-26ef-41b1-a41c-a508fd1aa483 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3330864049 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_same_source.3330864049 |
| Directory | /workspace/65.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_smoke.4179027993 |
| Short name | T2781 |
| Test name | |
| Test status | |
| Simulation time | 150271416 ps |
| CPU time | 7.76 seconds |
| Started | Jul 03 07:34:13 PM PDT 24 |
| Finished | Jul 03 07:34:22 PM PDT 24 |
| Peak memory | 573136 kb |
| Host | smart-bc8b71d8-c51d-47c3-92db-800f246529d1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4179027993 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_smoke.4179027993 |
| Directory | /workspace/65.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_smoke_large_delays.583786247 |
| Short name | T2650 |
| Test name | |
| Test status | |
| Simulation time | 6102825378 ps |
| CPU time | 59.43 seconds |
| Started | Jul 03 07:34:12 PM PDT 24 |
| Finished | Jul 03 07:35:12 PM PDT 24 |
| Peak memory | 573200 kb |
| Host | smart-742cb079-db81-4d13-9ceb-f1d99d54f7c6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=583786247 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_smoke_large_delays.583786247 |
| Directory | /workspace/65.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_smoke_slow_rsp.3935011094 |
| Short name | T1368 |
| Test name | |
| Test status | |
| Simulation time | 5270454288 ps |
| CPU time | 87.02 seconds |
| Started | Jul 03 07:34:15 PM PDT 24 |
| Finished | Jul 03 07:35:43 PM PDT 24 |
| Peak memory | 574024 kb |
| Host | smart-5c3d7d41-54b7-42d8-b21f-087542fcfb6e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3935011094 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_smoke_slow_rsp.3935011094 |
| Directory | /workspace/65.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_smoke_zero_delays.3515681956 |
| Short name | T1491 |
| Test name | |
| Test status | |
| Simulation time | 43178813 ps |
| CPU time | 5.93 seconds |
| Started | Jul 03 07:34:10 PM PDT 24 |
| Finished | Jul 03 07:34:17 PM PDT 24 |
| Peak memory | 574192 kb |
| Host | smart-3b7af696-05cd-4dad-8fd8-fb01c02f1b7d |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3515681956 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_smoke_zero_delay s.3515681956 |
| Directory | /workspace/65.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_stress_all.4121971156 |
| Short name | T1941 |
| Test name | |
| Test status | |
| Simulation time | 2104849377 ps |
| CPU time | 157.79 seconds |
| Started | Jul 03 07:34:23 PM PDT 24 |
| Finished | Jul 03 07:37:02 PM PDT 24 |
| Peak memory | 574208 kb |
| Host | smart-d3135d4d-19b3-40df-a930-0f5c418f7443 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4121971156 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_stress_all.4121971156 |
| Directory | /workspace/65.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_stress_all_with_error.4213086665 |
| Short name | T1927 |
| Test name | |
| Test status | |
| Simulation time | 1545870988 ps |
| CPU time | 57.67 seconds |
| Started | Jul 03 07:34:23 PM PDT 24 |
| Finished | Jul 03 07:35:22 PM PDT 24 |
| Peak memory | 574480 kb |
| Host | smart-846a0e94-0cd6-4d84-adf3-1438b59a4b52 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4213086665 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_stress_all_with_error.4213086665 |
| Directory | /workspace/65.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_stress_all_with_reset_error.2055774948 |
| Short name | T1523 |
| Test name | |
| Test status | |
| Simulation time | 5036242579 ps |
| CPU time | 374.16 seconds |
| Started | Jul 03 07:34:21 PM PDT 24 |
| Finished | Jul 03 07:40:36 PM PDT 24 |
| Peak memory | 574688 kb |
| Host | smart-da84ad73-af62-4b50-92ba-52bf3e21f1ed |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2055774948 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_stress_al l_with_reset_error.2055774948 |
| Directory | /workspace/65.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_unmapped_addr.1848634027 |
| Short name | T1942 |
| Test name | |
| Test status | |
| Simulation time | 513022263 ps |
| CPU time | 22.73 seconds |
| Started | Jul 03 07:34:16 PM PDT 24 |
| Finished | Jul 03 07:34:40 PM PDT 24 |
| Peak memory | 574220 kb |
| Host | smart-8cd39be8-0169-4189-8493-3ec9fde1a52a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1848634027 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_unmapped_addr.1848634027 |
| Directory | /workspace/65.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_access_same_device.2115576996 |
| Short name | T2639 |
| Test name | |
| Test status | |
| Simulation time | 119546712 ps |
| CPU time | 13.64 seconds |
| Started | Jul 03 07:34:25 PM PDT 24 |
| Finished | Jul 03 07:34:39 PM PDT 24 |
| Peak memory | 574160 kb |
| Host | smart-c1629546-9431-4597-9051-2277ff15383c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2115576996 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_access_same_device .2115576996 |
| Directory | /workspace/66.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_access_same_device_slow_rsp.934632786 |
| Short name | T1453 |
| Test name | |
| Test status | |
| Simulation time | 10237084424 ps |
| CPU time | 169.36 seconds |
| Started | Jul 03 07:34:25 PM PDT 24 |
| Finished | Jul 03 07:37:15 PM PDT 24 |
| Peak memory | 573204 kb |
| Host | smart-c7e83800-b78f-4423-94d7-48b4fea47f2e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=934632786 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_access_same_d evice_slow_rsp.934632786 |
| Directory | /workspace/66.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_error_and_unmapped_addr.2985442132 |
| Short name | T2333 |
| Test name | |
| Test status | |
| Simulation time | 252424448 ps |
| CPU time | 26.62 seconds |
| Started | Jul 03 07:34:28 PM PDT 24 |
| Finished | Jul 03 07:34:56 PM PDT 24 |
| Peak memory | 574456 kb |
| Host | smart-967a3729-9a6a-4688-876f-9224f5a544c8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2985442132 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_error_and_unmapped_add r.2985442132 |
| Directory | /workspace/66.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_error_random.2049962375 |
| Short name | T1320 |
| Test name | |
| Test status | |
| Simulation time | 2360831645 ps |
| CPU time | 92.81 seconds |
| Started | Jul 03 07:34:25 PM PDT 24 |
| Finished | Jul 03 07:35:59 PM PDT 24 |
| Peak memory | 574556 kb |
| Host | smart-54dd0f04-ca9b-493c-9756-231ac23daae0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2049962375 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_error_random.2049962375 |
| Directory | /workspace/66.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_random.1508920762 |
| Short name | T2701 |
| Test name | |
| Test status | |
| Simulation time | 601469177 ps |
| CPU time | 52.62 seconds |
| Started | Jul 03 07:34:22 PM PDT 24 |
| Finished | Jul 03 07:35:15 PM PDT 24 |
| Peak memory | 573972 kb |
| Host | smart-fc0da1b2-bd9a-4f7b-a153-aa615758399e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1508920762 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_random.1508920762 |
| Directory | /workspace/66.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_random_large_delays.3162467632 |
| Short name | T1394 |
| Test name | |
| Test status | |
| Simulation time | 76829333166 ps |
| CPU time | 831.12 seconds |
| Started | Jul 03 07:34:23 PM PDT 24 |
| Finished | Jul 03 07:48:15 PM PDT 24 |
| Peak memory | 574116 kb |
| Host | smart-af92daa4-aebb-4d7f-a457-443b0dfc770e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3162467632 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_random_large_delays.3162467632 |
| Directory | /workspace/66.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_random_slow_rsp.1654426516 |
| Short name | T2683 |
| Test name | |
| Test status | |
| Simulation time | 66492459042 ps |
| CPU time | 1147.56 seconds |
| Started | Jul 03 07:34:23 PM PDT 24 |
| Finished | Jul 03 07:53:31 PM PDT 24 |
| Peak memory | 574164 kb |
| Host | smart-1f6fe0d1-9c5f-4fbe-922e-1b0c0b37caeb |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1654426516 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_random_slow_rsp.1654426516 |
| Directory | /workspace/66.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_random_zero_delays.3397712557 |
| Short name | T1887 |
| Test name | |
| Test status | |
| Simulation time | 74057360 ps |
| CPU time | 9.83 seconds |
| Started | Jul 03 07:34:22 PM PDT 24 |
| Finished | Jul 03 07:34:33 PM PDT 24 |
| Peak memory | 574040 kb |
| Host | smart-1e8aa36f-a2d0-402d-b57c-76a5a53c183e |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3397712557 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_random_zero_del ays.3397712557 |
| Directory | /workspace/66.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_same_source.1840158885 |
| Short name | T1542 |
| Test name | |
| Test status | |
| Simulation time | 549920518 ps |
| CPU time | 39.62 seconds |
| Started | Jul 03 07:34:23 PM PDT 24 |
| Finished | Jul 03 07:35:03 PM PDT 24 |
| Peak memory | 574116 kb |
| Host | smart-7685ec96-b8a5-46c8-8409-1ab836efd624 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1840158885 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_same_source.1840158885 |
| Directory | /workspace/66.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_smoke.1504664251 |
| Short name | T2478 |
| Test name | |
| Test status | |
| Simulation time | 41515593 ps |
| CPU time | 5.88 seconds |
| Started | Jul 03 07:34:17 PM PDT 24 |
| Finished | Jul 03 07:34:23 PM PDT 24 |
| Peak memory | 573076 kb |
| Host | smart-773370ed-6bdc-4316-a4e2-c72f908d710f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1504664251 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_smoke.1504664251 |
| Directory | /workspace/66.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_smoke_large_delays.6364822 |
| Short name | T1985 |
| Test name | |
| Test status | |
| Simulation time | 7911678533 ps |
| CPU time | 85.9 seconds |
| Started | Jul 03 07:34:22 PM PDT 24 |
| Finished | Jul 03 07:35:48 PM PDT 24 |
| Peak memory | 574312 kb |
| Host | smart-f2eac6c9-184d-4545-8e18-2bb97c66ddc9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6364822 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_smoke_large_delays.6364822 |
| Directory | /workspace/66.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_smoke_slow_rsp.1308352270 |
| Short name | T1466 |
| Test name | |
| Test status | |
| Simulation time | 6175290460 ps |
| CPU time | 99.31 seconds |
| Started | Jul 03 07:34:20 PM PDT 24 |
| Finished | Jul 03 07:36:00 PM PDT 24 |
| Peak memory | 574192 kb |
| Host | smart-e25c6794-5aff-4c05-97c4-d9113cea1e2d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1308352270 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_smoke_slow_rsp.1308352270 |
| Directory | /workspace/66.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_smoke_zero_delays.398767519 |
| Short name | T2823 |
| Test name | |
| Test status | |
| Simulation time | 38833017 ps |
| CPU time | 5.75 seconds |
| Started | Jul 03 07:34:23 PM PDT 24 |
| Finished | Jul 03 07:34:30 PM PDT 24 |
| Peak memory | 574084 kb |
| Host | smart-17fa04e6-31b7-4695-b4b4-c641cf06da90 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=398767519 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_smoke_zero_delays .398767519 |
| Directory | /workspace/66.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_stress_all.3991449447 |
| Short name | T2684 |
| Test name | |
| Test status | |
| Simulation time | 5870970604 ps |
| CPU time | 209.72 seconds |
| Started | Jul 03 07:34:28 PM PDT 24 |
| Finished | Jul 03 07:37:58 PM PDT 24 |
| Peak memory | 574696 kb |
| Host | smart-bf195be0-4b2f-45f7-a08d-fb217fb23bff |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3991449447 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_stress_all.3991449447 |
| Directory | /workspace/66.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_stress_all_with_error.340371514 |
| Short name | T2296 |
| Test name | |
| Test status | |
| Simulation time | 6692383510 ps |
| CPU time | 223.83 seconds |
| Started | Jul 03 07:34:28 PM PDT 24 |
| Finished | Jul 03 07:38:13 PM PDT 24 |
| Peak memory | 574676 kb |
| Host | smart-c8e4f3b5-698e-40b8-9601-a7b97abfdedb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=340371514 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_stress_all_with_error.340371514 |
| Directory | /workspace/66.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_stress_all_with_rand_reset.4170659893 |
| Short name | T2513 |
| Test name | |
| Test status | |
| Simulation time | 6436656058 ps |
| CPU time | 307.28 seconds |
| Started | Jul 03 07:34:27 PM PDT 24 |
| Finished | Jul 03 07:39:36 PM PDT 24 |
| Peak memory | 574740 kb |
| Host | smart-04a8d1d5-11e3-46bf-a42f-573b46969327 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4170659893 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_stress_all _with_rand_reset.4170659893 |
| Directory | /workspace/66.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_unmapped_addr.429582379 |
| Short name | T1397 |
| Test name | |
| Test status | |
| Simulation time | 23595360 ps |
| CPU time | 5.81 seconds |
| Started | Jul 03 07:34:26 PM PDT 24 |
| Finished | Jul 03 07:34:32 PM PDT 24 |
| Peak memory | 573116 kb |
| Host | smart-6e1d93a3-7efb-4d45-a1e8-3b0a28b23ab8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=429582379 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_unmapped_addr.429582379 |
| Directory | /workspace/66.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_access_same_device.3503879714 |
| Short name | T2059 |
| Test name | |
| Test status | |
| Simulation time | 2338318643 ps |
| CPU time | 93.87 seconds |
| Started | Jul 03 07:34:35 PM PDT 24 |
| Finished | Jul 03 07:36:09 PM PDT 24 |
| Peak memory | 574188 kb |
| Host | smart-2ad125af-2c84-49f3-a434-7df1809bd9ba |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3503879714 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_access_same_device .3503879714 |
| Directory | /workspace/67.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_access_same_device_slow_rsp.788911994 |
| Short name | T2055 |
| Test name | |
| Test status | |
| Simulation time | 36147976934 ps |
| CPU time | 613.53 seconds |
| Started | Jul 03 07:34:30 PM PDT 24 |
| Finished | Jul 03 07:44:44 PM PDT 24 |
| Peak memory | 574084 kb |
| Host | smart-3f67b28a-c8e6-49ec-b752-abbecdc2b665 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=788911994 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_access_same_d evice_slow_rsp.788911994 |
| Directory | /workspace/67.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_error_and_unmapped_addr.4140918395 |
| Short name | T2428 |
| Test name | |
| Test status | |
| Simulation time | 230151617 ps |
| CPU time | 27.64 seconds |
| Started | Jul 03 07:34:31 PM PDT 24 |
| Finished | Jul 03 07:34:59 PM PDT 24 |
| Peak memory | 574428 kb |
| Host | smart-7bddce93-c6eb-4da7-9801-79d42befda79 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140918395 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_error_and_unmapped_add r.4140918395 |
| Directory | /workspace/67.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_error_random.2277269181 |
| Short name | T2524 |
| Test name | |
| Test status | |
| Simulation time | 487782650 ps |
| CPU time | 18.09 seconds |
| Started | Jul 03 07:34:31 PM PDT 24 |
| Finished | Jul 03 07:34:49 PM PDT 24 |
| Peak memory | 574412 kb |
| Host | smart-48928143-0015-45e9-bf25-0ecaca20c141 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2277269181 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_error_random.2277269181 |
| Directory | /workspace/67.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_random.657962134 |
| Short name | T2521 |
| Test name | |
| Test status | |
| Simulation time | 730762215 ps |
| CPU time | 27.65 seconds |
| Started | Jul 03 07:34:26 PM PDT 24 |
| Finished | Jul 03 07:34:54 PM PDT 24 |
| Peak memory | 574108 kb |
| Host | smart-3f6f9087-a887-4141-a2bf-e1bdba5bbb3b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657962134 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_random.657962134 |
| Directory | /workspace/67.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_random_large_delays.3701507162 |
| Short name | T2370 |
| Test name | |
| Test status | |
| Simulation time | 109920623087 ps |
| CPU time | 1192.98 seconds |
| Started | Jul 03 07:34:30 PM PDT 24 |
| Finished | Jul 03 07:54:24 PM PDT 24 |
| Peak memory | 574020 kb |
| Host | smart-89c5ca49-c64c-470c-829c-d04a036fed84 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3701507162 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_random_large_delays.3701507162 |
| Directory | /workspace/67.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_random_slow_rsp.3526131752 |
| Short name | T2595 |
| Test name | |
| Test status | |
| Simulation time | 48728034462 ps |
| CPU time | 839.08 seconds |
| Started | Jul 03 07:34:29 PM PDT 24 |
| Finished | Jul 03 07:48:29 PM PDT 24 |
| Peak memory | 574340 kb |
| Host | smart-ba4318ff-934d-413e-8d4a-f18eb7ab68ab |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3526131752 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_random_slow_rsp.3526131752 |
| Directory | /workspace/67.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_random_zero_delays.1263177431 |
| Short name | T2131 |
| Test name | |
| Test status | |
| Simulation time | 137741478 ps |
| CPU time | 14.15 seconds |
| Started | Jul 03 07:34:26 PM PDT 24 |
| Finished | Jul 03 07:34:41 PM PDT 24 |
| Peak memory | 574224 kb |
| Host | smart-9a11ef85-67b2-437a-8768-ed2de1d0db73 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1263177431 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_random_zero_del ays.1263177431 |
| Directory | /workspace/67.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_same_source.4274595906 |
| Short name | T1758 |
| Test name | |
| Test status | |
| Simulation time | 316731620 ps |
| CPU time | 24.97 seconds |
| Started | Jul 03 07:34:30 PM PDT 24 |
| Finished | Jul 03 07:34:55 PM PDT 24 |
| Peak memory | 573976 kb |
| Host | smart-21196944-0970-471a-bfa7-ff986abb61c0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4274595906 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_same_source.4274595906 |
| Directory | /workspace/67.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_smoke.2983954219 |
| Short name | T2084 |
| Test name | |
| Test status | |
| Simulation time | 47597732 ps |
| CPU time | 6.63 seconds |
| Started | Jul 03 07:34:27 PM PDT 24 |
| Finished | Jul 03 07:34:35 PM PDT 24 |
| Peak memory | 572912 kb |
| Host | smart-17530dc2-2843-4f22-98d5-cd9070c1fa6f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2983954219 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_smoke.2983954219 |
| Directory | /workspace/67.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_smoke_large_delays.1321459302 |
| Short name | T2420 |
| Test name | |
| Test status | |
| Simulation time | 4888148216 ps |
| CPU time | 48.65 seconds |
| Started | Jul 03 07:34:26 PM PDT 24 |
| Finished | Jul 03 07:35:15 PM PDT 24 |
| Peak memory | 574052 kb |
| Host | smart-f8d27c34-42ae-4707-9979-81497cbc1208 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1321459302 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_smoke_large_delays.1321459302 |
| Directory | /workspace/67.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_smoke_slow_rsp.2107714395 |
| Short name | T1786 |
| Test name | |
| Test status | |
| Simulation time | 6102126252 ps |
| CPU time | 102.5 seconds |
| Started | Jul 03 07:34:27 PM PDT 24 |
| Finished | Jul 03 07:36:11 PM PDT 24 |
| Peak memory | 572996 kb |
| Host | smart-1f9e5131-31e2-443e-a2be-fb1b78e5b92c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2107714395 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_smoke_slow_rsp.2107714395 |
| Directory | /workspace/67.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_smoke_zero_delays.3091377432 |
| Short name | T2473 |
| Test name | |
| Test status | |
| Simulation time | 42741819 ps |
| CPU time | 6.41 seconds |
| Started | Jul 03 07:34:26 PM PDT 24 |
| Finished | Jul 03 07:34:33 PM PDT 24 |
| Peak memory | 574068 kb |
| Host | smart-48949351-15a1-4876-9cea-7e99e2fb8a29 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3091377432 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_smoke_zero_delay s.3091377432 |
| Directory | /workspace/67.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_stress_all.2773023686 |
| Short name | T2891 |
| Test name | |
| Test status | |
| Simulation time | 17764969862 ps |
| CPU time | 779.44 seconds |
| Started | Jul 03 07:34:36 PM PDT 24 |
| Finished | Jul 03 07:47:37 PM PDT 24 |
| Peak memory | 574400 kb |
| Host | smart-87cdc034-9121-4b07-89db-cc0a91d0bc27 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2773023686 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_stress_all.2773023686 |
| Directory | /workspace/67.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_stress_all_with_error.653655582 |
| Short name | T1357 |
| Test name | |
| Test status | |
| Simulation time | 497235072 ps |
| CPU time | 35.94 seconds |
| Started | Jul 03 07:34:37 PM PDT 24 |
| Finished | Jul 03 07:35:14 PM PDT 24 |
| Peak memory | 574472 kb |
| Host | smart-14486ea2-6642-4e4f-a69d-8d3a888594ec |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=653655582 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_stress_all_with_error.653655582 |
| Directory | /workspace/67.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_stress_all_with_rand_reset.1453935350 |
| Short name | T805 |
| Test name | |
| Test status | |
| Simulation time | 983313263 ps |
| CPU time | 335.34 seconds |
| Started | Jul 03 07:34:37 PM PDT 24 |
| Finished | Jul 03 07:40:13 PM PDT 24 |
| Peak memory | 574792 kb |
| Host | smart-b7c11c0d-97e6-40eb-bddb-56aba27aad0c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1453935350 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_stress_all _with_rand_reset.1453935350 |
| Directory | /workspace/67.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_stress_all_with_reset_error.3686420081 |
| Short name | T1802 |
| Test name | |
| Test status | |
| Simulation time | 13849282016 ps |
| CPU time | 685.76 seconds |
| Started | Jul 03 07:34:37 PM PDT 24 |
| Finished | Jul 03 07:46:04 PM PDT 24 |
| Peak memory | 581088 kb |
| Host | smart-f802cf59-fdd5-4bb7-810e-924953aedf8e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3686420081 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_stress_al l_with_reset_error.3686420081 |
| Directory | /workspace/67.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_unmapped_addr.2836570840 |
| Short name | T450 |
| Test name | |
| Test status | |
| Simulation time | 232791179 ps |
| CPU time | 23.23 seconds |
| Started | Jul 03 07:34:33 PM PDT 24 |
| Finished | Jul 03 07:34:57 PM PDT 24 |
| Peak memory | 574348 kb |
| Host | smart-d6fdf9f3-b2e5-4613-a29e-85aac44f8ab9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2836570840 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_unmapped_addr.2836570840 |
| Directory | /workspace/67.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_access_same_device.1801219533 |
| Short name | T1811 |
| Test name | |
| Test status | |
| Simulation time | 531435435 ps |
| CPU time | 17.67 seconds |
| Started | Jul 03 07:34:42 PM PDT 24 |
| Finished | Jul 03 07:35:00 PM PDT 24 |
| Peak memory | 574108 kb |
| Host | smart-ec4a9e86-b821-45a9-97f7-e83e2a6b376d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1801219533 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_access_same_device .1801219533 |
| Directory | /workspace/68.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_access_same_device_slow_rsp.2185810629 |
| Short name | T495 |
| Test name | |
| Test status | |
| Simulation time | 84194843103 ps |
| CPU time | 1520.33 seconds |
| Started | Jul 03 07:34:43 PM PDT 24 |
| Finished | Jul 03 08:00:04 PM PDT 24 |
| Peak memory | 574288 kb |
| Host | smart-737ea6a5-761a-4ff1-b764-f0a34e337b5b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2185810629 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_access_same_ device_slow_rsp.2185810629 |
| Directory | /workspace/68.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_error_and_unmapped_addr.1771649213 |
| Short name | T2176 |
| Test name | |
| Test status | |
| Simulation time | 902660349 ps |
| CPU time | 35.54 seconds |
| Started | Jul 03 07:34:41 PM PDT 24 |
| Finished | Jul 03 07:35:17 PM PDT 24 |
| Peak memory | 574468 kb |
| Host | smart-4a421f79-c08d-4255-966f-8931d1ae24c2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1771649213 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_error_and_unmapped_add r.1771649213 |
| Directory | /workspace/68.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_error_random.1869381002 |
| Short name | T2877 |
| Test name | |
| Test status | |
| Simulation time | 495730396 ps |
| CPU time | 41.92 seconds |
| Started | Jul 03 07:34:39 PM PDT 24 |
| Finished | Jul 03 07:35:21 PM PDT 24 |
| Peak memory | 574540 kb |
| Host | smart-2d36dc3c-131e-4a38-85bb-efb28e5202da |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1869381002 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_error_random.1869381002 |
| Directory | /workspace/68.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_random.6807432 |
| Short name | T602 |
| Test name | |
| Test status | |
| Simulation time | 1875052002 ps |
| CPU time | 71.05 seconds |
| Started | Jul 03 07:34:35 PM PDT 24 |
| Finished | Jul 03 07:35:46 PM PDT 24 |
| Peak memory | 574152 kb |
| Host | smart-1f080855-c5c7-46df-874d-01c95f26c0f0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6807432 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_random.6807432 |
| Directory | /workspace/68.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_random_large_delays.1865297640 |
| Short name | T1484 |
| Test name | |
| Test status | |
| Simulation time | 34534650278 ps |
| CPU time | 340.83 seconds |
| Started | Jul 03 07:34:37 PM PDT 24 |
| Finished | Jul 03 07:40:19 PM PDT 24 |
| Peak memory | 574320 kb |
| Host | smart-2ea5486c-cbad-4ee6-8885-73313a37dea7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1865297640 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_random_large_delays.1865297640 |
| Directory | /workspace/68.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_random_slow_rsp.1356006840 |
| Short name | T2770 |
| Test name | |
| Test status | |
| Simulation time | 52658501831 ps |
| CPU time | 988.13 seconds |
| Started | Jul 03 07:34:39 PM PDT 24 |
| Finished | Jul 03 07:51:08 PM PDT 24 |
| Peak memory | 574196 kb |
| Host | smart-a7d34a9f-83cb-4fe8-bd29-dc49427bf0e3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1356006840 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_random_slow_rsp.1356006840 |
| Directory | /workspace/68.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_random_zero_delays.1961316485 |
| Short name | T1708 |
| Test name | |
| Test status | |
| Simulation time | 164563302 ps |
| CPU time | 17.05 seconds |
| Started | Jul 03 07:34:36 PM PDT 24 |
| Finished | Jul 03 07:34:54 PM PDT 24 |
| Peak memory | 574156 kb |
| Host | smart-c4202c3f-0470-4f59-a13d-1838ce023c23 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961316485 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_random_zero_del ays.1961316485 |
| Directory | /workspace/68.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_same_source.1651060230 |
| Short name | T2843 |
| Test name | |
| Test status | |
| Simulation time | 218890958 ps |
| CPU time | 9.27 seconds |
| Started | Jul 03 07:34:40 PM PDT 24 |
| Finished | Jul 03 07:34:50 PM PDT 24 |
| Peak memory | 573032 kb |
| Host | smart-16f74067-cdc5-450d-9b77-6fdb7e3df5f1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1651060230 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_same_source.1651060230 |
| Directory | /workspace/68.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_smoke.2112251072 |
| Short name | T2105 |
| Test name | |
| Test status | |
| Simulation time | 198171396 ps |
| CPU time | 9.39 seconds |
| Started | Jul 03 07:34:37 PM PDT 24 |
| Finished | Jul 03 07:34:47 PM PDT 24 |
| Peak memory | 574096 kb |
| Host | smart-9106edbb-0959-413b-b2fe-39f3e24ef5f7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2112251072 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_smoke.2112251072 |
| Directory | /workspace/68.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_smoke_large_delays.390253337 |
| Short name | T1304 |
| Test name | |
| Test status | |
| Simulation time | 9148641748 ps |
| CPU time | 93.37 seconds |
| Started | Jul 03 07:34:38 PM PDT 24 |
| Finished | Jul 03 07:36:12 PM PDT 24 |
| Peak memory | 573244 kb |
| Host | smart-5ee0fd8c-abf9-47a3-9791-57cb864e6ef5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=390253337 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_smoke_large_delays.390253337 |
| Directory | /workspace/68.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_smoke_slow_rsp.2702607516 |
| Short name | T2760 |
| Test name | |
| Test status | |
| Simulation time | 4775004643 ps |
| CPU time | 80.51 seconds |
| Started | Jul 03 07:34:37 PM PDT 24 |
| Finished | Jul 03 07:35:58 PM PDT 24 |
| Peak memory | 573236 kb |
| Host | smart-77b75533-f8d8-43c1-b559-32b74a98b309 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2702607516 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_smoke_slow_rsp.2702607516 |
| Directory | /workspace/68.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_smoke_zero_delays.940127982 |
| Short name | T2588 |
| Test name | |
| Test status | |
| Simulation time | 42134007 ps |
| CPU time | 6.25 seconds |
| Started | Jul 03 07:34:36 PM PDT 24 |
| Finished | Jul 03 07:34:42 PM PDT 24 |
| Peak memory | 573956 kb |
| Host | smart-b6edd72d-7145-4082-a616-82aa39aa6c3a |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=940127982 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_smoke_zero_delays .940127982 |
| Directory | /workspace/68.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_stress_all.1437846 |
| Short name | T2030 |
| Test name | |
| Test status | |
| Simulation time | 5577329196 ps |
| CPU time | 415.58 seconds |
| Started | Jul 03 07:34:46 PM PDT 24 |
| Finished | Jul 03 07:41:43 PM PDT 24 |
| Peak memory | 574712 kb |
| Host | smart-9190c062-b685-4c21-a5ab-0e6b7f8f5372 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1437846 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_stress_all.1437846 |
| Directory | /workspace/68.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_stress_all_with_error.216229471 |
| Short name | T1872 |
| Test name | |
| Test status | |
| Simulation time | 2861128107 ps |
| CPU time | 245.67 seconds |
| Started | Jul 03 07:34:45 PM PDT 24 |
| Finished | Jul 03 07:38:51 PM PDT 24 |
| Peak memory | 574700 kb |
| Host | smart-bf711fd9-e70b-494f-8f32-d707968d0e2c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216229471 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_stress_all_with_error.216229471 |
| Directory | /workspace/68.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_stress_all_with_rand_reset.3848473610 |
| Short name | T2766 |
| Test name | |
| Test status | |
| Simulation time | 4114871294 ps |
| CPU time | 443.65 seconds |
| Started | Jul 03 07:34:45 PM PDT 24 |
| Finished | Jul 03 07:42:10 PM PDT 24 |
| Peak memory | 574684 kb |
| Host | smart-5b3a629e-70b1-4ac8-9da6-fca95b3385c7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3848473610 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_stress_all _with_rand_reset.3848473610 |
| Directory | /workspace/68.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_stress_all_with_reset_error.3690042983 |
| Short name | T2386 |
| Test name | |
| Test status | |
| Simulation time | 596994402 ps |
| CPU time | 204.26 seconds |
| Started | Jul 03 07:34:46 PM PDT 24 |
| Finished | Jul 03 07:38:11 PM PDT 24 |
| Peak memory | 574640 kb |
| Host | smart-07714a55-8ae2-414e-ab73-17c4be30b8f2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3690042983 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_stress_al l_with_reset_error.3690042983 |
| Directory | /workspace/68.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_unmapped_addr.3140319216 |
| Short name | T2697 |
| Test name | |
| Test status | |
| Simulation time | 123265062 ps |
| CPU time | 18.34 seconds |
| Started | Jul 03 07:34:39 PM PDT 24 |
| Finished | Jul 03 07:34:58 PM PDT 24 |
| Peak memory | 574120 kb |
| Host | smart-f10b4310-1d09-4041-a6bf-3a20f928d38e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3140319216 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_unmapped_addr.3140319216 |
| Directory | /workspace/68.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_access_same_device.2579806880 |
| Short name | T1399 |
| Test name | |
| Test status | |
| Simulation time | 2609882872 ps |
| CPU time | 116.21 seconds |
| Started | Jul 03 07:34:55 PM PDT 24 |
| Finished | Jul 03 07:36:52 PM PDT 24 |
| Peak memory | 574260 kb |
| Host | smart-59c503c3-3d72-483f-a50e-9a4ca8f60250 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579806880 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_access_same_device .2579806880 |
| Directory | /workspace/69.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_access_same_device_slow_rsp.3837167880 |
| Short name | T2483 |
| Test name | |
| Test status | |
| Simulation time | 159389201664 ps |
| CPU time | 2857.75 seconds |
| Started | Jul 03 07:34:59 PM PDT 24 |
| Finished | Jul 03 08:22:38 PM PDT 24 |
| Peak memory | 574108 kb |
| Host | smart-85d9debf-8a16-4e77-a2c2-46274c369b23 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837167880 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_access_same_ device_slow_rsp.3837167880 |
| Directory | /workspace/69.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_error_and_unmapped_addr.112169724 |
| Short name | T1367 |
| Test name | |
| Test status | |
| Simulation time | 346450390 ps |
| CPU time | 16.82 seconds |
| Started | Jul 03 07:34:59 PM PDT 24 |
| Finished | Jul 03 07:35:17 PM PDT 24 |
| Peak memory | 574440 kb |
| Host | smart-bfdd63a2-728f-46e2-b2e1-ac22737fe77c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112169724 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_error_and_unmapped_addr .112169724 |
| Directory | /workspace/69.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_error_random.3732812446 |
| Short name | T2580 |
| Test name | |
| Test status | |
| Simulation time | 389716753 ps |
| CPU time | 32.03 seconds |
| Started | Jul 03 07:35:03 PM PDT 24 |
| Finished | Jul 03 07:35:36 PM PDT 24 |
| Peak memory | 574508 kb |
| Host | smart-5089b3d7-240b-4af4-8b8f-48cb73675687 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3732812446 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_error_random.3732812446 |
| Directory | /workspace/69.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_random.1782639801 |
| Short name | T2454 |
| Test name | |
| Test status | |
| Simulation time | 1905128111 ps |
| CPU time | 70.98 seconds |
| Started | Jul 03 07:34:52 PM PDT 24 |
| Finished | Jul 03 07:36:04 PM PDT 24 |
| Peak memory | 574208 kb |
| Host | smart-5cf54fb8-219a-495c-98b1-95174359b3e2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1782639801 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_random.1782639801 |
| Directory | /workspace/69.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_random_large_delays.3696123121 |
| Short name | T2772 |
| Test name | |
| Test status | |
| Simulation time | 21634730217 ps |
| CPU time | 224.65 seconds |
| Started | Jul 03 07:35:03 PM PDT 24 |
| Finished | Jul 03 07:38:49 PM PDT 24 |
| Peak memory | 574244 kb |
| Host | smart-7e710684-a9c9-4586-996d-3c2862502fc8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3696123121 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_random_large_delays.3696123121 |
| Directory | /workspace/69.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_random_slow_rsp.3264745568 |
| Short name | T1540 |
| Test name | |
| Test status | |
| Simulation time | 36225434242 ps |
| CPU time | 623.02 seconds |
| Started | Jul 03 07:34:57 PM PDT 24 |
| Finished | Jul 03 07:45:20 PM PDT 24 |
| Peak memory | 574068 kb |
| Host | smart-a023298f-f66d-474e-9397-1d8814a9bc5c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3264745568 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_random_slow_rsp.3264745568 |
| Directory | /workspace/69.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_random_zero_delays.3699392365 |
| Short name | T1748 |
| Test name | |
| Test status | |
| Simulation time | 656285003 ps |
| CPU time | 58.03 seconds |
| Started | Jul 03 07:34:51 PM PDT 24 |
| Finished | Jul 03 07:35:49 PM PDT 24 |
| Peak memory | 574224 kb |
| Host | smart-dc6101ab-1971-48e5-96ba-ab97d409c1af |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699392365 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_random_zero_del ays.3699392365 |
| Directory | /workspace/69.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_same_source.769785398 |
| Short name | T1999 |
| Test name | |
| Test status | |
| Simulation time | 285980390 ps |
| CPU time | 24.43 seconds |
| Started | Jul 03 07:34:59 PM PDT 24 |
| Finished | Jul 03 07:35:24 PM PDT 24 |
| Peak memory | 573932 kb |
| Host | smart-2673b219-1825-4817-a5ef-acd71729fa73 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769785398 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_same_source.769785398 |
| Directory | /workspace/69.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_smoke.3676385021 |
| Short name | T1774 |
| Test name | |
| Test status | |
| Simulation time | 46095121 ps |
| CPU time | 5.86 seconds |
| Started | Jul 03 07:34:53 PM PDT 24 |
| Finished | Jul 03 07:34:59 PM PDT 24 |
| Peak memory | 573920 kb |
| Host | smart-7dd6c6eb-6b65-4f29-84b7-2a7d64f56abe |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3676385021 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_smoke.3676385021 |
| Directory | /workspace/69.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_smoke_large_delays.3104739001 |
| Short name | T2450 |
| Test name | |
| Test status | |
| Simulation time | 10410130346 ps |
| CPU time | 104.47 seconds |
| Started | Jul 03 07:34:51 PM PDT 24 |
| Finished | Jul 03 07:36:36 PM PDT 24 |
| Peak memory | 573176 kb |
| Host | smart-4924c90f-b5ca-4204-a6fb-afd6a6f98419 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3104739001 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_smoke_large_delays.3104739001 |
| Directory | /workspace/69.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_smoke_slow_rsp.1802321338 |
| Short name | T2832 |
| Test name | |
| Test status | |
| Simulation time | 6251112689 ps |
| CPU time | 110.33 seconds |
| Started | Jul 03 07:34:48 PM PDT 24 |
| Finished | Jul 03 07:36:39 PM PDT 24 |
| Peak memory | 574156 kb |
| Host | smart-5d59509a-cbcb-43ac-94d5-9a96a25955a3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1802321338 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_smoke_slow_rsp.1802321338 |
| Directory | /workspace/69.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_smoke_zero_delays.3850903886 |
| Short name | T1503 |
| Test name | |
| Test status | |
| Simulation time | 45578376 ps |
| CPU time | 6.45 seconds |
| Started | Jul 03 07:34:51 PM PDT 24 |
| Finished | Jul 03 07:34:58 PM PDT 24 |
| Peak memory | 573972 kb |
| Host | smart-4819a249-72f0-4900-8549-79e5bd28b53d |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850903886 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_smoke_zero_delay s.3850903886 |
| Directory | /workspace/69.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_stress_all.2762390521 |
| Short name | T2377 |
| Test name | |
| Test status | |
| Simulation time | 13944130182 ps |
| CPU time | 530.2 seconds |
| Started | Jul 03 07:34:59 PM PDT 24 |
| Finished | Jul 03 07:43:51 PM PDT 24 |
| Peak memory | 574708 kb |
| Host | smart-1973feed-0a3c-42ef-890b-689c023827df |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2762390521 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_stress_all.2762390521 |
| Directory | /workspace/69.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_stress_all_with_error.4120576606 |
| Short name | T1464 |
| Test name | |
| Test status | |
| Simulation time | 1220085280 ps |
| CPU time | 106.71 seconds |
| Started | Jul 03 07:34:59 PM PDT 24 |
| Finished | Jul 03 07:36:47 PM PDT 24 |
| Peak memory | 574612 kb |
| Host | smart-eee853fe-52f9-4c6d-b72f-449a2130a096 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4120576606 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_stress_all_with_error.4120576606 |
| Directory | /workspace/69.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_stress_all_with_rand_reset.2135976354 |
| Short name | T1530 |
| Test name | |
| Test status | |
| Simulation time | 10143102730 ps |
| CPU time | 538.68 seconds |
| Started | Jul 03 07:34:59 PM PDT 24 |
| Finished | Jul 03 07:43:59 PM PDT 24 |
| Peak memory | 574764 kb |
| Host | smart-e6fe0c74-bee9-4690-9923-96200059aa8c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2135976354 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_stress_all _with_rand_reset.2135976354 |
| Directory | /workspace/69.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_stress_all_with_reset_error.3552945323 |
| Short name | T2549 |
| Test name | |
| Test status | |
| Simulation time | 7391838601 ps |
| CPU time | 356.55 seconds |
| Started | Jul 03 07:35:01 PM PDT 24 |
| Finished | Jul 03 07:40:58 PM PDT 24 |
| Peak memory | 574844 kb |
| Host | smart-c0daccac-aa6b-43e1-912b-5a4cf1073735 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3552945323 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_stress_al l_with_reset_error.3552945323 |
| Directory | /workspace/69.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_unmapped_addr.1949919690 |
| Short name | T572 |
| Test name | |
| Test status | |
| Simulation time | 1199394064 ps |
| CPU time | 47.05 seconds |
| Started | Jul 03 07:34:55 PM PDT 24 |
| Finished | Jul 03 07:35:43 PM PDT 24 |
| Peak memory | 574260 kb |
| Host | smart-9a443874-e34f-423a-8aad-b17d7857b602 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1949919690 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_unmapped_addr.1949919690 |
| Directory | /workspace/69.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/7.chip_csr_rw.2305466249 |
| Short name | T2779 |
| Test name | |
| Test status | |
| Simulation time | 6135990631 ps |
| CPU time | 588.33 seconds |
| Started | Jul 03 07:23:20 PM PDT 24 |
| Finished | Jul 03 07:33:10 PM PDT 24 |
| Peak memory | 596052 kb |
| Host | smart-6184bbd3-0bc5-4055-b91a-f3a0decf1de4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2305466249 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.chip_csr_rw.2305466249 |
| Directory | /workspace/7.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/7.chip_same_csr_outstanding.1244917362 |
| Short name | T2440 |
| Test name | |
| Test status | |
| Simulation time | 15292225392 ps |
| CPU time | 1837.23 seconds |
| Started | Jul 03 07:23:04 PM PDT 24 |
| Finished | Jul 03 07:53:43 PM PDT 24 |
| Peak memory | 592088 kb |
| Host | smart-a637b2ce-9127-40b5-996a-6267bc68520c |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1244917362 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 7.chip_same_csr_outstanding.1244917362 |
| Directory | /workspace/7.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/7.chip_tl_errors.3020281160 |
| Short name | T2107 |
| Test name | |
| Test status | |
| Simulation time | 2834464000 ps |
| CPU time | 88.49 seconds |
| Started | Jul 03 07:23:09 PM PDT 24 |
| Finished | Jul 03 07:24:39 PM PDT 24 |
| Peak memory | 603156 kb |
| Host | smart-d2e65ddf-7965-45b7-a995-8dcaee714e14 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3020281160 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.chip_tl_errors.3020281160 |
| Directory | /workspace/7.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_access_same_device.447022355 |
| Short name | T1918 |
| Test name | |
| Test status | |
| Simulation time | 492491192 ps |
| CPU time | 43.74 seconds |
| Started | Jul 03 07:23:17 PM PDT 24 |
| Finished | Jul 03 07:24:03 PM PDT 24 |
| Peak memory | 574196 kb |
| Host | smart-a4a5feea-09d4-4c85-a596-1f816511a03a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=447022355 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_access_same_device.447022355 |
| Directory | /workspace/7.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_access_same_device_slow_rsp.3901831312 |
| Short name | T1852 |
| Test name | |
| Test status | |
| Simulation time | 2421820144 ps |
| CPU time | 42.72 seconds |
| Started | Jul 03 07:23:15 PM PDT 24 |
| Finished | Jul 03 07:23:59 PM PDT 24 |
| Peak memory | 573036 kb |
| Host | smart-ff90ac23-50e6-4ce3-a6f4-38cc8f88c45c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3901831312 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_access_same_d evice_slow_rsp.3901831312 |
| Directory | /workspace/7.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_error_and_unmapped_addr.2459402572 |
| Short name | T1352 |
| Test name | |
| Test status | |
| Simulation time | 585199697 ps |
| CPU time | 26.63 seconds |
| Started | Jul 03 07:23:16 PM PDT 24 |
| Finished | Jul 03 07:23:45 PM PDT 24 |
| Peak memory | 574036 kb |
| Host | smart-ad545d35-146d-44ad-9df1-b12008943086 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2459402572 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_error_and_unmapped_addr .2459402572 |
| Directory | /workspace/7.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_error_random.4261105080 |
| Short name | T2180 |
| Test name | |
| Test status | |
| Simulation time | 453909788 ps |
| CPU time | 38.12 seconds |
| Started | Jul 03 07:23:18 PM PDT 24 |
| Finished | Jul 03 07:23:58 PM PDT 24 |
| Peak memory | 574044 kb |
| Host | smart-4332869c-9edc-4f6c-a612-6599f19d146d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4261105080 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_error_random.4261105080 |
| Directory | /workspace/7.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_random.2479935314 |
| Short name | T1638 |
| Test name | |
| Test status | |
| Simulation time | 1501144397 ps |
| CPU time | 47.96 seconds |
| Started | Jul 03 07:23:11 PM PDT 24 |
| Finished | Jul 03 07:24:01 PM PDT 24 |
| Peak memory | 573988 kb |
| Host | smart-9145d109-2feb-4ac5-a38e-254894faa489 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2479935314 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_random.2479935314 |
| Directory | /workspace/7.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_random_large_delays.1250771469 |
| Short name | T605 |
| Test name | |
| Test status | |
| Simulation time | 94227763005 ps |
| CPU time | 927.8 seconds |
| Started | Jul 03 07:23:16 PM PDT 24 |
| Finished | Jul 03 07:38:46 PM PDT 24 |
| Peak memory | 574332 kb |
| Host | smart-24183227-de49-494f-868d-fc3e0e425d75 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1250771469 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_random_large_delays.1250771469 |
| Directory | /workspace/7.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_random_slow_rsp.417173051 |
| Short name | T1861 |
| Test name | |
| Test status | |
| Simulation time | 72973391825 ps |
| CPU time | 1233.07 seconds |
| Started | Jul 03 07:23:16 PM PDT 24 |
| Finished | Jul 03 07:43:51 PM PDT 24 |
| Peak memory | 574140 kb |
| Host | smart-7aaa8ca6-79fd-4f1a-8ab1-b71c67a28d8e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=417173051 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_random_slow_rsp.417173051 |
| Directory | /workspace/7.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_random_zero_delays.716021465 |
| Short name | T490 |
| Test name | |
| Test status | |
| Simulation time | 416039830 ps |
| CPU time | 38.13 seconds |
| Started | Jul 03 07:23:16 PM PDT 24 |
| Finished | Jul 03 07:23:56 PM PDT 24 |
| Peak memory | 574188 kb |
| Host | smart-6bb1a698-ff01-4a30-aebb-06125cb9d1aa |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716021465 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_random_zero_delay s.716021465 |
| Directory | /workspace/7.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_same_source.2925685137 |
| Short name | T454 |
| Test name | |
| Test status | |
| Simulation time | 1673739559 ps |
| CPU time | 45.59 seconds |
| Started | Jul 03 07:23:15 PM PDT 24 |
| Finished | Jul 03 07:24:02 PM PDT 24 |
| Peak memory | 573940 kb |
| Host | smart-1ab24f58-692e-49ba-826e-878cec60e0ce |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2925685137 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_same_source.2925685137 |
| Directory | /workspace/7.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_smoke.1366572871 |
| Short name | T2093 |
| Test name | |
| Test status | |
| Simulation time | 150273997 ps |
| CPU time | 7.66 seconds |
| Started | Jul 03 07:23:13 PM PDT 24 |
| Finished | Jul 03 07:23:22 PM PDT 24 |
| Peak memory | 572968 kb |
| Host | smart-2a349075-1139-40a8-906d-50f78a02ea40 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1366572871 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_smoke.1366572871 |
| Directory | /workspace/7.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_smoke_large_delays.3397919828 |
| Short name | T1859 |
| Test name | |
| Test status | |
| Simulation time | 8434819734 ps |
| CPU time | 87.2 seconds |
| Started | Jul 03 07:23:12 PM PDT 24 |
| Finished | Jul 03 07:24:41 PM PDT 24 |
| Peak memory | 574204 kb |
| Host | smart-09fe9cf3-f8c9-410f-b978-8966b3a98527 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3397919828 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_large_delays.3397919828 |
| Directory | /workspace/7.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_smoke_slow_rsp.801289788 |
| Short name | T2647 |
| Test name | |
| Test status | |
| Simulation time | 3612032487 ps |
| CPU time | 63.8 seconds |
| Started | Jul 03 07:23:10 PM PDT 24 |
| Finished | Jul 03 07:24:15 PM PDT 24 |
| Peak memory | 573208 kb |
| Host | smart-3b33586d-8c4a-49dc-9625-6821ab268aa7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801289788 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_slow_rsp.801289788 |
| Directory | /workspace/7.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_smoke_zero_delays.164391757 |
| Short name | T1573 |
| Test name | |
| Test status | |
| Simulation time | 37297462 ps |
| CPU time | 6.05 seconds |
| Started | Jul 03 07:23:09 PM PDT 24 |
| Finished | Jul 03 07:23:17 PM PDT 24 |
| Peak memory | 572956 kb |
| Host | smart-4eeb03b9-ced4-4f43-a0a3-b5705e3da8ea |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=164391757 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_zero_delays. 164391757 |
| Directory | /workspace/7.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_stress_all.3656592254 |
| Short name | T2291 |
| Test name | |
| Test status | |
| Simulation time | 8011651707 ps |
| CPU time | 298.25 seconds |
| Started | Jul 03 07:23:20 PM PDT 24 |
| Finished | Jul 03 07:28:20 PM PDT 24 |
| Peak memory | 574720 kb |
| Host | smart-07883508-4195-4575-89a5-cdaa19a54a31 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3656592254 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all.3656592254 |
| Directory | /workspace/7.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_stress_all_with_error.1661723089 |
| Short name | T2676 |
| Test name | |
| Test status | |
| Simulation time | 2102154626 ps |
| CPU time | 193.88 seconds |
| Started | Jul 03 07:23:23 PM PDT 24 |
| Finished | Jul 03 07:26:38 PM PDT 24 |
| Peak memory | 574276 kb |
| Host | smart-f6bef8fe-af21-4300-aebb-39cb5e008b20 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1661723089 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_error.1661723089 |
| Directory | /workspace/7.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_stress_all_with_reset_error.3626724382 |
| Short name | T2605 |
| Test name | |
| Test status | |
| Simulation time | 200957131 ps |
| CPU time | 68.35 seconds |
| Started | Jul 03 07:23:20 PM PDT 24 |
| Finished | Jul 03 07:24:30 PM PDT 24 |
| Peak memory | 574652 kb |
| Host | smart-2595ca75-df35-4f08-a85b-bfb0a8b13aad |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3626724382 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all _with_reset_error.3626724382 |
| Directory | /workspace/7.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_unmapped_addr.2279358671 |
| Short name | T2783 |
| Test name | |
| Test status | |
| Simulation time | 146754110 ps |
| CPU time | 19.99 seconds |
| Started | Jul 03 07:23:17 PM PDT 24 |
| Finished | Jul 03 07:23:39 PM PDT 24 |
| Peak memory | 574100 kb |
| Host | smart-10318dc8-e4ee-4697-a1db-ba4c4eecb4d9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279358671 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_unmapped_addr.2279358671 |
| Directory | /workspace/7.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_access_same_device.3839796309 |
| Short name | T795 |
| Test name | |
| Test status | |
| Simulation time | 348921895 ps |
| CPU time | 19.36 seconds |
| Started | Jul 03 07:34:59 PM PDT 24 |
| Finished | Jul 03 07:35:20 PM PDT 24 |
| Peak memory | 574212 kb |
| Host | smart-f4b30a2e-874d-48c2-8fcc-b5afa1ef65b2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3839796309 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_access_same_device .3839796309 |
| Directory | /workspace/70.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_access_same_device_slow_rsp.3219665921 |
| Short name | T1694 |
| Test name | |
| Test status | |
| Simulation time | 143278590995 ps |
| CPU time | 2539.11 seconds |
| Started | Jul 03 07:34:59 PM PDT 24 |
| Finished | Jul 03 08:17:19 PM PDT 24 |
| Peak memory | 574072 kb |
| Host | smart-b2d14624-ddf1-4fc3-84a1-9402625caa49 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219665921 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_access_same_ device_slow_rsp.3219665921 |
| Directory | /workspace/70.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_error_and_unmapped_addr.4149328314 |
| Short name | T1329 |
| Test name | |
| Test status | |
| Simulation time | 1130241411 ps |
| CPU time | 47.21 seconds |
| Started | Jul 03 07:35:04 PM PDT 24 |
| Finished | Jul 03 07:35:52 PM PDT 24 |
| Peak memory | 574548 kb |
| Host | smart-a0193621-01ca-4e26-995d-820df7f57ff4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149328314 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_error_and_unmapped_add r.4149328314 |
| Directory | /workspace/70.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_error_random.3971604686 |
| Short name | T2536 |
| Test name | |
| Test status | |
| Simulation time | 1134350643 ps |
| CPU time | 37.23 seconds |
| Started | Jul 03 07:35:07 PM PDT 24 |
| Finished | Jul 03 07:35:45 PM PDT 24 |
| Peak memory | 574420 kb |
| Host | smart-47332206-34da-4426-871b-bea5ddece016 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3971604686 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_error_random.3971604686 |
| Directory | /workspace/70.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_random.2157911981 |
| Short name | T1977 |
| Test name | |
| Test status | |
| Simulation time | 422850866 ps |
| CPU time | 33.74 seconds |
| Started | Jul 03 07:34:59 PM PDT 24 |
| Finished | Jul 03 07:35:34 PM PDT 24 |
| Peak memory | 574184 kb |
| Host | smart-e2664bc9-f783-42f9-b0f7-fe1db2ba112a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2157911981 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_random.2157911981 |
| Directory | /workspace/70.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_random_large_delays.2814499079 |
| Short name | T1612 |
| Test name | |
| Test status | |
| Simulation time | 57690528306 ps |
| CPU time | 640.52 seconds |
| Started | Jul 03 07:34:59 PM PDT 24 |
| Finished | Jul 03 07:45:40 PM PDT 24 |
| Peak memory | 574304 kb |
| Host | smart-670a7722-8667-4a8d-ba4a-30575ee00552 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2814499079 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_random_large_delays.2814499079 |
| Directory | /workspace/70.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_random_slow_rsp.2616026611 |
| Short name | T528 |
| Test name | |
| Test status | |
| Simulation time | 44840144700 ps |
| CPU time | 794.85 seconds |
| Started | Jul 03 07:34:59 PM PDT 24 |
| Finished | Jul 03 07:48:15 PM PDT 24 |
| Peak memory | 574276 kb |
| Host | smart-03ef2016-e186-4828-b51e-34bf5942d826 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2616026611 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_random_slow_rsp.2616026611 |
| Directory | /workspace/70.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_random_zero_delays.281231567 |
| Short name | T2502 |
| Test name | |
| Test status | |
| Simulation time | 169840229 ps |
| CPU time | 15.92 seconds |
| Started | Jul 03 07:35:00 PM PDT 24 |
| Finished | Jul 03 07:35:17 PM PDT 24 |
| Peak memory | 573964 kb |
| Host | smart-32be8c27-b8ca-422b-b1e5-bdf223cb1a42 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=281231567 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_random_zero_dela ys.281231567 |
| Directory | /workspace/70.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_same_source.2847343241 |
| Short name | T2698 |
| Test name | |
| Test status | |
| Simulation time | 2069602342 ps |
| CPU time | 64.21 seconds |
| Started | Jul 03 07:35:00 PM PDT 24 |
| Finished | Jul 03 07:36:05 PM PDT 24 |
| Peak memory | 574084 kb |
| Host | smart-4befa80a-cbc6-4406-981c-29be1031b773 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2847343241 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_same_source.2847343241 |
| Directory | /workspace/70.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_smoke.1464332438 |
| Short name | T1576 |
| Test name | |
| Test status | |
| Simulation time | 184203058 ps |
| CPU time | 8.53 seconds |
| Started | Jul 03 07:35:00 PM PDT 24 |
| Finished | Jul 03 07:35:10 PM PDT 24 |
| Peak memory | 573104 kb |
| Host | smart-47cb1438-21e0-43cb-af87-bbdd944c461f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1464332438 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_smoke.1464332438 |
| Directory | /workspace/70.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_smoke_large_delays.971449560 |
| Short name | T2707 |
| Test name | |
| Test status | |
| Simulation time | 10388162916 ps |
| CPU time | 105.54 seconds |
| Started | Jul 03 07:35:01 PM PDT 24 |
| Finished | Jul 03 07:36:47 PM PDT 24 |
| Peak memory | 573164 kb |
| Host | smart-71d6f933-ac3f-4806-8aec-81166a869d0f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=971449560 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_smoke_large_delays.971449560 |
| Directory | /workspace/70.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_smoke_slow_rsp.4071762680 |
| Short name | T2014 |
| Test name | |
| Test status | |
| Simulation time | 5380591902 ps |
| CPU time | 97.09 seconds |
| Started | Jul 03 07:35:00 PM PDT 24 |
| Finished | Jul 03 07:36:38 PM PDT 24 |
| Peak memory | 573204 kb |
| Host | smart-73d27c5a-0514-4d36-a990-1416d4298d05 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4071762680 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_smoke_slow_rsp.4071762680 |
| Directory | /workspace/70.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_smoke_zero_delays.2908001780 |
| Short name | T2442 |
| Test name | |
| Test status | |
| Simulation time | 43243978 ps |
| CPU time | 5.5 seconds |
| Started | Jul 03 07:35:04 PM PDT 24 |
| Finished | Jul 03 07:35:10 PM PDT 24 |
| Peak memory | 574196 kb |
| Host | smart-5f7402ba-a1d7-4edf-a10a-5d26d9ba46bb |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2908001780 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_smoke_zero_delay s.2908001780 |
| Directory | /workspace/70.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_stress_all.2887289717 |
| Short name | T1808 |
| Test name | |
| Test status | |
| Simulation time | 1325690562 ps |
| CPU time | 113.36 seconds |
| Started | Jul 03 07:35:07 PM PDT 24 |
| Finished | Jul 03 07:37:01 PM PDT 24 |
| Peak memory | 574184 kb |
| Host | smart-64e6c2e9-a1b8-4a4a-9c8e-addf446e4f47 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2887289717 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_stress_all.2887289717 |
| Directory | /workspace/70.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_stress_all_with_error.3226164464 |
| Short name | T2123 |
| Test name | |
| Test status | |
| Simulation time | 2836219827 ps |
| CPU time | 95.34 seconds |
| Started | Jul 03 07:35:04 PM PDT 24 |
| Finished | Jul 03 07:36:40 PM PDT 24 |
| Peak memory | 574576 kb |
| Host | smart-253ad731-196e-4af9-9d16-4343b5b977fe |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3226164464 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_stress_all_with_error.3226164464 |
| Directory | /workspace/70.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_stress_all_with_rand_reset.2038629945 |
| Short name | T2744 |
| Test name | |
| Test status | |
| Simulation time | 151277207 ps |
| CPU time | 65.88 seconds |
| Started | Jul 03 07:35:05 PM PDT 24 |
| Finished | Jul 03 07:36:11 PM PDT 24 |
| Peak memory | 574652 kb |
| Host | smart-9626a30f-d55c-4648-a7bc-82b94d837da5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2038629945 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_stress_all _with_rand_reset.2038629945 |
| Directory | /workspace/70.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_stress_all_with_reset_error.22767702 |
| Short name | T1581 |
| Test name | |
| Test status | |
| Simulation time | 265492795 ps |
| CPU time | 49.04 seconds |
| Started | Jul 03 07:35:06 PM PDT 24 |
| Finished | Jul 03 07:35:55 PM PDT 24 |
| Peak memory | 574624 kb |
| Host | smart-3f32a5bb-f8d4-4e50-99e8-ce6072cd33cd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22767702 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_stress_all_ with_reset_error.22767702 |
| Directory | /workspace/70.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_unmapped_addr.2130512790 |
| Short name | T510 |
| Test name | |
| Test status | |
| Simulation time | 149636956 ps |
| CPU time | 9.28 seconds |
| Started | Jul 03 07:35:04 PM PDT 24 |
| Finished | Jul 03 07:35:14 PM PDT 24 |
| Peak memory | 573172 kb |
| Host | smart-951b94af-529a-4f45-8a6c-14c9aea649f6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2130512790 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_unmapped_addr.2130512790 |
| Directory | /workspace/70.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_access_same_device.3554307054 |
| Short name | T2498 |
| Test name | |
| Test status | |
| Simulation time | 138457385 ps |
| CPU time | 11.77 seconds |
| Started | Jul 03 07:35:10 PM PDT 24 |
| Finished | Jul 03 07:35:23 PM PDT 24 |
| Peak memory | 573832 kb |
| Host | smart-462a4825-68a7-426c-a5fe-93e6d63b80f0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3554307054 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_access_same_device .3554307054 |
| Directory | /workspace/71.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_access_same_device_slow_rsp.2581886864 |
| Short name | T2109 |
| Test name | |
| Test status | |
| Simulation time | 95981419494 ps |
| CPU time | 1794.96 seconds |
| Started | Jul 03 07:35:11 PM PDT 24 |
| Finished | Jul 03 08:05:06 PM PDT 24 |
| Peak memory | 574200 kb |
| Host | smart-56cc581e-019b-4236-aaef-f52bf5edc39c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581886864 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_access_same_ device_slow_rsp.2581886864 |
| Directory | /workspace/71.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_error_and_unmapped_addr.4026931339 |
| Short name | T1480 |
| Test name | |
| Test status | |
| Simulation time | 272067432 ps |
| CPU time | 27.54 seconds |
| Started | Jul 03 07:35:16 PM PDT 24 |
| Finished | Jul 03 07:35:45 PM PDT 24 |
| Peak memory | 574420 kb |
| Host | smart-a2e95254-dd09-430c-b3a4-eb99a15498de |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4026931339 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_error_and_unmapped_add r.4026931339 |
| Directory | /workspace/71.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_error_random.4005358627 |
| Short name | T661 |
| Test name | |
| Test status | |
| Simulation time | 587546455 ps |
| CPU time | 43.1 seconds |
| Started | Jul 03 07:35:16 PM PDT 24 |
| Finished | Jul 03 07:36:00 PM PDT 24 |
| Peak memory | 573972 kb |
| Host | smart-981be6c8-9732-42a1-8721-0143ea44b564 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4005358627 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_error_random.4005358627 |
| Directory | /workspace/71.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_random.1713669835 |
| Short name | T1547 |
| Test name | |
| Test status | |
| Simulation time | 1045711942 ps |
| CPU time | 40.23 seconds |
| Started | Jul 03 07:35:10 PM PDT 24 |
| Finished | Jul 03 07:35:51 PM PDT 24 |
| Peak memory | 574140 kb |
| Host | smart-3b4b9991-d877-4696-99ac-9d40e831fc36 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1713669835 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_random.1713669835 |
| Directory | /workspace/71.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_random_large_delays.3292428146 |
| Short name | T2753 |
| Test name | |
| Test status | |
| Simulation time | 78253026107 ps |
| CPU time | 908.51 seconds |
| Started | Jul 03 07:35:10 PM PDT 24 |
| Finished | Jul 03 07:50:19 PM PDT 24 |
| Peak memory | 574216 kb |
| Host | smart-fbbdca87-408b-4c75-8606-52f1feee34f7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292428146 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_random_large_delays.3292428146 |
| Directory | /workspace/71.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_random_slow_rsp.1619987832 |
| Short name | T563 |
| Test name | |
| Test status | |
| Simulation time | 70844076607 ps |
| CPU time | 1288.02 seconds |
| Started | Jul 03 07:35:09 PM PDT 24 |
| Finished | Jul 03 07:56:37 PM PDT 24 |
| Peak memory | 574324 kb |
| Host | smart-689379da-94f1-4dc7-80c7-9ef477aa21b5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619987832 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_random_slow_rsp.1619987832 |
| Directory | /workspace/71.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_random_zero_delays.394336590 |
| Short name | T1815 |
| Test name | |
| Test status | |
| Simulation time | 242170600 ps |
| CPU time | 21.86 seconds |
| Started | Jul 03 07:35:11 PM PDT 24 |
| Finished | Jul 03 07:35:33 PM PDT 24 |
| Peak memory | 574172 kb |
| Host | smart-5918c463-bf78-44e0-8fd8-4aa67eed828a |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394336590 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_random_zero_dela ys.394336590 |
| Directory | /workspace/71.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_same_source.3309656702 |
| Short name | T2449 |
| Test name | |
| Test status | |
| Simulation time | 707432862 ps |
| CPU time | 21.92 seconds |
| Started | Jul 03 07:35:11 PM PDT 24 |
| Finished | Jul 03 07:35:34 PM PDT 24 |
| Peak memory | 574088 kb |
| Host | smart-fca05618-5eda-4911-bf7d-ed4a6211e4d3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3309656702 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_same_source.3309656702 |
| Directory | /workspace/71.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_smoke.645864701 |
| Short name | T2637 |
| Test name | |
| Test status | |
| Simulation time | 195907308 ps |
| CPU time | 8.48 seconds |
| Started | Jul 03 07:35:05 PM PDT 24 |
| Finished | Jul 03 07:35:14 PM PDT 24 |
| Peak memory | 573988 kb |
| Host | smart-11067186-8769-469f-a6ba-1dbe2cca764f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=645864701 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_smoke.645864701 |
| Directory | /workspace/71.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_smoke_large_delays.4067745456 |
| Short name | T1807 |
| Test name | |
| Test status | |
| Simulation time | 9890821643 ps |
| CPU time | 112.77 seconds |
| Started | Jul 03 07:35:09 PM PDT 24 |
| Finished | Jul 03 07:37:03 PM PDT 24 |
| Peak memory | 573012 kb |
| Host | smart-e4f02bc7-8802-4677-9917-4f92f9c8d3f1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4067745456 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_smoke_large_delays.4067745456 |
| Directory | /workspace/71.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_smoke_slow_rsp.3633231257 |
| Short name | T2407 |
| Test name | |
| Test status | |
| Simulation time | 5018631354 ps |
| CPU time | 90.67 seconds |
| Started | Jul 03 07:35:09 PM PDT 24 |
| Finished | Jul 03 07:36:41 PM PDT 24 |
| Peak memory | 574228 kb |
| Host | smart-54509c4b-863a-462f-9d49-a178f920f66d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3633231257 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_smoke_slow_rsp.3633231257 |
| Directory | /workspace/71.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_smoke_zero_delays.1548886049 |
| Short name | T1991 |
| Test name | |
| Test status | |
| Simulation time | 37439891 ps |
| CPU time | 6.14 seconds |
| Started | Jul 03 07:35:07 PM PDT 24 |
| Finished | Jul 03 07:35:15 PM PDT 24 |
| Peak memory | 573144 kb |
| Host | smart-faf333b2-8737-42c1-860d-a450dcf9ff22 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1548886049 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_smoke_zero_delay s.1548886049 |
| Directory | /workspace/71.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_stress_all.261782006 |
| Short name | T2801 |
| Test name | |
| Test status | |
| Simulation time | 725005826 ps |
| CPU time | 59.09 seconds |
| Started | Jul 03 07:35:17 PM PDT 24 |
| Finished | Jul 03 07:36:17 PM PDT 24 |
| Peak memory | 574128 kb |
| Host | smart-2dc668e1-e846-4369-a9ee-0f009d293959 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=261782006 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_stress_all.261782006 |
| Directory | /workspace/71.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_stress_all_with_error.1972560922 |
| Short name | T1643 |
| Test name | |
| Test status | |
| Simulation time | 9147206190 ps |
| CPU time | 341.18 seconds |
| Started | Jul 03 07:35:16 PM PDT 24 |
| Finished | Jul 03 07:40:58 PM PDT 24 |
| Peak memory | 574688 kb |
| Host | smart-185fdfba-ffde-4c3a-9897-dd2467fca72f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972560922 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_stress_all_with_error.1972560922 |
| Directory | /workspace/71.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_stress_all_with_rand_reset.2166035748 |
| Short name | T449 |
| Test name | |
| Test status | |
| Simulation time | 2133428180 ps |
| CPU time | 296.77 seconds |
| Started | Jul 03 07:35:17 PM PDT 24 |
| Finished | Jul 03 07:40:15 PM PDT 24 |
| Peak memory | 574660 kb |
| Host | smart-bc340ab9-f9c0-4ff4-88c4-7b30d347cb1a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2166035748 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_stress_all _with_rand_reset.2166035748 |
| Directory | /workspace/71.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_stress_all_with_reset_error.507162684 |
| Short name | T2344 |
| Test name | |
| Test status | |
| Simulation time | 161637979 ps |
| CPU time | 38.02 seconds |
| Started | Jul 03 07:35:17 PM PDT 24 |
| Finished | Jul 03 07:35:56 PM PDT 24 |
| Peak memory | 574476 kb |
| Host | smart-ea44ac98-8e66-4e73-ac37-6fd72a6449e2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=507162684 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_stress_all _with_reset_error.507162684 |
| Directory | /workspace/71.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_unmapped_addr.521468950 |
| Short name | T2723 |
| Test name | |
| Test status | |
| Simulation time | 71890372 ps |
| CPU time | 10.79 seconds |
| Started | Jul 03 07:35:16 PM PDT 24 |
| Finished | Jul 03 07:35:29 PM PDT 24 |
| Peak memory | 574228 kb |
| Host | smart-0ccb52a4-1e85-499d-adb8-f6662e788219 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=521468950 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_unmapped_addr.521468950 |
| Directory | /workspace/71.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_access_same_device.1320181994 |
| Short name | T2681 |
| Test name | |
| Test status | |
| Simulation time | 3477898622 ps |
| CPU time | 147.6 seconds |
| Started | Jul 03 07:35:20 PM PDT 24 |
| Finished | Jul 03 07:37:48 PM PDT 24 |
| Peak memory | 574280 kb |
| Host | smart-f19161c4-8067-4a1e-8792-275aa79cb013 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1320181994 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_access_same_device .1320181994 |
| Directory | /workspace/72.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_access_same_device_slow_rsp.2365836 |
| Short name | T763 |
| Test name | |
| Test status | |
| Simulation time | 74768790577 ps |
| CPU time | 1326.28 seconds |
| Started | Jul 03 07:35:19 PM PDT 24 |
| Finished | Jul 03 07:57:26 PM PDT 24 |
| Peak memory | 574484 kb |
| Host | smart-12069d07-b1a4-49bd-9f8a-08a624833036 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2365836 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_access_same_dev ice_slow_rsp.2365836 |
| Directory | /workspace/72.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_error_and_unmapped_addr.1686199176 |
| Short name | T2859 |
| Test name | |
| Test status | |
| Simulation time | 249351222 ps |
| CPU time | 25.89 seconds |
| Started | Jul 03 07:35:26 PM PDT 24 |
| Finished | Jul 03 07:35:53 PM PDT 24 |
| Peak memory | 574424 kb |
| Host | smart-dcaa8528-bd71-4a3d-ba6d-644e20e67cd5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1686199176 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_error_and_unmapped_add r.1686199176 |
| Directory | /workspace/72.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_error_random.3794228787 |
| Short name | T2489 |
| Test name | |
| Test status | |
| Simulation time | 2561519746 ps |
| CPU time | 86.06 seconds |
| Started | Jul 03 07:35:22 PM PDT 24 |
| Finished | Jul 03 07:36:49 PM PDT 24 |
| Peak memory | 574076 kb |
| Host | smart-954e3d9e-b05b-44b5-9199-ab865d525906 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3794228787 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_error_random.3794228787 |
| Directory | /workspace/72.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_random.2700085852 |
| Short name | T2603 |
| Test name | |
| Test status | |
| Simulation time | 826607663 ps |
| CPU time | 29.92 seconds |
| Started | Jul 03 07:35:22 PM PDT 24 |
| Finished | Jul 03 07:35:54 PM PDT 24 |
| Peak memory | 574216 kb |
| Host | smart-7f427c5d-6a50-4d8d-abcf-a8ae63c0e295 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700085852 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_random.2700085852 |
| Directory | /workspace/72.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_random_large_delays.2658078358 |
| Short name | T2660 |
| Test name | |
| Test status | |
| Simulation time | 92027882062 ps |
| CPU time | 1082.8 seconds |
| Started | Jul 03 07:35:21 PM PDT 24 |
| Finished | Jul 03 07:53:25 PM PDT 24 |
| Peak memory | 574252 kb |
| Host | smart-359659bd-69a0-4202-9254-84e14e547a15 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2658078358 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_random_large_delays.2658078358 |
| Directory | /workspace/72.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_random_slow_rsp.753159950 |
| Short name | T2608 |
| Test name | |
| Test status | |
| Simulation time | 38642755489 ps |
| CPU time | 701.1 seconds |
| Started | Jul 03 07:35:20 PM PDT 24 |
| Finished | Jul 03 07:47:01 PM PDT 24 |
| Peak memory | 574140 kb |
| Host | smart-51c03278-035d-4647-a753-7ea5a0f636ca |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=753159950 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_random_slow_rsp.753159950 |
| Directory | /workspace/72.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_random_zero_delays.1455380374 |
| Short name | T2200 |
| Test name | |
| Test status | |
| Simulation time | 223440086 ps |
| CPU time | 22.77 seconds |
| Started | Jul 03 07:35:22 PM PDT 24 |
| Finished | Jul 03 07:35:46 PM PDT 24 |
| Peak memory | 574168 kb |
| Host | smart-a1e9e210-1405-4eb4-a092-88dc38f91a56 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1455380374 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_random_zero_del ays.1455380374 |
| Directory | /workspace/72.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_same_source.404295973 |
| Short name | T1963 |
| Test name | |
| Test status | |
| Simulation time | 2140214370 ps |
| CPU time | 66.63 seconds |
| Started | Jul 03 07:35:21 PM PDT 24 |
| Finished | Jul 03 07:36:29 PM PDT 24 |
| Peak memory | 573976 kb |
| Host | smart-b27cfbc5-7875-4b0c-b838-491fdaea98da |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=404295973 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_same_source.404295973 |
| Directory | /workspace/72.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_smoke.1878306373 |
| Short name | T1515 |
| Test name | |
| Test status | |
| Simulation time | 170264438 ps |
| CPU time | 7.89 seconds |
| Started | Jul 03 07:35:15 PM PDT 24 |
| Finished | Jul 03 07:35:23 PM PDT 24 |
| Peak memory | 573168 kb |
| Host | smart-e803960d-1b67-4142-bd4a-4ccbacd66f4e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1878306373 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_smoke.1878306373 |
| Directory | /workspace/72.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_smoke_large_delays.269513756 |
| Short name | T1324 |
| Test name | |
| Test status | |
| Simulation time | 8967414848 ps |
| CPU time | 88.46 seconds |
| Started | Jul 03 07:35:15 PM PDT 24 |
| Finished | Jul 03 07:36:44 PM PDT 24 |
| Peak memory | 573048 kb |
| Host | smart-bb41485a-b958-4d8c-930a-11c7bf0aa795 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269513756 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_smoke_large_delays.269513756 |
| Directory | /workspace/72.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_smoke_slow_rsp.3870263715 |
| Short name | T1587 |
| Test name | |
| Test status | |
| Simulation time | 3323130988 ps |
| CPU time | 56.74 seconds |
| Started | Jul 03 07:35:22 PM PDT 24 |
| Finished | Jul 03 07:36:19 PM PDT 24 |
| Peak memory | 573116 kb |
| Host | smart-6191bf67-0d83-45ca-9394-25d93d7d8a28 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3870263715 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_smoke_slow_rsp.3870263715 |
| Directory | /workspace/72.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_smoke_zero_delays.234858228 |
| Short name | T1653 |
| Test name | |
| Test status | |
| Simulation time | 44755065 ps |
| CPU time | 6.06 seconds |
| Started | Jul 03 07:35:15 PM PDT 24 |
| Finished | Jul 03 07:35:22 PM PDT 24 |
| Peak memory | 572916 kb |
| Host | smart-36c1799d-b4ec-4d93-a084-07d583d97ec5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=234858228 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_smoke_zero_delays .234858228 |
| Directory | /workspace/72.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_stress_all.4024206048 |
| Short name | T1935 |
| Test name | |
| Test status | |
| Simulation time | 391413059 ps |
| CPU time | 17.16 seconds |
| Started | Jul 03 07:35:25 PM PDT 24 |
| Finished | Jul 03 07:35:42 PM PDT 24 |
| Peak memory | 574320 kb |
| Host | smart-72e41217-c11d-4b75-b571-d14c2365f01a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024206048 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_stress_all.4024206048 |
| Directory | /workspace/72.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_stress_all_with_error.205740151 |
| Short name | T2363 |
| Test name | |
| Test status | |
| Simulation time | 980790761 ps |
| CPU time | 69.32 seconds |
| Started | Jul 03 07:35:27 PM PDT 24 |
| Finished | Jul 03 07:36:37 PM PDT 24 |
| Peak memory | 574628 kb |
| Host | smart-256e4318-8765-423d-be90-d53d7771e4ee |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205740151 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_stress_all_with_error.205740151 |
| Directory | /workspace/72.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_stress_all_with_rand_reset.2285530122 |
| Short name | T2493 |
| Test name | |
| Test status | |
| Simulation time | 4452822097 ps |
| CPU time | 345.25 seconds |
| Started | Jul 03 07:35:28 PM PDT 24 |
| Finished | Jul 03 07:41:14 PM PDT 24 |
| Peak memory | 574800 kb |
| Host | smart-24d5ac85-7541-4c2c-8949-0605c73e7450 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2285530122 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_stress_all _with_rand_reset.2285530122 |
| Directory | /workspace/72.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_stress_all_with_reset_error.3463525870 |
| Short name | T1752 |
| Test name | |
| Test status | |
| Simulation time | 1192710990 ps |
| CPU time | 136.87 seconds |
| Started | Jul 03 07:35:26 PM PDT 24 |
| Finished | Jul 03 07:37:43 PM PDT 24 |
| Peak memory | 574648 kb |
| Host | smart-a3e4e3df-c909-4633-be60-e9ba8705165c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3463525870 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_stress_al l_with_reset_error.3463525870 |
| Directory | /workspace/72.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_unmapped_addr.942918180 |
| Short name | T1414 |
| Test name | |
| Test status | |
| Simulation time | 169459195 ps |
| CPU time | 10.15 seconds |
| Started | Jul 03 07:35:27 PM PDT 24 |
| Finished | Jul 03 07:35:38 PM PDT 24 |
| Peak memory | 573268 kb |
| Host | smart-b9d1646b-4e18-4d0c-9ed9-771315efbb76 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=942918180 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_unmapped_addr.942918180 |
| Directory | /workspace/72.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_access_same_device.3753118072 |
| Short name | T2061 |
| Test name | |
| Test status | |
| Simulation time | 96011334 ps |
| CPU time | 9.75 seconds |
| Started | Jul 03 07:35:37 PM PDT 24 |
| Finished | Jul 03 07:35:48 PM PDT 24 |
| Peak memory | 574004 kb |
| Host | smart-0d734661-ee24-4e95-ab95-ce359dd6180c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3753118072 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_access_same_device .3753118072 |
| Directory | /workspace/73.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_access_same_device_slow_rsp.2027762265 |
| Short name | T771 |
| Test name | |
| Test status | |
| Simulation time | 87357841908 ps |
| CPU time | 1718.86 seconds |
| Started | Jul 03 07:35:33 PM PDT 24 |
| Finished | Jul 03 08:04:13 PM PDT 24 |
| Peak memory | 574092 kb |
| Host | smart-f802e622-a26e-4e64-a9cb-aa2e2cc81bc1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2027762265 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_access_same_ device_slow_rsp.2027762265 |
| Directory | /workspace/73.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_error_and_unmapped_addr.381473422 |
| Short name | T2257 |
| Test name | |
| Test status | |
| Simulation time | 1259230251 ps |
| CPU time | 47.22 seconds |
| Started | Jul 03 07:35:37 PM PDT 24 |
| Finished | Jul 03 07:36:26 PM PDT 24 |
| Peak memory | 574076 kb |
| Host | smart-e4d3d08f-1ce3-4cc9-a020-899c277fe12b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=381473422 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_error_and_unmapped_addr .381473422 |
| Directory | /workspace/73.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_error_random.1232749864 |
| Short name | T1971 |
| Test name | |
| Test status | |
| Simulation time | 1410822222 ps |
| CPU time | 55.08 seconds |
| Started | Jul 03 07:35:36 PM PDT 24 |
| Finished | Jul 03 07:36:32 PM PDT 24 |
| Peak memory | 574040 kb |
| Host | smart-2a856a47-aca6-48d2-b2b2-ba1092d983c2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1232749864 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_error_random.1232749864 |
| Directory | /workspace/73.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_random.1671907461 |
| Short name | T1440 |
| Test name | |
| Test status | |
| Simulation time | 562088073 ps |
| CPU time | 49.6 seconds |
| Started | Jul 03 07:35:33 PM PDT 24 |
| Finished | Jul 03 07:36:23 PM PDT 24 |
| Peak memory | 573980 kb |
| Host | smart-ea67c365-2ca6-490d-bbfc-395ca947c25f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671907461 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_random.1671907461 |
| Directory | /workspace/73.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_random_large_delays.951321615 |
| Short name | T2076 |
| Test name | |
| Test status | |
| Simulation time | 99226192327 ps |
| CPU time | 1082.01 seconds |
| Started | Jul 03 07:35:32 PM PDT 24 |
| Finished | Jul 03 07:53:35 PM PDT 24 |
| Peak memory | 574268 kb |
| Host | smart-ec004330-b36b-4bc3-aefe-ab30c857dd54 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=951321615 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_random_large_delays.951321615 |
| Directory | /workspace/73.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_random_slow_rsp.2705274024 |
| Short name | T2565 |
| Test name | |
| Test status | |
| Simulation time | 6285310374 ps |
| CPU time | 109.25 seconds |
| Started | Jul 03 07:35:34 PM PDT 24 |
| Finished | Jul 03 07:37:24 PM PDT 24 |
| Peak memory | 573288 kb |
| Host | smart-4f8fe604-fa4c-48e2-bcf5-ca122598a302 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705274024 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_random_slow_rsp.2705274024 |
| Directory | /workspace/73.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_random_zero_delays.1889736979 |
| Short name | T2322 |
| Test name | |
| Test status | |
| Simulation time | 265407038 ps |
| CPU time | 26.09 seconds |
| Started | Jul 03 07:35:35 PM PDT 24 |
| Finished | Jul 03 07:36:01 PM PDT 24 |
| Peak memory | 574176 kb |
| Host | smart-7b71712f-3945-4757-8429-26667394134b |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889736979 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_random_zero_del ays.1889736979 |
| Directory | /workspace/73.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_same_source.4001606490 |
| Short name | T531 |
| Test name | |
| Test status | |
| Simulation time | 1285107046 ps |
| CPU time | 44.36 seconds |
| Started | Jul 03 07:35:37 PM PDT 24 |
| Finished | Jul 03 07:36:23 PM PDT 24 |
| Peak memory | 574116 kb |
| Host | smart-4b77089a-4b68-4e9a-aea6-fafc4ece2c05 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4001606490 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_same_source.4001606490 |
| Directory | /workspace/73.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_smoke.803191540 |
| Short name | T1363 |
| Test name | |
| Test status | |
| Simulation time | 138219613 ps |
| CPU time | 7.69 seconds |
| Started | Jul 03 07:35:25 PM PDT 24 |
| Finished | Jul 03 07:35:33 PM PDT 24 |
| Peak memory | 573988 kb |
| Host | smart-ac03dae8-365e-43ae-b379-edc6419abd05 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=803191540 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_smoke.803191540 |
| Directory | /workspace/73.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_smoke_large_delays.2527989631 |
| Short name | T2292 |
| Test name | |
| Test status | |
| Simulation time | 4810031292 ps |
| CPU time | 50.33 seconds |
| Started | Jul 03 07:35:31 PM PDT 24 |
| Finished | Jul 03 07:36:22 PM PDT 24 |
| Peak memory | 573148 kb |
| Host | smart-7070c48c-fee3-4595-9540-9514ce10e29c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2527989631 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_smoke_large_delays.2527989631 |
| Directory | /workspace/73.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_smoke_slow_rsp.1605803443 |
| Short name | T1449 |
| Test name | |
| Test status | |
| Simulation time | 4952472413 ps |
| CPU time | 89.69 seconds |
| Started | Jul 03 07:35:35 PM PDT 24 |
| Finished | Jul 03 07:37:05 PM PDT 24 |
| Peak memory | 573180 kb |
| Host | smart-141201d9-895b-4164-9cef-a59fc4ee7ecb |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605803443 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_smoke_slow_rsp.1605803443 |
| Directory | /workspace/73.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_smoke_zero_delays.3218504600 |
| Short name | T1950 |
| Test name | |
| Test status | |
| Simulation time | 43576220 ps |
| CPU time | 6 seconds |
| Started | Jul 03 07:35:32 PM PDT 24 |
| Finished | Jul 03 07:35:39 PM PDT 24 |
| Peak memory | 573176 kb |
| Host | smart-82caf358-9edd-4ad9-8347-3fc8cce8b4c7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3218504600 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_smoke_zero_delay s.3218504600 |
| Directory | /workspace/73.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_stress_all.170622244 |
| Short name | T483 |
| Test name | |
| Test status | |
| Simulation time | 7504075919 ps |
| CPU time | 304.94 seconds |
| Started | Jul 03 07:35:38 PM PDT 24 |
| Finished | Jul 03 07:40:44 PM PDT 24 |
| Peak memory | 574204 kb |
| Host | smart-b99e0ab5-acd6-4e7a-8a75-4c59d3896852 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=170622244 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_stress_all.170622244 |
| Directory | /workspace/73.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_stress_all_with_error.1003616640 |
| Short name | T2506 |
| Test name | |
| Test status | |
| Simulation time | 953013098 ps |
| CPU time | 67.63 seconds |
| Started | Jul 03 07:35:37 PM PDT 24 |
| Finished | Jul 03 07:36:47 PM PDT 24 |
| Peak memory | 574100 kb |
| Host | smart-a62f0673-3e16-405c-aa5e-53fd3131ae09 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1003616640 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_stress_all_with_error.1003616640 |
| Directory | /workspace/73.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_stress_all_with_rand_reset.3049077693 |
| Short name | T480 |
| Test name | |
| Test status | |
| Simulation time | 6263987001 ps |
| CPU time | 287.52 seconds |
| Started | Jul 03 07:35:36 PM PDT 24 |
| Finished | Jul 03 07:40:24 PM PDT 24 |
| Peak memory | 574672 kb |
| Host | smart-f0d347c6-14b8-47b9-808e-8ddeb3e1f8a3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3049077693 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_stress_all _with_rand_reset.3049077693 |
| Directory | /workspace/73.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_stress_all_with_reset_error.582348576 |
| Short name | T2848 |
| Test name | |
| Test status | |
| Simulation time | 227456682 ps |
| CPU time | 130.54 seconds |
| Started | Jul 03 07:35:38 PM PDT 24 |
| Finished | Jul 03 07:37:50 PM PDT 24 |
| Peak memory | 574628 kb |
| Host | smart-5b72733c-09ec-412d-b1f4-304ec98348f4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582348576 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_stress_all _with_reset_error.582348576 |
| Directory | /workspace/73.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_unmapped_addr.711505241 |
| Short name | T2667 |
| Test name | |
| Test status | |
| Simulation time | 424177558 ps |
| CPU time | 18.76 seconds |
| Started | Jul 03 07:35:38 PM PDT 24 |
| Finished | Jul 03 07:35:58 PM PDT 24 |
| Peak memory | 574132 kb |
| Host | smart-de907289-bd2e-4cc9-be8c-41e8e703ef4b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=711505241 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_unmapped_addr.711505241 |
| Directory | /workspace/73.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_access_same_device.589581196 |
| Short name | T2477 |
| Test name | |
| Test status | |
| Simulation time | 2824004661 ps |
| CPU time | 119.38 seconds |
| Started | Jul 03 07:35:42 PM PDT 24 |
| Finished | Jul 03 07:37:42 PM PDT 24 |
| Peak memory | 574268 kb |
| Host | smart-f0b7d85b-4102-4274-8551-0a8745e2b3e6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589581196 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_access_same_device. 589581196 |
| Directory | /workspace/74.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_access_same_device_slow_rsp.751160906 |
| Short name | T1445 |
| Test name | |
| Test status | |
| Simulation time | 30040683641 ps |
| CPU time | 561.83 seconds |
| Started | Jul 03 07:35:41 PM PDT 24 |
| Finished | Jul 03 07:45:03 PM PDT 24 |
| Peak memory | 574288 kb |
| Host | smart-264530e5-fa8d-476f-b6ee-eab917b153c9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=751160906 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_access_same_d evice_slow_rsp.751160906 |
| Directory | /workspace/74.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_error_and_unmapped_addr.4156971234 |
| Short name | T2033 |
| Test name | |
| Test status | |
| Simulation time | 148800931 ps |
| CPU time | 16.61 seconds |
| Started | Jul 03 07:35:48 PM PDT 24 |
| Finished | Jul 03 07:36:05 PM PDT 24 |
| Peak memory | 574436 kb |
| Host | smart-17b53510-3cbd-4f54-91f7-bbe655d331ac |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4156971234 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_error_and_unmapped_add r.4156971234 |
| Directory | /workspace/74.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_error_random.3360597543 |
| Short name | T250 |
| Test name | |
| Test status | |
| Simulation time | 1890268345 ps |
| CPU time | 70.34 seconds |
| Started | Jul 03 07:35:47 PM PDT 24 |
| Finished | Jul 03 07:36:58 PM PDT 24 |
| Peak memory | 574448 kb |
| Host | smart-d94b3a01-b44f-4f8a-803a-5a757886f230 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3360597543 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_error_random.3360597543 |
| Directory | /workspace/74.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_random.24311736 |
| Short name | T2159 |
| Test name | |
| Test status | |
| Simulation time | 1005964868 ps |
| CPU time | 35.65 seconds |
| Started | Jul 03 07:35:45 PM PDT 24 |
| Finished | Jul 03 07:36:22 PM PDT 24 |
| Peak memory | 574232 kb |
| Host | smart-10f03401-d099-4cba-ad14-ecde583c1cd1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24311736 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_random.24311736 |
| Directory | /workspace/74.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_random_large_delays.1591580025 |
| Short name | T1389 |
| Test name | |
| Test status | |
| Simulation time | 36633059718 ps |
| CPU time | 394.14 seconds |
| Started | Jul 03 07:35:41 PM PDT 24 |
| Finished | Jul 03 07:42:16 PM PDT 24 |
| Peak memory | 574260 kb |
| Host | smart-8d7504fc-e554-4924-bdc1-0b47aa7dd5b4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1591580025 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_random_large_delays.1591580025 |
| Directory | /workspace/74.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_random_slow_rsp.1406380654 |
| Short name | T1690 |
| Test name | |
| Test status | |
| Simulation time | 35691445355 ps |
| CPU time | 611 seconds |
| Started | Jul 03 07:35:42 PM PDT 24 |
| Finished | Jul 03 07:45:54 PM PDT 24 |
| Peak memory | 574288 kb |
| Host | smart-878b1aa0-ce0c-4234-ade1-b0f9de8b7ad1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1406380654 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_random_slow_rsp.1406380654 |
| Directory | /workspace/74.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_random_zero_delays.1788368886 |
| Short name | T2850 |
| Test name | |
| Test status | |
| Simulation time | 576989056 ps |
| CPU time | 50.18 seconds |
| Started | Jul 03 07:35:45 PM PDT 24 |
| Finished | Jul 03 07:36:36 PM PDT 24 |
| Peak memory | 574192 kb |
| Host | smart-645eebb2-9421-4ece-8f8b-f4b09070f5cc |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1788368886 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_random_zero_del ays.1788368886 |
| Directory | /workspace/74.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_same_source.2475880976 |
| Short name | T1651 |
| Test name | |
| Test status | |
| Simulation time | 433254594 ps |
| CPU time | 30.01 seconds |
| Started | Jul 03 07:35:42 PM PDT 24 |
| Finished | Jul 03 07:36:12 PM PDT 24 |
| Peak memory | 574244 kb |
| Host | smart-48689026-509e-461b-9207-b62b7362bd54 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475880976 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_same_source.2475880976 |
| Directory | /workspace/74.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_smoke.2629306024 |
| Short name | T2115 |
| Test name | |
| Test status | |
| Simulation time | 121308106 ps |
| CPU time | 7.43 seconds |
| Started | Jul 03 07:35:38 PM PDT 24 |
| Finished | Jul 03 07:35:47 PM PDT 24 |
| Peak memory | 574196 kb |
| Host | smart-3d252f87-82d0-4193-85ac-5f79a709f1da |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2629306024 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_smoke.2629306024 |
| Directory | /workspace/74.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_smoke_large_delays.448731574 |
| Short name | T2138 |
| Test name | |
| Test status | |
| Simulation time | 9447436583 ps |
| CPU time | 94.17 seconds |
| Started | Jul 03 07:35:38 PM PDT 24 |
| Finished | Jul 03 07:37:14 PM PDT 24 |
| Peak memory | 573240 kb |
| Host | smart-9c3ae124-9fe7-41f8-b744-9652c1ef4744 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=448731574 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_smoke_large_delays.448731574 |
| Directory | /workspace/74.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_smoke_slow_rsp.336084056 |
| Short name | T1922 |
| Test name | |
| Test status | |
| Simulation time | 4486190654 ps |
| CPU time | 72.82 seconds |
| Started | Jul 03 07:35:37 PM PDT 24 |
| Finished | Jul 03 07:36:52 PM PDT 24 |
| Peak memory | 573032 kb |
| Host | smart-cb036b8d-b72f-4bc1-923c-6505587ce674 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=336084056 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_smoke_slow_rsp.336084056 |
| Directory | /workspace/74.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_smoke_zero_delays.2319531193 |
| Short name | T2015 |
| Test name | |
| Test status | |
| Simulation time | 48211675 ps |
| CPU time | 6.44 seconds |
| Started | Jul 03 07:35:37 PM PDT 24 |
| Finished | Jul 03 07:35:46 PM PDT 24 |
| Peak memory | 573888 kb |
| Host | smart-c82dc5ac-410d-4848-a074-668691e184eb |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2319531193 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_smoke_zero_delay s.2319531193 |
| Directory | /workspace/74.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_stress_all.414034257 |
| Short name | T2529 |
| Test name | |
| Test status | |
| Simulation time | 3636394587 ps |
| CPU time | 114.37 seconds |
| Started | Jul 03 07:35:46 PM PDT 24 |
| Finished | Jul 03 07:37:41 PM PDT 24 |
| Peak memory | 574312 kb |
| Host | smart-4977d3df-e187-4a65-83b9-c23bd639e00e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=414034257 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_stress_all.414034257 |
| Directory | /workspace/74.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_stress_all_with_error.2862141405 |
| Short name | T2376 |
| Test name | |
| Test status | |
| Simulation time | 1041334243 ps |
| CPU time | 76.56 seconds |
| Started | Jul 03 07:35:49 PM PDT 24 |
| Finished | Jul 03 07:37:06 PM PDT 24 |
| Peak memory | 574480 kb |
| Host | smart-d6b7db5d-16a3-4eb8-a91b-f8a1fca119ab |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2862141405 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_stress_all_with_error.2862141405 |
| Directory | /workspace/74.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_stress_all_with_rand_reset.1918531716 |
| Short name | T1471 |
| Test name | |
| Test status | |
| Simulation time | 3917613977 ps |
| CPU time | 224.41 seconds |
| Started | Jul 03 07:35:48 PM PDT 24 |
| Finished | Jul 03 07:39:33 PM PDT 24 |
| Peak memory | 574700 kb |
| Host | smart-85fb7753-8170-4bf1-ae5c-4d06debb3082 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1918531716 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_stress_all _with_rand_reset.1918531716 |
| Directory | /workspace/74.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_stress_all_with_reset_error.3719454707 |
| Short name | T1359 |
| Test name | |
| Test status | |
| Simulation time | 305985107 ps |
| CPU time | 85.7 seconds |
| Started | Jul 03 07:35:49 PM PDT 24 |
| Finished | Jul 03 07:37:16 PM PDT 24 |
| Peak memory | 574660 kb |
| Host | smart-5214ee03-659b-4acc-aeb0-61509fbc0697 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3719454707 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_stress_al l_with_reset_error.3719454707 |
| Directory | /workspace/74.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_unmapped_addr.550091229 |
| Short name | T1637 |
| Test name | |
| Test status | |
| Simulation time | 1171801284 ps |
| CPU time | 48.63 seconds |
| Started | Jul 03 07:35:47 PM PDT 24 |
| Finished | Jul 03 07:36:37 PM PDT 24 |
| Peak memory | 574060 kb |
| Host | smart-a29b6d55-cb9b-4fb9-9500-0f16e1390754 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550091229 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_unmapped_addr.550091229 |
| Directory | /workspace/74.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_access_same_device.1727818411 |
| Short name | T2072 |
| Test name | |
| Test status | |
| Simulation time | 507588435 ps |
| CPU time | 25.51 seconds |
| Started | Jul 03 07:35:59 PM PDT 24 |
| Finished | Jul 03 07:36:26 PM PDT 24 |
| Peak memory | 573980 kb |
| Host | smart-586c2a79-d498-408a-91d7-8a35174ba2be |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1727818411 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_access_same_device .1727818411 |
| Directory | /workspace/75.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_access_same_device_slow_rsp.1236986194 |
| Short name | T2626 |
| Test name | |
| Test status | |
| Simulation time | 56481526851 ps |
| CPU time | 1035.24 seconds |
| Started | Jul 03 07:36:01 PM PDT 24 |
| Finished | Jul 03 07:53:18 PM PDT 24 |
| Peak memory | 574056 kb |
| Host | smart-6e22ac2b-7e07-4f36-a83b-ac2c765b19e0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1236986194 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_access_same_ device_slow_rsp.1236986194 |
| Directory | /workspace/75.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_error_and_unmapped_addr.965012841 |
| Short name | T2889 |
| Test name | |
| Test status | |
| Simulation time | 458532087 ps |
| CPU time | 19.82 seconds |
| Started | Jul 03 07:35:59 PM PDT 24 |
| Finished | Jul 03 07:36:19 PM PDT 24 |
| Peak memory | 574420 kb |
| Host | smart-d701ca37-0d7f-4c02-a72f-8f1d44a8a01d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=965012841 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_error_and_unmapped_addr .965012841 |
| Directory | /workspace/75.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_error_random.2801967750 |
| Short name | T2780 |
| Test name | |
| Test status | |
| Simulation time | 702975083 ps |
| CPU time | 24.21 seconds |
| Started | Jul 03 07:35:58 PM PDT 24 |
| Finished | Jul 03 07:36:23 PM PDT 24 |
| Peak memory | 574560 kb |
| Host | smart-13a397c1-c08c-4404-8917-807d78c3d1a9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2801967750 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_error_random.2801967750 |
| Directory | /workspace/75.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_random.722063722 |
| Short name | T1507 |
| Test name | |
| Test status | |
| Simulation time | 1205119869 ps |
| CPU time | 43.59 seconds |
| Started | Jul 03 07:35:53 PM PDT 24 |
| Finished | Jul 03 07:36:37 PM PDT 24 |
| Peak memory | 573940 kb |
| Host | smart-4386f4d5-e7ed-4709-8239-e48d8a58c51b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=722063722 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_random.722063722 |
| Directory | /workspace/75.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_random_large_delays.1690867976 |
| Short name | T2541 |
| Test name | |
| Test status | |
| Simulation time | 46760129764 ps |
| CPU time | 465.38 seconds |
| Started | Jul 03 07:35:53 PM PDT 24 |
| Finished | Jul 03 07:43:39 PM PDT 24 |
| Peak memory | 574316 kb |
| Host | smart-6dd7b8c4-0a96-409c-ab61-8260b612486d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1690867976 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_random_large_delays.1690867976 |
| Directory | /workspace/75.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_random_slow_rsp.1807326780 |
| Short name | T1778 |
| Test name | |
| Test status | |
| Simulation time | 7243865944 ps |
| CPU time | 121.04 seconds |
| Started | Jul 03 07:35:51 PM PDT 24 |
| Finished | Jul 03 07:37:53 PM PDT 24 |
| Peak memory | 574040 kb |
| Host | smart-68e57d10-3a27-4cfa-987f-32428851ef8c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1807326780 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_random_slow_rsp.1807326780 |
| Directory | /workspace/75.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_random_zero_delays.1111919900 |
| Short name | T1770 |
| Test name | |
| Test status | |
| Simulation time | 82968056 ps |
| CPU time | 11.02 seconds |
| Started | Jul 03 07:35:54 PM PDT 24 |
| Finished | Jul 03 07:36:05 PM PDT 24 |
| Peak memory | 574000 kb |
| Host | smart-b22de794-ff59-40af-975d-3012179d1ddb |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1111919900 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_random_zero_del ays.1111919900 |
| Directory | /workspace/75.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_same_source.663938957 |
| Short name | T2616 |
| Test name | |
| Test status | |
| Simulation time | 109435552 ps |
| CPU time | 9.42 seconds |
| Started | Jul 03 07:36:01 PM PDT 24 |
| Finished | Jul 03 07:36:11 PM PDT 24 |
| Peak memory | 574180 kb |
| Host | smart-22dc61a4-cf5a-4fbd-a1b6-dff2bb33e981 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=663938957 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_same_source.663938957 |
| Directory | /workspace/75.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_smoke.421568116 |
| Short name | T1334 |
| Test name | |
| Test status | |
| Simulation time | 210302819 ps |
| CPU time | 9.77 seconds |
| Started | Jul 03 07:35:53 PM PDT 24 |
| Finished | Jul 03 07:36:04 PM PDT 24 |
| Peak memory | 573160 kb |
| Host | smart-08e7ce43-103d-4f61-a8e6-d622b37a7c68 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=421568116 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_smoke.421568116 |
| Directory | /workspace/75.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_smoke_large_delays.2481631963 |
| Short name | T1574 |
| Test name | |
| Test status | |
| Simulation time | 9366770304 ps |
| CPU time | 96.99 seconds |
| Started | Jul 03 07:35:52 PM PDT 24 |
| Finished | Jul 03 07:37:30 PM PDT 24 |
| Peak memory | 573204 kb |
| Host | smart-ce1d4d61-9373-4671-86bf-24436f2ca7f7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481631963 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_smoke_large_delays.2481631963 |
| Directory | /workspace/75.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_smoke_slow_rsp.2044232738 |
| Short name | T2568 |
| Test name | |
| Test status | |
| Simulation time | 5468887610 ps |
| CPU time | 95.47 seconds |
| Started | Jul 03 07:35:52 PM PDT 24 |
| Finished | Jul 03 07:37:28 PM PDT 24 |
| Peak memory | 573132 kb |
| Host | smart-11e36249-0090-4dc3-a6ab-5aef853fac69 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2044232738 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_smoke_slow_rsp.2044232738 |
| Directory | /workspace/75.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_smoke_zero_delays.2234396083 |
| Short name | T1728 |
| Test name | |
| Test status | |
| Simulation time | 44453576 ps |
| CPU time | 6.55 seconds |
| Started | Jul 03 07:35:52 PM PDT 24 |
| Finished | Jul 03 07:35:59 PM PDT 24 |
| Peak memory | 573044 kb |
| Host | smart-32159555-b4fd-4e66-89c5-b849134c0e56 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2234396083 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_smoke_zero_delay s.2234396083 |
| Directory | /workspace/75.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_stress_all.441735104 |
| Short name | T2410 |
| Test name | |
| Test status | |
| Simulation time | 1628262163 ps |
| CPU time | 57.32 seconds |
| Started | Jul 03 07:35:58 PM PDT 24 |
| Finished | Jul 03 07:36:56 PM PDT 24 |
| Peak memory | 574096 kb |
| Host | smart-746122bb-6450-4cfd-bb35-880d49e90714 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=441735104 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_stress_all.441735104 |
| Directory | /workspace/75.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_stress_all_with_error.1500994757 |
| Short name | T1965 |
| Test name | |
| Test status | |
| Simulation time | 872508670 ps |
| CPU time | 73.75 seconds |
| Started | Jul 03 07:36:01 PM PDT 24 |
| Finished | Jul 03 07:37:16 PM PDT 24 |
| Peak memory | 574168 kb |
| Host | smart-493a2027-8413-4122-a8e8-6e97c890c328 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1500994757 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_stress_all_with_error.1500994757 |
| Directory | /workspace/75.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_stress_all_with_rand_reset.2515841067 |
| Short name | T1970 |
| Test name | |
| Test status | |
| Simulation time | 450402723 ps |
| CPU time | 139.93 seconds |
| Started | Jul 03 07:36:02 PM PDT 24 |
| Finished | Jul 03 07:38:22 PM PDT 24 |
| Peak memory | 574608 kb |
| Host | smart-0bfed858-f51b-46f5-9b25-eae3f05329ca |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2515841067 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_stress_all _with_rand_reset.2515841067 |
| Directory | /workspace/75.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_stress_all_with_reset_error.2978669304 |
| Short name | T1672 |
| Test name | |
| Test status | |
| Simulation time | 28786580 ps |
| CPU time | 10.52 seconds |
| Started | Jul 03 07:36:01 PM PDT 24 |
| Finished | Jul 03 07:36:13 PM PDT 24 |
| Peak memory | 573556 kb |
| Host | smart-c2017ad4-3811-4df8-a487-c6bf71f7893d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2978669304 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_stress_al l_with_reset_error.2978669304 |
| Directory | /workspace/75.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_unmapped_addr.934200171 |
| Short name | T1383 |
| Test name | |
| Test status | |
| Simulation time | 452465911 ps |
| CPU time | 23.13 seconds |
| Started | Jul 03 07:36:03 PM PDT 24 |
| Finished | Jul 03 07:36:26 PM PDT 24 |
| Peak memory | 574172 kb |
| Host | smart-ae07119a-cdc3-4531-89dc-9494f092e780 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=934200171 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_unmapped_addr.934200171 |
| Directory | /workspace/75.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_access_same_device.3030951815 |
| Short name | T2861 |
| Test name | |
| Test status | |
| Simulation time | 601404710 ps |
| CPU time | 57.43 seconds |
| Started | Jul 03 07:36:01 PM PDT 24 |
| Finished | Jul 03 07:36:58 PM PDT 24 |
| Peak memory | 574284 kb |
| Host | smart-086409b4-08fe-416a-b1f5-7440d77518ca |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3030951815 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_access_same_device .3030951815 |
| Directory | /workspace/76.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_access_same_device_slow_rsp.2276824754 |
| Short name | T2297 |
| Test name | |
| Test status | |
| Simulation time | 103135777038 ps |
| CPU time | 1871.44 seconds |
| Started | Jul 03 07:36:02 PM PDT 24 |
| Finished | Jul 03 08:07:14 PM PDT 24 |
| Peak memory | 574492 kb |
| Host | smart-d57d2f97-7a3a-487e-8436-297c7da98447 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2276824754 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_access_same_ device_slow_rsp.2276824754 |
| Directory | /workspace/76.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_error_and_unmapped_addr.2192399118 |
| Short name | T2482 |
| Test name | |
| Test status | |
| Simulation time | 432853955 ps |
| CPU time | 19.99 seconds |
| Started | Jul 03 07:36:09 PM PDT 24 |
| Finished | Jul 03 07:36:31 PM PDT 24 |
| Peak memory | 574472 kb |
| Host | smart-fb61ab6b-d110-47b6-93ae-b1cfd68ef868 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2192399118 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_error_and_unmapped_add r.2192399118 |
| Directory | /workspace/76.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_error_random.567657730 |
| Short name | T1933 |
| Test name | |
| Test status | |
| Simulation time | 2161872008 ps |
| CPU time | 71.51 seconds |
| Started | Jul 03 07:36:05 PM PDT 24 |
| Finished | Jul 03 07:37:17 PM PDT 24 |
| Peak memory | 574144 kb |
| Host | smart-31657aec-23f4-4e96-8534-97a28b801b65 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=567657730 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_error_random.567657730 |
| Directory | /workspace/76.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_random.1103491876 |
| Short name | T2793 |
| Test name | |
| Test status | |
| Simulation time | 1456064455 ps |
| CPU time | 51.4 seconds |
| Started | Jul 03 07:36:03 PM PDT 24 |
| Finished | Jul 03 07:36:55 PM PDT 24 |
| Peak memory | 574108 kb |
| Host | smart-a9deb335-b7bf-4d2a-ac39-931fdfa69935 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1103491876 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_random.1103491876 |
| Directory | /workspace/76.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_random_large_delays.2383159908 |
| Short name | T2563 |
| Test name | |
| Test status | |
| Simulation time | 104324421149 ps |
| CPU time | 1129.79 seconds |
| Started | Jul 03 07:36:06 PM PDT 24 |
| Finished | Jul 03 07:54:57 PM PDT 24 |
| Peak memory | 574044 kb |
| Host | smart-48ae9b44-d0fc-454f-b157-427af1f83fca |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383159908 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_random_large_delays.2383159908 |
| Directory | /workspace/76.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_random_slow_rsp.2036518649 |
| Short name | T1949 |
| Test name | |
| Test status | |
| Simulation time | 46271233287 ps |
| CPU time | 780.69 seconds |
| Started | Jul 03 07:36:03 PM PDT 24 |
| Finished | Jul 03 07:49:04 PM PDT 24 |
| Peak memory | 574268 kb |
| Host | smart-949b8a97-c9a5-4e5a-929a-6e401a36fb3b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2036518649 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_random_slow_rsp.2036518649 |
| Directory | /workspace/76.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_random_zero_delays.1772568732 |
| Short name | T1773 |
| Test name | |
| Test status | |
| Simulation time | 612565047 ps |
| CPU time | 47.93 seconds |
| Started | Jul 03 07:36:05 PM PDT 24 |
| Finished | Jul 03 07:36:53 PM PDT 24 |
| Peak memory | 574168 kb |
| Host | smart-f66022dc-f8d8-44db-a00c-ee6e8974990c |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1772568732 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_random_zero_del ays.1772568732 |
| Directory | /workspace/76.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_same_source.941887698 |
| Short name | T554 |
| Test name | |
| Test status | |
| Simulation time | 437051090 ps |
| CPU time | 37.38 seconds |
| Started | Jul 03 07:36:02 PM PDT 24 |
| Finished | Jul 03 07:36:40 PM PDT 24 |
| Peak memory | 574196 kb |
| Host | smart-cbd8a2a6-5b67-4f40-9265-c995de9dce6f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=941887698 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_same_source.941887698 |
| Directory | /workspace/76.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_smoke.3937633028 |
| Short name | T1533 |
| Test name | |
| Test status | |
| Simulation time | 254083239 ps |
| CPU time | 9.81 seconds |
| Started | Jul 03 07:36:02 PM PDT 24 |
| Finished | Jul 03 07:36:12 PM PDT 24 |
| Peak memory | 572912 kb |
| Host | smart-a647cc5f-7b17-4430-b27e-d5fd9af7591a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3937633028 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_smoke.3937633028 |
| Directory | /workspace/76.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_smoke_large_delays.3573653042 |
| Short name | T2214 |
| Test name | |
| Test status | |
| Simulation time | 8858252293 ps |
| CPU time | 94.19 seconds |
| Started | Jul 03 07:35:59 PM PDT 24 |
| Finished | Jul 03 07:37:34 PM PDT 24 |
| Peak memory | 574040 kb |
| Host | smart-62857d03-7990-494f-9fb2-fc664be8437e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3573653042 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_smoke_large_delays.3573653042 |
| Directory | /workspace/76.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_smoke_slow_rsp.260120725 |
| Short name | T2509 |
| Test name | |
| Test status | |
| Simulation time | 5858433217 ps |
| CPU time | 103.42 seconds |
| Started | Jul 03 07:36:01 PM PDT 24 |
| Finished | Jul 03 07:37:45 PM PDT 24 |
| Peak memory | 574024 kb |
| Host | smart-28919d8e-bdc7-45c4-8fac-3c19429d0cac |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=260120725 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_smoke_slow_rsp.260120725 |
| Directory | /workspace/76.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_smoke_zero_delays.881326044 |
| Short name | T2726 |
| Test name | |
| Test status | |
| Simulation time | 54328865 ps |
| CPU time | 6.52 seconds |
| Started | Jul 03 07:35:56 PM PDT 24 |
| Finished | Jul 03 07:36:03 PM PDT 24 |
| Peak memory | 573140 kb |
| Host | smart-23799c37-42b1-4af0-bd7f-6bc4006a663d |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=881326044 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_smoke_zero_delays .881326044 |
| Directory | /workspace/76.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_stress_all.1063153785 |
| Short name | T2202 |
| Test name | |
| Test status | |
| Simulation time | 13025941181 ps |
| CPU time | 439.17 seconds |
| Started | Jul 03 07:36:08 PM PDT 24 |
| Finished | Jul 03 07:43:30 PM PDT 24 |
| Peak memory | 574728 kb |
| Host | smart-d76f5fb8-dbc6-4ec2-9179-a4725f26b1c4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1063153785 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_stress_all.1063153785 |
| Directory | /workspace/76.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_stress_all_with_error.210961546 |
| Short name | T2353 |
| Test name | |
| Test status | |
| Simulation time | 2809809247 ps |
| CPU time | 199.15 seconds |
| Started | Jul 03 07:36:08 PM PDT 24 |
| Finished | Jul 03 07:39:29 PM PDT 24 |
| Peak memory | 574732 kb |
| Host | smart-55e38f5b-ab7e-4c96-be45-c4337ce5a0fe |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=210961546 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_stress_all_with_error.210961546 |
| Directory | /workspace/76.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_stress_all_with_rand_reset.2035494262 |
| Short name | T2063 |
| Test name | |
| Test status | |
| Simulation time | 152850732 ps |
| CPU time | 32.17 seconds |
| Started | Jul 03 07:36:08 PM PDT 24 |
| Finished | Jul 03 07:36:42 PM PDT 24 |
| Peak memory | 574504 kb |
| Host | smart-0b76c7a9-2ae1-44a3-8f11-53278b5c6d26 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2035494262 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_stress_all _with_rand_reset.2035494262 |
| Directory | /workspace/76.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_unmapped_addr.414493458 |
| Short name | T2133 |
| Test name | |
| Test status | |
| Simulation time | 149956675 ps |
| CPU time | 18.27 seconds |
| Started | Jul 03 07:36:09 PM PDT 24 |
| Finished | Jul 03 07:36:29 PM PDT 24 |
| Peak memory | 574288 kb |
| Host | smart-f4afc507-4601-43cf-938a-a8f9c0f1ceaf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=414493458 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_unmapped_addr.414493458 |
| Directory | /workspace/76.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_access_same_device.1611058816 |
| Short name | T1610 |
| Test name | |
| Test status | |
| Simulation time | 604404240 ps |
| CPU time | 31.47 seconds |
| Started | Jul 03 07:36:14 PM PDT 24 |
| Finished | Jul 03 07:36:46 PM PDT 24 |
| Peak memory | 574004 kb |
| Host | smart-836da58b-467d-450c-b21d-a2ea8c1ee4b2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1611058816 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_access_same_device .1611058816 |
| Directory | /workspace/77.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_access_same_device_slow_rsp.1646250014 |
| Short name | T2725 |
| Test name | |
| Test status | |
| Simulation time | 58081552618 ps |
| CPU time | 1126.17 seconds |
| Started | Jul 03 07:36:21 PM PDT 24 |
| Finished | Jul 03 07:55:08 PM PDT 24 |
| Peak memory | 574176 kb |
| Host | smart-9c3e96a5-dbb3-4504-8a90-c96441029cc1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1646250014 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_access_same_ device_slow_rsp.1646250014 |
| Directory | /workspace/77.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_error_and_unmapped_addr.32378439 |
| Short name | T1616 |
| Test name | |
| Test status | |
| Simulation time | 857192843 ps |
| CPU time | 29.15 seconds |
| Started | Jul 03 07:36:21 PM PDT 24 |
| Finished | Jul 03 07:36:51 PM PDT 24 |
| Peak memory | 574328 kb |
| Host | smart-ab443d61-bede-4a70-a436-cc064291a9eb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32378439 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_error_and_unmapped_addr.32378439 |
| Directory | /workspace/77.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_error_random.317431475 |
| Short name | T2866 |
| Test name | |
| Test status | |
| Simulation time | 408563472 ps |
| CPU time | 33.23 seconds |
| Started | Jul 03 07:36:19 PM PDT 24 |
| Finished | Jul 03 07:36:54 PM PDT 24 |
| Peak memory | 573984 kb |
| Host | smart-dd62aaac-142d-4c17-8e27-8d2acd91656a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317431475 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_error_random.317431475 |
| Directory | /workspace/77.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_random.2548588709 |
| Short name | T1812 |
| Test name | |
| Test status | |
| Simulation time | 444809591 ps |
| CPU time | 39.28 seconds |
| Started | Jul 03 07:36:14 PM PDT 24 |
| Finished | Jul 03 07:36:54 PM PDT 24 |
| Peak memory | 574008 kb |
| Host | smart-ce053042-d430-4296-bb8c-493c0ba3e3a2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2548588709 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_random.2548588709 |
| Directory | /workspace/77.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_random_large_delays.3966288237 |
| Short name | T2465 |
| Test name | |
| Test status | |
| Simulation time | 48489758929 ps |
| CPU time | 526.23 seconds |
| Started | Jul 03 07:36:12 PM PDT 24 |
| Finished | Jul 03 07:44:59 PM PDT 24 |
| Peak memory | 574216 kb |
| Host | smart-725f1fdd-3e74-463e-92a4-545250869c15 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3966288237 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_random_large_delays.3966288237 |
| Directory | /workspace/77.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_random_slow_rsp.243956351 |
| Short name | T2522 |
| Test name | |
| Test status | |
| Simulation time | 19944456310 ps |
| CPU time | 328.79 seconds |
| Started | Jul 03 07:36:13 PM PDT 24 |
| Finished | Jul 03 07:41:42 PM PDT 24 |
| Peak memory | 574284 kb |
| Host | smart-6670baff-92be-4163-862d-b03a3bda4694 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=243956351 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_random_slow_rsp.243956351 |
| Directory | /workspace/77.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_random_zero_delays.1287478538 |
| Short name | T2265 |
| Test name | |
| Test status | |
| Simulation time | 495622625 ps |
| CPU time | 44.61 seconds |
| Started | Jul 03 07:36:13 PM PDT 24 |
| Finished | Jul 03 07:36:59 PM PDT 24 |
| Peak memory | 574120 kb |
| Host | smart-ca28b5f4-6d10-4658-b1ce-a134517ec088 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287478538 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_random_zero_del ays.1287478538 |
| Directory | /workspace/77.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_same_source.2795040510 |
| Short name | T1605 |
| Test name | |
| Test status | |
| Simulation time | 441910684 ps |
| CPU time | 30.99 seconds |
| Started | Jul 03 07:36:19 PM PDT 24 |
| Finished | Jul 03 07:36:51 PM PDT 24 |
| Peak memory | 574160 kb |
| Host | smart-ae7d9eb9-3c88-4b37-b0fa-629b8f9d3777 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2795040510 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_same_source.2795040510 |
| Directory | /workspace/77.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_smoke.859901088 |
| Short name | T2288 |
| Test name | |
| Test status | |
| Simulation time | 45687521 ps |
| CPU time | 6.16 seconds |
| Started | Jul 03 07:36:14 PM PDT 24 |
| Finished | Jul 03 07:36:21 PM PDT 24 |
| Peak memory | 574172 kb |
| Host | smart-b1fafbfa-36cf-457d-90a1-fc1c7d7553ad |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=859901088 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_smoke.859901088 |
| Directory | /workspace/77.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_smoke_large_delays.3190818920 |
| Short name | T1402 |
| Test name | |
| Test status | |
| Simulation time | 7792979622 ps |
| CPU time | 83.21 seconds |
| Started | Jul 03 07:36:12 PM PDT 24 |
| Finished | Jul 03 07:37:36 PM PDT 24 |
| Peak memory | 573124 kb |
| Host | smart-37e4c2da-42ca-4eee-abc0-a466af1c46e8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3190818920 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_smoke_large_delays.3190818920 |
| Directory | /workspace/77.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_smoke_slow_rsp.274272187 |
| Short name | T1937 |
| Test name | |
| Test status | |
| Simulation time | 5847559057 ps |
| CPU time | 99.45 seconds |
| Started | Jul 03 07:36:17 PM PDT 24 |
| Finished | Jul 03 07:37:57 PM PDT 24 |
| Peak memory | 574000 kb |
| Host | smart-f1e99caf-a9f5-4e28-af00-8b845d83bd95 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274272187 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_smoke_slow_rsp.274272187 |
| Directory | /workspace/77.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_smoke_zero_delays.319552883 |
| Short name | T2067 |
| Test name | |
| Test status | |
| Simulation time | 46372060 ps |
| CPU time | 6.86 seconds |
| Started | Jul 03 07:36:12 PM PDT 24 |
| Finished | Jul 03 07:36:20 PM PDT 24 |
| Peak memory | 573204 kb |
| Host | smart-0ae53582-f8fe-4b50-98cd-7d886bdfc6f2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319552883 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_smoke_zero_delays .319552883 |
| Directory | /workspace/77.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_stress_all.155770584 |
| Short name | T2566 |
| Test name | |
| Test status | |
| Simulation time | 2593333258 ps |
| CPU time | 241.96 seconds |
| Started | Jul 03 07:36:18 PM PDT 24 |
| Finished | Jul 03 07:40:21 PM PDT 24 |
| Peak memory | 574732 kb |
| Host | smart-aa0b4326-7ecf-4cf3-96ea-4cc533358c19 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=155770584 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_stress_all.155770584 |
| Directory | /workspace/77.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_stress_all_with_error.3488370135 |
| Short name | T2731 |
| Test name | |
| Test status | |
| Simulation time | 8597519906 ps |
| CPU time | 346.52 seconds |
| Started | Jul 03 07:36:18 PM PDT 24 |
| Finished | Jul 03 07:42:05 PM PDT 24 |
| Peak memory | 574716 kb |
| Host | smart-41e0729a-1a24-4449-a022-cfe44344d043 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3488370135 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_stress_all_with_error.3488370135 |
| Directory | /workspace/77.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_stress_all_with_rand_reset.546723494 |
| Short name | T459 |
| Test name | |
| Test status | |
| Simulation time | 4782845977 ps |
| CPU time | 702.78 seconds |
| Started | Jul 03 07:36:19 PM PDT 24 |
| Finished | Jul 03 07:48:02 PM PDT 24 |
| Peak memory | 574748 kb |
| Host | smart-2df10d3e-ac54-432c-8e4d-a973aabefdde |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=546723494 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_stress_all_ with_rand_reset.546723494 |
| Directory | /workspace/77.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_stress_all_with_reset_error.93557028 |
| Short name | T1754 |
| Test name | |
| Test status | |
| Simulation time | 233415671 ps |
| CPU time | 64.59 seconds |
| Started | Jul 03 07:36:19 PM PDT 24 |
| Finished | Jul 03 07:37:24 PM PDT 24 |
| Peak memory | 574668 kb |
| Host | smart-c814b38a-2910-4012-bf87-4dc00c5bb4ee |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93557028 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_stress_all_ with_reset_error.93557028 |
| Directory | /workspace/77.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_unmapped_addr.3693693437 |
| Short name | T1351 |
| Test name | |
| Test status | |
| Simulation time | 213087901 ps |
| CPU time | 23.76 seconds |
| Started | Jul 03 07:36:20 PM PDT 24 |
| Finished | Jul 03 07:36:45 PM PDT 24 |
| Peak memory | 574252 kb |
| Host | smart-a47fca3b-8b06-4e04-b58c-a91fff05f3e4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693693437 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_unmapped_addr.3693693437 |
| Directory | /workspace/77.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_access_same_device.135924091 |
| Short name | T2607 |
| Test name | |
| Test status | |
| Simulation time | 1144950784 ps |
| CPU time | 82.07 seconds |
| Started | Jul 03 07:36:26 PM PDT 24 |
| Finished | Jul 03 07:37:49 PM PDT 24 |
| Peak memory | 573984 kb |
| Host | smart-71f5427c-6b71-4081-b33f-028e51135521 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135924091 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_access_same_device. 135924091 |
| Directory | /workspace/78.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_access_same_device_slow_rsp.824877458 |
| Short name | T2792 |
| Test name | |
| Test status | |
| Simulation time | 150031915711 ps |
| CPU time | 2830.68 seconds |
| Started | Jul 03 07:36:23 PM PDT 24 |
| Finished | Jul 03 08:23:35 PM PDT 24 |
| Peak memory | 574108 kb |
| Host | smart-52134f63-d20f-4e01-9c91-361a77d14899 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=824877458 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_access_same_d evice_slow_rsp.824877458 |
| Directory | /workspace/78.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_error_and_unmapped_addr.1452801171 |
| Short name | T1328 |
| Test name | |
| Test status | |
| Simulation time | 1168406011 ps |
| CPU time | 43.26 seconds |
| Started | Jul 03 07:36:28 PM PDT 24 |
| Finished | Jul 03 07:37:12 PM PDT 24 |
| Peak memory | 574508 kb |
| Host | smart-5f390be7-db78-4d78-b6de-90834a43641b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1452801171 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_error_and_unmapped_add r.1452801171 |
| Directory | /workspace/78.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_error_random.2796167629 |
| Short name | T2085 |
| Test name | |
| Test status | |
| Simulation time | 159682653 ps |
| CPU time | 8.59 seconds |
| Started | Jul 03 07:36:27 PM PDT 24 |
| Finished | Jul 03 07:36:36 PM PDT 24 |
| Peak memory | 573424 kb |
| Host | smart-f27389b5-7c3b-4afb-b7ce-ed0b95841cd5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2796167629 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_error_random.2796167629 |
| Directory | /workspace/78.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_random.1389465213 |
| Short name | T493 |
| Test name | |
| Test status | |
| Simulation time | 2010676686 ps |
| CPU time | 71.07 seconds |
| Started | Jul 03 07:36:20 PM PDT 24 |
| Finished | Jul 03 07:37:32 PM PDT 24 |
| Peak memory | 574168 kb |
| Host | smart-a2bd2bbe-4ea2-4984-9cc2-20a34363c68a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1389465213 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_random.1389465213 |
| Directory | /workspace/78.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_random_large_delays.2581595061 |
| Short name | T2406 |
| Test name | |
| Test status | |
| Simulation time | 67024837990 ps |
| CPU time | 663.86 seconds |
| Started | Jul 03 07:36:24 PM PDT 24 |
| Finished | Jul 03 07:47:29 PM PDT 24 |
| Peak memory | 574240 kb |
| Host | smart-8a7b57ea-e2f0-4725-86b9-4e2a0509becd |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581595061 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_random_large_delays.2581595061 |
| Directory | /workspace/78.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_random_slow_rsp.1484735925 |
| Short name | T455 |
| Test name | |
| Test status | |
| Simulation time | 41361099885 ps |
| CPU time | 789.46 seconds |
| Started | Jul 03 07:36:26 PM PDT 24 |
| Finished | Jul 03 07:49:36 PM PDT 24 |
| Peak memory | 574280 kb |
| Host | smart-56c40492-99d8-4071-9fba-8733e1de3e96 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1484735925 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_random_slow_rsp.1484735925 |
| Directory | /workspace/78.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_random_zero_delays.1013307255 |
| Short name | T541 |
| Test name | |
| Test status | |
| Simulation time | 195671603 ps |
| CPU time | 17.28 seconds |
| Started | Jul 03 07:36:28 PM PDT 24 |
| Finished | Jul 03 07:36:46 PM PDT 24 |
| Peak memory | 574204 kb |
| Host | smart-36d34707-1b09-439c-bdaf-e632904fdb0f |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1013307255 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_random_zero_del ays.1013307255 |
| Directory | /workspace/78.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_same_source.3210038158 |
| Short name | T2261 |
| Test name | |
| Test status | |
| Simulation time | 2305951100 ps |
| CPU time | 58.19 seconds |
| Started | Jul 03 07:36:24 PM PDT 24 |
| Finished | Jul 03 07:37:23 PM PDT 24 |
| Peak memory | 574220 kb |
| Host | smart-34786359-26d3-43f5-893a-b072437ecd9e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210038158 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_same_source.3210038158 |
| Directory | /workspace/78.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_smoke.2104640868 |
| Short name | T1615 |
| Test name | |
| Test status | |
| Simulation time | 43454247 ps |
| CPU time | 6.62 seconds |
| Started | Jul 03 07:36:21 PM PDT 24 |
| Finished | Jul 03 07:36:28 PM PDT 24 |
| Peak memory | 574188 kb |
| Host | smart-fd0faea1-f108-43e8-9ac2-6931286d8d72 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104640868 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_smoke.2104640868 |
| Directory | /workspace/78.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_smoke_large_delays.2520744456 |
| Short name | T2023 |
| Test name | |
| Test status | |
| Simulation time | 6749966948 ps |
| CPU time | 67.37 seconds |
| Started | Jul 03 07:36:21 PM PDT 24 |
| Finished | Jul 03 07:37:29 PM PDT 24 |
| Peak memory | 574020 kb |
| Host | smart-b66f2336-9dcd-4820-a131-258e49a5768e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520744456 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_smoke_large_delays.2520744456 |
| Directory | /workspace/78.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_smoke_slow_rsp.2423747970 |
| Short name | T1419 |
| Test name | |
| Test status | |
| Simulation time | 5718455977 ps |
| CPU time | 93.89 seconds |
| Started | Jul 03 07:36:19 PM PDT 24 |
| Finished | Jul 03 07:37:54 PM PDT 24 |
| Peak memory | 573000 kb |
| Host | smart-30b4d8b6-658a-46b7-be8c-30e6cae93f6c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2423747970 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_smoke_slow_rsp.2423747970 |
| Directory | /workspace/78.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_smoke_zero_delays.344617048 |
| Short name | T1306 |
| Test name | |
| Test status | |
| Simulation time | 55356020 ps |
| CPU time | 6.68 seconds |
| Started | Jul 03 07:36:20 PM PDT 24 |
| Finished | Jul 03 07:36:27 PM PDT 24 |
| Peak memory | 573116 kb |
| Host | smart-89502d52-6d05-4a02-bcd7-f8a293fa1cbf |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344617048 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_smoke_zero_delays .344617048 |
| Directory | /workspace/78.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_stress_all.623520389 |
| Short name | T1487 |
| Test name | |
| Test status | |
| Simulation time | 267215206 ps |
| CPU time | 21.59 seconds |
| Started | Jul 03 07:36:27 PM PDT 24 |
| Finished | Jul 03 07:36:50 PM PDT 24 |
| Peak memory | 574172 kb |
| Host | smart-e374f42d-1da9-49d0-9188-3d7b0423cb47 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623520389 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_stress_all.623520389 |
| Directory | /workspace/78.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_stress_all_with_error.3062041936 |
| Short name | T1462 |
| Test name | |
| Test status | |
| Simulation time | 7430040444 ps |
| CPU time | 274.98 seconds |
| Started | Jul 03 07:36:23 PM PDT 24 |
| Finished | Jul 03 07:40:59 PM PDT 24 |
| Peak memory | 574660 kb |
| Host | smart-4ed818c2-6b2f-4c23-91ac-c42109f1b1af |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3062041936 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_stress_all_with_error.3062041936 |
| Directory | /workspace/78.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_stress_all_with_rand_reset.3650672911 |
| Short name | T2295 |
| Test name | |
| Test status | |
| Simulation time | 310283869 ps |
| CPU time | 137.57 seconds |
| Started | Jul 03 07:36:28 PM PDT 24 |
| Finished | Jul 03 07:38:46 PM PDT 24 |
| Peak memory | 574668 kb |
| Host | smart-b77c4535-322b-4770-b7ce-d3a81ca6cf58 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3650672911 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_stress_all _with_rand_reset.3650672911 |
| Directory | /workspace/78.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_stress_all_with_reset_error.4278665288 |
| Short name | T821 |
| Test name | |
| Test status | |
| Simulation time | 630230475 ps |
| CPU time | 225.18 seconds |
| Started | Jul 03 07:36:27 PM PDT 24 |
| Finished | Jul 03 07:40:13 PM PDT 24 |
| Peak memory | 574624 kb |
| Host | smart-6345aae8-59b2-40ce-9799-e96039fd55fe |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4278665288 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_stress_al l_with_reset_error.4278665288 |
| Directory | /workspace/78.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_unmapped_addr.2937011523 |
| Short name | T1618 |
| Test name | |
| Test status | |
| Simulation time | 177404547 ps |
| CPU time | 20.82 seconds |
| Started | Jul 03 07:36:22 PM PDT 24 |
| Finished | Jul 03 07:36:44 PM PDT 24 |
| Peak memory | 574352 kb |
| Host | smart-737c436f-a99a-447b-b73c-5a252ec49548 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2937011523 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_unmapped_addr.2937011523 |
| Directory | /workspace/78.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_access_same_device_slow_rsp.3507464726 |
| Short name | T2309 |
| Test name | |
| Test status | |
| Simulation time | 97001706866 ps |
| CPU time | 1754 seconds |
| Started | Jul 03 07:36:33 PM PDT 24 |
| Finished | Jul 03 08:05:48 PM PDT 24 |
| Peak memory | 574320 kb |
| Host | smart-ef9762b1-e7ea-4cad-9cfa-174c2c076d2d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3507464726 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_access_same_ device_slow_rsp.3507464726 |
| Directory | /workspace/79.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_error_and_unmapped_addr.2164923875 |
| Short name | T2156 |
| Test name | |
| Test status | |
| Simulation time | 262226269 ps |
| CPU time | 30.83 seconds |
| Started | Jul 03 07:36:34 PM PDT 24 |
| Finished | Jul 03 07:37:06 PM PDT 24 |
| Peak memory | 574432 kb |
| Host | smart-1a30aa47-dd08-40fc-aa4e-9355eed5b3ac |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164923875 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_error_and_unmapped_add r.2164923875 |
| Directory | /workspace/79.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_error_random.3227474617 |
| Short name | T1671 |
| Test name | |
| Test status | |
| Simulation time | 232961358 ps |
| CPU time | 20.52 seconds |
| Started | Jul 03 07:36:34 PM PDT 24 |
| Finished | Jul 03 07:36:56 PM PDT 24 |
| Peak memory | 574408 kb |
| Host | smart-72a77f16-d105-4a09-9755-f64583545067 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3227474617 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_error_random.3227474617 |
| Directory | /workspace/79.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_random.3780531063 |
| Short name | T2018 |
| Test name | |
| Test status | |
| Simulation time | 247824977 ps |
| CPU time | 22.56 seconds |
| Started | Jul 03 07:36:30 PM PDT 24 |
| Finished | Jul 03 07:36:53 PM PDT 24 |
| Peak memory | 573972 kb |
| Host | smart-46914859-9b7f-4e45-9cf4-0d722e9f41d3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3780531063 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_random.3780531063 |
| Directory | /workspace/79.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_random_large_delays.2519006637 |
| Short name | T2558 |
| Test name | |
| Test status | |
| Simulation time | 14626652358 ps |
| CPU time | 144.95 seconds |
| Started | Jul 03 07:36:32 PM PDT 24 |
| Finished | Jul 03 07:38:57 PM PDT 24 |
| Peak memory | 574272 kb |
| Host | smart-2b13c82a-eb4f-4d02-9dfe-609252782ec5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2519006637 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_random_large_delays.2519006637 |
| Directory | /workspace/79.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_random_slow_rsp.2996183683 |
| Short name | T1405 |
| Test name | |
| Test status | |
| Simulation time | 33791480209 ps |
| CPU time | 632.02 seconds |
| Started | Jul 03 07:36:36 PM PDT 24 |
| Finished | Jul 03 07:47:09 PM PDT 24 |
| Peak memory | 573968 kb |
| Host | smart-d3a2778c-0869-4177-9f0d-6f8ee3950073 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2996183683 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_random_slow_rsp.2996183683 |
| Directory | /workspace/79.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_random_zero_delays.3451933662 |
| Short name | T2355 |
| Test name | |
| Test status | |
| Simulation time | 443512335 ps |
| CPU time | 39.69 seconds |
| Started | Jul 03 07:36:29 PM PDT 24 |
| Finished | Jul 03 07:37:09 PM PDT 24 |
| Peak memory | 574244 kb |
| Host | smart-5f4dea68-f799-4d9c-ba11-c18f799d968e |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3451933662 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_random_zero_del ays.3451933662 |
| Directory | /workspace/79.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_same_source.2263765109 |
| Short name | T2682 |
| Test name | |
| Test status | |
| Simulation time | 355540177 ps |
| CPU time | 26.99 seconds |
| Started | Jul 03 07:36:33 PM PDT 24 |
| Finished | Jul 03 07:37:01 PM PDT 24 |
| Peak memory | 573948 kb |
| Host | smart-721fa09a-bdcd-48f3-9346-ff39d46a1b66 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2263765109 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_same_source.2263765109 |
| Directory | /workspace/79.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_smoke.2306420556 |
| Short name | T1997 |
| Test name | |
| Test status | |
| Simulation time | 48930815 ps |
| CPU time | 6.59 seconds |
| Started | Jul 03 07:36:24 PM PDT 24 |
| Finished | Jul 03 07:36:31 PM PDT 24 |
| Peak memory | 574116 kb |
| Host | smart-68c05e3a-7954-42b8-ad2b-cd7b57fea671 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2306420556 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_smoke.2306420556 |
| Directory | /workspace/79.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_smoke_large_delays.2504168883 |
| Short name | T1644 |
| Test name | |
| Test status | |
| Simulation time | 9909075051 ps |
| CPU time | 107.35 seconds |
| Started | Jul 03 07:36:24 PM PDT 24 |
| Finished | Jul 03 07:38:12 PM PDT 24 |
| Peak memory | 573212 kb |
| Host | smart-2b74761d-3214-408f-b9b7-7734d4d19576 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2504168883 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_smoke_large_delays.2504168883 |
| Directory | /workspace/79.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_smoke_slow_rsp.2525889174 |
| Short name | T2520 |
| Test name | |
| Test status | |
| Simulation time | 5416636226 ps |
| CPU time | 96.78 seconds |
| Started | Jul 03 07:36:29 PM PDT 24 |
| Finished | Jul 03 07:38:06 PM PDT 24 |
| Peak memory | 573224 kb |
| Host | smart-da6654dc-20ea-45ca-9f4a-9aa93871223c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2525889174 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_smoke_slow_rsp.2525889174 |
| Directory | /workspace/79.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_smoke_zero_delays.2296991442 |
| Short name | T1913 |
| Test name | |
| Test status | |
| Simulation time | 46286749 ps |
| CPU time | 6.43 seconds |
| Started | Jul 03 07:36:23 PM PDT 24 |
| Finished | Jul 03 07:36:30 PM PDT 24 |
| Peak memory | 574132 kb |
| Host | smart-83f33f46-1fe2-4ae3-a506-a614999254e1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2296991442 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_smoke_zero_delay s.2296991442 |
| Directory | /workspace/79.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_stress_all.9721962 |
| Short name | T2857 |
| Test name | |
| Test status | |
| Simulation time | 1124601210 ps |
| CPU time | 98.35 seconds |
| Started | Jul 03 07:36:36 PM PDT 24 |
| Finished | Jul 03 07:38:15 PM PDT 24 |
| Peak memory | 574636 kb |
| Host | smart-dd10e0ec-b6b3-45f6-86a1-00a40297ec39 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9721962 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_stress_all.9721962 |
| Directory | /workspace/79.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_stress_all_with_error.1342186217 |
| Short name | T549 |
| Test name | |
| Test status | |
| Simulation time | 9277092519 ps |
| CPU time | 330.9 seconds |
| Started | Jul 03 07:36:34 PM PDT 24 |
| Finished | Jul 03 07:42:06 PM PDT 24 |
| Peak memory | 574672 kb |
| Host | smart-9b490d90-a5b0-4602-a649-4f211c212c0e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1342186217 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_stress_all_with_error.1342186217 |
| Directory | /workspace/79.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_stress_all_with_rand_reset.867675514 |
| Short name | T2274 |
| Test name | |
| Test status | |
| Simulation time | 442136040 ps |
| CPU time | 94.26 seconds |
| Started | Jul 03 07:36:34 PM PDT 24 |
| Finished | Jul 03 07:38:09 PM PDT 24 |
| Peak memory | 574716 kb |
| Host | smart-ebdb5d02-356c-44b5-9d57-4342c75f44bb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=867675514 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_stress_all_ with_rand_reset.867675514 |
| Directory | /workspace/79.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_stress_all_with_reset_error.3652334850 |
| Short name | T807 |
| Test name | |
| Test status | |
| Simulation time | 191057212 ps |
| CPU time | 67.06 seconds |
| Started | Jul 03 07:36:39 PM PDT 24 |
| Finished | Jul 03 07:37:47 PM PDT 24 |
| Peak memory | 574636 kb |
| Host | smart-050b1fde-ea64-429e-9f3b-a4e9382fc5ad |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3652334850 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_stress_al l_with_reset_error.3652334850 |
| Directory | /workspace/79.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_unmapped_addr.4238859145 |
| Short name | T2245 |
| Test name | |
| Test status | |
| Simulation time | 456282796 ps |
| CPU time | 20.84 seconds |
| Started | Jul 03 07:36:35 PM PDT 24 |
| Finished | Jul 03 07:36:57 PM PDT 24 |
| Peak memory | 574028 kb |
| Host | smart-c1a5a1ea-2d29-4375-9949-2f94191a9a16 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4238859145 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_unmapped_addr.4238859145 |
| Directory | /workspace/79.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/8.chip_csr_rw.3430864143 |
| Short name | T2445 |
| Test name | |
| Test status | |
| Simulation time | 6350582832 ps |
| CPU time | 717.4 seconds |
| Started | Jul 03 07:23:38 PM PDT 24 |
| Finished | Jul 03 07:35:37 PM PDT 24 |
| Peak memory | 598204 kb |
| Host | smart-03d0750b-128f-4f05-9963-8085b133ff23 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430864143 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.chip_csr_rw.3430864143 |
| Directory | /workspace/8.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/8.chip_same_csr_outstanding.3850582998 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 16362991022 ps |
| CPU time | 1947.24 seconds |
| Started | Jul 03 07:23:21 PM PDT 24 |
| Finished | Jul 03 07:55:50 PM PDT 24 |
| Peak memory | 592160 kb |
| Host | smart-92245599-caaa-4f3c-ad5e-14374077098d |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850582998 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 8.chip_same_csr_outstanding.3850582998 |
| Directory | /workspace/8.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_access_same_device.3369344812 |
| Short name | T2752 |
| Test name | |
| Test status | |
| Simulation time | 747046086 ps |
| CPU time | 49.99 seconds |
| Started | Jul 03 07:23:28 PM PDT 24 |
| Finished | Jul 03 07:24:19 PM PDT 24 |
| Peak memory | 574148 kb |
| Host | smart-99f3c141-8cca-4b5a-9c36-df0aebdbee5b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3369344812 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_access_same_device. 3369344812 |
| Directory | /workspace/8.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_access_same_device_slow_rsp.362111005 |
| Short name | T765 |
| Test name | |
| Test status | |
| Simulation time | 96736044015 ps |
| CPU time | 1713.82 seconds |
| Started | Jul 03 07:23:35 PM PDT 24 |
| Finished | Jul 03 07:52:10 PM PDT 24 |
| Peak memory | 574088 kb |
| Host | smart-ff805d10-12bc-4e6f-8046-21c32b4ab843 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=362111005 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_access_same_de vice_slow_rsp.362111005 |
| Directory | /workspace/8.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_error_and_unmapped_addr.2799416673 |
| Short name | T1345 |
| Test name | |
| Test status | |
| Simulation time | 241231387 ps |
| CPU time | 30.31 seconds |
| Started | Jul 03 07:23:30 PM PDT 24 |
| Finished | Jul 03 07:24:01 PM PDT 24 |
| Peak memory | 574384 kb |
| Host | smart-02258d9f-a538-480b-af40-e97b89c34564 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2799416673 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_error_and_unmapped_addr .2799416673 |
| Directory | /workspace/8.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_error_random.1647105283 |
| Short name | T1625 |
| Test name | |
| Test status | |
| Simulation time | 247104993 ps |
| CPU time | 21.05 seconds |
| Started | Jul 03 07:23:33 PM PDT 24 |
| Finished | Jul 03 07:23:55 PM PDT 24 |
| Peak memory | 574420 kb |
| Host | smart-7562d29b-7efc-4a89-9815-5d07a826313b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1647105283 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_error_random.1647105283 |
| Directory | /workspace/8.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_random.2950535291 |
| Short name | T595 |
| Test name | |
| Test status | |
| Simulation time | 1512101307 ps |
| CPU time | 56.55 seconds |
| Started | Jul 03 07:23:26 PM PDT 24 |
| Finished | Jul 03 07:24:23 PM PDT 24 |
| Peak memory | 574208 kb |
| Host | smart-342e5c9d-9317-49d9-aeb2-9b828b39bcbc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2950535291 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_random.2950535291 |
| Directory | /workspace/8.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_random_large_delays.3502820990 |
| Short name | T1712 |
| Test name | |
| Test status | |
| Simulation time | 52747778691 ps |
| CPU time | 608.42 seconds |
| Started | Jul 03 07:23:27 PM PDT 24 |
| Finished | Jul 03 07:33:37 PM PDT 24 |
| Peak memory | 574088 kb |
| Host | smart-6c8ce9e7-26a7-4877-a815-c34b3fdca2b8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3502820990 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_random_large_delays.3502820990 |
| Directory | /workspace/8.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_random_slow_rsp.1871239887 |
| Short name | T2838 |
| Test name | |
| Test status | |
| Simulation time | 44081769732 ps |
| CPU time | 791.39 seconds |
| Started | Jul 03 07:23:26 PM PDT 24 |
| Finished | Jul 03 07:36:38 PM PDT 24 |
| Peak memory | 574212 kb |
| Host | smart-456c740b-a89a-4f59-98c1-f2e70996d28b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1871239887 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_random_slow_rsp.1871239887 |
| Directory | /workspace/8.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_random_zero_delays.4040209397 |
| Short name | T2787 |
| Test name | |
| Test status | |
| Simulation time | 490719143 ps |
| CPU time | 39.42 seconds |
| Started | Jul 03 07:23:26 PM PDT 24 |
| Finished | Jul 03 07:24:07 PM PDT 24 |
| Peak memory | 574244 kb |
| Host | smart-e78d4542-924a-45ea-aace-4f3314c534b9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4040209397 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_random_zero_dela ys.4040209397 |
| Directory | /workspace/8.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_same_source.452876433 |
| Short name | T1726 |
| Test name | |
| Test status | |
| Simulation time | 428679964 ps |
| CPU time | 29.84 seconds |
| Started | Jul 03 07:23:31 PM PDT 24 |
| Finished | Jul 03 07:24:02 PM PDT 24 |
| Peak memory | 574156 kb |
| Host | smart-a80ef31f-3d25-4442-8277-afc8549360fa |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=452876433 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_same_source.452876433 |
| Directory | /workspace/8.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_smoke.4012753221 |
| Short name | T1418 |
| Test name | |
| Test status | |
| Simulation time | 56549322 ps |
| CPU time | 7.12 seconds |
| Started | Jul 03 07:23:29 PM PDT 24 |
| Finished | Jul 03 07:23:37 PM PDT 24 |
| Peak memory | 574108 kb |
| Host | smart-15a2afd0-034c-44fb-ac63-b49af3d89e77 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4012753221 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_smoke.4012753221 |
| Directory | /workspace/8.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_smoke_large_delays.2739618010 |
| Short name | T2671 |
| Test name | |
| Test status | |
| Simulation time | 7525705083 ps |
| CPU time | 87.17 seconds |
| Started | Jul 03 07:23:25 PM PDT 24 |
| Finished | Jul 03 07:24:53 PM PDT 24 |
| Peak memory | 574020 kb |
| Host | smart-02f14acd-5a86-4984-abfb-c59a71c71671 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2739618010 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_large_delays.2739618010 |
| Directory | /workspace/8.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_smoke_slow_rsp.2551043089 |
| Short name | T1931 |
| Test name | |
| Test status | |
| Simulation time | 5280190844 ps |
| CPU time | 96.69 seconds |
| Started | Jul 03 07:23:27 PM PDT 24 |
| Finished | Jul 03 07:25:05 PM PDT 24 |
| Peak memory | 573204 kb |
| Host | smart-6ab0d8da-7c37-4100-8a76-fdd3130251cf |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2551043089 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_slow_rsp.2551043089 |
| Directory | /workspace/8.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_smoke_zero_delays.1477660666 |
| Short name | T1894 |
| Test name | |
| Test status | |
| Simulation time | 51879435 ps |
| CPU time | 6.73 seconds |
| Started | Jul 03 07:23:26 PM PDT 24 |
| Finished | Jul 03 07:23:34 PM PDT 24 |
| Peak memory | 572920 kb |
| Host | smart-b3039825-2de5-4b52-a43f-206ae36a535a |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1477660666 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_zero_delays .1477660666 |
| Directory | /workspace/8.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_stress_all.837389743 |
| Short name | T458 |
| Test name | |
| Test status | |
| Simulation time | 15700172408 ps |
| CPU time | 578.26 seconds |
| Started | Jul 03 07:23:32 PM PDT 24 |
| Finished | Jul 03 07:33:11 PM PDT 24 |
| Peak memory | 574728 kb |
| Host | smart-e6a4eecd-2cb5-4494-87d8-74fdd6e99f09 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=837389743 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all.837389743 |
| Directory | /workspace/8.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_stress_all_with_error.1384831819 |
| Short name | T1557 |
| Test name | |
| Test status | |
| Simulation time | 2993647577 ps |
| CPU time | 211.71 seconds |
| Started | Jul 03 07:23:38 PM PDT 24 |
| Finished | Jul 03 07:27:12 PM PDT 24 |
| Peak memory | 574688 kb |
| Host | smart-b45d3e8c-a1ca-44a9-ace7-357aa80406fb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1384831819 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_error.1384831819 |
| Directory | /workspace/8.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_stress_all_with_rand_reset.207043197 |
| Short name | T2390 |
| Test name | |
| Test status | |
| Simulation time | 339318727 ps |
| CPU time | 125.43 seconds |
| Started | Jul 03 07:23:35 PM PDT 24 |
| Finished | Jul 03 07:25:42 PM PDT 24 |
| Peak memory | 574544 kb |
| Host | smart-b6491df7-c9bd-4c2e-a1c0-cde1810c603e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207043197 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_w ith_rand_reset.207043197 |
| Directory | /workspace/8.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_unmapped_addr.779339913 |
| Short name | T2579 |
| Test name | |
| Test status | |
| Simulation time | 919079582 ps |
| CPU time | 45.05 seconds |
| Started | Jul 03 07:23:31 PM PDT 24 |
| Finished | Jul 03 07:24:17 PM PDT 24 |
| Peak memory | 574248 kb |
| Host | smart-32faf1b8-46b6-4e3a-becf-e634e554b7c5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=779339913 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_unmapped_addr.779339913 |
| Directory | /workspace/8.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_access_same_device.1851092322 |
| Short name | T773 |
| Test name | |
| Test status | |
| Simulation time | 2341431674 ps |
| CPU time | 97.69 seconds |
| Started | Jul 03 07:36:46 PM PDT 24 |
| Finished | Jul 03 07:38:24 PM PDT 24 |
| Peak memory | 574304 kb |
| Host | smart-35d1a299-024d-4fe9-9d85-48c59b57dc6f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1851092322 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_access_same_device .1851092322 |
| Directory | /workspace/80.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_error_and_unmapped_addr.340064299 |
| Short name | T1571 |
| Test name | |
| Test status | |
| Simulation time | 498204034 ps |
| CPU time | 23.39 seconds |
| Started | Jul 03 07:36:52 PM PDT 24 |
| Finished | Jul 03 07:37:17 PM PDT 24 |
| Peak memory | 574488 kb |
| Host | smart-72a57b68-b076-4cc4-b33f-c0d859dfeecf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=340064299 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_error_and_unmapped_addr .340064299 |
| Directory | /workspace/80.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_error_random.3289880106 |
| Short name | T2547 |
| Test name | |
| Test status | |
| Simulation time | 953763987 ps |
| CPU time | 34.61 seconds |
| Started | Jul 03 07:36:47 PM PDT 24 |
| Finished | Jul 03 07:37:22 PM PDT 24 |
| Peak memory | 574500 kb |
| Host | smart-c896c0e3-5388-419c-b60b-b451dc2401d3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3289880106 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_error_random.3289880106 |
| Directory | /workspace/80.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_random.3056553374 |
| Short name | T2199 |
| Test name | |
| Test status | |
| Simulation time | 1056694970 ps |
| CPU time | 32.96 seconds |
| Started | Jul 03 07:36:41 PM PDT 24 |
| Finished | Jul 03 07:37:14 PM PDT 24 |
| Peak memory | 574196 kb |
| Host | smart-c5ef3650-b333-4b3d-8490-fae8baa07877 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3056553374 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_random.3056553374 |
| Directory | /workspace/80.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_random_large_delays.1803676753 |
| Short name | T2504 |
| Test name | |
| Test status | |
| Simulation time | 38173077436 ps |
| CPU time | 357.88 seconds |
| Started | Jul 03 07:36:44 PM PDT 24 |
| Finished | Jul 03 07:42:43 PM PDT 24 |
| Peak memory | 574184 kb |
| Host | smart-ab7dca13-21d3-4965-b241-57fb698e57be |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1803676753 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_random_large_delays.1803676753 |
| Directory | /workspace/80.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_random_slow_rsp.2471280814 |
| Short name | T2629 |
| Test name | |
| Test status | |
| Simulation time | 30109907026 ps |
| CPU time | 550.79 seconds |
| Started | Jul 03 07:36:46 PM PDT 24 |
| Finished | Jul 03 07:45:58 PM PDT 24 |
| Peak memory | 574260 kb |
| Host | smart-e2508ec3-cc9f-4242-8519-b4073b53090c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2471280814 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_random_slow_rsp.2471280814 |
| Directory | /workspace/80.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_random_zero_delays.3441063310 |
| Short name | T1417 |
| Test name | |
| Test status | |
| Simulation time | 212038054 ps |
| CPU time | 17.49 seconds |
| Started | Jul 03 07:36:41 PM PDT 24 |
| Finished | Jul 03 07:36:59 PM PDT 24 |
| Peak memory | 573992 kb |
| Host | smart-f42c1c37-978f-43f8-b1d7-59538f306fc9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3441063310 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_random_zero_del ays.3441063310 |
| Directory | /workspace/80.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_same_source.797461136 |
| Short name | T2165 |
| Test name | |
| Test status | |
| Simulation time | 217346680 ps |
| CPU time | 9.6 seconds |
| Started | Jul 03 07:36:46 PM PDT 24 |
| Finished | Jul 03 07:36:56 PM PDT 24 |
| Peak memory | 572908 kb |
| Host | smart-20c661b8-5f03-425b-acbd-d5ecb2e28298 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=797461136 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_same_source.797461136 |
| Directory | /workspace/80.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_smoke.34755374 |
| Short name | T1375 |
| Test name | |
| Test status | |
| Simulation time | 186766580 ps |
| CPU time | 8.66 seconds |
| Started | Jul 03 07:36:40 PM PDT 24 |
| Finished | Jul 03 07:36:49 PM PDT 24 |
| Peak memory | 573120 kb |
| Host | smart-ab5fc910-e86d-4156-808c-4f6edcd60bd2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34755374 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_smoke.34755374 |
| Directory | /workspace/80.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_smoke_large_delays.1258997204 |
| Short name | T2599 |
| Test name | |
| Test status | |
| Simulation time | 8299690338 ps |
| CPU time | 81.57 seconds |
| Started | Jul 03 07:36:40 PM PDT 24 |
| Finished | Jul 03 07:38:02 PM PDT 24 |
| Peak memory | 574044 kb |
| Host | smart-61eb8c05-2c50-462d-8e8b-765b8f7908f6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1258997204 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_smoke_large_delays.1258997204 |
| Directory | /workspace/80.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_smoke_slow_rsp.2760321916 |
| Short name | T2642 |
| Test name | |
| Test status | |
| Simulation time | 4870343918 ps |
| CPU time | 81.29 seconds |
| Started | Jul 03 07:36:41 PM PDT 24 |
| Finished | Jul 03 07:38:02 PM PDT 24 |
| Peak memory | 573224 kb |
| Host | smart-a4980f66-9879-4c13-9825-d9f64c9f0840 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2760321916 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_smoke_slow_rsp.2760321916 |
| Directory | /workspace/80.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_smoke_zero_delays.3183460606 |
| Short name | T2718 |
| Test name | |
| Test status | |
| Simulation time | 41367891 ps |
| CPU time | 6.28 seconds |
| Started | Jul 03 07:36:37 PM PDT 24 |
| Finished | Jul 03 07:36:44 PM PDT 24 |
| Peak memory | 573064 kb |
| Host | smart-aeeb715b-1a53-45f7-b395-61e94ba0165a |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3183460606 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_smoke_zero_delay s.3183460606 |
| Directory | /workspace/80.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_stress_all.646349878 |
| Short name | T2757 |
| Test name | |
| Test status | |
| Simulation time | 4348642025 ps |
| CPU time | 349.4 seconds |
| Started | Jul 03 07:36:49 PM PDT 24 |
| Finished | Jul 03 07:42:40 PM PDT 24 |
| Peak memory | 574664 kb |
| Host | smart-04203d81-6f37-40f9-99e2-4310d259f7aa |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=646349878 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_stress_all.646349878 |
| Directory | /workspace/80.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_stress_all_with_error.1720345210 |
| Short name | T2659 |
| Test name | |
| Test status | |
| Simulation time | 3631972317 ps |
| CPU time | 106.05 seconds |
| Started | Jul 03 07:36:50 PM PDT 24 |
| Finished | Jul 03 07:38:38 PM PDT 24 |
| Peak memory | 574580 kb |
| Host | smart-737aeac3-3899-4e0f-be17-063972ef25aa |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1720345210 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_stress_all_with_error.1720345210 |
| Directory | /workspace/80.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_stress_all_with_reset_error.3050297355 |
| Short name | T2171 |
| Test name | |
| Test status | |
| Simulation time | 464526448 ps |
| CPU time | 130.86 seconds |
| Started | Jul 03 07:36:51 PM PDT 24 |
| Finished | Jul 03 07:39:04 PM PDT 24 |
| Peak memory | 574576 kb |
| Host | smart-76dbe4b8-de1c-4be1-8bc0-4efa773cd62c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3050297355 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_stress_al l_with_reset_error.3050297355 |
| Directory | /workspace/80.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_unmapped_addr.4234551816 |
| Short name | T1598 |
| Test name | |
| Test status | |
| Simulation time | 23432673 ps |
| CPU time | 5.25 seconds |
| Started | Jul 03 07:36:46 PM PDT 24 |
| Finished | Jul 03 07:36:52 PM PDT 24 |
| Peak memory | 573164 kb |
| Host | smart-4211fdf6-c716-4511-ad77-4387ee531445 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4234551816 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_unmapped_addr.4234551816 |
| Directory | /workspace/80.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_access_same_device.3492638171 |
| Short name | T1617 |
| Test name | |
| Test status | |
| Simulation time | 400243506 ps |
| CPU time | 37.11 seconds |
| Started | Jul 03 07:37:00 PM PDT 24 |
| Finished | Jul 03 07:37:37 PM PDT 24 |
| Peak memory | 574184 kb |
| Host | smart-a6eeead6-5bc3-4fac-9d3c-b42e5d19119d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492638171 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_access_same_device .3492638171 |
| Directory | /workspace/81.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_access_same_device_slow_rsp.4131367467 |
| Short name | T1663 |
| Test name | |
| Test status | |
| Simulation time | 17613745474 ps |
| CPU time | 297.71 seconds |
| Started | Jul 03 07:36:57 PM PDT 24 |
| Finished | Jul 03 07:41:55 PM PDT 24 |
| Peak memory | 574108 kb |
| Host | smart-0a609014-c170-4c4b-9efb-3d839d146802 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131367467 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_access_same_ device_slow_rsp.4131367467 |
| Directory | /workspace/81.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_error_and_unmapped_addr.1933504598 |
| Short name | T1385 |
| Test name | |
| Test status | |
| Simulation time | 1255286266 ps |
| CPU time | 50.88 seconds |
| Started | Jul 03 07:36:53 PM PDT 24 |
| Finished | Jul 03 07:37:45 PM PDT 24 |
| Peak memory | 574444 kb |
| Host | smart-934a43b9-7625-461f-9149-b7c1dc0c8177 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1933504598 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_error_and_unmapped_add r.1933504598 |
| Directory | /workspace/81.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_error_random.2306153223 |
| Short name | T2187 |
| Test name | |
| Test status | |
| Simulation time | 137190727 ps |
| CPU time | 11.78 seconds |
| Started | Jul 03 07:36:57 PM PDT 24 |
| Finished | Jul 03 07:37:09 PM PDT 24 |
| Peak memory | 574044 kb |
| Host | smart-2e2c2429-fa61-435c-a91c-e9d520ddea25 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2306153223 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_error_random.2306153223 |
| Directory | /workspace/81.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_random.3508308606 |
| Short name | T2378 |
| Test name | |
| Test status | |
| Simulation time | 471083344 ps |
| CPU time | 20.92 seconds |
| Started | Jul 03 07:36:50 PM PDT 24 |
| Finished | Jul 03 07:37:12 PM PDT 24 |
| Peak memory | 574016 kb |
| Host | smart-aa7e8b72-fda4-47c2-811e-a3af28c588c2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3508308606 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_random.3508308606 |
| Directory | /workspace/81.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_random_large_delays.2193072113 |
| Short name | T2713 |
| Test name | |
| Test status | |
| Simulation time | 49846054588 ps |
| CPU time | 570.25 seconds |
| Started | Jul 03 07:36:54 PM PDT 24 |
| Finished | Jul 03 07:46:25 PM PDT 24 |
| Peak memory | 574248 kb |
| Host | smart-51b35de4-e29d-4a3a-820d-57b09e55a36f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2193072113 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_random_large_delays.2193072113 |
| Directory | /workspace/81.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_random_slow_rsp.1953928236 |
| Short name | T1521 |
| Test name | |
| Test status | |
| Simulation time | 17713005078 ps |
| CPU time | 307.61 seconds |
| Started | Jul 03 07:36:55 PM PDT 24 |
| Finished | Jul 03 07:42:03 PM PDT 24 |
| Peak memory | 574016 kb |
| Host | smart-6fa97bee-1fc0-4d1e-ae19-a2841c546c48 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1953928236 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_random_slow_rsp.1953928236 |
| Directory | /workspace/81.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_random_zero_delays.2336689918 |
| Short name | T584 |
| Test name | |
| Test status | |
| Simulation time | 308527686 ps |
| CPU time | 26.25 seconds |
| Started | Jul 03 07:36:55 PM PDT 24 |
| Finished | Jul 03 07:37:22 PM PDT 24 |
| Peak memory | 574176 kb |
| Host | smart-852a9873-8d92-4f06-bef1-296f381afde1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2336689918 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_random_zero_del ays.2336689918 |
| Directory | /workspace/81.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_same_source.3356997660 |
| Short name | T1455 |
| Test name | |
| Test status | |
| Simulation time | 1934965958 ps |
| CPU time | 50.33 seconds |
| Started | Jul 03 07:36:56 PM PDT 24 |
| Finished | Jul 03 07:37:47 PM PDT 24 |
| Peak memory | 574272 kb |
| Host | smart-24ee4f26-ddc1-45ed-9821-fa2f04460f31 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3356997660 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_same_source.3356997660 |
| Directory | /workspace/81.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_smoke.2290513894 |
| Short name | T2357 |
| Test name | |
| Test status | |
| Simulation time | 43408828 ps |
| CPU time | 6.21 seconds |
| Started | Jul 03 07:36:51 PM PDT 24 |
| Finished | Jul 03 07:36:59 PM PDT 24 |
| Peak memory | 574112 kb |
| Host | smart-75120aad-e97e-4c2c-b8c3-ede3c21006b7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2290513894 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_smoke.2290513894 |
| Directory | /workspace/81.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_smoke_large_delays.4226597408 |
| Short name | T2570 |
| Test name | |
| Test status | |
| Simulation time | 7839462673 ps |
| CPU time | 86.52 seconds |
| Started | Jul 03 07:36:51 PM PDT 24 |
| Finished | Jul 03 07:38:18 PM PDT 24 |
| Peak memory | 574088 kb |
| Host | smart-1c607d5f-4178-467d-a7d4-1a206b92133f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4226597408 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_smoke_large_delays.4226597408 |
| Directory | /workspace/81.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_smoke_slow_rsp.633684779 |
| Short name | T559 |
| Test name | |
| Test status | |
| Simulation time | 5053504035 ps |
| CPU time | 87.53 seconds |
| Started | Jul 03 07:36:52 PM PDT 24 |
| Finished | Jul 03 07:38:21 PM PDT 24 |
| Peak memory | 573012 kb |
| Host | smart-967d225d-e45c-4c56-87f4-ebb5dad0bc96 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=633684779 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_smoke_slow_rsp.633684779 |
| Directory | /workspace/81.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_smoke_zero_delays.1400070696 |
| Short name | T2890 |
| Test name | |
| Test status | |
| Simulation time | 60616933 ps |
| CPU time | 7.18 seconds |
| Started | Jul 03 07:36:52 PM PDT 24 |
| Finished | Jul 03 07:37:01 PM PDT 24 |
| Peak memory | 574144 kb |
| Host | smart-05b556b3-1508-4829-936c-dba3998caa8a |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1400070696 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_smoke_zero_delay s.1400070696 |
| Directory | /workspace/81.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_stress_all.2465440659 |
| Short name | T1866 |
| Test name | |
| Test status | |
| Simulation time | 11539949566 ps |
| CPU time | 398.37 seconds |
| Started | Jul 03 07:37:05 PM PDT 24 |
| Finished | Jul 03 07:43:45 PM PDT 24 |
| Peak memory | 574780 kb |
| Host | smart-f8150184-60a7-47ec-8f55-46573e2dce20 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465440659 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_stress_all.2465440659 |
| Directory | /workspace/81.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_stress_all_with_error.1187475383 |
| Short name | T1499 |
| Test name | |
| Test status | |
| Simulation time | 1422251268 ps |
| CPU time | 103.56 seconds |
| Started | Jul 03 07:37:00 PM PDT 24 |
| Finished | Jul 03 07:38:44 PM PDT 24 |
| Peak memory | 574104 kb |
| Host | smart-d61c21f3-3d06-4839-84c1-b69f246c2a66 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187475383 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_stress_all_with_error.1187475383 |
| Directory | /workspace/81.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_stress_all_with_rand_reset.1843967010 |
| Short name | T814 |
| Test name | |
| Test status | |
| Simulation time | 177543886 ps |
| CPU time | 69.01 seconds |
| Started | Jul 03 07:37:00 PM PDT 24 |
| Finished | Jul 03 07:38:10 PM PDT 24 |
| Peak memory | 574592 kb |
| Host | smart-611bfc66-1f18-40fb-96fe-86e6b6c1800e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1843967010 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_stress_all _with_rand_reset.1843967010 |
| Directory | /workspace/81.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_stress_all_with_reset_error.1176618980 |
| Short name | T2548 |
| Test name | |
| Test status | |
| Simulation time | 320611435 ps |
| CPU time | 134.68 seconds |
| Started | Jul 03 07:37:02 PM PDT 24 |
| Finished | Jul 03 07:39:17 PM PDT 24 |
| Peak memory | 574636 kb |
| Host | smart-00eb444d-af0d-4953-b691-41b127d4ebea |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176618980 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_stress_al l_with_reset_error.1176618980 |
| Directory | /workspace/81.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_unmapped_addr.2127354834 |
| Short name | T2842 |
| Test name | |
| Test status | |
| Simulation time | 253006040 ps |
| CPU time | 28.46 seconds |
| Started | Jul 03 07:36:55 PM PDT 24 |
| Finished | Jul 03 07:37:24 PM PDT 24 |
| Peak memory | 574052 kb |
| Host | smart-b7d5bf21-07ca-4885-bf4e-09b5ea9851f9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2127354834 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_unmapped_addr.2127354834 |
| Directory | /workspace/81.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_access_same_device.3143627020 |
| Short name | T768 |
| Test name | |
| Test status | |
| Simulation time | 1776297896 ps |
| CPU time | 74.1 seconds |
| Started | Jul 03 07:37:07 PM PDT 24 |
| Finished | Jul 03 07:38:22 PM PDT 24 |
| Peak memory | 574148 kb |
| Host | smart-d56dec9b-683c-4ebd-95b9-833f2f331193 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3143627020 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_access_same_device .3143627020 |
| Directory | /workspace/82.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_error_and_unmapped_addr.1975782677 |
| Short name | T1513 |
| Test name | |
| Test status | |
| Simulation time | 132905092 ps |
| CPU time | 7.77 seconds |
| Started | Jul 03 07:37:05 PM PDT 24 |
| Finished | Jul 03 07:37:13 PM PDT 24 |
| Peak memory | 573012 kb |
| Host | smart-3a2c0138-0128-46a1-8b9d-699d07fc6749 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1975782677 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_error_and_unmapped_add r.1975782677 |
| Directory | /workspace/82.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_error_random.1301450114 |
| Short name | T2381 |
| Test name | |
| Test status | |
| Simulation time | 1258201444 ps |
| CPU time | 43.62 seconds |
| Started | Jul 03 07:37:08 PM PDT 24 |
| Finished | Jul 03 07:37:52 PM PDT 24 |
| Peak memory | 574496 kb |
| Host | smart-000e424a-74ae-4450-8930-ea1ccd53328d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1301450114 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_error_random.1301450114 |
| Directory | /workspace/82.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_random.625905453 |
| Short name | T2496 |
| Test name | |
| Test status | |
| Simulation time | 128006583 ps |
| CPU time | 13.89 seconds |
| Started | Jul 03 07:37:08 PM PDT 24 |
| Finished | Jul 03 07:37:23 PM PDT 24 |
| Peak memory | 574044 kb |
| Host | smart-347bfb63-6ffe-47ee-be03-e57c90f5bac4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=625905453 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_random.625905453 |
| Directory | /workspace/82.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_random_large_delays.1844589004 |
| Short name | T2432 |
| Test name | |
| Test status | |
| Simulation time | 16941906827 ps |
| CPU time | 171.94 seconds |
| Started | Jul 03 07:37:06 PM PDT 24 |
| Finished | Jul 03 07:39:59 PM PDT 24 |
| Peak memory | 574276 kb |
| Host | smart-01350447-3c81-4418-9caf-7e41b4bdc536 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1844589004 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_random_large_delays.1844589004 |
| Directory | /workspace/82.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_random_slow_rsp.327233061 |
| Short name | T2641 |
| Test name | |
| Test status | |
| Simulation time | 17825331844 ps |
| CPU time | 304.15 seconds |
| Started | Jul 03 07:37:05 PM PDT 24 |
| Finished | Jul 03 07:42:10 PM PDT 24 |
| Peak memory | 574088 kb |
| Host | smart-dd54a676-54ab-4994-a0c6-19d5ab566d28 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327233061 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_random_slow_rsp.327233061 |
| Directory | /workspace/82.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_random_zero_delays.1199575834 |
| Short name | T2892 |
| Test name | |
| Test status | |
| Simulation time | 245949062 ps |
| CPU time | 22.13 seconds |
| Started | Jul 03 07:37:07 PM PDT 24 |
| Finished | Jul 03 07:37:30 PM PDT 24 |
| Peak memory | 574212 kb |
| Host | smart-9a571a64-77d1-4206-a075-9c2c04a93151 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1199575834 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_random_zero_del ays.1199575834 |
| Directory | /workspace/82.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_same_source.464000102 |
| Short name | T1734 |
| Test name | |
| Test status | |
| Simulation time | 567846534 ps |
| CPU time | 42.78 seconds |
| Started | Jul 03 07:37:07 PM PDT 24 |
| Finished | Jul 03 07:37:51 PM PDT 24 |
| Peak memory | 573960 kb |
| Host | smart-f0736c6b-fa85-4597-9cab-dee6056f14ca |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=464000102 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_same_source.464000102 |
| Directory | /workspace/82.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_smoke.3417090560 |
| Short name | T1604 |
| Test name | |
| Test status | |
| Simulation time | 233760291 ps |
| CPU time | 9.95 seconds |
| Started | Jul 03 07:37:06 PM PDT 24 |
| Finished | Jul 03 07:37:17 PM PDT 24 |
| Peak memory | 574236 kb |
| Host | smart-63d4f522-9e91-450b-98d5-96071d4719c0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3417090560 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_smoke.3417090560 |
| Directory | /workspace/82.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_smoke_large_delays.3450405521 |
| Short name | T1488 |
| Test name | |
| Test status | |
| Simulation time | 6693368263 ps |
| CPU time | 69.26 seconds |
| Started | Jul 03 07:37:04 PM PDT 24 |
| Finished | Jul 03 07:38:14 PM PDT 24 |
| Peak memory | 573236 kb |
| Host | smart-6d460498-d42f-4909-b9c4-65bcbb4307e2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3450405521 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_smoke_large_delays.3450405521 |
| Directory | /workspace/82.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_smoke_slow_rsp.1599767709 |
| Short name | T1591 |
| Test name | |
| Test status | |
| Simulation time | 5565527570 ps |
| CPU time | 95.5 seconds |
| Started | Jul 03 07:37:01 PM PDT 24 |
| Finished | Jul 03 07:38:37 PM PDT 24 |
| Peak memory | 573244 kb |
| Host | smart-7e1cdb90-704c-4c42-b2ad-c1200ac610f0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599767709 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_smoke_slow_rsp.1599767709 |
| Directory | /workspace/82.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_smoke_zero_delays.2255500328 |
| Short name | T1902 |
| Test name | |
| Test status | |
| Simulation time | 47161923 ps |
| CPU time | 6.92 seconds |
| Started | Jul 03 07:37:04 PM PDT 24 |
| Finished | Jul 03 07:37:12 PM PDT 24 |
| Peak memory | 574124 kb |
| Host | smart-1575f3d3-ba23-48b9-8e2d-6e072000e732 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2255500328 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_smoke_zero_delay s.2255500328 |
| Directory | /workspace/82.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_stress_all.3526684518 |
| Short name | T1972 |
| Test name | |
| Test status | |
| Simulation time | 7158878840 ps |
| CPU time | 292.99 seconds |
| Started | Jul 03 07:37:06 PM PDT 24 |
| Finished | Jul 03 07:41:59 PM PDT 24 |
| Peak memory | 574732 kb |
| Host | smart-42b922e0-fdb4-455f-9989-ec3db5b674af |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3526684518 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_stress_all.3526684518 |
| Directory | /workspace/82.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_stress_all_with_error.2841285398 |
| Short name | T1422 |
| Test name | |
| Test status | |
| Simulation time | 6304329765 ps |
| CPU time | 249.02 seconds |
| Started | Jul 03 07:37:12 PM PDT 24 |
| Finished | Jul 03 07:41:22 PM PDT 24 |
| Peak memory | 574364 kb |
| Host | smart-1dec2f4a-e9a7-454c-a4c7-af1e8d5a4e36 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841285398 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_stress_all_with_error.2841285398 |
| Directory | /workspace/82.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_stress_all_with_reset_error.1993201417 |
| Short name | T2582 |
| Test name | |
| Test status | |
| Simulation time | 306992345 ps |
| CPU time | 65.5 seconds |
| Started | Jul 03 07:37:12 PM PDT 24 |
| Finished | Jul 03 07:38:19 PM PDT 24 |
| Peak memory | 574652 kb |
| Host | smart-ec1de279-88be-4d9f-9fff-7828a0762dad |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1993201417 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_stress_al l_with_reset_error.1993201417 |
| Directory | /workspace/82.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_unmapped_addr.3978560771 |
| Short name | T540 |
| Test name | |
| Test status | |
| Simulation time | 105620418 ps |
| CPU time | 13.72 seconds |
| Started | Jul 03 07:37:06 PM PDT 24 |
| Finished | Jul 03 07:37:21 PM PDT 24 |
| Peak memory | 574308 kb |
| Host | smart-b831454d-13c0-4cef-a039-44d7c87660b8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3978560771 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_unmapped_addr.3978560771 |
| Directory | /workspace/82.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_access_same_device.4291136131 |
| Short name | T2542 |
| Test name | |
| Test status | |
| Simulation time | 403429759 ps |
| CPU time | 33.58 seconds |
| Started | Jul 03 07:37:20 PM PDT 24 |
| Finished | Jul 03 07:37:54 PM PDT 24 |
| Peak memory | 573988 kb |
| Host | smart-f2dfb972-7066-47ba-b6fa-bb3c1ca4f729 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4291136131 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_access_same_device .4291136131 |
| Directory | /workspace/83.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_error_and_unmapped_addr.3458415349 |
| Short name | T1335 |
| Test name | |
| Test status | |
| Simulation time | 1278801998 ps |
| CPU time | 47.04 seconds |
| Started | Jul 03 07:37:23 PM PDT 24 |
| Finished | Jul 03 07:38:11 PM PDT 24 |
| Peak memory | 574456 kb |
| Host | smart-25b08a9a-4ac4-4d3e-a5dd-18cacb63c4ec |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3458415349 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_error_and_unmapped_add r.3458415349 |
| Directory | /workspace/83.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_error_random.3606698468 |
| Short name | T2250 |
| Test name | |
| Test status | |
| Simulation time | 2580575577 ps |
| CPU time | 95.87 seconds |
| Started | Jul 03 07:37:20 PM PDT 24 |
| Finished | Jul 03 07:38:56 PM PDT 24 |
| Peak memory | 574128 kb |
| Host | smart-ca02b47a-1386-408c-8dcf-83416fdb7056 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3606698468 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_error_random.3606698468 |
| Directory | /workspace/83.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_random.3894374804 |
| Short name | T1833 |
| Test name | |
| Test status | |
| Simulation time | 1528914700 ps |
| CPU time | 55.91 seconds |
| Started | Jul 03 07:37:16 PM PDT 24 |
| Finished | Jul 03 07:38:12 PM PDT 24 |
| Peak memory | 574112 kb |
| Host | smart-b6db1858-03d8-44e6-9af3-066f11b756e1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3894374804 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_random.3894374804 |
| Directory | /workspace/83.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_random_large_delays.2800957222 |
| Short name | T1472 |
| Test name | |
| Test status | |
| Simulation time | 11970055035 ps |
| CPU time | 122.1 seconds |
| Started | Jul 03 07:37:12 PM PDT 24 |
| Finished | Jul 03 07:39:15 PM PDT 24 |
| Peak memory | 574240 kb |
| Host | smart-8b9ccbc5-d378-427c-9570-1a8cb4e7b8de |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2800957222 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_random_large_delays.2800957222 |
| Directory | /workspace/83.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_random_slow_rsp.703425781 |
| Short name | T1790 |
| Test name | |
| Test status | |
| Simulation time | 30636378082 ps |
| CPU time | 533.02 seconds |
| Started | Jul 03 07:37:17 PM PDT 24 |
| Finished | Jul 03 07:46:10 PM PDT 24 |
| Peak memory | 574348 kb |
| Host | smart-9c01cd67-b482-4be5-b131-59e63d693259 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=703425781 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_random_slow_rsp.703425781 |
| Directory | /workspace/83.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_random_zero_delays.1121416334 |
| Short name | T2479 |
| Test name | |
| Test status | |
| Simulation time | 380770042 ps |
| CPU time | 38.09 seconds |
| Started | Jul 03 07:37:12 PM PDT 24 |
| Finished | Jul 03 07:37:52 PM PDT 24 |
| Peak memory | 574212 kb |
| Host | smart-fb3dc834-2228-46f7-9e79-94e868cad9cd |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1121416334 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_random_zero_del ays.1121416334 |
| Directory | /workspace/83.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_same_source.3327957556 |
| Short name | T2880 |
| Test name | |
| Test status | |
| Simulation time | 283987144 ps |
| CPU time | 11.38 seconds |
| Started | Jul 03 07:37:20 PM PDT 24 |
| Finished | Jul 03 07:37:32 PM PDT 24 |
| Peak memory | 574168 kb |
| Host | smart-1f098a79-1177-4c2c-b96e-4d00053414fe |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3327957556 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_same_source.3327957556 |
| Directory | /workspace/83.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_smoke.3279098521 |
| Short name | T2064 |
| Test name | |
| Test status | |
| Simulation time | 169076114 ps |
| CPU time | 7.48 seconds |
| Started | Jul 03 07:37:10 PM PDT 24 |
| Finished | Jul 03 07:37:18 PM PDT 24 |
| Peak memory | 573916 kb |
| Host | smart-a3491846-4953-4eb3-b031-1d38ae38931a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3279098521 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_smoke.3279098521 |
| Directory | /workspace/83.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_smoke_large_delays.3374044233 |
| Short name | T1344 |
| Test name | |
| Test status | |
| Simulation time | 8930779256 ps |
| CPU time | 96.07 seconds |
| Started | Jul 03 07:37:13 PM PDT 24 |
| Finished | Jul 03 07:38:50 PM PDT 24 |
| Peak memory | 572996 kb |
| Host | smart-fcf354fd-c068-4d0b-bfc5-3364bd238e97 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374044233 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_smoke_large_delays.3374044233 |
| Directory | /workspace/83.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_smoke_slow_rsp.1272323948 |
| Short name | T1635 |
| Test name | |
| Test status | |
| Simulation time | 5348932814 ps |
| CPU time | 90.1 seconds |
| Started | Jul 03 07:37:16 PM PDT 24 |
| Finished | Jul 03 07:38:46 PM PDT 24 |
| Peak memory | 573188 kb |
| Host | smart-4d32186c-052d-423d-bf71-c028edeb54dd |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1272323948 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_smoke_slow_rsp.1272323948 |
| Directory | /workspace/83.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_smoke_zero_delays.3592197730 |
| Short name | T1934 |
| Test name | |
| Test status | |
| Simulation time | 48661007 ps |
| CPU time | 6.01 seconds |
| Started | Jul 03 07:37:12 PM PDT 24 |
| Finished | Jul 03 07:37:19 PM PDT 24 |
| Peak memory | 573972 kb |
| Host | smart-4fb25934-a3c5-448a-8ff5-9c4d85437259 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3592197730 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_smoke_zero_delay s.3592197730 |
| Directory | /workspace/83.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_stress_all.3178584534 |
| Short name | T2423 |
| Test name | |
| Test status | |
| Simulation time | 1512953121 ps |
| CPU time | 124.63 seconds |
| Started | Jul 03 07:37:22 PM PDT 24 |
| Finished | Jul 03 07:39:27 PM PDT 24 |
| Peak memory | 574620 kb |
| Host | smart-5b16ecf2-daac-4579-8c68-1293039a602b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3178584534 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_stress_all.3178584534 |
| Directory | /workspace/83.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_stress_all_with_error.3994585474 |
| Short name | T2870 |
| Test name | |
| Test status | |
| Simulation time | 5254837870 ps |
| CPU time | 205.33 seconds |
| Started | Jul 03 07:37:23 PM PDT 24 |
| Finished | Jul 03 07:40:50 PM PDT 24 |
| Peak memory | 574624 kb |
| Host | smart-9457fe47-d6fb-45a2-adcb-46344cfe5882 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3994585474 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_stress_all_with_error.3994585474 |
| Directory | /workspace/83.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_stress_all_with_rand_reset.3510661933 |
| Short name | T2680 |
| Test name | |
| Test status | |
| Simulation time | 8758532304 ps |
| CPU time | 526.33 seconds |
| Started | Jul 03 07:37:23 PM PDT 24 |
| Finished | Jul 03 07:46:10 PM PDT 24 |
| Peak memory | 574604 kb |
| Host | smart-6ee5f41b-5bed-40b8-9133-eb28665ec354 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3510661933 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_stress_all _with_rand_reset.3510661933 |
| Directory | /workspace/83.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_stress_all_with_reset_error.2636881958 |
| Short name | T2535 |
| Test name | |
| Test status | |
| Simulation time | 379809629 ps |
| CPU time | 143.87 seconds |
| Started | Jul 03 07:37:22 PM PDT 24 |
| Finished | Jul 03 07:39:47 PM PDT 24 |
| Peak memory | 574640 kb |
| Host | smart-6cdb295d-d8f0-4a15-8d5d-250cf45f8f8e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2636881958 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_stress_al l_with_reset_error.2636881958 |
| Directory | /workspace/83.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_unmapped_addr.3184816566 |
| Short name | T567 |
| Test name | |
| Test status | |
| Simulation time | 1030630335 ps |
| CPU time | 39.99 seconds |
| Started | Jul 03 07:37:22 PM PDT 24 |
| Finished | Jul 03 07:38:02 PM PDT 24 |
| Peak memory | 574224 kb |
| Host | smart-75e32ba4-0015-46c6-8c8e-b7467ca59594 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3184816566 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_unmapped_addr.3184816566 |
| Directory | /workspace/83.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_access_same_device.4124921181 |
| Short name | T764 |
| Test name | |
| Test status | |
| Simulation time | 593957300 ps |
| CPU time | 24.78 seconds |
| Started | Jul 03 07:37:28 PM PDT 24 |
| Finished | Jul 03 07:37:54 PM PDT 24 |
| Peak memory | 574140 kb |
| Host | smart-14a09e85-b301-49b9-966e-133e5a66b5fd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4124921181 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_access_same_device .4124921181 |
| Directory | /workspace/84.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_access_same_device_slow_rsp.3635391810 |
| Short name | T2157 |
| Test name | |
| Test status | |
| Simulation time | 139959538047 ps |
| CPU time | 2589.16 seconds |
| Started | Jul 03 07:37:27 PM PDT 24 |
| Finished | Jul 03 08:20:37 PM PDT 24 |
| Peak memory | 574116 kb |
| Host | smart-9e4d24a2-5304-4f6f-b669-d264aff94084 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635391810 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_access_same_ device_slow_rsp.3635391810 |
| Directory | /workspace/84.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_error_and_unmapped_addr.3068005332 |
| Short name | T619 |
| Test name | |
| Test status | |
| Simulation time | 676852862 ps |
| CPU time | 28.42 seconds |
| Started | Jul 03 07:37:34 PM PDT 24 |
| Finished | Jul 03 07:38:03 PM PDT 24 |
| Peak memory | 574504 kb |
| Host | smart-f1902341-9def-46b2-ab12-a8cd03ba3415 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3068005332 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_error_and_unmapped_add r.3068005332 |
| Directory | /workspace/84.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_error_random.1843610739 |
| Short name | T2839 |
| Test name | |
| Test status | |
| Simulation time | 1495787536 ps |
| CPU time | 50.61 seconds |
| Started | Jul 03 07:37:34 PM PDT 24 |
| Finished | Jul 03 07:38:25 PM PDT 24 |
| Peak memory | 574480 kb |
| Host | smart-c807bc40-80f1-4f6b-bec1-cb2503cd5b19 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1843610739 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_error_random.1843610739 |
| Directory | /workspace/84.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_random.1178925063 |
| Short name | T2820 |
| Test name | |
| Test status | |
| Simulation time | 1804773293 ps |
| CPU time | 69.59 seconds |
| Started | Jul 03 07:37:29 PM PDT 24 |
| Finished | Jul 03 07:38:39 PM PDT 24 |
| Peak memory | 574160 kb |
| Host | smart-b04625d6-e0bf-4020-ae2e-c5ddd5862580 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1178925063 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_random.1178925063 |
| Directory | /workspace/84.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_random_large_delays.1388297806 |
| Short name | T445 |
| Test name | |
| Test status | |
| Simulation time | 78438541034 ps |
| CPU time | 945.28 seconds |
| Started | Jul 03 07:37:29 PM PDT 24 |
| Finished | Jul 03 07:53:15 PM PDT 24 |
| Peak memory | 574036 kb |
| Host | smart-2615b556-55fb-4440-bdde-7e5fcb989d6f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1388297806 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_random_large_delays.1388297806 |
| Directory | /workspace/84.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_random_slow_rsp.1218008475 |
| Short name | T508 |
| Test name | |
| Test status | |
| Simulation time | 8756090857 ps |
| CPU time | 149.38 seconds |
| Started | Jul 03 07:37:28 PM PDT 24 |
| Finished | Jul 03 07:39:58 PM PDT 24 |
| Peak memory | 574048 kb |
| Host | smart-83eff31d-af08-46b3-b36f-6459a1b129fe |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218008475 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_random_slow_rsp.1218008475 |
| Directory | /workspace/84.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_random_zero_delays.2177697387 |
| Short name | T433 |
| Test name | |
| Test status | |
| Simulation time | 386366432 ps |
| CPU time | 36.52 seconds |
| Started | Jul 03 07:37:29 PM PDT 24 |
| Finished | Jul 03 07:38:06 PM PDT 24 |
| Peak memory | 574132 kb |
| Host | smart-55719bd2-08df-4678-9e2f-52b4f85081ab |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177697387 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_random_zero_del ays.2177697387 |
| Directory | /workspace/84.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_same_source.678932776 |
| Short name | T2088 |
| Test name | |
| Test status | |
| Simulation time | 510835811 ps |
| CPU time | 35.23 seconds |
| Started | Jul 03 07:37:37 PM PDT 24 |
| Finished | Jul 03 07:38:12 PM PDT 24 |
| Peak memory | 574172 kb |
| Host | smart-e73272fc-f33e-4476-926a-34837cebde52 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=678932776 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_same_source.678932776 |
| Directory | /workspace/84.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_smoke.3680939682 |
| Short name | T1321 |
| Test name | |
| Test status | |
| Simulation time | 186093915 ps |
| CPU time | 7.98 seconds |
| Started | Jul 03 07:37:23 PM PDT 24 |
| Finished | Jul 03 07:37:31 PM PDT 24 |
| Peak memory | 574288 kb |
| Host | smart-854a7adc-04bd-4012-8558-89c2498a9644 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3680939682 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_smoke.3680939682 |
| Directory | /workspace/84.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_smoke_large_delays.1278623832 |
| Short name | T1569 |
| Test name | |
| Test status | |
| Simulation time | 7604428924 ps |
| CPU time | 79.98 seconds |
| Started | Jul 03 07:37:24 PM PDT 24 |
| Finished | Jul 03 07:38:44 PM PDT 24 |
| Peak memory | 574076 kb |
| Host | smart-3272dffa-22e6-4a94-8aca-3ba3037c9fc9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278623832 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_smoke_large_delays.1278623832 |
| Directory | /workspace/84.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_smoke_slow_rsp.911362758 |
| Short name | T507 |
| Test name | |
| Test status | |
| Simulation time | 7168964294 ps |
| CPU time | 118.55 seconds |
| Started | Jul 03 07:37:29 PM PDT 24 |
| Finished | Jul 03 07:39:29 PM PDT 24 |
| Peak memory | 573308 kb |
| Host | smart-86d94c5f-c3f8-4b97-8e1b-50445e89f825 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=911362758 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_smoke_slow_rsp.911362758 |
| Directory | /workspace/84.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_smoke_zero_delays.244275824 |
| Short name | T542 |
| Test name | |
| Test status | |
| Simulation time | 53371414 ps |
| CPU time | 6.82 seconds |
| Started | Jul 03 07:37:23 PM PDT 24 |
| Finished | Jul 03 07:37:31 PM PDT 24 |
| Peak memory | 574000 kb |
| Host | smart-7db11fbe-76e3-4148-8cf4-d19477ecd1c5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=244275824 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_smoke_zero_delays .244275824 |
| Directory | /workspace/84.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_stress_all.271332197 |
| Short name | T1725 |
| Test name | |
| Test status | |
| Simulation time | 2118783947 ps |
| CPU time | 166.78 seconds |
| Started | Jul 03 07:37:37 PM PDT 24 |
| Finished | Jul 03 07:40:24 PM PDT 24 |
| Peak memory | 574288 kb |
| Host | smart-aecea5f7-28b5-4ce1-b0f6-51d80747fb9d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=271332197 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_stress_all.271332197 |
| Directory | /workspace/84.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_stress_all_with_error.1549803068 |
| Short name | T2400 |
| Test name | |
| Test status | |
| Simulation time | 22679630334 ps |
| CPU time | 947.91 seconds |
| Started | Jul 03 07:37:35 PM PDT 24 |
| Finished | Jul 03 07:53:24 PM PDT 24 |
| Peak memory | 574616 kb |
| Host | smart-5e48c54e-c305-42df-93a2-b37d056ef5d8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1549803068 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_stress_all_with_error.1549803068 |
| Directory | /workspace/84.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_stress_all_with_rand_reset.3347923985 |
| Short name | T593 |
| Test name | |
| Test status | |
| Simulation time | 1918420950 ps |
| CPU time | 228.46 seconds |
| Started | Jul 03 07:37:35 PM PDT 24 |
| Finished | Jul 03 07:41:24 PM PDT 24 |
| Peak memory | 574652 kb |
| Host | smart-bf7403db-c294-4922-8d90-66596dda552f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3347923985 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_stress_all _with_rand_reset.3347923985 |
| Directory | /workspace/84.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_stress_all_with_reset_error.757240346 |
| Short name | T1921 |
| Test name | |
| Test status | |
| Simulation time | 380085301 ps |
| CPU time | 172.74 seconds |
| Started | Jul 03 07:37:37 PM PDT 24 |
| Finished | Jul 03 07:40:30 PM PDT 24 |
| Peak memory | 574652 kb |
| Host | smart-fb236e6f-c962-4b60-8fd9-0dfcee7f44b1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=757240346 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_stress_all _with_reset_error.757240346 |
| Directory | /workspace/84.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_unmapped_addr.1400844284 |
| Short name | T1370 |
| Test name | |
| Test status | |
| Simulation time | 212960728 ps |
| CPU time | 11.33 seconds |
| Started | Jul 03 07:37:36 PM PDT 24 |
| Finished | Jul 03 07:37:47 PM PDT 24 |
| Peak memory | 574056 kb |
| Host | smart-e42a8520-9d3f-45b8-9475-8a243c8135d4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1400844284 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_unmapped_addr.1400844284 |
| Directory | /workspace/84.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_access_same_device.3346088369 |
| Short name | T2525 |
| Test name | |
| Test status | |
| Simulation time | 355617202 ps |
| CPU time | 23.46 seconds |
| Started | Jul 03 07:37:45 PM PDT 24 |
| Finished | Jul 03 07:38:09 PM PDT 24 |
| Peak memory | 573996 kb |
| Host | smart-14f32020-b85b-4d3b-9a77-ea50ea0c0c09 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3346088369 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_access_same_device .3346088369 |
| Directory | /workspace/85.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_access_same_device_slow_rsp.3199169205 |
| Short name | T2340 |
| Test name | |
| Test status | |
| Simulation time | 96647792842 ps |
| CPU time | 1739.83 seconds |
| Started | Jul 03 07:37:51 PM PDT 24 |
| Finished | Jul 03 08:06:52 PM PDT 24 |
| Peak memory | 574312 kb |
| Host | smart-7a2ddd12-d3e5-4785-bd12-194a316ec8b8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3199169205 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_access_same_ device_slow_rsp.3199169205 |
| Directory | /workspace/85.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_error_and_unmapped_addr.4140443058 |
| Short name | T1631 |
| Test name | |
| Test status | |
| Simulation time | 901215836 ps |
| CPU time | 35.01 seconds |
| Started | Jul 03 07:37:52 PM PDT 24 |
| Finished | Jul 03 07:38:28 PM PDT 24 |
| Peak memory | 574484 kb |
| Host | smart-e0ce2cfc-1342-498f-962a-466716cf54b6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140443058 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_error_and_unmapped_add r.4140443058 |
| Directory | /workspace/85.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_error_random.2482365320 |
| Short name | T1678 |
| Test name | |
| Test status | |
| Simulation time | 475215622 ps |
| CPU time | 17.71 seconds |
| Started | Jul 03 07:37:42 PM PDT 24 |
| Finished | Jul 03 07:38:00 PM PDT 24 |
| Peak memory | 574464 kb |
| Host | smart-bb6504c2-f54c-4441-9313-1ce6985eb28d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2482365320 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_error_random.2482365320 |
| Directory | /workspace/85.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_random.1862459662 |
| Short name | T2755 |
| Test name | |
| Test status | |
| Simulation time | 525026659 ps |
| CPU time | 48 seconds |
| Started | Jul 03 07:37:37 PM PDT 24 |
| Finished | Jul 03 07:38:26 PM PDT 24 |
| Peak memory | 574188 kb |
| Host | smart-5778b76d-d804-44a7-b98f-fa5f9003f811 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1862459662 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_random.1862459662 |
| Directory | /workspace/85.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_random_large_delays.4215427857 |
| Short name | T1750 |
| Test name | |
| Test status | |
| Simulation time | 70250497328 ps |
| CPU time | 741.88 seconds |
| Started | Jul 03 07:37:50 PM PDT 24 |
| Finished | Jul 03 07:50:13 PM PDT 24 |
| Peak memory | 574104 kb |
| Host | smart-73d90075-8e1e-446a-bdfb-37806e62d3b3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4215427857 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_random_large_delays.4215427857 |
| Directory | /workspace/85.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_random_slow_rsp.1579415398 |
| Short name | T2130 |
| Test name | |
| Test status | |
| Simulation time | 9891277219 ps |
| CPU time | 166.29 seconds |
| Started | Jul 03 07:37:41 PM PDT 24 |
| Finished | Jul 03 07:40:28 PM PDT 24 |
| Peak memory | 574296 kb |
| Host | smart-43504457-a5c7-4dd2-b739-db59cc6c0931 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579415398 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_random_slow_rsp.1579415398 |
| Directory | /workspace/85.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_random_zero_delays.42215732 |
| Short name | T2044 |
| Test name | |
| Test status | |
| Simulation time | 365793593 ps |
| CPU time | 30.18 seconds |
| Started | Jul 03 07:37:41 PM PDT 24 |
| Finished | Jul 03 07:38:12 PM PDT 24 |
| Peak memory | 574016 kb |
| Host | smart-75f6ac83-ea07-48eb-86b8-d4226dea9f26 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42215732 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_random_zero_delay s.42215732 |
| Directory | /workspace/85.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_same_source.1977032764 |
| Short name | T2426 |
| Test name | |
| Test status | |
| Simulation time | 52117022 ps |
| CPU time | 6.41 seconds |
| Started | Jul 03 07:37:52 PM PDT 24 |
| Finished | Jul 03 07:38:00 PM PDT 24 |
| Peak memory | 572964 kb |
| Host | smart-075ce094-eca2-4c68-a002-b66db047862e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1977032764 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_same_source.1977032764 |
| Directory | /workspace/85.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_smoke.2712240585 |
| Short name | T2472 |
| Test name | |
| Test status | |
| Simulation time | 42369246 ps |
| CPU time | 5.95 seconds |
| Started | Jul 03 07:37:36 PM PDT 24 |
| Finished | Jul 03 07:37:43 PM PDT 24 |
| Peak memory | 573976 kb |
| Host | smart-e17ae690-8751-4434-a978-611657967219 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2712240585 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_smoke.2712240585 |
| Directory | /workspace/85.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_smoke_large_delays.2863367888 |
| Short name | T2177 |
| Test name | |
| Test status | |
| Simulation time | 7456519363 ps |
| CPU time | 76.1 seconds |
| Started | Jul 03 07:37:41 PM PDT 24 |
| Finished | Jul 03 07:38:58 PM PDT 24 |
| Peak memory | 573180 kb |
| Host | smart-30c883fe-fad7-4dfe-9469-72cd71f11a4d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2863367888 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_smoke_large_delays.2863367888 |
| Directory | /workspace/85.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_smoke_slow_rsp.833778649 |
| Short name | T1373 |
| Test name | |
| Test status | |
| Simulation time | 6270419003 ps |
| CPU time | 110.49 seconds |
| Started | Jul 03 07:37:35 PM PDT 24 |
| Finished | Jul 03 07:39:27 PM PDT 24 |
| Peak memory | 574144 kb |
| Host | smart-2532bc45-214b-4cc4-814a-c629f351df07 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=833778649 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_smoke_slow_rsp.833778649 |
| Directory | /workspace/85.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_smoke_zero_delays.2571002361 |
| Short name | T1343 |
| Test name | |
| Test status | |
| Simulation time | 56469203 ps |
| CPU time | 6.75 seconds |
| Started | Jul 03 07:37:35 PM PDT 24 |
| Finished | Jul 03 07:37:42 PM PDT 24 |
| Peak memory | 574076 kb |
| Host | smart-15bce645-4f77-43ff-a953-023a3535930c |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2571002361 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_smoke_zero_delay s.2571002361 |
| Directory | /workspace/85.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_stress_all.1059698314 |
| Short name | T2873 |
| Test name | |
| Test status | |
| Simulation time | 16335943098 ps |
| CPU time | 658.34 seconds |
| Started | Jul 03 07:37:42 PM PDT 24 |
| Finished | Jul 03 07:48:42 PM PDT 24 |
| Peak memory | 574736 kb |
| Host | smart-b0479103-6ecc-4b69-a0aa-a5ad40810cfd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1059698314 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_stress_all.1059698314 |
| Directory | /workspace/85.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_stress_all_with_error.1794798695 |
| Short name | T2037 |
| Test name | |
| Test status | |
| Simulation time | 8004958604 ps |
| CPU time | 254.06 seconds |
| Started | Jul 03 07:37:44 PM PDT 24 |
| Finished | Jul 03 07:41:58 PM PDT 24 |
| Peak memory | 574772 kb |
| Host | smart-8235e0df-dac9-47fa-8bcc-e000587dd9c6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1794798695 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_stress_all_with_error.1794798695 |
| Directory | /workspace/85.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_stress_all_with_rand_reset.3265531580 |
| Short name | T2690 |
| Test name | |
| Test status | |
| Simulation time | 1304339928 ps |
| CPU time | 306.03 seconds |
| Started | Jul 03 07:37:40 PM PDT 24 |
| Finished | Jul 03 07:42:47 PM PDT 24 |
| Peak memory | 574692 kb |
| Host | smart-7b8bdec6-2bc4-472b-b04d-29094066b0f4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3265531580 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_stress_all _with_rand_reset.3265531580 |
| Directory | /workspace/85.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_stress_all_with_reset_error.3963408982 |
| Short name | T1450 |
| Test name | |
| Test status | |
| Simulation time | 4053887923 ps |
| CPU time | 352.91 seconds |
| Started | Jul 03 07:37:45 PM PDT 24 |
| Finished | Jul 03 07:43:39 PM PDT 24 |
| Peak memory | 574680 kb |
| Host | smart-6e14aa7f-12a2-4c9c-9c4c-b8b83213dff3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3963408982 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_stress_al l_with_reset_error.3963408982 |
| Directory | /workspace/85.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_unmapped_addr.1286952350 |
| Short name | T1543 |
| Test name | |
| Test status | |
| Simulation time | 1266497008 ps |
| CPU time | 53.54 seconds |
| Started | Jul 03 07:37:42 PM PDT 24 |
| Finished | Jul 03 07:38:36 PM PDT 24 |
| Peak memory | 573964 kb |
| Host | smart-da050436-b766-4fcb-aadc-72f84643d8a1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1286952350 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_unmapped_addr.1286952350 |
| Directory | /workspace/85.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_access_same_device.4023667397 |
| Short name | T1474 |
| Test name | |
| Test status | |
| Simulation time | 1057740654 ps |
| CPU time | 78.18 seconds |
| Started | Jul 03 07:37:50 PM PDT 24 |
| Finished | Jul 03 07:39:09 PM PDT 24 |
| Peak memory | 574252 kb |
| Host | smart-16537476-7f9f-48ec-91f3-dceffb5b7f1e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4023667397 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_access_same_device .4023667397 |
| Directory | /workspace/86.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_access_same_device_slow_rsp.3730201797 |
| Short name | T1945 |
| Test name | |
| Test status | |
| Simulation time | 51460599881 ps |
| CPU time | 938.88 seconds |
| Started | Jul 03 07:37:45 PM PDT 24 |
| Finished | Jul 03 07:53:25 PM PDT 24 |
| Peak memory | 574376 kb |
| Host | smart-9b449e18-1205-4732-8c2b-e5e35bfe1cce |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3730201797 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_access_same_ device_slow_rsp.3730201797 |
| Directory | /workspace/86.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_error_and_unmapped_addr.164402138 |
| Short name | T2717 |
| Test name | |
| Test status | |
| Simulation time | 1354990257 ps |
| CPU time | 57.03 seconds |
| Started | Jul 03 07:37:50 PM PDT 24 |
| Finished | Jul 03 07:38:48 PM PDT 24 |
| Peak memory | 574032 kb |
| Host | smart-da788f44-dc37-42c4-ab98-18cf488cfa75 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=164402138 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_error_and_unmapped_addr .164402138 |
| Directory | /workspace/86.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_error_random.3902758598 |
| Short name | T1408 |
| Test name | |
| Test status | |
| Simulation time | 353626532 ps |
| CPU time | 27.74 seconds |
| Started | Jul 03 07:37:48 PM PDT 24 |
| Finished | Jul 03 07:38:17 PM PDT 24 |
| Peak memory | 574548 kb |
| Host | smart-23a88ca3-8107-4f33-b699-143a312cd3b0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3902758598 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_error_random.3902758598 |
| Directory | /workspace/86.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_random.518791776 |
| Short name | T2490 |
| Test name | |
| Test status | |
| Simulation time | 1305068896 ps |
| CPU time | 44.06 seconds |
| Started | Jul 03 07:37:44 PM PDT 24 |
| Finished | Jul 03 07:38:29 PM PDT 24 |
| Peak memory | 574100 kb |
| Host | smart-bd005d42-f1ce-4317-875f-673a5555298c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=518791776 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_random.518791776 |
| Directory | /workspace/86.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_random_large_delays.2714559524 |
| Short name | T1492 |
| Test name | |
| Test status | |
| Simulation time | 31330048267 ps |
| CPU time | 356.41 seconds |
| Started | Jul 03 07:37:44 PM PDT 24 |
| Finished | Jul 03 07:43:41 PM PDT 24 |
| Peak memory | 574268 kb |
| Host | smart-146b6895-b884-4dd0-84c2-c81b2f0e8727 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2714559524 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_random_large_delays.2714559524 |
| Directory | /workspace/86.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_random_slow_rsp.288769089 |
| Short name | T2505 |
| Test name | |
| Test status | |
| Simulation time | 15210615741 ps |
| CPU time | 252.72 seconds |
| Started | Jul 03 07:37:47 PM PDT 24 |
| Finished | Jul 03 07:42:01 PM PDT 24 |
| Peak memory | 574280 kb |
| Host | smart-349f2c9b-05ec-408a-b38d-f31749e560f1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288769089 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_random_slow_rsp.288769089 |
| Directory | /workspace/86.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_random_zero_delays.4276288855 |
| Short name | T2167 |
| Test name | |
| Test status | |
| Simulation time | 35662588 ps |
| CPU time | 5.8 seconds |
| Started | Jul 03 07:37:43 PM PDT 24 |
| Finished | Jul 03 07:37:49 PM PDT 24 |
| Peak memory | 572924 kb |
| Host | smart-160f6108-d3d9-4769-966a-f85dc686f85c |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4276288855 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_random_zero_del ays.4276288855 |
| Directory | /workspace/86.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_same_source.170184584 |
| Short name | T2784 |
| Test name | |
| Test status | |
| Simulation time | 2350893077 ps |
| CPU time | 70.63 seconds |
| Started | Jul 03 07:37:50 PM PDT 24 |
| Finished | Jul 03 07:39:02 PM PDT 24 |
| Peak memory | 574268 kb |
| Host | smart-497e6588-d654-4a75-93db-71d7a57367be |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=170184584 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_same_source.170184584 |
| Directory | /workspace/86.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_smoke.2283208967 |
| Short name | T1944 |
| Test name | |
| Test status | |
| Simulation time | 45913151 ps |
| CPU time | 6.06 seconds |
| Started | Jul 03 07:37:52 PM PDT 24 |
| Finished | Jul 03 07:38:00 PM PDT 24 |
| Peak memory | 574108 kb |
| Host | smart-a9825af9-09f8-4a34-a9f4-87e8d54d356e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2283208967 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_smoke.2283208967 |
| Directory | /workspace/86.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_smoke_large_delays.1860417720 |
| Short name | T1767 |
| Test name | |
| Test status | |
| Simulation time | 5541826030 ps |
| CPU time | 58.37 seconds |
| Started | Jul 03 07:37:46 PM PDT 24 |
| Finished | Jul 03 07:38:45 PM PDT 24 |
| Peak memory | 573200 kb |
| Host | smart-dd870a97-c67c-4bdd-ab26-e5884f9a913e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1860417720 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_smoke_large_delays.1860417720 |
| Directory | /workspace/86.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_smoke_slow_rsp.3609974516 |
| Short name | T2298 |
| Test name | |
| Test status | |
| Simulation time | 5532022893 ps |
| CPU time | 96.3 seconds |
| Started | Jul 03 07:37:44 PM PDT 24 |
| Finished | Jul 03 07:39:21 PM PDT 24 |
| Peak memory | 573056 kb |
| Host | smart-eeb3aa69-f67b-458d-826c-6e09d607c551 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3609974516 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_smoke_slow_rsp.3609974516 |
| Directory | /workspace/86.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_smoke_zero_delays.909216314 |
| Short name | T1632 |
| Test name | |
| Test status | |
| Simulation time | 50308504 ps |
| CPU time | 6.67 seconds |
| Started | Jul 03 07:37:43 PM PDT 24 |
| Finished | Jul 03 07:37:50 PM PDT 24 |
| Peak memory | 572912 kb |
| Host | smart-ff2c791d-d3c6-4ad6-978e-f4019feb3753 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=909216314 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_smoke_zero_delays .909216314 |
| Directory | /workspace/86.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_stress_all.1032843440 |
| Short name | T2785 |
| Test name | |
| Test status | |
| Simulation time | 3766539890 ps |
| CPU time | 116.01 seconds |
| Started | Jul 03 07:37:51 PM PDT 24 |
| Finished | Jul 03 07:39:48 PM PDT 24 |
| Peak memory | 574316 kb |
| Host | smart-bf7674e4-905b-435c-ba1a-9c95128e3d82 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1032843440 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_stress_all.1032843440 |
| Directory | /workspace/86.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_stress_all_with_error.3255520097 |
| Short name | T2540 |
| Test name | |
| Test status | |
| Simulation time | 5377807208 ps |
| CPU time | 203.84 seconds |
| Started | Jul 03 07:37:48 PM PDT 24 |
| Finished | Jul 03 07:41:12 PM PDT 24 |
| Peak memory | 574608 kb |
| Host | smart-3e6944ab-8c9b-4a2d-b998-ca80aba27a4d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3255520097 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_stress_all_with_error.3255520097 |
| Directory | /workspace/86.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_stress_all_with_rand_reset.3910357960 |
| Short name | T1761 |
| Test name | |
| Test status | |
| Simulation time | 14874170127 ps |
| CPU time | 895.26 seconds |
| Started | Jul 03 07:37:50 PM PDT 24 |
| Finished | Jul 03 07:52:46 PM PDT 24 |
| Peak memory | 574740 kb |
| Host | smart-84f704b9-cb1f-4b32-b8c3-43845240933e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3910357960 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_stress_all _with_rand_reset.3910357960 |
| Directory | /workspace/86.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_stress_all_with_reset_error.427321150 |
| Short name | T2000 |
| Test name | |
| Test status | |
| Simulation time | 333068079 ps |
| CPU time | 146.47 seconds |
| Started | Jul 03 07:37:53 PM PDT 24 |
| Finished | Jul 03 07:40:21 PM PDT 24 |
| Peak memory | 574664 kb |
| Host | smart-eb2b12a5-e2dd-4d63-9f80-41713613b02e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427321150 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_stress_all _with_reset_error.427321150 |
| Directory | /workspace/86.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_unmapped_addr.3284240127 |
| Short name | T1839 |
| Test name | |
| Test status | |
| Simulation time | 634345246 ps |
| CPU time | 29.77 seconds |
| Started | Jul 03 07:37:51 PM PDT 24 |
| Finished | Jul 03 07:38:21 PM PDT 24 |
| Peak memory | 574224 kb |
| Host | smart-5cd9b664-7528-4091-81d7-58f07fa5756d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3284240127 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_unmapped_addr.3284240127 |
| Directory | /workspace/86.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_access_same_device.2903799470 |
| Short name | T2325 |
| Test name | |
| Test status | |
| Simulation time | 2400526695 ps |
| CPU time | 87 seconds |
| Started | Jul 03 07:37:54 PM PDT 24 |
| Finished | Jul 03 07:39:22 PM PDT 24 |
| Peak memory | 574224 kb |
| Host | smart-59c2c9a8-a640-4db4-a984-56efe6b8b26a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2903799470 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_access_same_device .2903799470 |
| Directory | /workspace/87.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_access_same_device_slow_rsp.1233813996 |
| Short name | T786 |
| Test name | |
| Test status | |
| Simulation time | 101161204900 ps |
| CPU time | 1836.89 seconds |
| Started | Jul 03 07:37:57 PM PDT 24 |
| Finished | Jul 03 08:08:35 PM PDT 24 |
| Peak memory | 574188 kb |
| Host | smart-0b9b0067-c422-493c-84b1-c247f19b28c5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233813996 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_access_same_ device_slow_rsp.1233813996 |
| Directory | /workspace/87.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_error_and_unmapped_addr.2270095975 |
| Short name | T2361 |
| Test name | |
| Test status | |
| Simulation time | 236394716 ps |
| CPU time | 12.1 seconds |
| Started | Jul 03 07:37:56 PM PDT 24 |
| Finished | Jul 03 07:38:09 PM PDT 24 |
| Peak memory | 574044 kb |
| Host | smart-0f4d7ca0-50bb-4bf2-9ee5-98ae3fb8d4c3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2270095975 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_error_and_unmapped_add r.2270095975 |
| Directory | /workspace/87.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_error_random.2086351533 |
| Short name | T2670 |
| Test name | |
| Test status | |
| Simulation time | 1603304380 ps |
| CPU time | 55.09 seconds |
| Started | Jul 03 07:37:54 PM PDT 24 |
| Finished | Jul 03 07:38:50 PM PDT 24 |
| Peak memory | 574452 kb |
| Host | smart-06d260e7-dfbb-464c-a2eb-c7ba5cd2f302 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2086351533 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_error_random.2086351533 |
| Directory | /workspace/87.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_random.3498110510 |
| Short name | T1765 |
| Test name | |
| Test status | |
| Simulation time | 1014550511 ps |
| CPU time | 37.79 seconds |
| Started | Jul 03 07:37:56 PM PDT 24 |
| Finished | Jul 03 07:38:34 PM PDT 24 |
| Peak memory | 574212 kb |
| Host | smart-e98dd207-9387-4fee-a10d-770f472f15c7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3498110510 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_random.3498110510 |
| Directory | /workspace/87.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_random_large_delays.1019880097 |
| Short name | T2433 |
| Test name | |
| Test status | |
| Simulation time | 11425193918 ps |
| CPU time | 115.99 seconds |
| Started | Jul 03 07:37:57 PM PDT 24 |
| Finished | Jul 03 07:39:53 PM PDT 24 |
| Peak memory | 574240 kb |
| Host | smart-9771ffed-9038-40c7-acea-4a07a937da4a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1019880097 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_random_large_delays.1019880097 |
| Directory | /workspace/87.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_random_slow_rsp.2060091362 |
| Short name | T494 |
| Test name | |
| Test status | |
| Simulation time | 44325695755 ps |
| CPU time | 741.4 seconds |
| Started | Jul 03 07:37:59 PM PDT 24 |
| Finished | Jul 03 07:50:21 PM PDT 24 |
| Peak memory | 574288 kb |
| Host | smart-0b7d2227-79d2-4c02-8f49-0b4de84a2a7d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2060091362 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_random_slow_rsp.2060091362 |
| Directory | /workspace/87.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_random_zero_delays.4053182891 |
| Short name | T462 |
| Test name | |
| Test status | |
| Simulation time | 253630909 ps |
| CPU time | 21.85 seconds |
| Started | Jul 03 07:37:54 PM PDT 24 |
| Finished | Jul 03 07:38:17 PM PDT 24 |
| Peak memory | 574244 kb |
| Host | smart-04217052-2a42-4df3-abcd-5316571e01c9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4053182891 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_random_zero_del ays.4053182891 |
| Directory | /workspace/87.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_same_source.3037238187 |
| Short name | T571 |
| Test name | |
| Test status | |
| Simulation time | 1082767069 ps |
| CPU time | 30.19 seconds |
| Started | Jul 03 07:37:58 PM PDT 24 |
| Finished | Jul 03 07:38:29 PM PDT 24 |
| Peak memory | 574208 kb |
| Host | smart-60947177-e8f7-405f-966c-fcb02d64efab |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3037238187 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_same_source.3037238187 |
| Directory | /workspace/87.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_smoke.381283254 |
| Short name | T2577 |
| Test name | |
| Test status | |
| Simulation time | 197558067 ps |
| CPU time | 8.99 seconds |
| Started | Jul 03 07:37:51 PM PDT 24 |
| Finished | Jul 03 07:38:01 PM PDT 24 |
| Peak memory | 573128 kb |
| Host | smart-96020a7b-0bc0-47b8-ad6b-1d7dabfe0781 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=381283254 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_smoke.381283254 |
| Directory | /workspace/87.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_smoke_large_delays.1863714440 |
| Short name | T2550 |
| Test name | |
| Test status | |
| Simulation time | 9685770881 ps |
| CPU time | 105.15 seconds |
| Started | Jul 03 07:37:55 PM PDT 24 |
| Finished | Jul 03 07:39:40 PM PDT 24 |
| Peak memory | 573044 kb |
| Host | smart-7d1f8b0d-6025-412e-9364-3e3ba2e1e992 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1863714440 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_smoke_large_delays.1863714440 |
| Directory | /workspace/87.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_smoke_slow_rsp.1987186745 |
| Short name | T2598 |
| Test name | |
| Test status | |
| Simulation time | 4510164839 ps |
| CPU time | 75.86 seconds |
| Started | Jul 03 07:37:57 PM PDT 24 |
| Finished | Jul 03 07:39:14 PM PDT 24 |
| Peak memory | 572964 kb |
| Host | smart-322b0dee-6639-45f6-8bb9-0262dd444d53 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1987186745 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_smoke_slow_rsp.1987186745 |
| Directory | /workspace/87.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_smoke_zero_delays.1818482698 |
| Short name | T2314 |
| Test name | |
| Test status | |
| Simulation time | 57560620 ps |
| CPU time | 7.05 seconds |
| Started | Jul 03 07:37:57 PM PDT 24 |
| Finished | Jul 03 07:38:05 PM PDT 24 |
| Peak memory | 573160 kb |
| Host | smart-caa5580f-27ba-44cc-aebc-86f352fc8ea4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818482698 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_smoke_zero_delay s.1818482698 |
| Directory | /workspace/87.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_stress_all.2904818057 |
| Short name | T467 |
| Test name | |
| Test status | |
| Simulation time | 3914800998 ps |
| CPU time | 332.66 seconds |
| Started | Jul 03 07:37:55 PM PDT 24 |
| Finished | Jul 03 07:43:28 PM PDT 24 |
| Peak memory | 574704 kb |
| Host | smart-2ed80054-ef3f-4ac2-b595-dc087233feea |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2904818057 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_stress_all.2904818057 |
| Directory | /workspace/87.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_stress_all_with_error.1043159563 |
| Short name | T1362 |
| Test name | |
| Test status | |
| Simulation time | 1716391244 ps |
| CPU time | 139.97 seconds |
| Started | Jul 03 07:37:59 PM PDT 24 |
| Finished | Jul 03 07:40:19 PM PDT 24 |
| Peak memory | 574540 kb |
| Host | smart-b8b6eddb-d891-4042-b765-6248f5d4461b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1043159563 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_stress_all_with_error.1043159563 |
| Directory | /workspace/87.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_stress_all_with_rand_reset.1577416535 |
| Short name | T1842 |
| Test name | |
| Test status | |
| Simulation time | 182394818 ps |
| CPU time | 129.5 seconds |
| Started | Jul 03 07:37:59 PM PDT 24 |
| Finished | Jul 03 07:40:09 PM PDT 24 |
| Peak memory | 574660 kb |
| Host | smart-87dd18cb-d2ea-40a8-aeab-6adbbb61a3dd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1577416535 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_stress_all _with_rand_reset.1577416535 |
| Directory | /workspace/87.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_stress_all_with_reset_error.1196934250 |
| Short name | T2099 |
| Test name | |
| Test status | |
| Simulation time | 977372025 ps |
| CPU time | 127.7 seconds |
| Started | Jul 03 07:37:58 PM PDT 24 |
| Finished | Jul 03 07:40:06 PM PDT 24 |
| Peak memory | 574684 kb |
| Host | smart-3299fea3-a255-44e7-98dc-e42ee99c4da7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1196934250 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_stress_al l_with_reset_error.1196934250 |
| Directory | /workspace/87.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_unmapped_addr.3213528712 |
| Short name | T2383 |
| Test name | |
| Test status | |
| Simulation time | 517878508 ps |
| CPU time | 24.69 seconds |
| Started | Jul 03 07:37:56 PM PDT 24 |
| Finished | Jul 03 07:38:22 PM PDT 24 |
| Peak memory | 574216 kb |
| Host | smart-6f84525b-6c65-4542-b9a0-13491dac36bd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3213528712 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_unmapped_addr.3213528712 |
| Directory | /workspace/87.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_access_same_device.2236846135 |
| Short name | T2816 |
| Test name | |
| Test status | |
| Simulation time | 293818634 ps |
| CPU time | 22.58 seconds |
| Started | Jul 03 07:38:09 PM PDT 24 |
| Finished | Jul 03 07:38:32 PM PDT 24 |
| Peak memory | 574032 kb |
| Host | smart-42ff15b5-727d-4432-ba78-0e94928abe79 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2236846135 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_access_same_device .2236846135 |
| Directory | /workspace/88.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_access_same_device_slow_rsp.823074338 |
| Short name | T2396 |
| Test name | |
| Test status | |
| Simulation time | 71044096647 ps |
| CPU time | 1333.92 seconds |
| Started | Jul 03 07:38:06 PM PDT 24 |
| Finished | Jul 03 08:00:21 PM PDT 24 |
| Peak memory | 574240 kb |
| Host | smart-a6e138ff-6d22-45d3-9314-2e24d088c0bb |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=823074338 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_access_same_d evice_slow_rsp.823074338 |
| Directory | /workspace/88.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_error_and_unmapped_addr.1316344416 |
| Short name | T2485 |
| Test name | |
| Test status | |
| Simulation time | 485616672 ps |
| CPU time | 19.8 seconds |
| Started | Jul 03 07:38:07 PM PDT 24 |
| Finished | Jul 03 07:38:27 PM PDT 24 |
| Peak memory | 574012 kb |
| Host | smart-f50bd344-14e3-4cf0-8aeb-b6fc57d10c02 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1316344416 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_error_and_unmapped_add r.1316344416 |
| Directory | /workspace/88.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_error_random.2968478701 |
| Short name | T2311 |
| Test name | |
| Test status | |
| Simulation time | 1617858615 ps |
| CPU time | 60.46 seconds |
| Started | Jul 03 07:38:05 PM PDT 24 |
| Finished | Jul 03 07:39:06 PM PDT 24 |
| Peak memory | 574472 kb |
| Host | smart-fd9eb459-553c-467d-9eff-f05577570aca |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2968478701 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_error_random.2968478701 |
| Directory | /workspace/88.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_random.2885064188 |
| Short name | T1314 |
| Test name | |
| Test status | |
| Simulation time | 110586357 ps |
| CPU time | 7.58 seconds |
| Started | Jul 03 07:37:59 PM PDT 24 |
| Finished | Jul 03 07:38:08 PM PDT 24 |
| Peak memory | 574136 kb |
| Host | smart-e9204140-ea86-4cc0-be82-352e189d87be |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885064188 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_random.2885064188 |
| Directory | /workspace/88.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_random_large_delays.3868917101 |
| Short name | T2303 |
| Test name | |
| Test status | |
| Simulation time | 98204961621 ps |
| CPU time | 1068.83 seconds |
| Started | Jul 03 07:38:01 PM PDT 24 |
| Finished | Jul 03 07:55:51 PM PDT 24 |
| Peak memory | 574180 kb |
| Host | smart-4cdcb2d0-4a31-4709-9dc1-d23e63cba47e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3868917101 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_random_large_delays.3868917101 |
| Directory | /workspace/88.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_random_slow_rsp.1751352451 |
| Short name | T1441 |
| Test name | |
| Test status | |
| Simulation time | 50728868385 ps |
| CPU time | 796.52 seconds |
| Started | Jul 03 07:38:02 PM PDT 24 |
| Finished | Jul 03 07:51:19 PM PDT 24 |
| Peak memory | 574240 kb |
| Host | smart-07c1329b-7c56-4236-9c06-c68dcaf484b2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1751352451 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_random_slow_rsp.1751352451 |
| Directory | /workspace/88.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_random_zero_delays.3430199757 |
| Short name | T1508 |
| Test name | |
| Test status | |
| Simulation time | 282411937 ps |
| CPU time | 26.39 seconds |
| Started | Jul 03 07:38:01 PM PDT 24 |
| Finished | Jul 03 07:38:28 PM PDT 24 |
| Peak memory | 574216 kb |
| Host | smart-ae2ce7f8-c44d-4142-a37d-447ab5fc3f5d |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430199757 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_random_zero_del ays.3430199757 |
| Directory | /workspace/88.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_same_source.3570714055 |
| Short name | T1827 |
| Test name | |
| Test status | |
| Simulation time | 292162266 ps |
| CPU time | 21.43 seconds |
| Started | Jul 03 07:38:03 PM PDT 24 |
| Finished | Jul 03 07:38:25 PM PDT 24 |
| Peak memory | 573992 kb |
| Host | smart-6daced06-0214-4d83-bbe0-81dc1391257e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3570714055 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_same_source.3570714055 |
| Directory | /workspace/88.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_smoke.2889991704 |
| Short name | T2330 |
| Test name | |
| Test status | |
| Simulation time | 46020915 ps |
| CPU time | 6.72 seconds |
| Started | Jul 03 07:37:59 PM PDT 24 |
| Finished | Jul 03 07:38:06 PM PDT 24 |
| Peak memory | 573120 kb |
| Host | smart-dca183e4-0489-4e0a-9048-9750820a9b71 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2889991704 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_smoke.2889991704 |
| Directory | /workspace/88.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_smoke_large_delays.2319242810 |
| Short name | T2368 |
| Test name | |
| Test status | |
| Simulation time | 8105662193 ps |
| CPU time | 87.24 seconds |
| Started | Jul 03 07:38:01 PM PDT 24 |
| Finished | Jul 03 07:39:29 PM PDT 24 |
| Peak memory | 573176 kb |
| Host | smart-c62f932d-4365-4b98-bd36-66dd3bfdc073 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2319242810 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_smoke_large_delays.2319242810 |
| Directory | /workspace/88.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_smoke_slow_rsp.1015446977 |
| Short name | T2302 |
| Test name | |
| Test status | |
| Simulation time | 5325860723 ps |
| CPU time | 89.02 seconds |
| Started | Jul 03 07:38:03 PM PDT 24 |
| Finished | Jul 03 07:39:33 PM PDT 24 |
| Peak memory | 574160 kb |
| Host | smart-5cf22043-c1f4-4569-9bef-2c81b8bab606 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1015446977 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_smoke_slow_rsp.1015446977 |
| Directory | /workspace/88.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_smoke_zero_delays.925311163 |
| Short name | T2227 |
| Test name | |
| Test status | |
| Simulation time | 48360121 ps |
| CPU time | 6.55 seconds |
| Started | Jul 03 07:38:00 PM PDT 24 |
| Finished | Jul 03 07:38:07 PM PDT 24 |
| Peak memory | 573236 kb |
| Host | smart-c6a25535-647b-45a7-9a0c-50df74ff4dc5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=925311163 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_smoke_zero_delays .925311163 |
| Directory | /workspace/88.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_stress_all.2959065628 |
| Short name | T2254 |
| Test name | |
| Test status | |
| Simulation time | 15530911624 ps |
| CPU time | 582.08 seconds |
| Started | Jul 03 07:38:04 PM PDT 24 |
| Finished | Jul 03 07:47:47 PM PDT 24 |
| Peak memory | 574796 kb |
| Host | smart-bfc65108-ed84-4715-b081-a96e08071918 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2959065628 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_stress_all.2959065628 |
| Directory | /workspace/88.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_stress_all_with_rand_reset.3038218895 |
| Short name | T2836 |
| Test name | |
| Test status | |
| Simulation time | 4886027253 ps |
| CPU time | 350.18 seconds |
| Started | Jul 03 07:38:04 PM PDT 24 |
| Finished | Jul 03 07:43:54 PM PDT 24 |
| Peak memory | 574724 kb |
| Host | smart-04d27173-00d4-4668-ad5b-1d64107e459e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3038218895 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_stress_all _with_rand_reset.3038218895 |
| Directory | /workspace/88.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_stress_all_with_reset_error.2024119157 |
| Short name | T2231 |
| Test name | |
| Test status | |
| Simulation time | 199174474 ps |
| CPU time | 44.77 seconds |
| Started | Jul 03 07:38:12 PM PDT 24 |
| Finished | Jul 03 07:38:58 PM PDT 24 |
| Peak memory | 574192 kb |
| Host | smart-e3df4cbe-6e4c-4fbf-8016-965d5b822030 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024119157 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_stress_al l_with_reset_error.2024119157 |
| Directory | /workspace/88.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_unmapped_addr.3203968991 |
| Short name | T2623 |
| Test name | |
| Test status | |
| Simulation time | 53566307 ps |
| CPU time | 9.33 seconds |
| Started | Jul 03 07:38:06 PM PDT 24 |
| Finished | Jul 03 07:38:16 PM PDT 24 |
| Peak memory | 574164 kb |
| Host | smart-f58f004f-e4f2-4577-9b84-9b5036374665 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3203968991 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_unmapped_addr.3203968991 |
| Directory | /workspace/88.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_access_same_device.854022556 |
| Short name | T776 |
| Test name | |
| Test status | |
| Simulation time | 2076641404 ps |
| CPU time | 79.88 seconds |
| Started | Jul 03 07:38:14 PM PDT 24 |
| Finished | Jul 03 07:39:35 PM PDT 24 |
| Peak memory | 574248 kb |
| Host | smart-406cf4f0-596a-434a-a137-696c5557fb66 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=854022556 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_access_same_device. 854022556 |
| Directory | /workspace/89.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_access_same_device_slow_rsp.1750545165 |
| Short name | T2329 |
| Test name | |
| Test status | |
| Simulation time | 48624299359 ps |
| CPU time | 893.04 seconds |
| Started | Jul 03 07:38:16 PM PDT 24 |
| Finished | Jul 03 07:53:10 PM PDT 24 |
| Peak memory | 574432 kb |
| Host | smart-f7173305-1291-471e-b377-94890eb438ae |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1750545165 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_access_same_ device_slow_rsp.1750545165 |
| Directory | /workspace/89.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_error_and_unmapped_addr.2632896842 |
| Short name | T2534 |
| Test name | |
| Test status | |
| Simulation time | 146133130 ps |
| CPU time | 17.25 seconds |
| Started | Jul 03 07:38:18 PM PDT 24 |
| Finished | Jul 03 07:38:36 PM PDT 24 |
| Peak memory | 574436 kb |
| Host | smart-731f05a7-f6b1-4857-8cba-57dd368acd7c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632896842 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_error_and_unmapped_add r.2632896842 |
| Directory | /workspace/89.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_error_random.431353910 |
| Short name | T2528 |
| Test name | |
| Test status | |
| Simulation time | 2116646723 ps |
| CPU time | 68.24 seconds |
| Started | Jul 03 07:38:15 PM PDT 24 |
| Finished | Jul 03 07:39:24 PM PDT 24 |
| Peak memory | 574396 kb |
| Host | smart-e49e0992-9acb-4fdf-81d4-4a41f08f8eac |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=431353910 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_error_random.431353910 |
| Directory | /workspace/89.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_random.2937382444 |
| Short name | T1461 |
| Test name | |
| Test status | |
| Simulation time | 506062651 ps |
| CPU time | 22.14 seconds |
| Started | Jul 03 07:38:15 PM PDT 24 |
| Finished | Jul 03 07:38:38 PM PDT 24 |
| Peak memory | 574192 kb |
| Host | smart-6e7e27d4-4133-4955-9928-2884ed3ff1b1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2937382444 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_random.2937382444 |
| Directory | /workspace/89.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_random_large_delays.513694924 |
| Short name | T1532 |
| Test name | |
| Test status | |
| Simulation time | 98003740506 ps |
| CPU time | 1125.27 seconds |
| Started | Jul 03 07:38:14 PM PDT 24 |
| Finished | Jul 03 07:57:00 PM PDT 24 |
| Peak memory | 574208 kb |
| Host | smart-5195499d-12e2-4e9d-ab34-6a3bba1c85d7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=513694924 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_random_large_delays.513694924 |
| Directory | /workspace/89.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_random_slow_rsp.3831643650 |
| Short name | T2530 |
| Test name | |
| Test status | |
| Simulation time | 42518289554 ps |
| CPU time | 846.26 seconds |
| Started | Jul 03 07:38:13 PM PDT 24 |
| Finished | Jul 03 07:52:20 PM PDT 24 |
| Peak memory | 574124 kb |
| Host | smart-629d68c2-fed8-4881-9ef0-b5b9737f954b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3831643650 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_random_slow_rsp.3831643650 |
| Directory | /workspace/89.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_random_zero_delays.1321477626 |
| Short name | T2244 |
| Test name | |
| Test status | |
| Simulation time | 93642722 ps |
| CPU time | 10.86 seconds |
| Started | Jul 03 07:38:18 PM PDT 24 |
| Finished | Jul 03 07:38:30 PM PDT 24 |
| Peak memory | 574216 kb |
| Host | smart-d138891c-2474-4559-8879-b7fe6026e9a6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1321477626 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_random_zero_del ays.1321477626 |
| Directory | /workspace/89.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_same_source.2044641505 |
| Short name | T1810 |
| Test name | |
| Test status | |
| Simulation time | 339339618 ps |
| CPU time | 25.79 seconds |
| Started | Jul 03 07:38:17 PM PDT 24 |
| Finished | Jul 03 07:38:43 PM PDT 24 |
| Peak memory | 574172 kb |
| Host | smart-f3f17d35-baa4-4ff4-b0e0-38031235a896 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2044641505 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_same_source.2044641505 |
| Directory | /workspace/89.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_smoke.3710075984 |
| Short name | T2574 |
| Test name | |
| Test status | |
| Simulation time | 45747147 ps |
| CPU time | 6.22 seconds |
| Started | Jul 03 07:38:12 PM PDT 24 |
| Finished | Jul 03 07:38:19 PM PDT 24 |
| Peak memory | 572980 kb |
| Host | smart-db551229-4291-41c8-a647-b64771917861 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3710075984 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_smoke.3710075984 |
| Directory | /workspace/89.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_smoke_large_delays.3721667003 |
| Short name | T1537 |
| Test name | |
| Test status | |
| Simulation time | 7533650222 ps |
| CPU time | 81.25 seconds |
| Started | Jul 03 07:38:10 PM PDT 24 |
| Finished | Jul 03 07:39:32 PM PDT 24 |
| Peak memory | 573188 kb |
| Host | smart-7a9d8ceb-df10-40e1-904a-6c7cda46f6a2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3721667003 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_smoke_large_delays.3721667003 |
| Directory | /workspace/89.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_smoke_slow_rsp.223668195 |
| Short name | T1988 |
| Test name | |
| Test status | |
| Simulation time | 5537048847 ps |
| CPU time | 90.27 seconds |
| Started | Jul 03 07:38:16 PM PDT 24 |
| Finished | Jul 03 07:39:47 PM PDT 24 |
| Peak memory | 573192 kb |
| Host | smart-348e7bab-e2aa-4494-a1c9-ea4a97cdec6b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=223668195 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_smoke_slow_rsp.223668195 |
| Directory | /workspace/89.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_smoke_zero_delays.2929442617 |
| Short name | T1303 |
| Test name | |
| Test status | |
| Simulation time | 43220113 ps |
| CPU time | 6.49 seconds |
| Started | Jul 03 07:38:10 PM PDT 24 |
| Finished | Jul 03 07:38:18 PM PDT 24 |
| Peak memory | 572940 kb |
| Host | smart-a0199f17-7052-46d6-8737-e3ef9f44ed12 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2929442617 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_smoke_zero_delay s.2929442617 |
| Directory | /workspace/89.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_stress_all.2455042092 |
| Short name | T1682 |
| Test name | |
| Test status | |
| Simulation time | 2504346647 ps |
| CPU time | 194.64 seconds |
| Started | Jul 03 07:38:15 PM PDT 24 |
| Finished | Jul 03 07:41:30 PM PDT 24 |
| Peak memory | 574744 kb |
| Host | smart-e24da3b7-e7f2-4458-b396-21d88cd2e7d9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2455042092 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_stress_all.2455042092 |
| Directory | /workspace/89.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_stress_all_with_error.2559396251 |
| Short name | T778 |
| Test name | |
| Test status | |
| Simulation time | 8462310253 ps |
| CPU time | 291.42 seconds |
| Started | Jul 03 07:38:21 PM PDT 24 |
| Finished | Jul 03 07:43:14 PM PDT 24 |
| Peak memory | 574588 kb |
| Host | smart-8210ed63-2691-41e3-ab54-2c8bab027a93 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2559396251 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_stress_all_with_error.2559396251 |
| Directory | /workspace/89.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_stress_all_with_rand_reset.2804291541 |
| Short name | T608 |
| Test name | |
| Test status | |
| Simulation time | 322712496 ps |
| CPU time | 131.94 seconds |
| Started | Jul 03 07:38:18 PM PDT 24 |
| Finished | Jul 03 07:40:31 PM PDT 24 |
| Peak memory | 574692 kb |
| Host | smart-1f7f6c47-b98e-4566-8513-37ae1627f129 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804291541 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_stress_all _with_rand_reset.2804291541 |
| Directory | /workspace/89.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_stress_all_with_reset_error.3835798469 |
| Short name | T2500 |
| Test name | |
| Test status | |
| Simulation time | 2411433660 ps |
| CPU time | 264.93 seconds |
| Started | Jul 03 07:38:20 PM PDT 24 |
| Finished | Jul 03 07:42:46 PM PDT 24 |
| Peak memory | 574760 kb |
| Host | smart-7a86a4bc-ed25-4b69-8f7d-82e2afd9cd23 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3835798469 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_stress_al l_with_reset_error.3835798469 |
| Directory | /workspace/89.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_unmapped_addr.1414548104 |
| Short name | T1954 |
| Test name | |
| Test status | |
| Simulation time | 108173547 ps |
| CPU time | 15.18 seconds |
| Started | Jul 03 07:38:18 PM PDT 24 |
| Finished | Jul 03 07:38:34 PM PDT 24 |
| Peak memory | 574272 kb |
| Host | smart-e34e2ad9-b492-426e-9fb9-dddae9bc9f99 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1414548104 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_unmapped_addr.1414548104 |
| Directory | /workspace/89.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/9.chip_csr_rw.1463817088 |
| Short name | T2460 |
| Test name | |
| Test status | |
| Simulation time | 6118916059 ps |
| CPU time | 514.66 seconds |
| Started | Jul 03 07:23:46 PM PDT 24 |
| Finished | Jul 03 07:32:22 PM PDT 24 |
| Peak memory | 595988 kb |
| Host | smart-65eece2d-0f39-4e13-b713-873ac871e4c1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1463817088 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.chip_csr_rw.1463817088 |
| Directory | /workspace/9.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/9.chip_same_csr_outstanding.1667811125 |
| Short name | T379 |
| Test name | |
| Test status | |
| Simulation time | 16976081262 ps |
| CPU time | 2495.76 seconds |
| Started | Jul 03 07:23:48 PM PDT 24 |
| Finished | Jul 03 08:05:25 PM PDT 24 |
| Peak memory | 592116 kb |
| Host | smart-e289212e-911a-488f-a5d7-df19a02f4b8e |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667811125 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 9.chip_same_csr_outstanding.1667811125 |
| Directory | /workspace/9.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_access_same_device.2503356099 |
| Short name | T797 |
| Test name | |
| Test status | |
| Simulation time | 1279622282 ps |
| CPU time | 48.71 seconds |
| Started | Jul 03 07:23:46 PM PDT 24 |
| Finished | Jul 03 07:24:36 PM PDT 24 |
| Peak memory | 574220 kb |
| Host | smart-22223a62-87c0-4b7a-a6b6-96fd7854a198 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2503356099 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_access_same_device. 2503356099 |
| Directory | /workspace/9.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_access_same_device_slow_rsp.933694596 |
| Short name | T2027 |
| Test name | |
| Test status | |
| Simulation time | 8467832879 ps |
| CPU time | 154.49 seconds |
| Started | Jul 03 07:23:44 PM PDT 24 |
| Finished | Jul 03 07:26:20 PM PDT 24 |
| Peak memory | 574112 kb |
| Host | smart-20818861-b965-4164-96e5-51335d0d57ac |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=933694596 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_access_same_de vice_slow_rsp.933694596 |
| Directory | /workspace/9.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_error_and_unmapped_addr.2009508621 |
| Short name | T2074 |
| Test name | |
| Test status | |
| Simulation time | 169730961 ps |
| CPU time | 11.03 seconds |
| Started | Jul 03 07:23:44 PM PDT 24 |
| Finished | Jul 03 07:23:57 PM PDT 24 |
| Peak memory | 573004 kb |
| Host | smart-65c88016-2a1b-4192-819b-1ff6a2d9474d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2009508621 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_error_and_unmapped_addr .2009508621 |
| Directory | /workspace/9.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_error_random.4079814390 |
| Short name | T2038 |
| Test name | |
| Test status | |
| Simulation time | 437826890 ps |
| CPU time | 40.65 seconds |
| Started | Jul 03 07:23:45 PM PDT 24 |
| Finished | Jul 03 07:24:27 PM PDT 24 |
| Peak memory | 574508 kb |
| Host | smart-447e310d-dc26-4545-af58-0b66eda1d423 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4079814390 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_error_random.4079814390 |
| Directory | /workspace/9.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_random.1660242926 |
| Short name | T2371 |
| Test name | |
| Test status | |
| Simulation time | 2285222979 ps |
| CPU time | 89.77 seconds |
| Started | Jul 03 07:23:42 PM PDT 24 |
| Finished | Jul 03 07:25:13 PM PDT 24 |
| Peak memory | 574324 kb |
| Host | smart-2393cf4c-c8b8-4c31-b134-d5dbd39ed9ac |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1660242926 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_random.1660242926 |
| Directory | /workspace/9.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_random_large_delays.3129695695 |
| Short name | T1582 |
| Test name | |
| Test status | |
| Simulation time | 103292678734 ps |
| CPU time | 1135.72 seconds |
| Started | Jul 03 07:23:37 PM PDT 24 |
| Finished | Jul 03 07:42:34 PM PDT 24 |
| Peak memory | 574180 kb |
| Host | smart-e807594d-d808-4731-9992-ca9f6ca4e14f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3129695695 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_random_large_delays.3129695695 |
| Directory | /workspace/9.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_random_slow_rsp.3128368800 |
| Short name | T2048 |
| Test name | |
| Test status | |
| Simulation time | 73995777077 ps |
| CPU time | 1228.45 seconds |
| Started | Jul 03 07:23:48 PM PDT 24 |
| Finished | Jul 03 07:44:17 PM PDT 24 |
| Peak memory | 574332 kb |
| Host | smart-ab327acf-5ca9-41a7-a994-bb3c03234de7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3128368800 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_random_slow_rsp.3128368800 |
| Directory | /workspace/9.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_random_zero_delays.2777219904 |
| Short name | T2754 |
| Test name | |
| Test status | |
| Simulation time | 350049122 ps |
| CPU time | 28.5 seconds |
| Started | Jul 03 07:23:42 PM PDT 24 |
| Finished | Jul 03 07:24:11 PM PDT 24 |
| Peak memory | 573988 kb |
| Host | smart-6d535586-8785-4983-a51f-99934700a1a8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777219904 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_random_zero_dela ys.2777219904 |
| Directory | /workspace/9.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_same_source.899884827 |
| Short name | T1575 |
| Test name | |
| Test status | |
| Simulation time | 2494496703 ps |
| CPU time | 73.76 seconds |
| Started | Jul 03 07:23:52 PM PDT 24 |
| Finished | Jul 03 07:25:07 PM PDT 24 |
| Peak memory | 574260 kb |
| Host | smart-cd4aa687-2ceb-42eb-850d-6f48298f8632 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=899884827 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_same_source.899884827 |
| Directory | /workspace/9.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_smoke.347577780 |
| Short name | T1706 |
| Test name | |
| Test status | |
| Simulation time | 228787195 ps |
| CPU time | 9.78 seconds |
| Started | Jul 03 07:23:39 PM PDT 24 |
| Finished | Jul 03 07:23:50 PM PDT 24 |
| Peak memory | 573108 kb |
| Host | smart-8f74e2a0-547e-421f-9892-dbffb8629ad3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=347577780 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_smoke.347577780 |
| Directory | /workspace/9.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_smoke_large_delays.2738817162 |
| Short name | T1468 |
| Test name | |
| Test status | |
| Simulation time | 7927145768 ps |
| CPU time | 84.28 seconds |
| Started | Jul 03 07:23:38 PM PDT 24 |
| Finished | Jul 03 07:25:04 PM PDT 24 |
| Peak memory | 573200 kb |
| Host | smart-e4f07ee1-7447-43ff-988f-0f903eac6605 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2738817162 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_large_delays.2738817162 |
| Directory | /workspace/9.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_smoke_slow_rsp.3646003172 |
| Short name | T1686 |
| Test name | |
| Test status | |
| Simulation time | 5966472661 ps |
| CPU time | 97.85 seconds |
| Started | Jul 03 07:23:37 PM PDT 24 |
| Finished | Jul 03 07:25:16 PM PDT 24 |
| Peak memory | 574140 kb |
| Host | smart-d45f8b95-3bd1-4d32-9345-c62e88970c38 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3646003172 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_slow_rsp.3646003172 |
| Directory | /workspace/9.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_smoke_zero_delays.3071563832 |
| Short name | T1356 |
| Test name | |
| Test status | |
| Simulation time | 50898786 ps |
| CPU time | 7 seconds |
| Started | Jul 03 07:23:40 PM PDT 24 |
| Finished | Jul 03 07:23:48 PM PDT 24 |
| Peak memory | 574160 kb |
| Host | smart-73f9cf2b-4ff6-46b0-a33f-61101e3c3093 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3071563832 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_zero_delays .3071563832 |
| Directory | /workspace/9.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_stress_all.2682490666 |
| Short name | T2280 |
| Test name | |
| Test status | |
| Simulation time | 687143805 ps |
| CPU time | 69.02 seconds |
| Started | Jul 03 07:23:45 PM PDT 24 |
| Finished | Jul 03 07:24:55 PM PDT 24 |
| Peak memory | 574452 kb |
| Host | smart-f1beb7df-160e-4eb5-95fd-d29b8deb58f7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682490666 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all.2682490666 |
| Directory | /workspace/9.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_stress_all_with_error.978540811 |
| Short name | T633 |
| Test name | |
| Test status | |
| Simulation time | 1177079827 ps |
| CPU time | 83.79 seconds |
| Started | Jul 03 07:23:46 PM PDT 24 |
| Finished | Jul 03 07:25:11 PM PDT 24 |
| Peak memory | 574576 kb |
| Host | smart-a8b0e53a-08f6-4d61-9dd7-af4a369164fa |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=978540811 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_error.978540811 |
| Directory | /workspace/9.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_stress_all_with_rand_reset.726059806 |
| Short name | T1457 |
| Test name | |
| Test status | |
| Simulation time | 4378175725 ps |
| CPU time | 282.7 seconds |
| Started | Jul 03 07:23:47 PM PDT 24 |
| Finished | Jul 03 07:28:30 PM PDT 24 |
| Peak memory | 574644 kb |
| Host | smart-61e68db1-c695-460a-8537-90d36db8f4b5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=726059806 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_w ith_rand_reset.726059806 |
| Directory | /workspace/9.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_unmapped_addr.2655609501 |
| Short name | T2408 |
| Test name | |
| Test status | |
| Simulation time | 900005383 ps |
| CPU time | 36.72 seconds |
| Started | Jul 03 07:23:44 PM PDT 24 |
| Finished | Jul 03 07:24:23 PM PDT 24 |
| Peak memory | 574196 kb |
| Host | smart-97cb3f67-47dc-437a-94ce-d3c7b3863d92 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2655609501 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_unmapped_addr.2655609501 |
| Directory | /workspace/9.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_access_same_device.3817660590 |
| Short name | T2606 |
| Test name | |
| Test status | |
| Simulation time | 662173335 ps |
| CPU time | 30.58 seconds |
| Started | Jul 03 07:38:27 PM PDT 24 |
| Finished | Jul 03 07:38:58 PM PDT 24 |
| Peak memory | 574028 kb |
| Host | smart-9929643f-9fe4-459e-be83-e731c4f440df |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3817660590 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_access_same_device .3817660590 |
| Directory | /workspace/90.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_access_same_device_slow_rsp.3983795930 |
| Short name | T2539 |
| Test name | |
| Test status | |
| Simulation time | 113751152568 ps |
| CPU time | 2251.71 seconds |
| Started | Jul 03 07:38:33 PM PDT 24 |
| Finished | Jul 03 08:16:06 PM PDT 24 |
| Peak memory | 574160 kb |
| Host | smart-b530b7f5-bc2f-4c3f-a97a-639215593614 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3983795930 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_access_same_ device_slow_rsp.3983795930 |
| Directory | /workspace/90.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_error_and_unmapped_addr.1375564804 |
| Short name | T2411 |
| Test name | |
| Test status | |
| Simulation time | 171763204 ps |
| CPU time | 9.32 seconds |
| Started | Jul 03 07:38:25 PM PDT 24 |
| Finished | Jul 03 07:38:35 PM PDT 24 |
| Peak memory | 573404 kb |
| Host | smart-167e5801-57e7-4bd1-b5ff-c39e8bd78cbf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1375564804 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_error_and_unmapped_add r.1375564804 |
| Directory | /workspace/90.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_error_random.4164618231 |
| Short name | T2255 |
| Test name | |
| Test status | |
| Simulation time | 305600616 ps |
| CPU time | 12.94 seconds |
| Started | Jul 03 07:38:29 PM PDT 24 |
| Finished | Jul 03 07:38:42 PM PDT 24 |
| Peak memory | 574460 kb |
| Host | smart-1623c3e0-b367-4371-a056-dfdbc6068ec8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4164618231 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_error_random.4164618231 |
| Directory | /workspace/90.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_random.613851536 |
| Short name | T1495 |
| Test name | |
| Test status | |
| Simulation time | 2551748762 ps |
| CPU time | 91.83 seconds |
| Started | Jul 03 07:38:20 PM PDT 24 |
| Finished | Jul 03 07:39:52 PM PDT 24 |
| Peak memory | 574052 kb |
| Host | smart-aaf201cd-8cbe-40f8-bd08-82af8c267d86 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=613851536 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_random.613851536 |
| Directory | /workspace/90.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_random_large_delays.2888327921 |
| Short name | T1681 |
| Test name | |
| Test status | |
| Simulation time | 73948061231 ps |
| CPU time | 749.81 seconds |
| Started | Jul 03 07:38:23 PM PDT 24 |
| Finished | Jul 03 07:50:53 PM PDT 24 |
| Peak memory | 574296 kb |
| Host | smart-549014c0-f1b1-4e69-bed8-19b7705082d0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2888327921 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_random_large_delays.2888327921 |
| Directory | /workspace/90.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_random_slow_rsp.2979776003 |
| Short name | T1946 |
| Test name | |
| Test status | |
| Simulation time | 11329669328 ps |
| CPU time | 198.76 seconds |
| Started | Jul 03 07:38:25 PM PDT 24 |
| Finished | Jul 03 07:41:44 PM PDT 24 |
| Peak memory | 574292 kb |
| Host | smart-680cf43e-902c-4330-8074-ef578c96c74d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2979776003 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_random_slow_rsp.2979776003 |
| Directory | /workspace/90.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_random_zero_delays.2208736687 |
| Short name | T460 |
| Test name | |
| Test status | |
| Simulation time | 88862107 ps |
| CPU time | 9.43 seconds |
| Started | Jul 03 07:38:18 PM PDT 24 |
| Finished | Jul 03 07:38:28 PM PDT 24 |
| Peak memory | 574208 kb |
| Host | smart-fb53da18-2000-4795-a4c0-6778b4d958d2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2208736687 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_random_zero_del ays.2208736687 |
| Directory | /workspace/90.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_same_source.812671162 |
| Short name | T2604 |
| Test name | |
| Test status | |
| Simulation time | 440082259 ps |
| CPU time | 34.76 seconds |
| Started | Jul 03 07:38:27 PM PDT 24 |
| Finished | Jul 03 07:39:02 PM PDT 24 |
| Peak memory | 573992 kb |
| Host | smart-9ca86ea3-5cd8-465f-b800-344683c6206f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=812671162 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_same_source.812671162 |
| Directory | /workspace/90.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_smoke.2418141475 |
| Short name | T1800 |
| Test name | |
| Test status | |
| Simulation time | 216926065 ps |
| CPU time | 8.53 seconds |
| Started | Jul 03 07:38:22 PM PDT 24 |
| Finished | Jul 03 07:38:31 PM PDT 24 |
| Peak memory | 574208 kb |
| Host | smart-bfb64deb-2ba5-4a10-bab8-4efb228149c2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2418141475 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_smoke.2418141475 |
| Directory | /workspace/90.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_smoke_large_delays.1451069702 |
| Short name | T1980 |
| Test name | |
| Test status | |
| Simulation time | 5994359154 ps |
| CPU time | 61.54 seconds |
| Started | Jul 03 07:38:20 PM PDT 24 |
| Finished | Jul 03 07:39:22 PM PDT 24 |
| Peak memory | 574140 kb |
| Host | smart-02881205-2a17-4d62-8b9c-72ecf7d65828 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1451069702 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_smoke_large_delays.1451069702 |
| Directory | /workspace/90.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_smoke_slow_rsp.581950504 |
| Short name | T2219 |
| Test name | |
| Test status | |
| Simulation time | 4900956806 ps |
| CPU time | 76.65 seconds |
| Started | Jul 03 07:38:20 PM PDT 24 |
| Finished | Jul 03 07:39:37 PM PDT 24 |
| Peak memory | 573160 kb |
| Host | smart-9aa02015-53b3-4183-8e65-0ccd1cbdf8ba |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=581950504 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_smoke_slow_rsp.581950504 |
| Directory | /workspace/90.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_smoke_zero_delays.641372812 |
| Short name | T1369 |
| Test name | |
| Test status | |
| Simulation time | 47285310 ps |
| CPU time | 6.61 seconds |
| Started | Jul 03 07:38:22 PM PDT 24 |
| Finished | Jul 03 07:38:30 PM PDT 24 |
| Peak memory | 574156 kb |
| Host | smart-043df907-9ac8-41f8-bb39-fc134ad3ad38 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=641372812 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_smoke_zero_delays .641372812 |
| Directory | /workspace/90.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_stress_all.2975934168 |
| Short name | T2398 |
| Test name | |
| Test status | |
| Simulation time | 852125238 ps |
| CPU time | 73.3 seconds |
| Started | Jul 03 07:38:24 PM PDT 24 |
| Finished | Jul 03 07:39:37 PM PDT 24 |
| Peak memory | 574200 kb |
| Host | smart-852becb2-df7a-4750-a129-fc5d3d2d57a3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2975934168 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_stress_all.2975934168 |
| Directory | /workspace/90.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_stress_all_with_error.1493045350 |
| Short name | T1415 |
| Test name | |
| Test status | |
| Simulation time | 2346738180 ps |
| CPU time | 88.31 seconds |
| Started | Jul 03 07:38:24 PM PDT 24 |
| Finished | Jul 03 07:39:53 PM PDT 24 |
| Peak memory | 574588 kb |
| Host | smart-3dae7e7e-0ba8-400a-a24e-6537fffdb8a4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1493045350 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_stress_all_with_error.1493045350 |
| Directory | /workspace/90.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_stress_all_with_rand_reset.727347634 |
| Short name | T806 |
| Test name | |
| Test status | |
| Simulation time | 363866155 ps |
| CPU time | 131.06 seconds |
| Started | Jul 03 07:38:24 PM PDT 24 |
| Finished | Jul 03 07:40:36 PM PDT 24 |
| Peak memory | 574668 kb |
| Host | smart-22c1bcaf-0ffc-42fa-9be6-2665a45683a9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=727347634 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_stress_all_ with_rand_reset.727347634 |
| Directory | /workspace/90.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_stress_all_with_reset_error.3343648188 |
| Short name | T1955 |
| Test name | |
| Test status | |
| Simulation time | 102831495 ps |
| CPU time | 38.05 seconds |
| Started | Jul 03 07:38:33 PM PDT 24 |
| Finished | Jul 03 07:39:12 PM PDT 24 |
| Peak memory | 574620 kb |
| Host | smart-e67a438b-e9ab-4493-b111-fc9051ec065e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3343648188 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_stress_al l_with_reset_error.3343648188 |
| Directory | /workspace/90.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_unmapped_addr.3872723142 |
| Short name | T1347 |
| Test name | |
| Test status | |
| Simulation time | 127745989 ps |
| CPU time | 17.53 seconds |
| Started | Jul 03 07:38:33 PM PDT 24 |
| Finished | Jul 03 07:38:51 PM PDT 24 |
| Peak memory | 574168 kb |
| Host | smart-7e721b5d-0502-488d-897e-505a4251f6e3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3872723142 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_unmapped_addr.3872723142 |
| Directory | /workspace/90.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_access_same_device.352258706 |
| Short name | T1481 |
| Test name | |
| Test status | |
| Simulation time | 518431173 ps |
| CPU time | 45.33 seconds |
| Started | Jul 03 07:38:34 PM PDT 24 |
| Finished | Jul 03 07:39:20 PM PDT 24 |
| Peak memory | 574212 kb |
| Host | smart-72582131-c05e-437b-bcb4-e79557654d08 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352258706 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_access_same_device. 352258706 |
| Directory | /workspace/91.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_access_same_device_slow_rsp.814062731 |
| Short name | T1960 |
| Test name | |
| Test status | |
| Simulation time | 120219986236 ps |
| CPU time | 2168.04 seconds |
| Started | Jul 03 07:38:33 PM PDT 24 |
| Finished | Jul 03 08:14:42 PM PDT 24 |
| Peak memory | 574708 kb |
| Host | smart-51e9e4ae-34be-42f2-9a6e-fd069d84146b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=814062731 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_access_same_d evice_slow_rsp.814062731 |
| Directory | /workspace/91.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_error_and_unmapped_addr.713412941 |
| Short name | T2514 |
| Test name | |
| Test status | |
| Simulation time | 1018091700 ps |
| CPU time | 39.33 seconds |
| Started | Jul 03 07:38:35 PM PDT 24 |
| Finished | Jul 03 07:39:15 PM PDT 24 |
| Peak memory | 574492 kb |
| Host | smart-54cfd622-cf94-4da2-8c02-c0c194ed0907 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=713412941 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_error_and_unmapped_addr .713412941 |
| Directory | /workspace/91.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_error_random.3003530744 |
| Short name | T1355 |
| Test name | |
| Test status | |
| Simulation time | 2246898538 ps |
| CPU time | 78.54 seconds |
| Started | Jul 03 07:38:32 PM PDT 24 |
| Finished | Jul 03 07:39:51 PM PDT 24 |
| Peak memory | 574468 kb |
| Host | smart-5fc4c3ae-6fb6-4f44-a810-18bbb788f04d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3003530744 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_error_random.3003530744 |
| Directory | /workspace/91.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_random.1543495730 |
| Short name | T2559 |
| Test name | |
| Test status | |
| Simulation time | 1765674673 ps |
| CPU time | 68.39 seconds |
| Started | Jul 03 07:38:29 PM PDT 24 |
| Finished | Jul 03 07:39:38 PM PDT 24 |
| Peak memory | 574192 kb |
| Host | smart-8855c164-0f98-47fb-a216-198539859d9d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1543495730 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_random.1543495730 |
| Directory | /workspace/91.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_random_large_delays.1272116945 |
| Short name | T2553 |
| Test name | |
| Test status | |
| Simulation time | 36575143930 ps |
| CPU time | 451.04 seconds |
| Started | Jul 03 07:38:30 PM PDT 24 |
| Finished | Jul 03 07:46:02 PM PDT 24 |
| Peak memory | 574276 kb |
| Host | smart-c16741e3-523d-421b-bd59-e818bfd96b5f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1272116945 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_random_large_delays.1272116945 |
| Directory | /workspace/91.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_random_slow_rsp.3769717371 |
| Short name | T2046 |
| Test name | |
| Test status | |
| Simulation time | 43179102319 ps |
| CPU time | 744.9 seconds |
| Started | Jul 03 07:38:33 PM PDT 24 |
| Finished | Jul 03 07:50:58 PM PDT 24 |
| Peak memory | 574336 kb |
| Host | smart-1e0b2953-db72-4302-ba4a-029bea4a5757 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3769717371 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_random_slow_rsp.3769717371 |
| Directory | /workspace/91.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_random_zero_delays.4001477078 |
| Short name | T2150 |
| Test name | |
| Test status | |
| Simulation time | 269971459 ps |
| CPU time | 25.46 seconds |
| Started | Jul 03 07:38:32 PM PDT 24 |
| Finished | Jul 03 07:38:58 PM PDT 24 |
| Peak memory | 574236 kb |
| Host | smart-54893320-e80a-4634-a7ac-fe9638674c18 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4001477078 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_random_zero_del ays.4001477078 |
| Directory | /workspace/91.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_same_source.557855009 |
| Short name | T2045 |
| Test name | |
| Test status | |
| Simulation time | 1929962287 ps |
| CPU time | 60.28 seconds |
| Started | Jul 03 07:38:31 PM PDT 24 |
| Finished | Jul 03 07:39:32 PM PDT 24 |
| Peak memory | 574200 kb |
| Host | smart-4a0b60d7-67c9-4495-bfbd-2cc46e4c9926 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=557855009 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_same_source.557855009 |
| Directory | /workspace/91.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_smoke.2272768855 |
| Short name | T1895 |
| Test name | |
| Test status | |
| Simulation time | 54966582 ps |
| CPU time | 6.38 seconds |
| Started | Jul 03 07:38:25 PM PDT 24 |
| Finished | Jul 03 07:38:32 PM PDT 24 |
| Peak memory | 574024 kb |
| Host | smart-e370eb03-ecd7-4d5a-ba25-f72e41736fd7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2272768855 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_smoke.2272768855 |
| Directory | /workspace/91.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_smoke_large_delays.2144140580 |
| Short name | T1463 |
| Test name | |
| Test status | |
| Simulation time | 9103077754 ps |
| CPU time | 92.02 seconds |
| Started | Jul 03 07:38:26 PM PDT 24 |
| Finished | Jul 03 07:39:59 PM PDT 24 |
| Peak memory | 573052 kb |
| Host | smart-115639d1-ff5a-4eab-a4f5-d6ac3264cb72 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144140580 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_smoke_large_delays.2144140580 |
| Directory | /workspace/91.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_smoke_slow_rsp.1366059322 |
| Short name | T1381 |
| Test name | |
| Test status | |
| Simulation time | 4993167976 ps |
| CPU time | 85.32 seconds |
| Started | Jul 03 07:38:28 PM PDT 24 |
| Finished | Jul 03 07:39:54 PM PDT 24 |
| Peak memory | 574252 kb |
| Host | smart-fb52e958-09c5-4481-8a87-ee5171d19568 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1366059322 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_smoke_slow_rsp.1366059322 |
| Directory | /workspace/91.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_smoke_zero_delays.459005374 |
| Short name | T2409 |
| Test name | |
| Test status | |
| Simulation time | 47629633 ps |
| CPU time | 6.33 seconds |
| Started | Jul 03 07:38:25 PM PDT 24 |
| Finished | Jul 03 07:38:32 PM PDT 24 |
| Peak memory | 572892 kb |
| Host | smart-93a16597-eead-492a-b921-5ee34ee3586d |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=459005374 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_smoke_zero_delays .459005374 |
| Directory | /workspace/91.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_stress_all.367976245 |
| Short name | T2009 |
| Test name | |
| Test status | |
| Simulation time | 10252912919 ps |
| CPU time | 414.4 seconds |
| Started | Jul 03 07:38:35 PM PDT 24 |
| Finished | Jul 03 07:45:30 PM PDT 24 |
| Peak memory | 574688 kb |
| Host | smart-53be1795-5489-44c4-a2a7-f209271cd8f5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=367976245 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_stress_all.367976245 |
| Directory | /workspace/91.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_stress_all_with_error.584506301 |
| Short name | T2651 |
| Test name | |
| Test status | |
| Simulation time | 20905630330 ps |
| CPU time | 801.34 seconds |
| Started | Jul 03 07:38:35 PM PDT 24 |
| Finished | Jul 03 07:51:57 PM PDT 24 |
| Peak memory | 574732 kb |
| Host | smart-3a604a4a-83a8-48eb-95cd-00c7e8919bef |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=584506301 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_stress_all_with_error.584506301 |
| Directory | /workspace/91.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_stress_all_with_rand_reset.3118570552 |
| Short name | T2082 |
| Test name | |
| Test status | |
| Simulation time | 452533064 ps |
| CPU time | 202.53 seconds |
| Started | Jul 03 07:38:34 PM PDT 24 |
| Finished | Jul 03 07:41:57 PM PDT 24 |
| Peak memory | 574664 kb |
| Host | smart-2601e372-1b54-4293-afc1-930d716827ab |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3118570552 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_stress_all _with_rand_reset.3118570552 |
| Directory | /workspace/91.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_stress_all_with_reset_error.2600057468 |
| Short name | T2796 |
| Test name | |
| Test status | |
| Simulation time | 23097809 ps |
| CPU time | 9.82 seconds |
| Started | Jul 03 07:38:37 PM PDT 24 |
| Finished | Jul 03 07:38:48 PM PDT 24 |
| Peak memory | 573444 kb |
| Host | smart-057c7736-8dde-4b56-8798-075bcddd1be1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2600057468 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_stress_al l_with_reset_error.2600057468 |
| Directory | /workspace/91.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_unmapped_addr.3131264999 |
| Short name | T2677 |
| Test name | |
| Test status | |
| Simulation time | 294293170 ps |
| CPU time | 38.57 seconds |
| Started | Jul 03 07:38:35 PM PDT 24 |
| Finished | Jul 03 07:39:14 PM PDT 24 |
| Peak memory | 574284 kb |
| Host | smart-603545e2-e3d4-4c63-a227-c2e337f9de0f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131264999 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_unmapped_addr.3131264999 |
| Directory | /workspace/91.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_access_same_device.3775273890 |
| Short name | T1689 |
| Test name | |
| Test status | |
| Simulation time | 311751195 ps |
| CPU time | 25.9 seconds |
| Started | Jul 03 07:38:47 PM PDT 24 |
| Finished | Jul 03 07:39:14 PM PDT 24 |
| Peak memory | 574240 kb |
| Host | smart-a4287dec-7c04-405e-8ed1-a6ee0001c698 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3775273890 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_access_same_device .3775273890 |
| Directory | /workspace/92.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_access_same_device_slow_rsp.751878988 |
| Short name | T2768 |
| Test name | |
| Test status | |
| Simulation time | 102456584660 ps |
| CPU time | 1937.22 seconds |
| Started | Jul 03 07:38:46 PM PDT 24 |
| Finished | Jul 03 08:11:04 PM PDT 24 |
| Peak memory | 574692 kb |
| Host | smart-bc1fc606-2603-43a8-9127-5585d0f10711 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=751878988 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_access_same_d evice_slow_rsp.751878988 |
| Directory | /workspace/92.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_error_and_unmapped_addr.3107428485 |
| Short name | T2631 |
| Test name | |
| Test status | |
| Simulation time | 139927669 ps |
| CPU time | 17.92 seconds |
| Started | Jul 03 07:38:51 PM PDT 24 |
| Finished | Jul 03 07:39:10 PM PDT 24 |
| Peak memory | 574464 kb |
| Host | smart-17f471e4-3595-402e-b0e7-c015cbc1f449 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3107428485 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_error_and_unmapped_add r.3107428485 |
| Directory | /workspace/92.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_error_random.1627249679 |
| Short name | T1392 |
| Test name | |
| Test status | |
| Simulation time | 534459025 ps |
| CPU time | 45.77 seconds |
| Started | Jul 03 07:38:56 PM PDT 24 |
| Finished | Jul 03 07:39:44 PM PDT 24 |
| Peak memory | 574476 kb |
| Host | smart-c2ad5802-3bc0-42b3-9f9f-d9a1bda39739 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1627249679 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_error_random.1627249679 |
| Directory | /workspace/92.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_random.1397503236 |
| Short name | T2609 |
| Test name | |
| Test status | |
| Simulation time | 472117023 ps |
| CPU time | 43.42 seconds |
| Started | Jul 03 07:38:46 PM PDT 24 |
| Finished | Jul 03 07:39:30 PM PDT 24 |
| Peak memory | 574004 kb |
| Host | smart-31501b8b-f0ab-448c-ba58-295900a13640 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1397503236 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_random.1397503236 |
| Directory | /workspace/92.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_random_large_delays.997657337 |
| Short name | T2800 |
| Test name | |
| Test status | |
| Simulation time | 47176646318 ps |
| CPU time | 497.15 seconds |
| Started | Jul 03 07:38:45 PM PDT 24 |
| Finished | Jul 03 07:47:03 PM PDT 24 |
| Peak memory | 574140 kb |
| Host | smart-21d6f0fd-05c9-4a53-86e2-7ce59c97445a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=997657337 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_random_large_delays.997657337 |
| Directory | /workspace/92.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_random_slow_rsp.3465861718 |
| Short name | T596 |
| Test name | |
| Test status | |
| Simulation time | 45891807031 ps |
| CPU time | 862.58 seconds |
| Started | Jul 03 07:38:56 PM PDT 24 |
| Finished | Jul 03 07:53:19 PM PDT 24 |
| Peak memory | 574208 kb |
| Host | smart-86c971e9-f02b-400a-89ad-cadcbe81d33d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465861718 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_random_slow_rsp.3465861718 |
| Directory | /workspace/92.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_random_zero_delays.584048379 |
| Short name | T535 |
| Test name | |
| Test status | |
| Simulation time | 395368380 ps |
| CPU time | 34.8 seconds |
| Started | Jul 03 07:38:46 PM PDT 24 |
| Finished | Jul 03 07:39:21 PM PDT 24 |
| Peak memory | 574220 kb |
| Host | smart-a9a64832-4b52-4608-ab25-23d04ab128fc |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=584048379 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_random_zero_dela ys.584048379 |
| Directory | /workspace/92.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_same_source.3052398386 |
| Short name | T1835 |
| Test name | |
| Test status | |
| Simulation time | 253293415 ps |
| CPU time | 20.99 seconds |
| Started | Jul 03 07:38:56 PM PDT 24 |
| Finished | Jul 03 07:39:18 PM PDT 24 |
| Peak memory | 574164 kb |
| Host | smart-e992b407-b2c8-455b-b368-6f9499e46107 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3052398386 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_same_source.3052398386 |
| Directory | /workspace/92.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_smoke.461466367 |
| Short name | T1348 |
| Test name | |
| Test status | |
| Simulation time | 172876880 ps |
| CPU time | 8.1 seconds |
| Started | Jul 03 07:38:40 PM PDT 24 |
| Finished | Jul 03 07:38:48 PM PDT 24 |
| Peak memory | 572948 kb |
| Host | smart-a4e7e1f5-8b0d-4425-a657-5fead0688fd4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=461466367 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_smoke.461466367 |
| Directory | /workspace/92.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_smoke_large_delays.3297927779 |
| Short name | T2266 |
| Test name | |
| Test status | |
| Simulation time | 6228144990 ps |
| CPU time | 62.37 seconds |
| Started | Jul 03 07:38:38 PM PDT 24 |
| Finished | Jul 03 07:39:41 PM PDT 24 |
| Peak memory | 573180 kb |
| Host | smart-b1f5fd08-34ee-4a72-a7b3-20ade10f07e0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3297927779 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_smoke_large_delays.3297927779 |
| Directory | /workspace/92.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_smoke_slow_rsp.951639634 |
| Short name | T2663 |
| Test name | |
| Test status | |
| Simulation time | 5508003091 ps |
| CPU time | 93.12 seconds |
| Started | Jul 03 07:38:56 PM PDT 24 |
| Finished | Jul 03 07:40:30 PM PDT 24 |
| Peak memory | 574000 kb |
| Host | smart-203e234f-062c-40cb-9c06-3b45038c9e8e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=951639634 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_smoke_slow_rsp.951639634 |
| Directory | /workspace/92.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_smoke_zero_delays.1182319578 |
| Short name | T1300 |
| Test name | |
| Test status | |
| Simulation time | 53690860 ps |
| CPU time | 6.44 seconds |
| Started | Jul 03 07:38:48 PM PDT 24 |
| Finished | Jul 03 07:38:55 PM PDT 24 |
| Peak memory | 574168 kb |
| Host | smart-a7238ae5-f21c-4509-a547-2803f24823bf |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1182319578 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_smoke_zero_delay s.1182319578 |
| Directory | /workspace/92.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_stress_all.872189812 |
| Short name | T439 |
| Test name | |
| Test status | |
| Simulation time | 4763760029 ps |
| CPU time | 171.53 seconds |
| Started | Jul 03 07:38:50 PM PDT 24 |
| Finished | Jul 03 07:41:42 PM PDT 24 |
| Peak memory | 574392 kb |
| Host | smart-a292f745-154f-4fa9-baed-9e0d48391597 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=872189812 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_stress_all.872189812 |
| Directory | /workspace/92.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_stress_all_with_error.967394448 |
| Short name | T426 |
| Test name | |
| Test status | |
| Simulation time | 2846662191 ps |
| CPU time | 245.49 seconds |
| Started | Jul 03 07:38:50 PM PDT 24 |
| Finished | Jul 03 07:42:57 PM PDT 24 |
| Peak memory | 574752 kb |
| Host | smart-952a5e7e-810a-469f-8df0-b6aa88b6fe24 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=967394448 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_stress_all_with_error.967394448 |
| Directory | /workspace/92.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_stress_all_with_rand_reset.4069010432 |
| Short name | T2106 |
| Test name | |
| Test status | |
| Simulation time | 111385146 ps |
| CPU time | 61.71 seconds |
| Started | Jul 03 07:38:51 PM PDT 24 |
| Finished | Jul 03 07:39:54 PM PDT 24 |
| Peak memory | 574612 kb |
| Host | smart-eb1ea3aa-c176-4c47-a5b4-792fee4c7808 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4069010432 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_stress_all _with_rand_reset.4069010432 |
| Directory | /workspace/92.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_stress_all_with_reset_error.1133611657 |
| Short name | T2347 |
| Test name | |
| Test status | |
| Simulation time | 9200761 ps |
| CPU time | 13.54 seconds |
| Started | Jul 03 07:38:51 PM PDT 24 |
| Finished | Jul 03 07:39:05 PM PDT 24 |
| Peak memory | 573012 kb |
| Host | smart-b4365703-2bce-490e-8b29-3baf6a7360d7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1133611657 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_stress_al l_with_reset_error.1133611657 |
| Directory | /workspace/92.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_unmapped_addr.139845122 |
| Short name | T547 |
| Test name | |
| Test status | |
| Simulation time | 244388316 ps |
| CPU time | 30.64 seconds |
| Started | Jul 03 07:38:51 PM PDT 24 |
| Finished | Jul 03 07:39:23 PM PDT 24 |
| Peak memory | 574036 kb |
| Host | smart-b662c854-1a6c-4fcc-ab2a-7346406c74ca |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=139845122 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_unmapped_addr.139845122 |
| Directory | /workspace/92.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_access_same_device.2845065986 |
| Short name | T2279 |
| Test name | |
| Test status | |
| Simulation time | 255179487 ps |
| CPU time | 19.03 seconds |
| Started | Jul 03 07:38:56 PM PDT 24 |
| Finished | Jul 03 07:39:17 PM PDT 24 |
| Peak memory | 574220 kb |
| Host | smart-dd26591a-21e1-4b42-bc0f-378b91fdac52 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2845065986 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_access_same_device .2845065986 |
| Directory | /workspace/93.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_access_same_device_slow_rsp.3130854756 |
| Short name | T2612 |
| Test name | |
| Test status | |
| Simulation time | 65825524548 ps |
| CPU time | 1161.38 seconds |
| Started | Jul 03 07:38:56 PM PDT 24 |
| Finished | Jul 03 07:58:18 PM PDT 24 |
| Peak memory | 574324 kb |
| Host | smart-62c67fae-040e-42ed-b339-1ff6ccd3cbbc |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3130854756 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_access_same_ device_slow_rsp.3130854756 |
| Directory | /workspace/93.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_error_and_unmapped_addr.980978271 |
| Short name | T1354 |
| Test name | |
| Test status | |
| Simulation time | 777834699 ps |
| CPU time | 28.21 seconds |
| Started | Jul 03 07:38:56 PM PDT 24 |
| Finished | Jul 03 07:39:25 PM PDT 24 |
| Peak memory | 574428 kb |
| Host | smart-676c3fb0-96dc-449a-8da9-a3fe51a768a2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=980978271 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_error_and_unmapped_addr .980978271 |
| Directory | /workspace/93.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_error_random.4161422069 |
| Short name | T2211 |
| Test name | |
| Test status | |
| Simulation time | 156177497 ps |
| CPU time | 14.57 seconds |
| Started | Jul 03 07:38:56 PM PDT 24 |
| Finished | Jul 03 07:39:12 PM PDT 24 |
| Peak memory | 574404 kb |
| Host | smart-3c606944-c77b-4614-8e39-0c11799746e0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161422069 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_error_random.4161422069 |
| Directory | /workspace/93.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_random.2580613249 |
| Short name | T2769 |
| Test name | |
| Test status | |
| Simulation time | 1514057458 ps |
| CPU time | 50.75 seconds |
| Started | Jul 03 07:38:56 PM PDT 24 |
| Finished | Jul 03 07:39:48 PM PDT 24 |
| Peak memory | 574108 kb |
| Host | smart-283ad5a8-1689-4d8a-b13c-5200a560902e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2580613249 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_random.2580613249 |
| Directory | /workspace/93.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_random_large_delays.4224478303 |
| Short name | T2252 |
| Test name | |
| Test status | |
| Simulation time | 106888161634 ps |
| CPU time | 1140.83 seconds |
| Started | Jul 03 07:38:56 PM PDT 24 |
| Finished | Jul 03 07:57:58 PM PDT 24 |
| Peak memory | 574264 kb |
| Host | smart-67689440-e92d-41ed-acdb-e2725e85fcf7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4224478303 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_random_large_delays.4224478303 |
| Directory | /workspace/93.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_random_slow_rsp.1870040778 |
| Short name | T1916 |
| Test name | |
| Test status | |
| Simulation time | 61808580361 ps |
| CPU time | 1094.01 seconds |
| Started | Jul 03 07:38:56 PM PDT 24 |
| Finished | Jul 03 07:57:11 PM PDT 24 |
| Peak memory | 574248 kb |
| Host | smart-5c1af9e0-94a6-4108-831b-0ecbc979e439 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1870040778 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_random_slow_rsp.1870040778 |
| Directory | /workspace/93.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_random_zero_delays.3180959763 |
| Short name | T1421 |
| Test name | |
| Test status | |
| Simulation time | 122981904 ps |
| CPU time | 12.36 seconds |
| Started | Jul 03 07:38:57 PM PDT 24 |
| Finished | Jul 03 07:39:10 PM PDT 24 |
| Peak memory | 573976 kb |
| Host | smart-c459c78d-3e09-4e40-aff7-308e4cae3adf |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3180959763 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_random_zero_del ays.3180959763 |
| Directory | /workspace/93.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_same_source.344432018 |
| Short name | T1759 |
| Test name | |
| Test status | |
| Simulation time | 2346440588 ps |
| CPU time | 68.59 seconds |
| Started | Jul 03 07:38:56 PM PDT 24 |
| Finished | Jul 03 07:40:06 PM PDT 24 |
| Peak memory | 574132 kb |
| Host | smart-1e444024-6845-4ad2-b539-1d728e757b6c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344432018 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_same_source.344432018 |
| Directory | /workspace/93.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_smoke.967767155 |
| Short name | T1792 |
| Test name | |
| Test status | |
| Simulation time | 41688376 ps |
| CPU time | 6.17 seconds |
| Started | Jul 03 07:38:50 PM PDT 24 |
| Finished | Jul 03 07:38:57 PM PDT 24 |
| Peak memory | 573128 kb |
| Host | smart-d99b993c-c9a1-46da-928f-d31144e23fca |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=967767155 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_smoke.967767155 |
| Directory | /workspace/93.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_smoke_large_delays.850010288 |
| Short name | T1794 |
| Test name | |
| Test status | |
| Simulation time | 9100621138 ps |
| CPU time | 96.45 seconds |
| Started | Jul 03 07:38:49 PM PDT 24 |
| Finished | Jul 03 07:40:27 PM PDT 24 |
| Peak memory | 574252 kb |
| Host | smart-1282f95a-224b-43df-8cfe-59730795f298 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850010288 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_smoke_large_delays.850010288 |
| Directory | /workspace/93.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_smoke_slow_rsp.1885687779 |
| Short name | T1763 |
| Test name | |
| Test status | |
| Simulation time | 6216075945 ps |
| CPU time | 108.69 seconds |
| Started | Jul 03 07:38:58 PM PDT 24 |
| Finished | Jul 03 07:40:47 PM PDT 24 |
| Peak memory | 573216 kb |
| Host | smart-4f51484a-1648-40ae-9b3d-25513a8765b5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1885687779 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_smoke_slow_rsp.1885687779 |
| Directory | /workspace/93.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_smoke_zero_delays.4012688078 |
| Short name | T2161 |
| Test name | |
| Test status | |
| Simulation time | 40403384 ps |
| CPU time | 6.22 seconds |
| Started | Jul 03 07:38:51 PM PDT 24 |
| Finished | Jul 03 07:38:58 PM PDT 24 |
| Peak memory | 573124 kb |
| Host | smart-241b1670-57d6-4c4e-a5fd-d4975c203cac |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4012688078 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_smoke_zero_delay s.4012688078 |
| Directory | /workspace/93.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_stress_all.115148575 |
| Short name | T537 |
| Test name | |
| Test status | |
| Simulation time | 736642136 ps |
| CPU time | 64.12 seconds |
| Started | Jul 03 07:38:56 PM PDT 24 |
| Finished | Jul 03 07:40:02 PM PDT 24 |
| Peak memory | 574228 kb |
| Host | smart-f7f76b68-205e-495b-9000-b7b00b35f74d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115148575 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_stress_all.115148575 |
| Directory | /workspace/93.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_stress_all_with_error.3546258986 |
| Short name | T2709 |
| Test name | |
| Test status | |
| Simulation time | 16006080129 ps |
| CPU time | 657.3 seconds |
| Started | Jul 03 07:39:01 PM PDT 24 |
| Finished | Jul 03 07:49:59 PM PDT 24 |
| Peak memory | 574740 kb |
| Host | smart-13c34ed4-39ef-4219-9cb2-918c9f24bbb8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546258986 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_stress_all_with_error.3546258986 |
| Directory | /workspace/93.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_stress_all_with_rand_reset.443394126 |
| Short name | T2345 |
| Test name | |
| Test status | |
| Simulation time | 171757454 ps |
| CPU time | 67.3 seconds |
| Started | Jul 03 07:39:01 PM PDT 24 |
| Finished | Jul 03 07:40:09 PM PDT 24 |
| Peak memory | 574648 kb |
| Host | smart-3bb6ca4c-0467-4d84-99dc-6b6a9a3e8988 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=443394126 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_stress_all_ with_rand_reset.443394126 |
| Directory | /workspace/93.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_stress_all_with_reset_error.722783962 |
| Short name | T1380 |
| Test name | |
| Test status | |
| Simulation time | 1117004654 ps |
| CPU time | 209.62 seconds |
| Started | Jul 03 07:39:03 PM PDT 24 |
| Finished | Jul 03 07:42:33 PM PDT 24 |
| Peak memory | 574676 kb |
| Host | smart-42b10977-9e8f-485c-8259-e6e49f09255f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=722783962 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_stress_all _with_reset_error.722783962 |
| Directory | /workspace/93.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_unmapped_addr.2448823841 |
| Short name | T1953 |
| Test name | |
| Test status | |
| Simulation time | 283009566 ps |
| CPU time | 38.32 seconds |
| Started | Jul 03 07:38:55 PM PDT 24 |
| Finished | Jul 03 07:39:33 PM PDT 24 |
| Peak memory | 574324 kb |
| Host | smart-6355e00e-e86d-402a-a705-c83e72ce2bd5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2448823841 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_unmapped_addr.2448823841 |
| Directory | /workspace/93.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_access_same_device.1469921221 |
| Short name | T1387 |
| Test name | |
| Test status | |
| Simulation time | 17042965 ps |
| CPU time | 6.63 seconds |
| Started | Jul 03 07:39:04 PM PDT 24 |
| Finished | Jul 03 07:39:11 PM PDT 24 |
| Peak memory | 574108 kb |
| Host | smart-ae556536-766b-4411-942c-880b0a45be14 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1469921221 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_access_same_device .1469921221 |
| Directory | /workspace/94.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_access_same_device_slow_rsp.1501219278 |
| Short name | T1684 |
| Test name | |
| Test status | |
| Simulation time | 113817135327 ps |
| CPU time | 2218.02 seconds |
| Started | Jul 03 07:39:05 PM PDT 24 |
| Finished | Jul 03 08:16:04 PM PDT 24 |
| Peak memory | 574304 kb |
| Host | smart-fcac793e-812c-48aa-a571-fb9a3ba6e80a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1501219278 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_access_same_ device_slow_rsp.1501219278 |
| Directory | /workspace/94.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_error_and_unmapped_addr.3198821368 |
| Short name | T2610 |
| Test name | |
| Test status | |
| Simulation time | 553867181 ps |
| CPU time | 26.13 seconds |
| Started | Jul 03 07:39:13 PM PDT 24 |
| Finished | Jul 03 07:39:40 PM PDT 24 |
| Peak memory | 574412 kb |
| Host | smart-d42c1770-0721-4984-8b04-adec2f067583 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198821368 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_error_and_unmapped_add r.3198821368 |
| Directory | /workspace/94.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_error_random.3503308325 |
| Short name | T2840 |
| Test name | |
| Test status | |
| Simulation time | 487682023 ps |
| CPU time | 18.94 seconds |
| Started | Jul 03 07:39:05 PM PDT 24 |
| Finished | Jul 03 07:39:24 PM PDT 24 |
| Peak memory | 574396 kb |
| Host | smart-cae614df-bc40-47c7-bf40-7995c1f4669e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3503308325 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_error_random.3503308325 |
| Directory | /workspace/94.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_random.1195703004 |
| Short name | T2178 |
| Test name | |
| Test status | |
| Simulation time | 1225432848 ps |
| CPU time | 43.58 seconds |
| Started | Jul 03 07:39:05 PM PDT 24 |
| Finished | Jul 03 07:39:49 PM PDT 24 |
| Peak memory | 573980 kb |
| Host | smart-0c99fa19-86c2-4fb5-9583-dee9c3a0c1c0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1195703004 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_random.1195703004 |
| Directory | /workspace/94.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_random_large_delays.4095477350 |
| Short name | T1768 |
| Test name | |
| Test status | |
| Simulation time | 70693485478 ps |
| CPU time | 743.16 seconds |
| Started | Jul 03 07:39:04 PM PDT 24 |
| Finished | Jul 03 07:51:28 PM PDT 24 |
| Peak memory | 574292 kb |
| Host | smart-7a7f6b07-b871-4edf-948f-f68924c045b1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4095477350 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_random_large_delays.4095477350 |
| Directory | /workspace/94.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_random_slow_rsp.3966764583 |
| Short name | T1713 |
| Test name | |
| Test status | |
| Simulation time | 25869511600 ps |
| CPU time | 438.18 seconds |
| Started | Jul 03 07:39:08 PM PDT 24 |
| Finished | Jul 03 07:46:26 PM PDT 24 |
| Peak memory | 574204 kb |
| Host | smart-d2fd5e89-7053-4fc8-8e75-37a94ed6e540 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3966764583 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_random_slow_rsp.3966764583 |
| Directory | /workspace/94.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_random_zero_delays.3264399916 |
| Short name | T2218 |
| Test name | |
| Test status | |
| Simulation time | 155022208 ps |
| CPU time | 13.44 seconds |
| Started | Jul 03 07:39:04 PM PDT 24 |
| Finished | Jul 03 07:39:18 PM PDT 24 |
| Peak memory | 574008 kb |
| Host | smart-41614211-75f6-4e5e-93ed-51da63862507 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3264399916 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_random_zero_del ays.3264399916 |
| Directory | /workspace/94.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_same_source.3846637975 |
| Short name | T2794 |
| Test name | |
| Test status | |
| Simulation time | 1699835411 ps |
| CPU time | 51.84 seconds |
| Started | Jul 03 07:39:05 PM PDT 24 |
| Finished | Jul 03 07:39:57 PM PDT 24 |
| Peak memory | 574136 kb |
| Host | smart-f972c88b-dbb7-49f5-9d39-fc22023b6920 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3846637975 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_same_source.3846637975 |
| Directory | /workspace/94.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_smoke.2023423377 |
| Short name | T609 |
| Test name | |
| Test status | |
| Simulation time | 56802694 ps |
| CPU time | 6.91 seconds |
| Started | Jul 03 07:39:00 PM PDT 24 |
| Finished | Jul 03 07:39:07 PM PDT 24 |
| Peak memory | 573240 kb |
| Host | smart-975547c8-b369-4173-b093-9260c3c47676 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2023423377 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_smoke.2023423377 |
| Directory | /workspace/94.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_smoke_large_delays.1828267622 |
| Short name | T2657 |
| Test name | |
| Test status | |
| Simulation time | 5060873565 ps |
| CPU time | 50.85 seconds |
| Started | Jul 03 07:38:58 PM PDT 24 |
| Finished | Jul 03 07:39:49 PM PDT 24 |
| Peak memory | 573164 kb |
| Host | smart-513513e8-9ec1-4508-9b1a-81a41f581d8e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1828267622 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_smoke_large_delays.1828267622 |
| Directory | /workspace/94.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_smoke_slow_rsp.2736919960 |
| Short name | T1365 |
| Test name | |
| Test status | |
| Simulation time | 5033767911 ps |
| CPU time | 88.99 seconds |
| Started | Jul 03 07:39:01 PM PDT 24 |
| Finished | Jul 03 07:40:31 PM PDT 24 |
| Peak memory | 573164 kb |
| Host | smart-b571c302-2c26-450f-948a-0b9194df39bc |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2736919960 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_smoke_slow_rsp.2736919960 |
| Directory | /workspace/94.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_smoke_zero_delays.1431871336 |
| Short name | T1593 |
| Test name | |
| Test status | |
| Simulation time | 52705982 ps |
| CPU time | 6.52 seconds |
| Started | Jul 03 07:39:02 PM PDT 24 |
| Finished | Jul 03 07:39:09 PM PDT 24 |
| Peak memory | 572980 kb |
| Host | smart-6b8b267e-5c0b-45db-a9eb-37c9b6983d5e |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1431871336 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_smoke_zero_delay s.1431871336 |
| Directory | /workspace/94.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_stress_all.2147118543 |
| Short name | T2193 |
| Test name | |
| Test status | |
| Simulation time | 4846053205 ps |
| CPU time | 467.97 seconds |
| Started | Jul 03 07:39:08 PM PDT 24 |
| Finished | Jul 03 07:46:57 PM PDT 24 |
| Peak memory | 574696 kb |
| Host | smart-c25367cb-d8f8-4a71-b705-2e3fdf0c51fc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2147118543 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_stress_all.2147118543 |
| Directory | /workspace/94.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_stress_all_with_error.1757841280 |
| Short name | T2124 |
| Test name | |
| Test status | |
| Simulation time | 5787015 ps |
| CPU time | 3.63 seconds |
| Started | Jul 03 07:39:10 PM PDT 24 |
| Finished | Jul 03 07:39:15 PM PDT 24 |
| Peak memory | 564636 kb |
| Host | smart-6d331666-e1c5-483b-9649-ebc24428c507 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1757841280 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_stress_all_with_error.1757841280 |
| Directory | /workspace/94.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_stress_all_with_rand_reset.2251347787 |
| Short name | T601 |
| Test name | |
| Test status | |
| Simulation time | 460962146 ps |
| CPU time | 190.28 seconds |
| Started | Jul 03 07:39:11 PM PDT 24 |
| Finished | Jul 03 07:42:22 PM PDT 24 |
| Peak memory | 574604 kb |
| Host | smart-1d2305f3-46b5-4010-811b-7cfe3937f154 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2251347787 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_stress_all _with_rand_reset.2251347787 |
| Directory | /workspace/94.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_stress_all_with_reset_error.3060336063 |
| Short name | T2740 |
| Test name | |
| Test status | |
| Simulation time | 2227168575 ps |
| CPU time | 311.51 seconds |
| Started | Jul 03 07:39:11 PM PDT 24 |
| Finished | Jul 03 07:44:23 PM PDT 24 |
| Peak memory | 574756 kb |
| Host | smart-0bc871f7-525c-4bfd-bedf-0f7d56051847 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3060336063 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_stress_al l_with_reset_error.3060336063 |
| Directory | /workspace/94.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_unmapped_addr.4153698437 |
| Short name | T1555 |
| Test name | |
| Test status | |
| Simulation time | 93059385 ps |
| CPU time | 11.95 seconds |
| Started | Jul 03 07:39:07 PM PDT 24 |
| Finished | Jul 03 07:39:19 PM PDT 24 |
| Peak memory | 574276 kb |
| Host | smart-945b8314-41f9-4acb-a9b2-cb5d36d68bf5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4153698437 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_unmapped_addr.4153698437 |
| Directory | /workspace/94.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_access_same_device.858677518 |
| Short name | T1846 |
| Test name | |
| Test status | |
| Simulation time | 567541781 ps |
| CPU time | 40.64 seconds |
| Started | Jul 03 07:39:15 PM PDT 24 |
| Finished | Jul 03 07:39:56 PM PDT 24 |
| Peak memory | 574056 kb |
| Host | smart-d909b8f0-c621-4f31-9b27-d129e0826c10 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=858677518 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_access_same_device. 858677518 |
| Directory | /workspace/95.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_access_same_device_slow_rsp.622517303 |
| Short name | T1677 |
| Test name | |
| Test status | |
| Simulation time | 11036190551 ps |
| CPU time | 185.4 seconds |
| Started | Jul 03 07:39:13 PM PDT 24 |
| Finished | Jul 03 07:42:19 PM PDT 24 |
| Peak memory | 573180 kb |
| Host | smart-5d580262-8a4e-45bd-9ab1-fed352175166 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=622517303 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_access_same_d evice_slow_rsp.622517303 |
| Directory | /workspace/95.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_error_and_unmapped_addr.3314807629 |
| Short name | T2846 |
| Test name | |
| Test status | |
| Simulation time | 340601291 ps |
| CPU time | 16.34 seconds |
| Started | Jul 03 07:39:16 PM PDT 24 |
| Finished | Jul 03 07:39:33 PM PDT 24 |
| Peak memory | 574064 kb |
| Host | smart-88220cd8-f37f-4b6b-9acb-e1481594b876 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3314807629 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_error_and_unmapped_add r.3314807629 |
| Directory | /workspace/95.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_error_random.1164661408 |
| Short name | T1901 |
| Test name | |
| Test status | |
| Simulation time | 1019893411 ps |
| CPU time | 36.48 seconds |
| Started | Jul 03 07:39:15 PM PDT 24 |
| Finished | Jul 03 07:39:53 PM PDT 24 |
| Peak memory | 574568 kb |
| Host | smart-fc06c732-ae70-46d1-8658-65ff1f21e049 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1164661408 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_error_random.1164661408 |
| Directory | /workspace/95.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_random.322436242 |
| Short name | T1349 |
| Test name | |
| Test status | |
| Simulation time | 1664010768 ps |
| CPU time | 57.96 seconds |
| Started | Jul 03 07:39:09 PM PDT 24 |
| Finished | Jul 03 07:40:07 PM PDT 24 |
| Peak memory | 574048 kb |
| Host | smart-a4ec087b-7773-42c9-a15b-0a8e7d1149cc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322436242 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_random.322436242 |
| Directory | /workspace/95.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_random_large_delays.3236437249 |
| Short name | T2321 |
| Test name | |
| Test status | |
| Simulation time | 83638630688 ps |
| CPU time | 978.49 seconds |
| Started | Jul 03 07:39:14 PM PDT 24 |
| Finished | Jul 03 07:55:33 PM PDT 24 |
| Peak memory | 574296 kb |
| Host | smart-76b85581-2e1f-48a3-bc6e-191a3e33e5a7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236437249 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_random_large_delays.3236437249 |
| Directory | /workspace/95.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_random_slow_rsp.1361930649 |
| Short name | T1666 |
| Test name | |
| Test status | |
| Simulation time | 10189125992 ps |
| CPU time | 177.4 seconds |
| Started | Jul 03 07:39:13 PM PDT 24 |
| Finished | Jul 03 07:42:11 PM PDT 24 |
| Peak memory | 574052 kb |
| Host | smart-ac5d623d-dbac-4657-996e-6a750bd02646 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1361930649 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_random_slow_rsp.1361930649 |
| Directory | /workspace/95.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_random_zero_delays.2472846694 |
| Short name | T2184 |
| Test name | |
| Test status | |
| Simulation time | 546053348 ps |
| CPU time | 50.37 seconds |
| Started | Jul 03 07:39:12 PM PDT 24 |
| Finished | Jul 03 07:40:03 PM PDT 24 |
| Peak memory | 574288 kb |
| Host | smart-640481d5-6a00-425a-bda0-5545e8ebf798 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2472846694 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_random_zero_del ays.2472846694 |
| Directory | /workspace/95.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_same_source.2152225080 |
| Short name | T1900 |
| Test name | |
| Test status | |
| Simulation time | 1685717676 ps |
| CPU time | 51.02 seconds |
| Started | Jul 03 07:39:14 PM PDT 24 |
| Finished | Jul 03 07:40:05 PM PDT 24 |
| Peak memory | 574068 kb |
| Host | smart-20070347-b6f7-46ce-af5d-709c17a62809 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2152225080 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_same_source.2152225080 |
| Directory | /workspace/95.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_smoke.2315588605 |
| Short name | T2466 |
| Test name | |
| Test status | |
| Simulation time | 256395578 ps |
| CPU time | 9.75 seconds |
| Started | Jul 03 07:39:09 PM PDT 24 |
| Finished | Jul 03 07:39:20 PM PDT 24 |
| Peak memory | 573116 kb |
| Host | smart-a9cef7fb-b08e-4060-b775-69106abb56c7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2315588605 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_smoke.2315588605 |
| Directory | /workspace/95.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_smoke_large_delays.2373291839 |
| Short name | T2141 |
| Test name | |
| Test status | |
| Simulation time | 8265792047 ps |
| CPU time | 87.56 seconds |
| Started | Jul 03 07:39:11 PM PDT 24 |
| Finished | Jul 03 07:40:39 PM PDT 24 |
| Peak memory | 573200 kb |
| Host | smart-7dcd945f-ce91-45e3-bffe-dc9edb9a8ab9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2373291839 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_smoke_large_delays.2373291839 |
| Directory | /workspace/95.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_smoke_slow_rsp.3294012581 |
| Short name | T1442 |
| Test name | |
| Test status | |
| Simulation time | 4864617353 ps |
| CPU time | 80.07 seconds |
| Started | Jul 03 07:39:11 PM PDT 24 |
| Finished | Jul 03 07:40:32 PM PDT 24 |
| Peak memory | 574160 kb |
| Host | smart-c384e9bc-d1b8-4c5f-9d18-5e30e0152f2d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294012581 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_smoke_slow_rsp.3294012581 |
| Directory | /workspace/95.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_smoke_zero_delays.1267974592 |
| Short name | T1798 |
| Test name | |
| Test status | |
| Simulation time | 39600272 ps |
| CPU time | 6.2 seconds |
| Started | Jul 03 07:39:12 PM PDT 24 |
| Finished | Jul 03 07:39:19 PM PDT 24 |
| Peak memory | 574084 kb |
| Host | smart-b958d318-a490-48ec-b664-4c53053e996e |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1267974592 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_smoke_zero_delay s.1267974592 |
| Directory | /workspace/95.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_stress_all.2912318320 |
| Short name | T1862 |
| Test name | |
| Test status | |
| Simulation time | 5552774448 ps |
| CPU time | 497.71 seconds |
| Started | Jul 03 07:39:20 PM PDT 24 |
| Finished | Jul 03 07:47:38 PM PDT 24 |
| Peak memory | 574772 kb |
| Host | smart-bc98f15c-b3c6-4b59-aeda-22b2e3c1b9c8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2912318320 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_stress_all.2912318320 |
| Directory | /workspace/95.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_stress_all_with_error.685952106 |
| Short name | T2517 |
| Test name | |
| Test status | |
| Simulation time | 845468792 ps |
| CPU time | 65.68 seconds |
| Started | Jul 03 07:39:18 PM PDT 24 |
| Finished | Jul 03 07:40:25 PM PDT 24 |
| Peak memory | 574516 kb |
| Host | smart-5c411c60-e97c-4d19-9328-2fe84febf0db |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=685952106 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_stress_all_with_error.685952106 |
| Directory | /workspace/95.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_stress_all_with_rand_reset.3403612641 |
| Short name | T2630 |
| Test name | |
| Test status | |
| Simulation time | 1634152233 ps |
| CPU time | 241.3 seconds |
| Started | Jul 03 07:39:19 PM PDT 24 |
| Finished | Jul 03 07:43:21 PM PDT 24 |
| Peak memory | 574628 kb |
| Host | smart-5b631adf-5e5e-48e6-871b-7d787e3f1900 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3403612641 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_stress_all _with_rand_reset.3403612641 |
| Directory | /workspace/95.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_stress_all_with_reset_error.3504088227 |
| Short name | T2807 |
| Test name | |
| Test status | |
| Simulation time | 303908160 ps |
| CPU time | 85.55 seconds |
| Started | Jul 03 07:39:19 PM PDT 24 |
| Finished | Jul 03 07:40:46 PM PDT 24 |
| Peak memory | 574624 kb |
| Host | smart-0ac5aa56-7fce-4454-9fd2-7f43ac40fedf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504088227 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_stress_al l_with_reset_error.3504088227 |
| Directory | /workspace/95.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_unmapped_addr.179542428 |
| Short name | T1877 |
| Test name | |
| Test status | |
| Simulation time | 119333501 ps |
| CPU time | 15.94 seconds |
| Started | Jul 03 07:39:15 PM PDT 24 |
| Finished | Jul 03 07:39:32 PM PDT 24 |
| Peak memory | 574260 kb |
| Host | smart-b41fe1c5-5898-4f39-9101-f2e13865455a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=179542428 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_unmapped_addr.179542428 |
| Directory | /workspace/95.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_access_same_device.1120240864 |
| Short name | T1928 |
| Test name | |
| Test status | |
| Simulation time | 763336606 ps |
| CPU time | 57.96 seconds |
| Started | Jul 03 07:39:26 PM PDT 24 |
| Finished | Jul 03 07:40:25 PM PDT 24 |
| Peak memory | 574128 kb |
| Host | smart-5d2f952d-4248-45ad-afb5-2e7d40af99c8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120240864 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_access_same_device .1120240864 |
| Directory | /workspace/96.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_access_same_device_slow_rsp.1345509552 |
| Short name | T761 |
| Test name | |
| Test status | |
| Simulation time | 85865446851 ps |
| CPU time | 1648.99 seconds |
| Started | Jul 03 07:39:26 PM PDT 24 |
| Finished | Jul 03 08:06:56 PM PDT 24 |
| Peak memory | 574264 kb |
| Host | smart-8df70342-75e6-4672-a151-5fe8f28e4f53 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1345509552 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_access_same_ device_slow_rsp.1345509552 |
| Directory | /workspace/96.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_error_and_unmapped_addr.3699487555 |
| Short name | T1714 |
| Test name | |
| Test status | |
| Simulation time | 194894353 ps |
| CPU time | 21.09 seconds |
| Started | Jul 03 07:39:29 PM PDT 24 |
| Finished | Jul 03 07:39:51 PM PDT 24 |
| Peak memory | 574452 kb |
| Host | smart-3f572757-71b7-414d-a328-85202c380b24 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699487555 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_error_and_unmapped_add r.3699487555 |
| Directory | /workspace/96.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_error_random.902273659 |
| Short name | T2664 |
| Test name | |
| Test status | |
| Simulation time | 429811213 ps |
| CPU time | 38.95 seconds |
| Started | Jul 03 07:39:27 PM PDT 24 |
| Finished | Jul 03 07:40:06 PM PDT 24 |
| Peak memory | 574496 kb |
| Host | smart-3a0b7e49-3166-42a7-9b00-7343bbb37639 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902273659 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_error_random.902273659 |
| Directory | /workspace/96.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_random.714636747 |
| Short name | T2737 |
| Test name | |
| Test status | |
| Simulation time | 780821168 ps |
| CPU time | 29.21 seconds |
| Started | Jul 03 07:39:26 PM PDT 24 |
| Finished | Jul 03 07:39:56 PM PDT 24 |
| Peak memory | 574244 kb |
| Host | smart-1b862a81-e6a4-4d73-b11e-ba71b2014bb8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=714636747 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_random.714636747 |
| Directory | /workspace/96.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_random_large_delays.20029903 |
| Short name | T556 |
| Test name | |
| Test status | |
| Simulation time | 104135901815 ps |
| CPU time | 1232.88 seconds |
| Started | Jul 03 07:39:27 PM PDT 24 |
| Finished | Jul 03 08:00:00 PM PDT 24 |
| Peak memory | 574288 kb |
| Host | smart-117c6c99-2141-4836-8813-c94a77e2e5e8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20029903 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_random_large_delays.20029903 |
| Directory | /workspace/96.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_random_slow_rsp.1650785777 |
| Short name | T2097 |
| Test name | |
| Test status | |
| Simulation time | 64046723616 ps |
| CPU time | 1204.68 seconds |
| Started | Jul 03 07:39:25 PM PDT 24 |
| Finished | Jul 03 07:59:30 PM PDT 24 |
| Peak memory | 574204 kb |
| Host | smart-4b7249ab-9b99-4f72-89cb-59e3ab5583a0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1650785777 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_random_slow_rsp.1650785777 |
| Directory | /workspace/96.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_random_zero_delays.3929780040 |
| Short name | T435 |
| Test name | |
| Test status | |
| Simulation time | 402703215 ps |
| CPU time | 34.19 seconds |
| Started | Jul 03 07:39:24 PM PDT 24 |
| Finished | Jul 03 07:39:59 PM PDT 24 |
| Peak memory | 574200 kb |
| Host | smart-3ef13746-ca8b-4efa-8de5-cbe54183bd5f |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3929780040 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_random_zero_del ays.3929780040 |
| Directory | /workspace/96.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_same_source.3031763236 |
| Short name | T1828 |
| Test name | |
| Test status | |
| Simulation time | 102610459 ps |
| CPU time | 9.96 seconds |
| Started | Jul 03 07:39:30 PM PDT 24 |
| Finished | Jul 03 07:39:40 PM PDT 24 |
| Peak memory | 573960 kb |
| Host | smart-ebfd4a3a-4ae4-4b54-83b4-0709a594e29a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3031763236 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_same_source.3031763236 |
| Directory | /workspace/96.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_smoke.2183507432 |
| Short name | T2831 |
| Test name | |
| Test status | |
| Simulation time | 218868256 ps |
| CPU time | 9.43 seconds |
| Started | Jul 03 07:39:20 PM PDT 24 |
| Finished | Jul 03 07:39:30 PM PDT 24 |
| Peak memory | 574160 kb |
| Host | smart-b943da19-3f11-4cc1-aeb7-28d5fb9e029a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2183507432 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_smoke.2183507432 |
| Directory | /workspace/96.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_smoke_large_delays.1687383758 |
| Short name | T1775 |
| Test name | |
| Test status | |
| Simulation time | 8125664467 ps |
| CPU time | 90.69 seconds |
| Started | Jul 03 07:39:19 PM PDT 24 |
| Finished | Jul 03 07:40:50 PM PDT 24 |
| Peak memory | 574136 kb |
| Host | smart-ad6c0df1-ad2d-4767-a64f-232b86230760 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1687383758 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_smoke_large_delays.1687383758 |
| Directory | /workspace/96.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_smoke_slow_rsp.2976162368 |
| Short name | T1624 |
| Test name | |
| Test status | |
| Simulation time | 4779938296 ps |
| CPU time | 85.18 seconds |
| Started | Jul 03 07:39:17 PM PDT 24 |
| Finished | Jul 03 07:40:43 PM PDT 24 |
| Peak memory | 574252 kb |
| Host | smart-1d64d09a-f8bf-44d7-899e-e06950eda99c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976162368 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_smoke_slow_rsp.2976162368 |
| Directory | /workspace/96.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_smoke_zero_delays.4041499834 |
| Short name | T2468 |
| Test name | |
| Test status | |
| Simulation time | 38372647 ps |
| CPU time | 6.23 seconds |
| Started | Jul 03 07:39:19 PM PDT 24 |
| Finished | Jul 03 07:39:26 PM PDT 24 |
| Peak memory | 573216 kb |
| Host | smart-af268d53-1afa-43ab-895e-3646fe04deb8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4041499834 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_smoke_zero_delay s.4041499834 |
| Directory | /workspace/96.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_stress_all.2066191128 |
| Short name | T2615 |
| Test name | |
| Test status | |
| Simulation time | 379155785 ps |
| CPU time | 16.36 seconds |
| Started | Jul 03 07:39:27 PM PDT 24 |
| Finished | Jul 03 07:39:44 PM PDT 24 |
| Peak memory | 574152 kb |
| Host | smart-4da44412-5a61-44be-9602-cba5df15ea5f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2066191128 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_stress_all.2066191128 |
| Directory | /workspace/96.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_stress_all_with_error.2279699316 |
| Short name | T1494 |
| Test name | |
| Test status | |
| Simulation time | 13828966775 ps |
| CPU time | 605.88 seconds |
| Started | Jul 03 07:39:26 PM PDT 24 |
| Finished | Jul 03 07:49:33 PM PDT 24 |
| Peak memory | 574736 kb |
| Host | smart-284a5784-6362-4699-a224-2a9dafe663b8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279699316 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_stress_all_with_error.2279699316 |
| Directory | /workspace/96.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_stress_all_with_rand_reset.3003766619 |
| Short name | T1784 |
| Test name | |
| Test status | |
| Simulation time | 399966900 ps |
| CPU time | 199.44 seconds |
| Started | Jul 03 07:39:26 PM PDT 24 |
| Finished | Jul 03 07:42:47 PM PDT 24 |
| Peak memory | 574684 kb |
| Host | smart-a3886792-4ab6-4829-8a54-67b66d7deb98 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3003766619 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_stress_all _with_rand_reset.3003766619 |
| Directory | /workspace/96.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_stress_all_with_reset_error.991652995 |
| Short name | T1448 |
| Test name | |
| Test status | |
| Simulation time | 4494189967 ps |
| CPU time | 473.77 seconds |
| Started | Jul 03 07:39:31 PM PDT 24 |
| Finished | Jul 03 07:47:25 PM PDT 24 |
| Peak memory | 574716 kb |
| Host | smart-1e5608e2-f66c-4ca3-896d-58d22971aae0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=991652995 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_stress_all _with_reset_error.991652995 |
| Directory | /workspace/96.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_unmapped_addr.2036911043 |
| Short name | T2052 |
| Test name | |
| Test status | |
| Simulation time | 52070946 ps |
| CPU time | 9.31 seconds |
| Started | Jul 03 07:39:27 PM PDT 24 |
| Finished | Jul 03 07:39:37 PM PDT 24 |
| Peak memory | 574204 kb |
| Host | smart-bdb46b74-6a1b-4566-b2ba-4ce11017e931 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2036911043 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_unmapped_addr.2036911043 |
| Directory | /workspace/96.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_access_same_device.3777488997 |
| Short name | T1519 |
| Test name | |
| Test status | |
| Simulation time | 529151197 ps |
| CPU time | 41.37 seconds |
| Started | Jul 03 07:39:37 PM PDT 24 |
| Finished | Jul 03 07:40:19 PM PDT 24 |
| Peak memory | 574072 kb |
| Host | smart-6c92478e-aa45-4e5b-b090-d86b928ecf13 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3777488997 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_access_same_device .3777488997 |
| Directory | /workspace/97.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_access_same_device_slow_rsp.1692253800 |
| Short name | T2094 |
| Test name | |
| Test status | |
| Simulation time | 138197535616 ps |
| CPU time | 2530.14 seconds |
| Started | Jul 03 07:39:39 PM PDT 24 |
| Finished | Jul 03 08:21:50 PM PDT 24 |
| Peak memory | 574184 kb |
| Host | smart-c42154e3-504c-4585-94d4-bc7cb6896e82 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1692253800 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_access_same_ device_slow_rsp.1692253800 |
| Directory | /workspace/97.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_error_and_unmapped_addr.3499153100 |
| Short name | T2576 |
| Test name | |
| Test status | |
| Simulation time | 529603865 ps |
| CPU time | 22.6 seconds |
| Started | Jul 03 07:39:39 PM PDT 24 |
| Finished | Jul 03 07:40:02 PM PDT 24 |
| Peak memory | 574460 kb |
| Host | smart-d70b568b-82c2-464d-8465-08afb8eb1252 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3499153100 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_error_and_unmapped_add r.3499153100 |
| Directory | /workspace/97.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_error_random.2164674256 |
| Short name | T1718 |
| Test name | |
| Test status | |
| Simulation time | 2244972024 ps |
| CPU time | 63.96 seconds |
| Started | Jul 03 07:39:36 PM PDT 24 |
| Finished | Jul 03 07:40:40 PM PDT 24 |
| Peak memory | 574528 kb |
| Host | smart-1f8a47f9-657d-4dc7-985d-16ffbdc11836 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164674256 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_error_random.2164674256 |
| Directory | /workspace/97.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_random.3196995929 |
| Short name | T1395 |
| Test name | |
| Test status | |
| Simulation time | 783817401 ps |
| CPU time | 28.21 seconds |
| Started | Jul 03 07:39:45 PM PDT 24 |
| Finished | Jul 03 07:40:14 PM PDT 24 |
| Peak memory | 574180 kb |
| Host | smart-117b1cc1-db64-462a-834f-304f8eda9266 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3196995929 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_random.3196995929 |
| Directory | /workspace/97.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_random_large_delays.1167753201 |
| Short name | T1891 |
| Test name | |
| Test status | |
| Simulation time | 30743725357 ps |
| CPU time | 318.76 seconds |
| Started | Jul 03 07:39:31 PM PDT 24 |
| Finished | Jul 03 07:44:51 PM PDT 24 |
| Peak memory | 574084 kb |
| Host | smart-ed4f3d76-9f1e-4fe4-b05b-2c0cf3afd32a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1167753201 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_random_large_delays.1167753201 |
| Directory | /workspace/97.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_random_slow_rsp.2786083852 |
| Short name | T1819 |
| Test name | |
| Test status | |
| Simulation time | 53019764889 ps |
| CPU time | 879.59 seconds |
| Started | Jul 03 07:39:34 PM PDT 24 |
| Finished | Jul 03 07:54:14 PM PDT 24 |
| Peak memory | 574148 kb |
| Host | smart-2c9ecafa-0bab-4df2-b146-96846c142854 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786083852 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_random_slow_rsp.2786083852 |
| Directory | /workspace/97.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_random_zero_delays.2588772484 |
| Short name | T1992 |
| Test name | |
| Test status | |
| Simulation time | 100913328 ps |
| CPU time | 10.23 seconds |
| Started | Jul 03 07:39:31 PM PDT 24 |
| Finished | Jul 03 07:39:42 PM PDT 24 |
| Peak memory | 574228 kb |
| Host | smart-1e6d3563-f33b-4aec-969f-c4b1147192c9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2588772484 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_random_zero_del ays.2588772484 |
| Directory | /workspace/97.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_same_source.4033725860 |
| Short name | T2204 |
| Test name | |
| Test status | |
| Simulation time | 572578896 ps |
| CPU time | 43.47 seconds |
| Started | Jul 03 07:39:36 PM PDT 24 |
| Finished | Jul 03 07:40:20 PM PDT 24 |
| Peak memory | 574176 kb |
| Host | smart-2f106393-ba96-456f-b904-efe1eef73a50 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4033725860 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_same_source.4033725860 |
| Directory | /workspace/97.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_smoke.295840916 |
| Short name | T1358 |
| Test name | |
| Test status | |
| Simulation time | 157440500 ps |
| CPU time | 7.37 seconds |
| Started | Jul 03 07:39:33 PM PDT 24 |
| Finished | Jul 03 07:39:41 PM PDT 24 |
| Peak memory | 573996 kb |
| Host | smart-14160d0f-e5a3-4c21-8c39-93d0c7f9fd96 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=295840916 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_smoke.295840916 |
| Directory | /workspace/97.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_smoke_large_delays.2678776947 |
| Short name | T1446 |
| Test name | |
| Test status | |
| Simulation time | 6768238131 ps |
| CPU time | 68.18 seconds |
| Started | Jul 03 07:39:33 PM PDT 24 |
| Finished | Jul 03 07:40:41 PM PDT 24 |
| Peak memory | 574148 kb |
| Host | smart-b4cffc05-351c-4e81-9479-08744ef5d9d9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2678776947 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_smoke_large_delays.2678776947 |
| Directory | /workspace/97.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_smoke_slow_rsp.4035063841 |
| Short name | T2699 |
| Test name | |
| Test status | |
| Simulation time | 4105220673 ps |
| CPU time | 68.99 seconds |
| Started | Jul 03 07:39:30 PM PDT 24 |
| Finished | Jul 03 07:40:40 PM PDT 24 |
| Peak memory | 573008 kb |
| Host | smart-a5d39876-92bd-497d-85b8-1e7a0b09e10f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4035063841 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_smoke_slow_rsp.4035063841 |
| Directory | /workspace/97.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_smoke_zero_delays.2382402138 |
| Short name | T1707 |
| Test name | |
| Test status | |
| Simulation time | 48899000 ps |
| CPU time | 6.26 seconds |
| Started | Jul 03 07:39:30 PM PDT 24 |
| Finished | Jul 03 07:39:36 PM PDT 24 |
| Peak memory | 574360 kb |
| Host | smart-b96b9f3a-4cde-4f15-a901-f11630f454c0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2382402138 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_smoke_zero_delay s.2382402138 |
| Directory | /workspace/97.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_stress_all.3164956937 |
| Short name | T2806 |
| Test name | |
| Test status | |
| Simulation time | 1281493869 ps |
| CPU time | 111.6 seconds |
| Started | Jul 03 07:39:50 PM PDT 24 |
| Finished | Jul 03 07:41:42 PM PDT 24 |
| Peak memory | 574420 kb |
| Host | smart-d3409531-d79e-44a0-9c5d-7f77195b7a91 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3164956937 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_stress_all.3164956937 |
| Directory | /workspace/97.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_stress_all_with_error.731652500 |
| Short name | T782 |
| Test name | |
| Test status | |
| Simulation time | 4767951159 ps |
| CPU time | 429.12 seconds |
| Started | Jul 03 07:39:38 PM PDT 24 |
| Finished | Jul 03 07:46:48 PM PDT 24 |
| Peak memory | 574696 kb |
| Host | smart-4e22fe25-ca31-4316-b4ca-5a8e04192f2a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=731652500 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_stress_all_with_error.731652500 |
| Directory | /workspace/97.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_stress_all_with_rand_reset.3016836601 |
| Short name | T2169 |
| Test name | |
| Test status | |
| Simulation time | 484751195 ps |
| CPU time | 55.92 seconds |
| Started | Jul 03 07:39:37 PM PDT 24 |
| Finished | Jul 03 07:40:34 PM PDT 24 |
| Peak memory | 574660 kb |
| Host | smart-4577bb99-dde9-4765-89e1-602cfa206a65 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3016836601 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_stress_all _with_rand_reset.3016836601 |
| Directory | /workspace/97.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_stress_all_with_reset_error.3490575999 |
| Short name | T1771 |
| Test name | |
| Test status | |
| Simulation time | 1657765397 ps |
| CPU time | 160.23 seconds |
| Started | Jul 03 07:39:50 PM PDT 24 |
| Finished | Jul 03 07:42:31 PM PDT 24 |
| Peak memory | 574704 kb |
| Host | smart-f0fa9f49-d51d-46a1-84ce-557ba39b2fe6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3490575999 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_stress_al l_with_reset_error.3490575999 |
| Directory | /workspace/97.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_unmapped_addr.1537811177 |
| Short name | T2654 |
| Test name | |
| Test status | |
| Simulation time | 1368275138 ps |
| CPU time | 57.95 seconds |
| Started | Jul 03 07:39:39 PM PDT 24 |
| Finished | Jul 03 07:40:37 PM PDT 24 |
| Peak memory | 574084 kb |
| Host | smart-eb7f5028-6f8f-42a0-b2b9-9c3db6c3285e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1537811177 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_unmapped_addr.1537811177 |
| Directory | /workspace/97.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_access_same_device.1438663093 |
| Short name | T2281 |
| Test name | |
| Test status | |
| Simulation time | 3915341426 ps |
| CPU time | 152.79 seconds |
| Started | Jul 03 07:39:41 PM PDT 24 |
| Finished | Jul 03 07:42:15 PM PDT 24 |
| Peak memory | 574348 kb |
| Host | smart-651f9b28-403d-497b-9bbe-430f6cf2170d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1438663093 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_access_same_device .1438663093 |
| Directory | /workspace/98.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_access_same_device_slow_rsp.1612905531 |
| Short name | T2463 |
| Test name | |
| Test status | |
| Simulation time | 15304430296 ps |
| CPU time | 271.27 seconds |
| Started | Jul 03 07:39:44 PM PDT 24 |
| Finished | Jul 03 07:44:16 PM PDT 24 |
| Peak memory | 574296 kb |
| Host | smart-bf6de0fb-761e-4c21-ba61-8159e7deab19 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612905531 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_access_same_ device_slow_rsp.1612905531 |
| Directory | /workspace/98.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_error_and_unmapped_addr.284370483 |
| Short name | T1366 |
| Test name | |
| Test status | |
| Simulation time | 154578774 ps |
| CPU time | 9.64 seconds |
| Started | Jul 03 07:39:48 PM PDT 24 |
| Finished | Jul 03 07:39:59 PM PDT 24 |
| Peak memory | 573448 kb |
| Host | smart-4b445430-8a12-44d6-a87f-86e70b632ea0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=284370483 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_error_and_unmapped_addr .284370483 |
| Directory | /workspace/98.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_error_random.832090295 |
| Short name | T1756 |
| Test name | |
| Test status | |
| Simulation time | 1019283324 ps |
| CPU time | 32.69 seconds |
| Started | Jul 03 07:39:46 PM PDT 24 |
| Finished | Jul 03 07:40:19 PM PDT 24 |
| Peak memory | 574508 kb |
| Host | smart-8717595c-926e-49b9-b1a4-45dc087dc9f0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=832090295 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_error_random.832090295 |
| Directory | /workspace/98.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_random.3484394893 |
| Short name | T536 |
| Test name | |
| Test status | |
| Simulation time | 1262996183 ps |
| CPU time | 46.59 seconds |
| Started | Jul 03 07:39:38 PM PDT 24 |
| Finished | Jul 03 07:40:25 PM PDT 24 |
| Peak memory | 574112 kb |
| Host | smart-52aaa62d-dae9-4b66-8eef-65fc7e94d734 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3484394893 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_random.3484394893 |
| Directory | /workspace/98.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_random_large_delays.3985108714 |
| Short name | T1452 |
| Test name | |
| Test status | |
| Simulation time | 28038433045 ps |
| CPU time | 277.2 seconds |
| Started | Jul 03 07:39:42 PM PDT 24 |
| Finished | Jul 03 07:44:21 PM PDT 24 |
| Peak memory | 574280 kb |
| Host | smart-dd747862-98bf-4c53-b350-995bd1d1061b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3985108714 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_random_large_delays.3985108714 |
| Directory | /workspace/98.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_random_slow_rsp.1399119063 |
| Short name | T1787 |
| Test name | |
| Test status | |
| Simulation time | 11772622602 ps |
| CPU time | 203.89 seconds |
| Started | Jul 03 07:39:42 PM PDT 24 |
| Finished | Jul 03 07:43:07 PM PDT 24 |
| Peak memory | 574280 kb |
| Host | smart-6d78efbf-8cd7-463a-8fb2-17e961171df1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1399119063 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_random_slow_rsp.1399119063 |
| Directory | /workspace/98.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_random_zero_delays.365401377 |
| Short name | T1427 |
| Test name | |
| Test status | |
| Simulation time | 480884325 ps |
| CPU time | 42.72 seconds |
| Started | Jul 03 07:39:36 PM PDT 24 |
| Finished | Jul 03 07:40:20 PM PDT 24 |
| Peak memory | 574192 kb |
| Host | smart-691389f4-e295-4d36-a007-778b56e48c24 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=365401377 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_random_zero_dela ys.365401377 |
| Directory | /workspace/98.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_same_source.951945914 |
| Short name | T1899 |
| Test name | |
| Test status | |
| Simulation time | 2611174952 ps |
| CPU time | 75.81 seconds |
| Started | Jul 03 07:39:49 PM PDT 24 |
| Finished | Jul 03 07:41:05 PM PDT 24 |
| Peak memory | 574196 kb |
| Host | smart-241428c3-9fa0-4df5-9018-c9ce2bf49de7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=951945914 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_same_source.951945914 |
| Directory | /workspace/98.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_smoke.688636719 |
| Short name | T2429 |
| Test name | |
| Test status | |
| Simulation time | 185881640 ps |
| CPU time | 8.48 seconds |
| Started | Jul 03 07:39:49 PM PDT 24 |
| Finished | Jul 03 07:39:58 PM PDT 24 |
| Peak memory | 573988 kb |
| Host | smart-4765c441-80dd-4da8-8b1b-ca788f54dd40 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=688636719 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_smoke.688636719 |
| Directory | /workspace/98.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_smoke_large_delays.1152469540 |
| Short name | T1657 |
| Test name | |
| Test status | |
| Simulation time | 6058209452 ps |
| CPU time | 60.04 seconds |
| Started | Jul 03 07:39:37 PM PDT 24 |
| Finished | Jul 03 07:40:38 PM PDT 24 |
| Peak memory | 574032 kb |
| Host | smart-7577a1aa-3f96-4c27-b900-a723a0264874 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1152469540 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_smoke_large_delays.1152469540 |
| Directory | /workspace/98.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_smoke_slow_rsp.2033762834 |
| Short name | T1360 |
| Test name | |
| Test status | |
| Simulation time | 5716263302 ps |
| CPU time | 96.91 seconds |
| Started | Jul 03 07:39:39 PM PDT 24 |
| Finished | Jul 03 07:41:17 PM PDT 24 |
| Peak memory | 573268 kb |
| Host | smart-0ccd4e41-f010-4a6b-8440-96286e65b4fc |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2033762834 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_smoke_slow_rsp.2033762834 |
| Directory | /workspace/98.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_smoke_zero_delays.383204086 |
| Short name | T2081 |
| Test name | |
| Test status | |
| Simulation time | 45988446 ps |
| CPU time | 6.55 seconds |
| Started | Jul 03 07:39:38 PM PDT 24 |
| Finished | Jul 03 07:39:46 PM PDT 24 |
| Peak memory | 573112 kb |
| Host | smart-2f65bddb-bc21-44cc-808a-49d3863595b5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=383204086 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_smoke_zero_delays .383204086 |
| Directory | /workspace/98.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_stress_all.114529522 |
| Short name | T488 |
| Test name | |
| Test status | |
| Simulation time | 2861534635 ps |
| CPU time | 242.27 seconds |
| Started | Jul 03 07:39:46 PM PDT 24 |
| Finished | Jul 03 07:43:49 PM PDT 24 |
| Peak memory | 574708 kb |
| Host | smart-f36fb816-da17-41d7-a128-51aecf68b2f7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114529522 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_stress_all.114529522 |
| Directory | /workspace/98.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_stress_all_with_error.156437010 |
| Short name | T785 |
| Test name | |
| Test status | |
| Simulation time | 2233424034 ps |
| CPU time | 176.94 seconds |
| Started | Jul 03 07:39:48 PM PDT 24 |
| Finished | Jul 03 07:42:45 PM PDT 24 |
| Peak memory | 574268 kb |
| Host | smart-c009ede2-2ffd-486c-9f9e-022aafc5b23b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=156437010 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_stress_all_with_error.156437010 |
| Directory | /workspace/98.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_stress_all_with_rand_reset.4160757806 |
| Short name | T604 |
| Test name | |
| Test status | |
| Simulation time | 10751217628 ps |
| CPU time | 750.56 seconds |
| Started | Jul 03 07:39:47 PM PDT 24 |
| Finished | Jul 03 07:52:18 PM PDT 24 |
| Peak memory | 574768 kb |
| Host | smart-6ddd2e89-2357-476a-be52-96cf5c34dca1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4160757806 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_stress_all _with_rand_reset.4160757806 |
| Directory | /workspace/98.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_stress_all_with_reset_error.1207944261 |
| Short name | T635 |
| Test name | |
| Test status | |
| Simulation time | 378817276 ps |
| CPU time | 116.49 seconds |
| Started | Jul 03 07:39:47 PM PDT 24 |
| Finished | Jul 03 07:41:45 PM PDT 24 |
| Peak memory | 574696 kb |
| Host | smart-8e7fc02d-d52d-47dd-a029-cdf84974e9f7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207944261 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_stress_al l_with_reset_error.1207944261 |
| Directory | /workspace/98.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_unmapped_addr.1785843807 |
| Short name | T2349 |
| Test name | |
| Test status | |
| Simulation time | 77208116 ps |
| CPU time | 11.54 seconds |
| Started | Jul 03 07:40:02 PM PDT 24 |
| Finished | Jul 03 07:40:14 PM PDT 24 |
| Peak memory | 574260 kb |
| Host | smart-bc01ce67-955e-4d45-bde1-f552705b61da |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1785843807 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_unmapped_addr.1785843807 |
| Directory | /workspace/98.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_access_same_device.1330660210 |
| Short name | T491 |
| Test name | |
| Test status | |
| Simulation time | 342963003 ps |
| CPU time | 32.16 seconds |
| Started | Jul 03 07:39:51 PM PDT 24 |
| Finished | Jul 03 07:40:24 PM PDT 24 |
| Peak memory | 574052 kb |
| Host | smart-727c6485-87d2-4cf0-9fe3-4814de6f1e62 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1330660210 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_access_same_device .1330660210 |
| Directory | /workspace/99.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_access_same_device_slow_rsp.4285252023 |
| Short name | T1840 |
| Test name | |
| Test status | |
| Simulation time | 59187825608 ps |
| CPU time | 1100.87 seconds |
| Started | Jul 03 07:40:00 PM PDT 24 |
| Finished | Jul 03 07:58:22 PM PDT 24 |
| Peak memory | 574360 kb |
| Host | smart-365503e5-19c1-4c99-bb86-5d4f5c082d69 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4285252023 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_access_same_ device_slow_rsp.4285252023 |
| Directory | /workspace/99.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_error_and_unmapped_addr.691085902 |
| Short name | T1656 |
| Test name | |
| Test status | |
| Simulation time | 298608981 ps |
| CPU time | 14.65 seconds |
| Started | Jul 03 07:39:56 PM PDT 24 |
| Finished | Jul 03 07:40:11 PM PDT 24 |
| Peak memory | 574464 kb |
| Host | smart-4fac8c9d-d2b0-4484-81da-adb1bb371d00 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=691085902 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_error_and_unmapped_addr .691085902 |
| Directory | /workspace/99.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_error_random.928604161 |
| Short name | T1529 |
| Test name | |
| Test status | |
| Simulation time | 380848766 ps |
| CPU time | 32.46 seconds |
| Started | Jul 03 07:39:58 PM PDT 24 |
| Finished | Jul 03 07:40:31 PM PDT 24 |
| Peak memory | 574400 kb |
| Host | smart-ea57b5b3-0d82-4a69-a205-1e381023aaa3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=928604161 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_error_random.928604161 |
| Directory | /workspace/99.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_random.3130780262 |
| Short name | T2486 |
| Test name | |
| Test status | |
| Simulation time | 978971855 ps |
| CPU time | 35.75 seconds |
| Started | Jul 03 07:39:52 PM PDT 24 |
| Finished | Jul 03 07:40:29 PM PDT 24 |
| Peak memory | 574204 kb |
| Host | smart-c54988dc-7431-4dbe-ac30-0ecc444e5f50 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3130780262 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_random.3130780262 |
| Directory | /workspace/99.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_random_large_delays.1943434086 |
| Short name | T1987 |
| Test name | |
| Test status | |
| Simulation time | 17911007837 ps |
| CPU time | 169.63 seconds |
| Started | Jul 03 07:39:52 PM PDT 24 |
| Finished | Jul 03 07:42:44 PM PDT 24 |
| Peak memory | 574044 kb |
| Host | smart-2eba89f0-e07f-4dc7-9194-c604ba747c48 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1943434086 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_random_large_delays.1943434086 |
| Directory | /workspace/99.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_random_slow_rsp.2372166124 |
| Short name | T2673 |
| Test name | |
| Test status | |
| Simulation time | 14884102655 ps |
| CPU time | 247.98 seconds |
| Started | Jul 03 07:40:02 PM PDT 24 |
| Finished | Jul 03 07:44:11 PM PDT 24 |
| Peak memory | 574296 kb |
| Host | smart-e57dfd95-3ee8-4f78-8eef-7091ce788d0b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2372166124 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_random_slow_rsp.2372166124 |
| Directory | /workspace/99.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_random_zero_delays.2900226076 |
| Short name | T2300 |
| Test name | |
| Test status | |
| Simulation time | 243457810 ps |
| CPU time | 25.32 seconds |
| Started | Jul 03 07:39:53 PM PDT 24 |
| Finished | Jul 03 07:40:19 PM PDT 24 |
| Peak memory | 574240 kb |
| Host | smart-d8d2d7b3-8d53-4499-b87a-cdf90a148a41 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2900226076 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_random_zero_del ays.2900226076 |
| Directory | /workspace/99.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_same_source.104049574 |
| Short name | T1633 |
| Test name | |
| Test status | |
| Simulation time | 476081808 ps |
| CPU time | 35.93 seconds |
| Started | Jul 03 07:39:52 PM PDT 24 |
| Finished | Jul 03 07:40:30 PM PDT 24 |
| Peak memory | 574176 kb |
| Host | smart-458cb621-e426-4b52-a61f-77586de97b16 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104049574 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_same_source.104049574 |
| Directory | /workspace/99.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_smoke.278984754 |
| Short name | T1420 |
| Test name | |
| Test status | |
| Simulation time | 53121702 ps |
| CPU time | 6.79 seconds |
| Started | Jul 03 07:39:43 PM PDT 24 |
| Finished | Jul 03 07:39:52 PM PDT 24 |
| Peak memory | 573160 kb |
| Host | smart-1c5cc5a7-6579-445b-beda-83934fdeff72 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=278984754 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_smoke.278984754 |
| Directory | /workspace/99.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_smoke_large_delays.2350797980 |
| Short name | T2213 |
| Test name | |
| Test status | |
| Simulation time | 8105677076 ps |
| CPU time | 93.32 seconds |
| Started | Jul 03 07:40:00 PM PDT 24 |
| Finished | Jul 03 07:41:34 PM PDT 24 |
| Peak memory | 573180 kb |
| Host | smart-f0d4984a-3223-4783-8db5-adb3091c9f2b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2350797980 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_smoke_large_delays.2350797980 |
| Directory | /workspace/99.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_smoke_slow_rsp.484668625 |
| Short name | T2436 |
| Test name | |
| Test status | |
| Simulation time | 5133909345 ps |
| CPU time | 79.08 seconds |
| Started | Jul 03 07:39:51 PM PDT 24 |
| Finished | Jul 03 07:41:10 PM PDT 24 |
| Peak memory | 574224 kb |
| Host | smart-cfbb316f-2ad9-4710-86bf-072167ddc807 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=484668625 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_smoke_slow_rsp.484668625 |
| Directory | /workspace/99.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_smoke_zero_delays.1255282468 |
| Short name | T2188 |
| Test name | |
| Test status | |
| Simulation time | 52395947 ps |
| CPU time | 6.95 seconds |
| Started | Jul 03 07:39:49 PM PDT 24 |
| Finished | Jul 03 07:39:57 PM PDT 24 |
| Peak memory | 573944 kb |
| Host | smart-77785ff7-14ea-47b2-a17a-b347d50058b5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1255282468 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_smoke_zero_delay s.1255282468 |
| Directory | /workspace/99.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_stress_all.2804793969 |
| Short name | T1431 |
| Test name | |
| Test status | |
| Simulation time | 836763362 ps |
| CPU time | 76.19 seconds |
| Started | Jul 03 07:39:58 PM PDT 24 |
| Finished | Jul 03 07:41:14 PM PDT 24 |
| Peak memory | 574108 kb |
| Host | smart-ad6839ac-e5cb-40ce-b1f8-2a7513594111 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804793969 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_stress_all.2804793969 |
| Directory | /workspace/99.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_stress_all_with_error.1948472689 |
| Short name | T2716 |
| Test name | |
| Test status | |
| Simulation time | 4405671950 ps |
| CPU time | 147.39 seconds |
| Started | Jul 03 07:39:57 PM PDT 24 |
| Finished | Jul 03 07:42:25 PM PDT 24 |
| Peak memory | 574588 kb |
| Host | smart-9a6c4601-9536-4736-97c5-ae5cb547b54c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1948472689 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_stress_all_with_error.1948472689 |
| Directory | /workspace/99.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_stress_all_with_rand_reset.4233902339 |
| Short name | T2135 |
| Test name | |
| Test status | |
| Simulation time | 728654838 ps |
| CPU time | 284.2 seconds |
| Started | Jul 03 07:39:58 PM PDT 24 |
| Finished | Jul 03 07:44:44 PM PDT 24 |
| Peak memory | 574644 kb |
| Host | smart-d68c78f1-35ef-4321-800d-21ca0e7cdde3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4233902339 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_stress_all _with_rand_reset.4233902339 |
| Directory | /workspace/99.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_stress_all_with_reset_error.2014980981 |
| Short name | T2232 |
| Test name | |
| Test status | |
| Simulation time | 765785910 ps |
| CPU time | 277.82 seconds |
| Started | Jul 03 07:39:59 PM PDT 24 |
| Finished | Jul 03 07:44:38 PM PDT 24 |
| Peak memory | 574652 kb |
| Host | smart-cc8bccfe-a3cc-4412-9e1e-26b53860fa49 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014980981 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_stress_al l_with_reset_error.2014980981 |
| Directory | /workspace/99.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_unmapped_addr.1384454198 |
| Short name | T2415 |
| Test name | |
| Test status | |
| Simulation time | 1350258344 ps |
| CPU time | 53.18 seconds |
| Started | Jul 03 07:39:58 PM PDT 24 |
| Finished | Jul 03 07:40:52 PM PDT 24 |
| Peak memory | 573988 kb |
| Host | smart-e7209b2b-aa7b-4c55-a2cf-7ad4b72ac4c7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1384454198 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_unmapped_addr.1384454198 |
| Directory | /workspace/99.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/default/0.chip_jtag_mem_access.3676013587 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 13213718280 ps |
| CPU time | 1536.93 seconds |
| Started | Jul 03 07:41:50 PM PDT 24 |
| Finished | Jul 03 08:07:28 PM PDT 24 |
| Peak memory | 607972 kb |
| Host | smart-2698e6b0-78a5-4052-9834-46d159e8014c |
| User | root |
| Command | /workspace/default/simv +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3676013587 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_jtag_ mem_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_jtag_mem_access.3 676013587 |
| Directory | /workspace/0.chip_jtag_mem_access/latest |
| Test location | /workspace/coverage/default/0.chip_sival_flash_info_access.4133641921 |
| Short name | T344 |
| Test name | |
| Test status | |
| Simulation time | 2801834248 ps |
| CPU time | 329.79 seconds |
| Started | Jul 03 07:51:53 PM PDT 24 |
| Finished | Jul 03 07:57:25 PM PDT 24 |
| Peak memory | 610624 kb |
| Host | smart-16078765-8275-494c-9ffd-adb8084d83fb |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +sw_build_device=sim_dv +sw_images=flash_ctrl_info_access_lc:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s eed=4133641921 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sival_flash_info_access.4133641921 |
| Directory | /workspace/0.chip_sival_flash_info_access/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aes_enc.2192057487 |
| Short name | T418 |
| Test name | |
| Test status | |
| Simulation time | 2800526450 ps |
| CPU time | 268.32 seconds |
| Started | Jul 03 07:48:08 PM PDT 24 |
| Finished | Jul 03 07:52:38 PM PDT 24 |
| Peak memory | 610592 kb |
| Host | smart-be99c878-d662-4af4-a574-c5610abfdca6 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=22_000_000 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2192057487 -asser t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aes_enc.2192057487 |
| Directory | /workspace/0.chip_sw_aes_enc/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aes_enc_jitter_en.2279456697 |
| Short name | T1122 |
| Test name | |
| Test status | |
| Simulation time | 2345643959 ps |
| CPU time | 343.25 seconds |
| Started | Jul 03 07:51:03 PM PDT 24 |
| Finished | Jul 03 07:56:48 PM PDT 24 |
| Peak memory | 610632 kb |
| Host | smart-fcc44c3e-55ab-4c88-a6e6-d37ce09f6b9f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=26_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279 456697 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work space/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aes_enc_jitter_en.2279456697 |
| Directory | /workspace/0.chip_sw_aes_enc_jitter_en/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aes_enc_jitter_en_reduced_freq.3991017452 |
| Short name | T950 |
| Test name | |
| Test status | |
| Simulation time | 2951803842 ps |
| CPU time | 345.39 seconds |
| Started | Jul 03 07:50:29 PM PDT 24 |
| Finished | Jul 03 07:56:16 PM PDT 24 |
| Peak memory | 608948 kb |
| Host | smart-366aca04-bc1c-4538-aacd-aa820cc6f4de |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=26_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules, test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3991017452 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aes_enc_jitter_en_reduced_freq.3991017452 |
| Directory | /workspace/0.chip_sw_aes_enc_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aes_entropy.737943937 |
| Short name | T1129 |
| Test name | |
| Test status | |
| Simulation time | 3537939620 ps |
| CPU time | 300.38 seconds |
| Started | Jul 03 07:50:38 PM PDT 24 |
| Finished | Jul 03 07:55:39 PM PDT 24 |
| Peak memory | 607964 kb |
| Host | smart-fe21d1a6-0963-4069-8355-daded6e25267 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=aes_entropy_test:1:new_rules,test_rom:0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=737943937 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aes_entropy.737943937 |
| Directory | /workspace/0.chip_sw_aes_entropy/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aes_idle.1700329370 |
| Short name | T854 |
| Test name | |
| Test status | |
| Simulation time | 2251184616 ps |
| CPU time | 183.38 seconds |
| Started | Jul 03 07:49:46 PM PDT 24 |
| Finished | Jul 03 07:52:50 PM PDT 24 |
| Peak memory | 610588 kb |
| Host | smart-5924235d-7d64-4160-b0cf-974aebcf3d67 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=25_000_000 +sw_build_device=sim_dv +sw_images=aes_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1700329370 -asser t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aes_idle.1700329370 |
| Directory | /workspace/0.chip_sw_aes_idle/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aes_masking_off.2937816315 |
| Short name | T1085 |
| Test name | |
| Test status | |
| Simulation time | 3065701547 ps |
| CPU time | 327.68 seconds |
| Started | Jul 03 07:49:37 PM PDT 24 |
| Finished | Jul 03 07:55:06 PM PDT 24 |
| Peak memory | 610660 kb |
| Host | smart-7c323b72-d4f2-4293-8c3e-3e6bcdda98f7 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=aes_masking_off_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2937816315 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_aes_masking_off_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aes_masking_off.2937816315 |
| Directory | /workspace/0.chip_sw_aes_masking_off/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aes_smoketest.877925357 |
| Short name | T865 |
| Test name | |
| Test status | |
| Simulation time | 3407873380 ps |
| CPU time | 311.41 seconds |
| Started | Jul 03 07:55:12 PM PDT 24 |
| Finished | Jul 03 08:00:24 PM PDT 24 |
| Peak memory | 610628 kb |
| Host | smart-210fea39-e407-449b-8930-e78ba53bfb3a |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=877925357 -assert nopostproc +UVM_TESTNAME=chip_ base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aes_smoketest.877925357 |
| Directory | /workspace/0.chip_sw_aes_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_alert_handler_entropy.1593237783 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 3549966615 ps |
| CPU time | 380.72 seconds |
| Started | Jul 03 07:51:25 PM PDT 24 |
| Finished | Jul 03 07:57:46 PM PDT 24 |
| Peak memory | 609192 kb |
| Host | smart-c4218d91-352a-4a33-ba75-6916b0b73dcf |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler_entropy_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1593237783 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_entropy.1593237783 |
| Directory | /workspace/0.chip_sw_alert_handler_entropy/latest |
| Test location | /workspace/coverage/default/0.chip_sw_alert_handler_escalation.2472410980 |
| Short name | T1140 |
| Test name | |
| Test status | |
| Simulation time | 4865427886 ps |
| CPU time | 520.49 seconds |
| Started | Jul 03 07:49:46 PM PDT 24 |
| Finished | Jul 03 07:58:28 PM PDT 24 |
| Peak memory | 618708 kb |
| Host | smart-ced31c18-a99f-47eb-a550-f9e1358640b4 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler_escalation_test:1:new_rules,test _rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb _random_seed=2472410980 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_escalation_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_escalation.2472410980 |
| Directory | /workspace/0.chip_sw_alert_handler_escalation/latest |
| Test location | /workspace/coverage/default/0.chip_sw_alert_handler_lpg_clkoff.596701495 |
| Short name | T351 |
| Test name | |
| Test status | |
| Simulation time | 7554253016 ps |
| CPU time | 1765.04 seconds |
| Started | Jul 03 07:51:03 PM PDT 24 |
| Finished | Jul 03 08:20:29 PM PDT 24 |
| Peak memory | 609592 kb |
| Host | smart-632460a1-38ff-499f-9735-ab9173bd7530 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_lpg_clkoff_test:1:new_rules,test_r om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=596701495 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_lpg_clkoff_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_lpg_clkoff.596701495 |
| Directory | /workspace/0.chip_sw_alert_handler_lpg_clkoff/latest |
| Test location | /workspace/coverage/default/0.chip_sw_alert_handler_lpg_reset_toggle.3078834189 |
| Short name | T1256 |
| Test name | |
| Test status | |
| Simulation time | 8580007250 ps |
| CPU time | 1896.57 seconds |
| Started | Jul 03 07:47:22 PM PDT 24 |
| Finished | Jul 03 08:18:59 PM PDT 24 |
| Peak memory | 608828 kb |
| Host | smart-65fbc097-c49d-422b-88e3-4dd94c1923f4 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_lpg_reset_toggle_test:1:new_rules, test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3078834189 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_shorten_ping_wait_cycle_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_lpg_reset_togg le.3078834189 |
| Directory | /workspace/0.chip_sw_alert_handler_lpg_reset_toggle/latest |
| Test location | /workspace/coverage/default/0.chip_sw_alert_handler_ping_ok.3058772659 |
| Short name | T1146 |
| Test name | |
| Test status | |
| Simulation time | 8247163024 ps |
| CPU time | 1445.75 seconds |
| Started | Jul 03 07:51:27 PM PDT 24 |
| Finished | Jul 03 08:15:33 PM PDT 24 |
| Peak memory | 608824 kb |
| Host | smart-da036d76-954c-4860-9dc1-1d32fe0db12e |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=24000000 +sw_build_device=sim_dv +sw_images=alert_handler_ping_ok_test:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s eed=3058772659 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_ping_ok.3058772659 |
| Directory | /workspace/0.chip_sw_alert_handler_ping_ok/latest |
| Test location | /workspace/coverage/default/0.chip_sw_alert_handler_ping_timeout.1481271136 |
| Short name | T263 |
| Test name | |
| Test status | |
| Simulation time | 6268653184 ps |
| CPU time | 653.52 seconds |
| Started | Jul 03 07:50:49 PM PDT 24 |
| Finished | Jul 03 08:01:43 PM PDT 24 |
| Peak memory | 608408 kb |
| Host | smart-735e78e8-41f0-4d09-84a5-20faa9acf333 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=24000000 +sw_build_device=sim_dv +sw_images=alert_handler_ping_timeout_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1481271136 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_ping_timeout.1481271136 |
| Directory | /workspace/0.chip_sw_alert_handler_ping_timeout/latest |
| Test location | /workspace/coverage/default/0.chip_sw_alert_handler_reverse_ping_in_deep_sleep.2428313943 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 255370804394 ps |
| CPU time | 13101.8 seconds |
| Started | Jul 03 07:49:38 PM PDT 24 |
| Finished | Jul 03 11:28:02 PM PDT 24 |
| Peak memory | 610192 kb |
| Host | smart-23cc642e-79c0-451e-b4e4-dde527ec7a85 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=300_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_reverse_ping_in_deep_sleep_test:1:n ew_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2428313943 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_reverse_ping_in_deep_sleep.2428313943 |
| Directory | /workspace/0.chip_sw_alert_handler_reverse_ping_in_deep_sleep/latest |
| Test location | /workspace/coverage/default/0.chip_sw_alert_test.3375083392 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 3416562000 ps |
| CPU time | 252.21 seconds |
| Started | Jul 03 07:48:29 PM PDT 24 |
| Finished | Jul 03 07:52:42 PM PDT 24 |
| Peak memory | 610648 kb |
| Host | smart-b045126b-ed23-4986-9152-728ffc3707d9 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=alert_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3375083392 -assert nopostproc +UVM_TESTNAME=chip_ba se_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 0.chip_sw_alert_test.3375083392 |
| Directory | /workspace/0.chip_sw_alert_test/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aon_timer_irq.3929710333 |
| Short name | T343 |
| Test name | |
| Test status | |
| Simulation time | 4004520778 ps |
| CPU time | 340.96 seconds |
| Started | Jul 03 07:49:19 PM PDT 24 |
| Finished | Jul 03 07:55:01 PM PDT 24 |
| Peak memory | 607948 kb |
| Host | smart-4541760a-cef6-40d7-9645-42ca67018279 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_irq_test:1:new_rules,test_rom:0 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3929710333 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aon_timer_irq.3929710333 |
| Directory | /workspace/0.chip_sw_aon_timer_irq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aon_timer_sleep_wdog_sleep_pause.2328886123 |
| Short name | T1014 |
| Test name | |
| Test status | |
| Simulation time | 7908209736 ps |
| CPU time | 443.4 seconds |
| Started | Jul 03 07:49:14 PM PDT 24 |
| Finished | Jul 03 07:56:38 PM PDT 24 |
| Peak memory | 608556 kb |
| Host | smart-da50b04b-cf21-4b42-b94b-f3abbcf9334f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_sleep_wdog_sleep_pause_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2328886123 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aon_timer_sleep_wdog_sleep_pause.2328886123 |
| Directory | /workspace/0.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aon_timer_smoketest.136594383 |
| Short name | T1200 |
| Test name | |
| Test status | |
| Simulation time | 3032304628 ps |
| CPU time | 304.5 seconds |
| Started | Jul 03 07:57:16 PM PDT 24 |
| Finished | Jul 03 08:02:21 PM PDT 24 |
| Peak memory | 607704 kb |
| Host | smart-994455ef-a453-451e-9f19-9b9fab1bed0f |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=aon_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=136594383 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 0.chip_sw_aon_timer_smoketest.136594383 |
| Directory | /workspace/0.chip_sw_aon_timer_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aon_timer_wdog_bite_reset.3845650305 |
| Short name | T1251 |
| Test name | |
| Test status | |
| Simulation time | 9170609144 ps |
| CPU time | 836.11 seconds |
| Started | Jul 03 07:49:18 PM PDT 24 |
| Finished | Jul 03 08:03:14 PM PDT 24 |
| Peak memory | 610640 kb |
| Host | smart-853a0c59-838e-4c11-b2b7-d3a8c82b36eb |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_wdog_bite_reset_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3845650305 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aon_timer_wdog_bite_reset.3845650305 |
| Directory | /workspace/0.chip_sw_aon_timer_wdog_bite_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aon_timer_wdog_lc_escalate.301274102 |
| Short name | T949 |
| Test name | |
| Test status | |
| Simulation time | 4060245528 ps |
| CPU time | 503.72 seconds |
| Started | Jul 03 07:50:35 PM PDT 24 |
| Finished | Jul 03 07:58:59 PM PDT 24 |
| Peak memory | 608396 kb |
| Host | smart-840a8e30-2b63-4894-b9ff-19c5cebe935e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_wdog_lc_escalate_test:1:new_rules,test_rom:0 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed =301274102 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aon_timer_wdog_lc_escalate.301274102 |
| Directory | /workspace/0.chip_sw_aon_timer_wdog_lc_escalate/latest |
| Test location | /workspace/coverage/default/0.chip_sw_ast_clk_outputs.981648024 |
| Short name | T1131 |
| Test name | |
| Test status | |
| Simulation time | 7615511318 ps |
| CPU time | 1007.56 seconds |
| Started | Jul 03 07:52:10 PM PDT 24 |
| Finished | Jul 03 08:08:58 PM PDT 24 |
| Peak memory | 616400 kb |
| Host | smart-7630c334-027b-4cd9-9d80-51b3a67d8a9f |
| User | root |
| Command | /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=ast_clk_outs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=981648024 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ast_clk_outputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_ast_clk_outputs.981648024 |
| Directory | /workspace/0.chip_sw_ast_clk_outputs/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_lc.1196859303 |
| Short name | T1260 |
| Test name | |
| Test status | |
| Simulation time | 12515305559 ps |
| CPU time | 658.39 seconds |
| Started | Jul 03 07:49:03 PM PDT 24 |
| Finished | Jul 03 08:00:02 PM PDT 24 |
| Peak memory | 622808 kb |
| Host | smart-1300b9cc-6278-4273-a436-00920e2da233 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +sw_images=clkmgr_external_clk_src_for_lc_test:1:new_r ules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim .tcl +ntb_random_seed=1196859303 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_clkmgr_external_clk_src_for_lc.1196859303 |
| Directory | /workspace/0.chip_sw_clkmgr_external_clk_src_for_lc/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.3678923472 |
| Short name | T1243 |
| Test name | |
| Test status | |
| Simulation time | 4157220840 ps |
| CPU time | 721.93 seconds |
| Started | Jul 03 07:50:41 PM PDT 24 |
| Finished | Jul 03 08:02:44 PM PDT 24 |
| Peak memory | 613228 kb |
| Host | smart-3790de63-1885-4a71-a863-43094e94753d |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStDev +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3678923472 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_c lkmgr_external_clk_src_for_sw_fast_dev.3678923472 |
| Directory | /workspace/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.556682652 |
| Short name | T1037 |
| Test name | |
| Test status | |
| Simulation time | 4638675952 ps |
| CPU time | 787.23 seconds |
| Started | Jul 03 07:51:33 PM PDT 24 |
| Finished | Jul 03 08:04:42 PM PDT 24 |
| Peak memory | 613184 kb |
| Host | smart-ce8c4889-e6e3-48f2-b62c-455b1c026e82 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=556682652 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_cl kmgr_external_clk_src_for_sw_fast_rma.556682652 |
| Directory | /workspace/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.3906088074 |
| Short name | T1016 |
| Test name | |
| Test status | |
| Simulation time | 5223965850 ps |
| CPU time | 731.52 seconds |
| Started | Jul 03 07:52:53 PM PDT 24 |
| Finished | Jul 03 08:05:06 PM PDT 24 |
| Peak memory | 613144 kb |
| Host | smart-64124604-0ebd-451f-bd49-920e997a8075 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStDev +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3906088074 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_c lkmgr_external_clk_src_for_sw_slow_dev.3906088074 |
| Directory | /workspace/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.2358620417 |
| Short name | T1080 |
| Test name | |
| Test status | |
| Simulation time | 4964307568 ps |
| CPU time | 564.74 seconds |
| Started | Jul 03 07:48:42 PM PDT 24 |
| Finished | Jul 03 07:58:07 PM PDT 24 |
| Peak memory | 613216 kb |
| Host | smart-566e7065-d1c1-4b79-9769-346e164260e1 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2358620417 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_c lkmgr_external_clk_src_for_sw_slow_rma.2358620417 |
| Directory | /workspace/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.1638404962 |
| Short name | T1252 |
| Test name | |
| Test status | |
| Simulation time | 4262054576 ps |
| CPU time | 784.75 seconds |
| Started | Jul 03 07:49:24 PM PDT 24 |
| Finished | Jul 03 08:02:30 PM PDT 24 |
| Peak memory | 610832 kb |
| Host | smart-a3e2b620-81f9-4add-9f6c-6ce424f61300 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStTestUnlocked0 +sw_build_device=sim_ dv +sw_images=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1638404962 -assert nopostproc +UVM_TESTNAME=chip_base_test +UV M_TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0 .chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.1638404962 |
| Directory | /workspace/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_jitter.1718701365 |
| Short name | T954 |
| Test name | |
| Test status | |
| Simulation time | 2686119138 ps |
| CPU time | 213.08 seconds |
| Started | Jul 03 07:50:15 PM PDT 24 |
| Finished | Jul 03 07:53:49 PM PDT 24 |
| Peak memory | 607664 kb |
| Host | smart-37c9b98d-a4ef-4627-b889-6ab7e14017b6 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_jitter_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1718701365 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 0.chip_sw_clkmgr_jitter.1718701365 |
| Directory | /workspace/0.chip_sw_clkmgr_jitter/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_jitter_frequency.2584696019 |
| Short name | T1253 |
| Test name | |
| Test status | |
| Simulation time | 3332510408 ps |
| CPU time | 396.92 seconds |
| Started | Jul 03 07:50:59 PM PDT 24 |
| Finished | Jul 03 07:57:38 PM PDT 24 |
| Peak memory | 607668 kb |
| Host | smart-01098dc0-d2e3-4608-8cd5-3db3576a05f7 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_jitter_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2584696019 -assert nopostproc +UV M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c m_log /dev/null -cm_name 0.chip_sw_clkmgr_jitter_frequency.2584696019 |
| Directory | /workspace/0.chip_sw_clkmgr_jitter_frequency/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_jitter_reduced_freq.2278360463 |
| Short name | T1298 |
| Test name | |
| Test status | |
| Simulation time | 3254225924 ps |
| CPU time | 246.35 seconds |
| Started | Jul 03 07:51:52 PM PDT 24 |
| Finished | Jul 03 07:56:01 PM PDT 24 |
| Peak memory | 610588 kb |
| Host | smart-4ca9adba-5718-40e5-979d-216cb5a7772b |
| User | root |
| Command | /workspace/default/simv +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=clkmgr_jitter_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2278360463 -assert nop ostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 0.chip_sw_clkmgr_jitter_reduced_freq.2278360463 |
| Directory | /workspace/0.chip_sw_clkmgr_jitter_reduced_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_off_aes_trans.3666946385 |
| Short name | T1209 |
| Test name | |
| Test status | |
| Simulation time | 4787795112 ps |
| CPU time | 442.84 seconds |
| Started | Jul 03 07:50:58 PM PDT 24 |
| Finished | Jul 03 07:58:21 PM PDT 24 |
| Peak memory | 609280 kb |
| Host | smart-946f5c67-0af0-43ea-b1f7-2f11769e14e0 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_aes_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3666946385 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 0.chip_sw_clkmgr_off_aes_trans.3666946385 |
| Directory | /workspace/0.chip_sw_clkmgr_off_aes_trans/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_off_hmac_trans.4020853798 |
| Short name | T988 |
| Test name | |
| Test status | |
| Simulation time | 5279496720 ps |
| CPU time | 477.12 seconds |
| Started | Jul 03 07:49:29 PM PDT 24 |
| Finished | Jul 03 07:57:26 PM PDT 24 |
| Peak memory | 610672 kb |
| Host | smart-7c7bf0b4-a494-4ec8-ac60-dc2c483fe8e0 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_hmac_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4020853798 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 0.chip_sw_clkmgr_off_hmac_trans.4020853798 |
| Directory | /workspace/0.chip_sw_clkmgr_off_hmac_trans/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_off_kmac_trans.2105046826 |
| Short name | T845 |
| Test name | |
| Test status | |
| Simulation time | 4380223026 ps |
| CPU time | 385.55 seconds |
| Started | Jul 03 07:51:53 PM PDT 24 |
| Finished | Jul 03 07:58:20 PM PDT 24 |
| Peak memory | 609324 kb |
| Host | smart-1040699f-e0ba-4c95-9d94-40da68e8f51b |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_kmac_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2105046826 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 0.chip_sw_clkmgr_off_kmac_trans.2105046826 |
| Directory | /workspace/0.chip_sw_clkmgr_off_kmac_trans/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_off_otbn_trans.2886662710 |
| Short name | T958 |
| Test name | |
| Test status | |
| Simulation time | 5243549376 ps |
| CPU time | 555.33 seconds |
| Started | Jul 03 07:50:32 PM PDT 24 |
| Finished | Jul 03 07:59:48 PM PDT 24 |
| Peak memory | 610664 kb |
| Host | smart-5a2e09d3-ca42-45d5-bab9-de9b723f8c18 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_otbn_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2886662710 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 0.chip_sw_clkmgr_off_otbn_trans.2886662710 |
| Directory | /workspace/0.chip_sw_clkmgr_off_otbn_trans/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_off_peri.1463382313 |
| Short name | T374 |
| Test name | |
| Test status | |
| Simulation time | 10361163758 ps |
| CPU time | 1391.67 seconds |
| Started | Jul 03 07:53:30 PM PDT 24 |
| Finished | Jul 03 08:16:43 PM PDT 24 |
| Peak memory | 610640 kb |
| Host | smart-f8c5356e-2909-4537-adf3-5c7d5829d458 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=30_000_000 +sw_build_device=sim_dv +sw_images=clkmgr_off_peri_test:1:new_rules,test_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1463382313 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/ coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_clkmgr_off_peri.1463382313 |
| Directory | /workspace/0.chip_sw_clkmgr_off_peri/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_reset_frequency.1148814913 |
| Short name | T1214 |
| Test name | |
| Test status | |
| Simulation time | 3304843818 ps |
| CPU time | 475.33 seconds |
| Started | Jul 03 07:50:41 PM PDT 24 |
| Finished | Jul 03 07:58:37 PM PDT 24 |
| Peak memory | 610628 kb |
| Host | smart-c701c4cd-a466-467b-bb62-61aa056c5daf |
| User | root |
| Command | /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=clkmgr_reset_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1148814913 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_clkmgr_reset_frequency.1148814913 |
| Directory | /workspace/0.chip_sw_clkmgr_reset_frequency/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_sleep_frequency.2392790287 |
| Short name | T1250 |
| Test name | |
| Test status | |
| Simulation time | 4366477832 ps |
| CPU time | 566.73 seconds |
| Started | Jul 03 07:48:49 PM PDT 24 |
| Finished | Jul 03 07:58:16 PM PDT 24 |
| Peak memory | 610708 kb |
| Host | smart-2d2faef5-d676-4e88-a50e-7548e0c69ef1 |
| User | root |
| Command | /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=clkmgr_sleep_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2392790287 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_clkmgr_sleep_frequency.2392790287 |
| Directory | /workspace/0.chip_sw_clkmgr_sleep_frequency/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_smoketest.3137073877 |
| Short name | T929 |
| Test name | |
| Test status | |
| Simulation time | 3439283182 ps |
| CPU time | 252.89 seconds |
| Started | Jul 03 07:55:17 PM PDT 24 |
| Finished | Jul 03 07:59:31 PM PDT 24 |
| Peak memory | 610644 kb |
| Host | smart-c9b859eb-3933-45ff-848a-5e914343a3e9 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3137073877 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 0.chip_sw_clkmgr_smoketest.3137073877 |
| Directory | /workspace/0.chip_sw_clkmgr_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_coremark.1467525313 |
| Short name | T873 |
| Test name | |
| Test status | |
| Simulation time | 70966485240 ps |
| CPU time | 13443 seconds |
| Started | Jul 03 07:51:50 PM PDT 24 |
| Finished | Jul 03 11:35:54 PM PDT 24 |
| Peak memory | 610628 kb |
| Host | smart-485084b9-4c85-4317-9b3c-89818b07fb84 |
| User | root |
| Command | /workspace/default/simv +en_uart_logger=1 +sw_test_timeout_ns=200_000_000 +sw_build_device=sim_dv +sw_images=coremark_test:1:new_rules,test_rom:0 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=1467525313 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_coremark.1467525313 |
| Directory | /workspace/0.chip_sw_coremark/latest |
| Test location | /workspace/coverage/default/0.chip_sw_csrng_edn_concurrency.2191309832 |
| Short name | T612 |
| Test name | |
| Test status | |
| Simulation time | 28063061120 ps |
| CPU time | 6465.1 seconds |
| Started | Jul 03 07:49:50 PM PDT 24 |
| Finished | Jul 03 09:37:37 PM PDT 24 |
| Peak memory | 609800 kb |
| Host | smart-0742c03b-9a2f-4155-b366-5eebd8d9d9f0 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +accelerate_cold_power_up_time=3 +accelerate_r egulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191309832 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 0.chip_sw_csrng_edn_concurrency.2191309832 |
| Directory | /workspace/0.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspace/coverage/default/0.chip_sw_csrng_edn_concurrency_reduced_freq.3658973081 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 79745242388 ps |
| CPU time | 11300.7 seconds |
| Started | Jul 03 07:50:20 PM PDT 24 |
| Finished | Jul 03 10:58:43 PM PDT 24 |
| Peak memory | 609764 kb |
| Host | smart-b5ef2463-5a4d-4e70-b3b0-5bf1c38617fc |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=360_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +cal_sys_clk_70mhz=1 +en_jitter=1 +accelerate_ cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=3658973081 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_csrng_edn_concurrency_reduced_freq.3658973081 |
| Directory | /workspace/0.chip_sw_csrng_edn_concurrency_reduced_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_csrng_fuse_en_sw_app_read_test.220810365 |
| Short name | T204 |
| Test name | |
| Test status | |
| Simulation time | 4858363900 ps |
| CPU time | 616.79 seconds |
| Started | Jul 03 07:53:56 PM PDT 24 |
| Finished | Jul 03 08:04:14 PM PDT 24 |
| Peak memory | 610624 kb |
| Host | smart-ca73be3f-e911-46b7-970a-918125f0e44a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=csrng_fuse_en_sw_app_read:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22081 0365 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_entropy_src_fuse_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_csrng_fuse_en_sw_app_read_test.220810365 |
| Directory | /workspace/0.chip_sw_csrng_fuse_en_sw_app_read_test/latest |
| Test location | /workspace/coverage/default/0.chip_sw_csrng_kat_test.2955538121 |
| Short name | T879 |
| Test name | |
| Test status | |
| Simulation time | 2815242696 ps |
| CPU time | 233.74 seconds |
| Started | Jul 03 07:48:40 PM PDT 24 |
| Finished | Jul 03 07:52:34 PM PDT 24 |
| Peak memory | 610540 kb |
| Host | smart-3aafd04c-190d-4653-b660-3c82bc728fdb |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=csrng_kat_test:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2955538121 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_csrng_kat_test.2955538121 |
| Directory | /workspace/0.chip_sw_csrng_kat_test/latest |
| Test location | /workspace/coverage/default/0.chip_sw_csrng_lc_hw_debug_en_test.260536184 |
| Short name | T1211 |
| Test name | |
| Test status | |
| Simulation time | 4770940668 ps |
| CPU time | 661.4 seconds |
| Started | Jul 03 07:48:14 PM PDT 24 |
| Finished | Jul 03 07:59:16 PM PDT 24 |
| Peak memory | 611028 kb |
| Host | smart-48204b52-e7be-4a37-95cc-fb1d598e6afd |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +rng_srate_value_min=15 +use_otp_image=OtpTypeLcStTestUnlocked0 +sw_build_device=sim_dv +sw_ima ges=csrng_lc_hw_debug_en_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=260536184 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_csrng_l c_hw_debug_en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_csrn g_lc_hw_debug_en_test.260536184 |
| Directory | /workspace/0.chip_sw_csrng_lc_hw_debug_en_test/latest |
| Test location | /workspace/coverage/default/0.chip_sw_csrng_smoketest.2422258481 |
| Short name | T837 |
| Test name | |
| Test status | |
| Simulation time | 2578750620 ps |
| CPU time | 207.33 seconds |
| Started | Jul 03 07:55:26 PM PDT 24 |
| Finished | Jul 03 07:58:54 PM PDT 24 |
| Peak memory | 610608 kb |
| Host | smart-34b9e3f5-67f2-4eaf-b9d3-9fab17ac665a |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=csrng_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2422258481 -assert nopostproc +UVM_TESTNAME=ch ip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 0.chip_sw_csrng_smoketest.2422258481 |
| Directory | /workspace/0.chip_sw_csrng_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_edn_auto_mode.3587803513 |
| Short name | T1163 |
| Test name | |
| Test status | |
| Simulation time | 5891093370 ps |
| CPU time | 1605.55 seconds |
| Started | Jul 03 07:48:42 PM PDT 24 |
| Finished | Jul 03 08:15:29 PM PDT 24 |
| Peak memory | 610780 kb |
| Host | smart-32b56c9d-14cd-4816-a409-563e6f7ac702 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_ build_device=sim_dv +sw_images=edn_auto_mode:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3587803513 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_edn_ auto_mode.3587803513 |
| Directory | /workspace/0.chip_sw_edn_auto_mode/latest |
| Test location | /workspace/coverage/default/0.chip_sw_edn_entropy_reqs_jitter.472075 |
| Short name | T1157 |
| Test name | |
| Test status | |
| Simulation time | 4897488256 ps |
| CPU time | 846.06 seconds |
| Started | Jul 03 07:51:10 PM PDT 24 |
| Finished | Jul 03 08:05:17 PM PDT 24 |
| Peak memory | 610800 kb |
| Host | smart-5c45d125-5a47-4848-9661-7298ad158eb3 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15000000 +rng_srate_value_min=15 +rng_srate_value_max=30 +en_jitter=1 +sw_build_device=sim_dv +sw_images=e ntropy_src_edn_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=472075 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_edn_entropy_reqs_jitter.472075 |
| Directory | /workspace/0.chip_sw_edn_entropy_reqs_jitter/latest |
| Test location | /workspace/coverage/default/0.chip_sw_edn_kat.1535391861 |
| Short name | T1069 |
| Test name | |
| Test status | |
| Simulation time | 2900229448 ps |
| CPU time | 564.96 seconds |
| Started | Jul 03 07:49:51 PM PDT 24 |
| Finished | Jul 03 07:59:17 PM PDT 24 |
| Peak memory | 614776 kb |
| Host | smart-4ee14b1f-f2cc-4d72-83d3-4447fae8ea19 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +disable_assert_edn_output_diff_from_prev=1 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=edn_kat:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1535391861 -assert nopostproc +UVM _TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 0.chip_sw_edn_kat.1535391861 |
| Directory | /workspace/0.chip_sw_edn_kat/latest |
| Test location | /workspace/coverage/default/0.chip_sw_edn_sw_mode.2347926787 |
| Short name | T1207 |
| Test name | |
| Test status | |
| Simulation time | 5455204088 ps |
| CPU time | 1263.19 seconds |
| Started | Jul 03 07:54:00 PM PDT 24 |
| Finished | Jul 03 08:15:04 PM PDT 24 |
| Peak memory | 610592 kb |
| Host | smart-a9b7779c-2c68-4d7f-85bf-34acf7592da6 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=edn_sw_mode:1:new_rules,test_rom:0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2347926787 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/ default.vdb -cm_log /dev/null -cm_name 0.chip_sw_edn_sw_mode.2347926787 |
| Directory | /workspace/0.chip_sw_edn_sw_mode/latest |
| Test location | /workspace/coverage/default/0.chip_sw_entropy_src_ast_rng_req.1122372426 |
| Short name | T1213 |
| Test name | |
| Test status | |
| Simulation time | 2404756772 ps |
| CPU time | 198.94 seconds |
| Started | Jul 03 07:53:55 PM PDT 24 |
| Finished | Jul 03 07:57:15 PM PDT 24 |
| Peak memory | 608028 kb |
| Host | smart-6583bec5-2c22-4436-9266-de5755d99694 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=entropy_src_ast_rng_req_test:1:new_rules,test_rom:0 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11 22372426 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_entropy_src_ast_rng_req.1122372426 |
| Directory | /workspace/0.chip_sw_entropy_src_ast_rng_req/latest |
| Test location | /workspace/coverage/default/0.chip_sw_entropy_src_csrng.2989224809 |
| Short name | T314 |
| Test name | |
| Test status | |
| Simulation time | 5462248240 ps |
| CPU time | 1298.39 seconds |
| Started | Jul 03 07:49:01 PM PDT 24 |
| Finished | Jul 03 08:10:40 PM PDT 24 |
| Peak memory | 609416 kb |
| Host | smart-20362adf-6d52-4886-88ea-8d1cc5de73d3 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_ csrng_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2989224809 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_entropy_src_csrng.2989224809 |
| Directory | /workspace/0.chip_sw_entropy_src_csrng/latest |
| Test location | /workspace/coverage/default/0.chip_sw_entropy_src_kat_test.156784830 |
| Short name | T871 |
| Test name | |
| Test status | |
| Simulation time | 2813663060 ps |
| CPU time | 277.88 seconds |
| Started | Jul 03 07:49:19 PM PDT 24 |
| Finished | Jul 03 07:53:58 PM PDT 24 |
| Peak memory | 607932 kb |
| Host | smart-e5a60219-9386-47c6-b229-32d2f1b4bbc2 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=entropy_src_kat_test:1:new_rules,test_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=156784830 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_entropy_src_kat_test.156784830 |
| Directory | /workspace/0.chip_sw_entropy_src_kat_test/latest |
| Test location | /workspace/coverage/default/0.chip_sw_entropy_src_smoketest.2824137442 |
| Short name | T923 |
| Test name | |
| Test status | |
| Simulation time | 3727380200 ps |
| CPU time | 382.72 seconds |
| Started | Jul 03 07:53:31 PM PDT 24 |
| Finished | Jul 03 07:59:54 PM PDT 24 |
| Peak memory | 608688 kb |
| Host | smart-f6b40d94-d060-46b2-bd8e-bba752626ff3 |
| User | root |
| Command | /workspace/default/simv +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_smoketest:1:new_rules,test_rom: 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=2824137442 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_entropy_src_smoketest.2824137442 |
| Directory | /workspace/0.chip_sw_entropy_src_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_example_concurrency.1074012513 |
| Short name | T1036 |
| Test name | |
| Test status | |
| Simulation time | 3027280496 ps |
| CPU time | 284.49 seconds |
| Started | Jul 03 07:48:39 PM PDT 24 |
| Finished | Jul 03 07:53:25 PM PDT 24 |
| Peak memory | 610652 kb |
| Host | smart-5996520d-f31e-46d4-92bd-15245ca391fb |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1074012513 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo g /dev/null -cm_name 0.chip_sw_example_concurrency.1074012513 |
| Directory | /workspace/0.chip_sw_example_concurrency/latest |
| Test location | /workspace/coverage/default/0.chip_sw_example_flash.2001667452 |
| Short name | T823 |
| Test name | |
| Test status | |
| Simulation time | 3107670808 ps |
| CPU time | 205.28 seconds |
| Started | Jul 03 07:46:19 PM PDT 24 |
| Finished | Jul 03 07:49:45 PM PDT 24 |
| Peak memory | 608640 kb |
| Host | smart-0bb8bc9b-36f8-4106-bbde-8369fb35cb4d |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test_from_flash:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2001667452 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_example_flash.2001667452 |
| Directory | /workspace/0.chip_sw_example_flash/latest |
| Test location | /workspace/coverage/default/0.chip_sw_example_manufacturer.1610068045 |
| Short name | T1040 |
| Test name | |
| Test status | |
| Simulation time | 2943727220 ps |
| CPU time | 277.57 seconds |
| Started | Jul 03 07:51:19 PM PDT 24 |
| Finished | Jul 03 07:55:58 PM PDT 24 |
| Peak memory | 610644 kb |
| Host | smart-d9cca526-1dd9-4ca7-b9c6-3bedf744d496 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1610068045 -assert nopostproc +UVM_TESTNAME=chip_ base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_example_manufacturer.1610068045 |
| Directory | /workspace/0.chip_sw_example_manufacturer/latest |
| Test location | /workspace/coverage/default/0.chip_sw_example_rom.1829387382 |
| Short name | T1289 |
| Test name | |
| Test status | |
| Simulation time | 2533755120 ps |
| CPU time | 137.22 seconds |
| Started | Jul 03 07:46:20 PM PDT 24 |
| Finished | Jul 03 07:48:39 PM PDT 24 |
| Peak memory | 610248 kb |
| Host | smart-9c46492f-88b9-4baa-ae0e-d949b7095696 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1829387382 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_example_rom.1829387382 |
| Directory | /workspace/0.chip_sw_example_rom/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_crash_alert.719055814 |
| Short name | T335 |
| Test name | |
| Test status | |
| Simulation time | 5608796394 ps |
| CPU time | 802.31 seconds |
| Started | Jul 03 07:51:02 PM PDT 24 |
| Finished | Jul 03 08:04:25 PM PDT 24 |
| Peak memory | 610824 kb |
| Host | smart-9b6deee6-76fa-49fa-beb9-9e4ebd13d635 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=8_000_000 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1: new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tool s/sim.tcl +ntb_random_seed=719055814 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_host_gnt_err_inj_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_crash_alert.719055814 |
| Directory | /workspace/0.chip_sw_flash_crash_alert/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_ctrl_access.3039489961 |
| Short name | T300 |
| Test name | |
| Test status | |
| Simulation time | 5162403620 ps |
| CPU time | 1119.91 seconds |
| Started | Jul 03 07:48:15 PM PDT 24 |
| Finished | Jul 03 08:06:56 PM PDT 24 |
| Peak memory | 610928 kb |
| Host | smart-e3d54b93-9e84-4bb6-901c-2496bafe4bbf |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3039489961 -assert nopostproc +UVM_TESTNAME=ch ip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 0.chip_sw_flash_ctrl_access.3039489961 |
| Directory | /workspace/0.chip_sw_flash_ctrl_access/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en.1780100777 |
| Short name | T955 |
| Test name | |
| Test status | |
| Simulation time | 5963011082 ps |
| CPU time | 1336.39 seconds |
| Started | Jul 03 07:48:00 PM PDT 24 |
| Finished | Jul 03 08:10:17 PM PDT 24 |
| Peak memory | 610592 kb |
| Host | smart-d80a565f-a746-4478-aaf8-b0e990778b41 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1780100777 -assert nopostproc +UV M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c m_log /dev/null -cm_name 0.chip_sw_flash_ctrl_access_jitter_en.1780100777 |
| Directory | /workspace/0.chip_sw_flash_ctrl_access_jitter_en/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.3405241814 |
| Short name | T359 |
| Test name | |
| Test status | |
| Simulation time | 7172220371 ps |
| CPU time | 1138.58 seconds |
| Started | Jul 03 07:56:44 PM PDT 24 |
| Finished | Jul 03 08:15:44 PM PDT 24 |
| Peak memory | 610624 kb |
| Host | smart-5e1c47ef-c568-4048-8d04-53f3d6b82f74 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3405241814 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.3405241814 |
| Directory | /workspace/0.chip_sw_flash_ctrl_access_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_ctrl_clock_freqs.114224014 |
| Short name | T900 |
| Test name | |
| Test status | |
| Simulation time | 5585298312 ps |
| CPU time | 1213.1 seconds |
| Started | Jul 03 07:48:04 PM PDT 24 |
| Finished | Jul 03 08:08:17 PM PDT 24 |
| Peak memory | 610632 kb |
| Host | smart-0c495982-24cf-4449-ab02-2343630ada77 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_clock_freqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114224014 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 0.chip_sw_flash_ctrl_clock_freqs.114224014 |
| Directory | /workspace/0.chip_sw_flash_ctrl_clock_freqs/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_ctrl_idle_low_power.2208033917 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 3313779080 ps |
| CPU time | 323.22 seconds |
| Started | Jul 03 07:49:27 PM PDT 24 |
| Finished | Jul 03 07:54:51 PM PDT 24 |
| Peak memory | 610656 kb |
| Host | smart-fe19bb20-6759-4da5-83c4-0eb9e97ef08a |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_idle_low_power_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2208033917 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_idle_low_power.2208033917 |
| Directory | /workspace/0.chip_sw_flash_ctrl_idle_low_power/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_ctrl_lc_rw_en.1289993022 |
| Short name | T238 |
| Test name | |
| Test status | |
| Simulation time | 4185281902 ps |
| CPU time | 397.33 seconds |
| Started | Jul 03 07:48:11 PM PDT 24 |
| Finished | Jul 03 07:54:49 PM PDT 24 |
| Peak memory | 609432 kb |
| Host | smart-074200eb-c660-45d3-9a91-5434ac57799e |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_lc_rw_en_test:1:new_rules,test_rom:0 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12 89993022 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_ctrl_lc_rw_en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_lc_rw_en.1289993022 |
| Directory | /workspace/0.chip_sw_flash_ctrl_lc_rw_en/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_ctrl_mem_protection.1239486638 |
| Short name | T1287 |
| Test name | |
| Test status | |
| Simulation time | 6129313672 ps |
| CPU time | 1244.57 seconds |
| Started | Jul 03 07:53:44 PM PDT 24 |
| Finished | Jul 03 08:14:29 PM PDT 24 |
| Peak memory | 610608 kb |
| Host | smart-b9958ccd-9c01-49ba-a39b-339444b1fa05 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_mem_protection_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1239486638 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_mem_protection.1239486638 |
| Directory | /workspace/0.chip_sw_flash_ctrl_mem_protection/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_ctrl_ops.3923337098 |
| Short name | T327 |
| Test name | |
| Test status | |
| Simulation time | 4431265860 ps |
| CPU time | 581.91 seconds |
| Started | Jul 03 07:47:54 PM PDT 24 |
| Finished | Jul 03 07:57:36 PM PDT 24 |
| Peak memory | 610556 kb |
| Host | smart-5f2f3c89-195e-4098-b989-87dd76a93099 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3923337098 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_ops.3923337098 |
| Directory | /workspace/0.chip_sw_flash_ctrl_ops/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en.915698995 |
| Short name | T346 |
| Test name | |
| Test status | |
| Simulation time | 4247850609 ps |
| CPU time | 596.64 seconds |
| Started | Jul 03 07:47:01 PM PDT 24 |
| Finished | Jul 03 07:56:58 PM PDT 24 |
| Peak memory | 610628 kb |
| Host | smart-5ab6ecde-b60c-4aa1-8a0b-fd8ae4186434 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_rules,test_rom:0 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=915698995 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_ops_jitter_en.915698995 |
| Directory | /workspace/0.chip_sw_flash_ctrl_ops_jitter_en/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.136263484 |
| Short name | T328 |
| Test name | |
| Test status | |
| Simulation time | 4987920225 ps |
| CPU time | 632.9 seconds |
| Started | Jul 03 07:49:45 PM PDT 24 |
| Finished | Jul 03 08:00:19 PM PDT 24 |
| Peak memory | 610576 kb |
| Host | smart-f3f28d41-7deb-4de3-8402-7ccbb28f756d |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_ rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si m.tcl +ntb_random_seed=136263484 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.136263484 |
| Directory | /workspace/0.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_ctrl_write_clear.2854589975 |
| Short name | T991 |
| Test name | |
| Test status | |
| Simulation time | 2734037602 ps |
| CPU time | 327.53 seconds |
| Started | Jul 03 07:50:07 PM PDT 24 |
| Finished | Jul 03 07:55:36 PM PDT 24 |
| Peak memory | 610604 kb |
| Host | smart-ce585c4c-b80e-49e6-bea5-b73dcb63dd0a |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=8_000_000 +sw_build_device=sim_dv +sw_images=flash_ctrl_write_clear_test:1:new_rules,test_rom:0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2854589 975 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_write_clear.2854589975 |
| Directory | /workspace/0.chip_sw_flash_ctrl_write_clear/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_init.3771867086 |
| Short name | T229 |
| Test name | |
| Test status | |
| Simulation time | 23682463208 ps |
| CPU time | 2271.85 seconds |
| Started | Jul 03 07:46:50 PM PDT 24 |
| Finished | Jul 03 08:24:44 PM PDT 24 |
| Peak memory | 615284 kb |
| Host | smart-471844fd-9d8e-4aea-99a2-5f6e10cf930f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=25_000_000 +sw_build_device=sim_dv +sw_images=flash_init_test:0:test_in_rom:new_rules +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3771867086 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_init.3771867086 |
| Directory | /workspace/0.chip_sw_flash_init/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_init_reduced_freq.3789356740 |
| Short name | T235 |
| Test name | |
| Test status | |
| Simulation time | 25394110997 ps |
| CPU time | 2278.83 seconds |
| Started | Jul 03 07:49:27 PM PDT 24 |
| Finished | Jul 03 08:27:27 PM PDT 24 |
| Peak memory | 614228 kb |
| Host | smart-f6b98576-4a80-49fc-9227-7c5ae530095f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=25_000_000 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_init_test:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3789356740 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_init_reduced_freq.3789356740 |
| Directory | /workspace/0.chip_sw_flash_init_reduced_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_scrambling_smoketest.2355500094 |
| Short name | T1071 |
| Test name | |
| Test status | |
| Simulation time | 2797997482 ps |
| CPU time | 279.62 seconds |
| Started | Jul 03 08:00:51 PM PDT 24 |
| Finished | Jul 03 08:05:31 PM PDT 24 |
| Peak memory | 610588 kb |
| Host | smart-ba201bf2-8c3b-454c-a757-064c13ac0df3 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=flash_scrambling_smoketest:1:new_rules,flash_scrambling_smoket est_otp_img_rma:4,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2355500094 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_scrambling_smoketest.2355500094 |
| Directory | /workspace/0.chip_sw_flash_scrambling_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_gpio_smoketest.9542692 |
| Short name | T1107 |
| Test name | |
| Test status | |
| Simulation time | 2349609419 ps |
| CPU time | 302.26 seconds |
| Started | Jul 03 07:51:28 PM PDT 24 |
| Finished | Jul 03 07:56:31 PM PDT 24 |
| Peak memory | 609636 kb |
| Host | smart-9075d95c-9475-40fc-8d28-bac570c8e808 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=gpio_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9542692 -assert nopostproc +UVM_TESTNAME=chip_b ase_test +UVM_TEST_SEQ=chip_sw_gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 0.chip_sw_gpio_smoketest.9542692 |
| Directory | /workspace/0.chip_sw_gpio_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_hmac_enc.3694626407 |
| Short name | T838 |
| Test name | |
| Test status | |
| Simulation time | 2336085348 ps |
| CPU time | 277.05 seconds |
| Started | Jul 03 07:50:19 PM PDT 24 |
| Finished | Jul 03 07:54:57 PM PDT 24 |
| Peak memory | 610664 kb |
| Host | smart-131b6d87-7554-4738-bbb1-21d0a209daf1 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3694626407 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_hmac_enc.3694626407 |
| Directory | /workspace/0.chip_sw_hmac_enc/latest |
| Test location | /workspace/coverage/default/0.chip_sw_hmac_enc_idle.2289795526 |
| Short name | T1033 |
| Test name | |
| Test status | |
| Simulation time | 2636972440 ps |
| CPU time | 298.15 seconds |
| Started | Jul 03 07:48:38 PM PDT 24 |
| Finished | Jul 03 07:53:36 PM PDT 24 |
| Peak memory | 607672 kb |
| Host | smart-03459e3f-bee4-4495-81e9-b191df3fc90c |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_enc_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2289795526 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 0.chip_sw_hmac_enc_idle.2289795526 |
| Directory | /workspace/0.chip_sw_hmac_enc_idle/latest |
| Test location | /workspace/coverage/default/0.chip_sw_hmac_enc_jitter_en.4025108465 |
| Short name | T288 |
| Test name | |
| Test status | |
| Simulation time | 3209700814 ps |
| CPU time | 257.67 seconds |
| Started | Jul 03 07:52:05 PM PDT 24 |
| Finished | Jul 03 07:56:23 PM PDT 24 |
| Peak memory | 610612 kb |
| Host | smart-a34cd574-a9c2-4006-adf1-92f9b3d82402 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4025108465 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 0.chip_sw_hmac_enc_jitter_en.4025108465 |
| Directory | /workspace/0.chip_sw_hmac_enc_jitter_en/latest |
| Test location | /workspace/coverage/default/0.chip_sw_hmac_enc_jitter_en_reduced_freq.1861592076 |
| Short name | T329 |
| Test name | |
| Test status | |
| Simulation time | 3116433593 ps |
| CPU time | 220.45 seconds |
| Started | Jul 03 07:54:23 PM PDT 24 |
| Finished | Jul 03 07:58:04 PM PDT 24 |
| Peak memory | 610732 kb |
| Host | smart-158478ff-992e-4ae0-bf33-3811163755ff |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1861592076 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove rage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_hmac_enc_jitter_en_reduced_freq.1861592076 |
| Directory | /workspace/0.chip_sw_hmac_enc_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_hmac_multistream.4040830916 |
| Short name | T844 |
| Test name | |
| Test status | |
| Simulation time | 7769701500 ps |
| CPU time | 1976.78 seconds |
| Started | Jul 03 07:51:18 PM PDT 24 |
| Finished | Jul 03 08:24:15 PM PDT 24 |
| Peak memory | 610684 kb |
| Host | smart-c2e6305b-f789-4129-98f3-807fda6561fd |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_multistream_functest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4040830916 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 0.chip_sw_hmac_multistream.4040830916 |
| Directory | /workspace/0.chip_sw_hmac_multistream/latest |
| Test location | /workspace/coverage/default/0.chip_sw_hmac_oneshot.320055381 |
| Short name | T651 |
| Test name | |
| Test status | |
| Simulation time | 2843495048 ps |
| CPU time | 249.64 seconds |
| Started | Jul 03 07:49:20 PM PDT 24 |
| Finished | Jul 03 07:53:30 PM PDT 24 |
| Peak memory | 607624 kb |
| Host | smart-4ae8d0cd-5dc0-4c10-a229-bf33ad00c83c |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_functest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=320055381 -assert nopostproc +UVM_TESTNAME=chip_ base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_hmac_oneshot.320055381 |
| Directory | /workspace/0.chip_sw_hmac_oneshot/latest |
| Test location | /workspace/coverage/default/0.chip_sw_hmac_smoketest.929978580 |
| Short name | T857 |
| Test name | |
| Test status | |
| Simulation time | 3010370712 ps |
| CPU time | 340.78 seconds |
| Started | Jul 03 07:53:42 PM PDT 24 |
| Finished | Jul 03 07:59:23 PM PDT 24 |
| Peak memory | 607700 kb |
| Host | smart-7859e91b-e6b1-4979-a00a-a79bf72de75e |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=929978580 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_hmac_smoketest.929978580 |
| Directory | /workspace/0.chip_sw_hmac_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_i2c_device_tx_rx.1587420542 |
| Short name | T320 |
| Test name | |
| Test status | |
| Simulation time | 3966737806 ps |
| CPU time | 642.93 seconds |
| Started | Jul 03 07:48:12 PM PDT 24 |
| Finished | Jul 03 07:58:56 PM PDT 24 |
| Peak memory | 609660 kb |
| Host | smart-f9aaf7b1-647d-465f-8f3d-9f4453ab2849 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=i2c_device_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1587420542 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_device_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 0.chip_sw_i2c_device_tx_rx.1587420542 |
| Directory | /workspace/0.chip_sw_i2c_device_tx_rx/latest |
| Test location | /workspace/coverage/default/0.chip_sw_inject_scramble_seed.170590555 |
| Short name | T1076 |
| Test name | |
| Test status | |
| Simulation time | 64830145509 ps |
| CPU time | 12924.9 seconds |
| Started | Jul 03 07:48:03 PM PDT 24 |
| Finished | Jul 03 11:23:30 PM PDT 24 |
| Peak memory | 625044 kb |
| Host | smart-7da81f3a-7489-4fef-8c3e-034b6a4271cf |
| User | root |
| Command | /workspace/default/simv +lc_at_prod=1 +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=inject_scramble_seed :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=170590555 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_inject_scramble_seed_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_inject_scramble_seed.170590555 |
| Directory | /workspace/0.chip_sw_inject_scramble_seed/latest |
| Test location | /workspace/coverage/default/0.chip_sw_keymgr_key_derivation.466866550 |
| Short name | T855 |
| Test name | |
| Test status | |
| Simulation time | 9200272476 ps |
| CPU time | 2081.26 seconds |
| Started | Jul 03 07:49:39 PM PDT 24 |
| Finished | Jul 03 08:24:21 PM PDT 24 |
| Peak memory | 616092 kb |
| Host | smart-ddfd122f-2fa7-44c1-b166-a1c22c50e66b |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4668 66550 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_key_derivation.466866550 |
| Directory | /workspace/0.chip_sw_keymgr_key_derivation/latest |
| Test location | /workspace/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en.279145782 |
| Short name | T944 |
| Test name | |
| Test status | |
| Simulation time | 6575690554 ps |
| CPU time | 1224.3 seconds |
| Started | Jul 03 07:48:52 PM PDT 24 |
| Finished | Jul 03 08:09:17 PM PDT 24 |
| Peak memory | 617056 kb |
| Host | smart-5c1c5793-6fb1-45f3-8f5f-c20d26dd3997 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=279145782 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_key_derivation_jitter_en.279145782 |
| Directory | /workspace/0.chip_sw_keymgr_key_derivation_jitter_en/latest |
| Test location | /workspace/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.3212761394 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 7856706823 ps |
| CPU time | 768.21 seconds |
| Started | Jul 03 07:57:31 PM PDT 24 |
| Finished | Jul 03 08:10:19 PM PDT 24 |
| Peak memory | 617044 kb |
| Host | smart-10ef64d6-0946-4a7b-86cb-0b5529deb09b |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3212761394 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_key_derivation_jitter_en _reduced_freq.3212761394 |
| Directory | /workspace/0.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_keymgr_key_derivation_prod.3623319573 |
| Short name | T880 |
| Test name | |
| Test status | |
| Simulation time | 6701097728 ps |
| CPU time | 1449.82 seconds |
| Started | Jul 03 07:48:49 PM PDT 24 |
| Finished | Jul 03 08:12:59 PM PDT 24 |
| Peak memory | 617176 kb |
| Host | smart-34ce7356-88f2-49ef-9efc-fcfd33815484 |
| User | root |
| Command | /workspace/default/simv +lc_at_prod=1 +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3623319573 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_key_derivation_prod.3623319573 |
| Directory | /workspace/0.chip_sw_keymgr_key_derivation_prod/latest |
| Test location | /workspace/coverage/default/0.chip_sw_keymgr_sideload_aes.1813518532 |
| Short name | T223 |
| Test name | |
| Test status | |
| Simulation time | 11613709368 ps |
| CPU time | 2529.16 seconds |
| Started | Jul 03 07:49:29 PM PDT 24 |
| Finished | Jul 03 08:31:39 PM PDT 24 |
| Peak memory | 610728 kb |
| Host | smart-488d59a8-791b-43d1-87a6-10b55162a7a5 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_aes_test:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=181351 8532 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_sideload_aes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_sideload_aes.1813518532 |
| Directory | /workspace/0.chip_sw_keymgr_sideload_aes/latest |
| Test location | /workspace/coverage/default/0.chip_sw_keymgr_sideload_kmac.2332532739 |
| Short name | T892 |
| Test name | |
| Test status | |
| Simulation time | 13010802264 ps |
| CPU time | 2529.86 seconds |
| Started | Jul 03 07:49:43 PM PDT 24 |
| Finished | Jul 03 08:31:54 PM PDT 24 |
| Peak memory | 610700 kb |
| Host | smart-efd137a2-ccf9-4e49-9118-0378c00fa1b1 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_kmac_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23325 32739 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_sideload_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_sideload_kmac.2332532739 |
| Directory | /workspace/0.chip_sw_keymgr_sideload_kmac/latest |
| Test location | /workspace/coverage/default/0.chip_sw_kmac_app_rom.2583221865 |
| Short name | T385 |
| Test name | |
| Test status | |
| Simulation time | 3088275510 ps |
| CPU time | 267.06 seconds |
| Started | Jul 03 07:50:14 PM PDT 24 |
| Finished | Jul 03 07:54:42 PM PDT 24 |
| Peak memory | 610600 kb |
| Host | smart-4f5697ec-a81b-4e86-a034-dd8c6e1958b5 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_app_rom_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2583221865 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 0.chip_sw_kmac_app_rom.2583221865 |
| Directory | /workspace/0.chip_sw_kmac_app_rom/latest |
| Test location | /workspace/coverage/default/0.chip_sw_kmac_entropy.82644711 |
| Short name | T1230 |
| Test name | |
| Test status | |
| Simulation time | 2493847300 ps |
| CPU time | 230.37 seconds |
| Started | Jul 03 07:47:59 PM PDT 24 |
| Finished | Jul 03 07:51:50 PM PDT 24 |
| Peak memory | 610656 kb |
| Host | smart-a99ee802-61f3-4f5b-8b5a-80fc2b0ec88c |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_entropy_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82644711 -assert nopostproc +UVM_TESTNAME=ch ip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 0.chip_sw_kmac_entropy.82644711 |
| Directory | /workspace/0.chip_sw_kmac_entropy/latest |
| Test location | /workspace/coverage/default/0.chip_sw_kmac_idle.2227126649 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 2932642660 ps |
| CPU time | 287.13 seconds |
| Started | Jul 03 07:49:38 PM PDT 24 |
| Finished | Jul 03 07:54:26 PM PDT 24 |
| Peak memory | 607684 kb |
| Host | smart-04784801-2c2f-4f24-8b1a-18e5ff3ae15d |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227126649 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 0.chip_sw_kmac_idle.2227126649 |
| Directory | /workspace/0.chip_sw_kmac_idle/latest |
| Test location | /workspace/coverage/default/0.chip_sw_kmac_mode_cshake.3435758922 |
| Short name | T835 |
| Test name | |
| Test status | |
| Simulation time | 3191958304 ps |
| CPU time | 224.86 seconds |
| Started | Jul 03 07:50:04 PM PDT 24 |
| Finished | Jul 03 07:53:49 PM PDT 24 |
| Peak memory | 608712 kb |
| Host | smart-9d28afb6-d99d-442f-acb2-003d1e8aa402 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_mode_cshake_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3435758922 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 0.chip_sw_kmac_mode_cshake.3435758922 |
| Directory | /workspace/0.chip_sw_kmac_mode_cshake/latest |
| Test location | /workspace/coverage/default/0.chip_sw_kmac_mode_kmac.2067397997 |
| Short name | T1198 |
| Test name | |
| Test status | |
| Simulation time | 2695484288 ps |
| CPU time | 363.28 seconds |
| Started | Jul 03 07:49:21 PM PDT 24 |
| Finished | Jul 03 07:55:25 PM PDT 24 |
| Peak memory | 610644 kb |
| Host | smart-3320dcc8-599d-46fb-8cf5-abbf8b158f85 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2067397997 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 0.chip_sw_kmac_mode_kmac.2067397997 |
| Directory | /workspace/0.chip_sw_kmac_mode_kmac/latest |
| Test location | /workspace/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en.2398250445 |
| Short name | T1142 |
| Test name | |
| Test status | |
| Simulation time | 2756617168 ps |
| CPU time | 321.87 seconds |
| Started | Jul 03 07:49:55 PM PDT 24 |
| Finished | Jul 03 07:55:17 PM PDT 24 |
| Peak memory | 610636 kb |
| Host | smart-fd14ef60-7fbe-476d-9503-6f85aa2c9942 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2398250445 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 0.chip_sw_kmac_mode_kmac_jitter_en.2398250445 |
| Directory | /workspace/0.chip_sw_kmac_mode_kmac_jitter_en/latest |
| Test location | /workspace/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.3256525761 |
| Short name | T1233 |
| Test name | |
| Test status | |
| Simulation time | 3102877214 ps |
| CPU time | 346.55 seconds |
| Started | Jul 03 07:50:23 PM PDT 24 |
| Finished | Jul 03 07:56:10 PM PDT 24 |
| Peak memory | 610632 kb |
| Host | smart-4fbc136f-6ba5-4832-b3fe-59347b720ee6 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32565257 61 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.3256525761 |
| Directory | /workspace/0.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_kmac_smoketest.2421985440 |
| Short name | T302 |
| Test name | |
| Test status | |
| Simulation time | 2967612316 ps |
| CPU time | 351.35 seconds |
| Started | Jul 03 07:52:36 PM PDT 24 |
| Finished | Jul 03 07:58:28 PM PDT 24 |
| Peak memory | 610592 kb |
| Host | smart-3b4c19a3-882c-45e7-a42f-082089828317 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2421985440 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 0.chip_sw_kmac_smoketest.2421985440 |
| Directory | /workspace/0.chip_sw_kmac_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_ctrl_otp_hw_cfg0.3076260198 |
| Short name | T882 |
| Test name | |
| Test status | |
| Simulation time | 2873775880 ps |
| CPU time | 283.18 seconds |
| Started | Jul 03 07:47:49 PM PDT 24 |
| Finished | Jul 03 07:52:32 PM PDT 24 |
| Peak memory | 610656 kb |
| Host | smart-d737710e-2c08-43e9-b0b2-92c07023c604 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_otp_hw_cfg0_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3076260198 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo g /dev/null -cm_name 0.chip_sw_lc_ctrl_otp_hw_cfg0.3076260198 |
| Directory | /workspace/0.chip_sw_lc_ctrl_otp_hw_cfg0/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_ctrl_raw_to_scrap.1343379242 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 3542340513 ps |
| CPU time | 189.42 seconds |
| Started | Jul 03 07:49:39 PM PDT 24 |
| Finished | Jul 03 07:52:50 PM PDT 24 |
| Peak memory | 619036 kb |
| Host | smart-6445dee6-283d-47d4-8894-98bb238dc10c |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +src_dec_state=DecLcStRaw +sw_build_device=sim_dv +sw_images=lc_ctrl_scrap_test:1:new_rules ,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1343379242 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_scrap_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_raw_to_scrap.1343379242 |
| Directory | /workspace/0.chip_sw_lc_ctrl_raw_to_scrap/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_ctrl_rma_to_scrap.1003728809 |
| Short name | T624 |
| Test name | |
| Test status | |
| Simulation time | 2556603513 ps |
| CPU time | 128.08 seconds |
| Started | Jul 03 07:50:58 PM PDT 24 |
| Finished | Jul 03 07:53:08 PM PDT 24 |
| Peak memory | 619456 kb |
| Host | smart-7826d74e-13b8-4f9a-934c-f61495efa2db |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_images=lc_ctrl_scrap_test:1:new_rules ,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1003728809 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_scrap_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_rma_to_scrap.1003728809 |
| Directory | /workspace/0.chip_sw_lc_ctrl_rma_to_scrap/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_ctrl_test_locked0_to_scrap.4153452493 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 3715767147 ps |
| CPU time | 122.27 seconds |
| Started | Jul 03 07:47:18 PM PDT 24 |
| Finished | Jul 03 07:49:20 PM PDT 24 |
| Peak memory | 619136 kb |
| Host | smart-c76dbd4a-b885-4b5d-9783-71f0caf41b91 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +src_dec_state=DecLcStTestLocked0 +sw_build_device=sim_dv +sw_images=lc_ctrl_scrap_test:1:n ew_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4153452493 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_scrap_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_test_locked0_to_scrap.4153452493 |
| Directory | /workspace/0.chip_sw_lc_ctrl_test_locked0_to_scrap/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_ctrl_transition.1179829331 |
| Short name | T1059 |
| Test name | |
| Test status | |
| Simulation time | 8954675156 ps |
| CPU time | 1288.39 seconds |
| Started | Jul 03 07:47:46 PM PDT 24 |
| Finished | Jul 03 08:09:15 PM PDT 24 |
| Peak memory | 620948 kb |
| Host | smart-a873a5d6-5f5d-4a93-b9d0-7f7d69e5eb76 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1179829331 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_transition.1179829331 |
| Directory | /workspace/0.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock.2802718320 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 2183070211 ps |
| CPU time | 136.17 seconds |
| Started | Jul 03 07:50:19 PM PDT 24 |
| Finished | Jul 03 07:52:35 PM PDT 24 |
| Peak memory | 616912 kb |
| Host | smart-2e15e4fd-bd30-4dde-9983-19bf6de90919 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +exp_volatile_raw_unlock_en=0 +sw_build_device=sim_dv +sw_images=lc_ctrl_volatile_raw_unlock_tes t:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=2802718320 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_volatile_raw_unlock.2802718320 |
| Directory | /workspace/0.chip_sw_lc_ctrl_volatile_raw_unlock/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.4278236949 |
| Short name | T625 |
| Test name | |
| Test status | |
| Simulation time | 1863928725 ps |
| CPU time | 109.6 seconds |
| Started | Jul 03 07:47:35 PM PDT 24 |
| Finished | Jul 03 07:49:25 PM PDT 24 |
| Peak memory | 616832 kb |
| Host | smart-31dab739-3906-42a7-94d4-4770da46f754 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceExternal48Mhz +exp_volatile_raw_unlock_en=0 +sw_build_device=s im_dv +sw_images=lc_ctrl_volatile_raw_unlock_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4278236949 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TES T_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.4278236949 |
| Directory | /workspace/0.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_walkthrough_dev.2476147000 |
| Short name | T228 |
| Test name | |
| Test status | |
| Simulation time | 46912402100 ps |
| CPU time | 5905.49 seconds |
| Started | Jul 03 07:51:17 PM PDT 24 |
| Finished | Jul 03 09:29:44 PM PDT 24 |
| Peak memory | 624164 kb |
| Host | smart-4cbdec87-96fd-4305-a6a8-8f1dd6a136b2 |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStDev +sw_test_timeout_ns=200_000_000 +sw_build_de vice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2476147000 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=c hip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip _sw_lc_walkthrough_dev.2476147000 |
| Directory | /workspace/0.chip_sw_lc_walkthrough_dev/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_walkthrough_prod.1224545468 |
| Short name | T1296 |
| Test name | |
| Test status | |
| Simulation time | 48403854982 ps |
| CPU time | 5268.9 seconds |
| Started | Jul 03 07:51:01 PM PDT 24 |
| Finished | Jul 03 09:18:52 PM PDT 24 |
| Peak memory | 624160 kb |
| Host | smart-0b373655-26b7-46b2-9ea3-94b6ec891a1c |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStProd +sw_test_timeout_ns=200_000_000 +sw_build_d evice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1224545468 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chi p_sw_lc_walkthrough_prod.1224545468 |
| Directory | /workspace/0.chip_sw_lc_walkthrough_prod/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_walkthrough_prodend.2112252880 |
| Short name | T1087 |
| Test name | |
| Test status | |
| Simulation time | 8857607593 ps |
| CPU time | 927.27 seconds |
| Started | Jul 03 07:50:16 PM PDT 24 |
| Finished | Jul 03 08:05:44 PM PDT 24 |
| Peak memory | 624104 kb |
| Host | smart-8a7450e5-a23f-4b7e-83c4-53531fd101e2 |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStProdEnd +sw_build_device=sim_dv +sw_images=lc_wa lkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2112252880 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_walkthrough_prodend.2112252880 |
| Directory | /workspace/0.chip_sw_lc_walkthrough_prodend/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_walkthrough_rma.519287829 |
| Short name | T1247 |
| Test name | |
| Test status | |
| Simulation time | 45713589372 ps |
| CPU time | 5830.22 seconds |
| Started | Jul 03 07:51:35 PM PDT 24 |
| Finished | Jul 03 09:28:48 PM PDT 24 |
| Peak memory | 619628 kb |
| Host | smart-cc055e22-4ece-4b0e-bedb-fdd9166ddeb5 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStRma +flash_program_latency=5 +sw_test_timeout_ns=200_000_000 +sw_build_de vice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=519287829 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=ch ip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_ sw_lc_walkthrough_rma.519287829 |
| Directory | /workspace/0.chip_sw_lc_walkthrough_rma/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_walkthrough_testunlocks.118300609 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 28788882585 ps |
| CPU time | 2395.25 seconds |
| Started | Jul 03 07:48:13 PM PDT 24 |
| Finished | Jul 03 08:28:10 PM PDT 24 |
| Peak memory | 624064 kb |
| Host | smart-c79a78bf-9b4a-45fc-a294-0a9ae8413a22 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStTestUnlock7 +sw_build_device=sim_dv +sw_images=lc_walkthrough_testunlocks _test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=118300609 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_testunlocks_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_walkthrough_testunl ocks.118300609 |
| Directory | /workspace/0.chip_sw_lc_walkthrough_testunlocks/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en.2430382210 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 18950153433 ps |
| CPU time | 3815.91 seconds |
| Started | Jul 03 07:50:40 PM PDT 24 |
| Finished | Jul 03 08:54:17 PM PDT 24 |
| Peak memory | 610756 kb |
| Host | smart-cf20ee65-f8f7-4944-a421-7deff8d7ecf6 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=33_000_000 +rng_srate_value=30 +en_jitter=1 +sw_build_device=sim_dv +sw_images=otbn_ecdsa_op_irq_test:1:ne w_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=2430382210 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otbn_ecdsa_op_irq_jitter_en.2430382210 |
| Directory | /workspace/0.chip_sw_otbn_ecdsa_op_irq_jitter_en/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.3857690168 |
| Short name | T318 |
| Test name | |
| Test status | |
| Simulation time | 24633614358 ps |
| CPU time | 4023.15 seconds |
| Started | Jul 03 07:51:00 PM PDT 24 |
| Finished | Jul 03 08:58:04 PM PDT 24 |
| Peak memory | 610792 kb |
| Host | smart-606bd658-e9bb-4b9b-b764-b57c61159298 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=33_000_000 +rng_srate_value=30 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=otbn_e cdsa_op_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3857690168 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otbn_ecdsa_op_irq_jitter_en_redu ced_freq.3857690168 |
| Directory | /workspace/0.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otbn_mem_scramble.1222325608 |
| Short name | T278 |
| Test name | |
| Test status | |
| Simulation time | 3202402824 ps |
| CPU time | 413.53 seconds |
| Started | Jul 03 07:48:12 PM PDT 24 |
| Finished | Jul 03 07:55:06 PM PDT 24 |
| Peak memory | 608984 kb |
| Host | smart-565d1b6f-adde-4bde-9f5b-23a9028baeb3 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=otbn _mem_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1222325608 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otbn_mem_scramble.1222325608 |
| Directory | /workspace/0.chip_sw_otbn_mem_scramble/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otbn_randomness.2674393555 |
| Short name | T925 |
| Test name | |
| Test status | |
| Simulation time | 6678144000 ps |
| CPU time | 997.09 seconds |
| Started | Jul 03 07:47:59 PM PDT 24 |
| Finished | Jul 03 08:04:36 PM PDT 24 |
| Peak memory | 610768 kb |
| Host | smart-a17895a8-5d47-4966-8e15-c6adeff23bda |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=30 +sw_build_device=sim_dv +sw_images=otbn_randomness_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2674393555 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otbn_randomness.2674393555 |
| Directory | /workspace/0.chip_sw_otbn_randomness/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otbn_smoketest.2663959166 |
| Short name | T1176 |
| Test name | |
| Test status | |
| Simulation time | 6482536810 ps |
| CPU time | 1713.62 seconds |
| Started | Jul 03 07:54:39 PM PDT 24 |
| Finished | Jul 03 08:23:14 PM PDT 24 |
| Peak memory | 610848 kb |
| Host | smart-69d53611-e0fd-4b47-aafe-ea8621047467 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otbn_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2663959166 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 0.chip_sw_otbn_smoketest.2663959166 |
| Directory | /workspace/0.chip_sw_otbn_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otp_ctrl_dai_lock.2595674434 |
| Short name | T969 |
| Test name | |
| Test status | |
| Simulation time | 27613739240 ps |
| CPU time | 5247.73 seconds |
| Started | Jul 03 07:47:37 PM PDT 24 |
| Finished | Jul 03 09:15:06 PM PDT 24 |
| Peak memory | 608616 kb |
| Host | smart-e3063fab-c6dd-4c60-ae8d-7a777faf5e8c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=30_000_000 +sw_build_device=sim_dv +sw_images=otp_ctrl_mem_access_test:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=259567 4434 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_dai_lock.2595674434 |
| Directory | /workspace/0.chip_sw_otp_ctrl_dai_lock/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otp_ctrl_ecc_error_vendor_test.3424831406 |
| Short name | T936 |
| Test name | |
| Test status | |
| Simulation time | 2790395962 ps |
| CPU time | 287.82 seconds |
| Started | Jul 03 07:51:00 PM PDT 24 |
| Finished | Jul 03 07:55:50 PM PDT 24 |
| Peak memory | 610640 kb |
| Host | smart-fc9b98b3-4b65-4589-b215-cef290af7398 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_vendor_test_ecc_error_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3424831406 -assert nopostp roc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_vendor_test_ecc_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_ecc_error_vendor_test.3424831406 |
| Directory | /workspace/0.chip_sw_otp_ctrl_ecc_error_vendor_test/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_dev.2963672336 |
| Short name | T1103 |
| Test name | |
| Test status | |
| Simulation time | 9210798614 ps |
| CPU time | 1176.48 seconds |
| Started | Jul 03 07:48:14 PM PDT 24 |
| Finished | Jul 03 08:07:51 PM PDT 24 |
| Peak memory | 610692 kb |
| Host | smart-861fce96-c9c8-4fa7-8bef-d204f0533cf9 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStDev +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,tes t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=2963672336 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_lc_signals_dev.2963672336 |
| Directory | /workspace/0.chip_sw_otp_ctrl_lc_signals_dev/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_prod.552170286 |
| Short name | T1141 |
| Test name | |
| Test status | |
| Simulation time | 7096395070 ps |
| CPU time | 1367.79 seconds |
| Started | Jul 03 07:48:05 PM PDT 24 |
| Finished | Jul 03 08:10:54 PM PDT 24 |
| Peak memory | 609492 kb |
| Host | smart-32d9ccf3-8185-49aa-97c0-18ec363ab9d7 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=552170286 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_lc_signals_prod.552170286 |
| Directory | /workspace/0.chip_sw_otp_ctrl_lc_signals_prod/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_rma.1183273077 |
| Short name | T225 |
| Test name | |
| Test status | |
| Simulation time | 6975578892 ps |
| CPU time | 1430.49 seconds |
| Started | Jul 03 07:47:44 PM PDT 24 |
| Finished | Jul 03 08:11:36 PM PDT 24 |
| Peak memory | 609480 kb |
| Host | smart-15f9ff3f-48d3-4014-bf56-c488ae3278da |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRma +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,tes t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=1183273077 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_lc_signals_rma.1183273077 |
| Directory | /workspace/0.chip_sw_otp_ctrl_lc_signals_rma/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_test_unlocked0.2433316642 |
| Short name | T867 |
| Test name | |
| Test status | |
| Simulation time | 4059324808 ps |
| CPU time | 845.69 seconds |
| Started | Jul 03 07:47:58 PM PDT 24 |
| Finished | Jul 03 08:02:04 PM PDT 24 |
| Peak memory | 610624 kb |
| Host | smart-b8c54d32-460c-4a5f-ab10-e21ffd330e7f |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new _rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/s im.tcl +ntb_random_seed=2433316642 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_lc_signals_test_unlocked0.2433316642 |
| Directory | /workspace/0.chip_sw_otp_ctrl_lc_signals_test_unlocked0/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otp_ctrl_smoketest.4006599565 |
| Short name | T270 |
| Test name | |
| Test status | |
| Simulation time | 3267440084 ps |
| CPU time | 291.5 seconds |
| Started | Jul 03 07:52:17 PM PDT 24 |
| Finished | Jul 03 07:57:09 PM PDT 24 |
| Peak memory | 610624 kb |
| Host | smart-565b0273-9d36-4e55-b1d1-88f1ce535d95 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4006599565 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 0.chip_sw_otp_ctrl_smoketest.4006599565 |
| Directory | /workspace/0.chip_sw_otp_ctrl_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pattgen_ios.1120864049 |
| Short name | T1276 |
| Test name | |
| Test status | |
| Simulation time | 2718704128 ps |
| CPU time | 318.99 seconds |
| Started | Jul 03 07:49:09 PM PDT 24 |
| Finished | Jul 03 07:54:31 PM PDT 24 |
| Peak memory | 610460 kb |
| Host | smart-66b37575-32a3-4db5-bb7e-6af8a92e4de8 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=5_000_000 +sw_build_device=sim_dv +sw_images=pattgen_ios_test:1:new_rules,test_rom:0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120864049 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_patt_ios_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pattgen_ios.1120864049 |
| Directory | /workspace/0.chip_sw_pattgen_ios/latest |
| Test location | /workspace/coverage/default/0.chip_sw_power_idle_load.977118545 |
| Short name | T1153 |
| Test name | |
| Test status | |
| Simulation time | 4240606806 ps |
| CPU time | 893.41 seconds |
| Started | Jul 03 07:57:44 PM PDT 24 |
| Finished | Jul 03 08:12:38 PM PDT 24 |
| Peak memory | 609600 kb |
| Host | smart-a631f832-85cf-40f0-9e64-5541abda9d39 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=chip_power_idle_load:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977118545 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_power_idle_load_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_power_idle_load.977118545 |
| Directory | /workspace/0.chip_sw_power_idle_load/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_all_reset_reqs.3513465621 |
| Short name | T305 |
| Test name | |
| Test status | |
| Simulation time | 11841271991 ps |
| CPU time | 1379.87 seconds |
| Started | Jul 03 07:49:02 PM PDT 24 |
| Finished | Jul 03 08:12:02 PM PDT 24 |
| Peak memory | 610284 kb |
| Host | smart-cea5ecaf-33b1-4824-aff9-c939e54955d6 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3513 465621 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_all_reset_reqs.3513465621 |
| Directory | /workspace/0.chip_sw_pwrmgr_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_b2b_sleep_reset_req.491858345 |
| Short name | T1092 |
| Test name | |
| Test status | |
| Simulation time | 26736274197 ps |
| CPU time | 2653.72 seconds |
| Started | Jul 03 07:50:15 PM PDT 24 |
| Finished | Jul 03 08:34:30 PM PDT 24 |
| Peak memory | 610692 kb |
| Host | smart-8a3f3207-370f-4717-9a7c-e3be5dc38555 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=35_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_b2b_sleep_reset_test:1:new_rules,test_rom:0 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=491 858345 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_repeat_reset_wkup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_b2b_sleep_reset_req.491858345 |
| Directory | /workspace/0.chip_sw_pwrmgr_b2b_sleep_reset_req/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.4147330728 |
| Short name | T397 |
| Test name | |
| Test status | |
| Simulation time | 13577709553 ps |
| CPU time | 1500.06 seconds |
| Started | Jul 03 07:47:55 PM PDT 24 |
| Finished | Jul 03 08:12:56 PM PDT 24 |
| Peak memory | 610824 kb |
| Host | smart-33fe316f-8823-4f62-be33-c954152a5cd7 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=4147330728 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.4147330728 |
| Directory | /workspace/0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_wake_ups.197929653 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 25790366280 ps |
| CPU time | 1662.7 seconds |
| Started | Jul 03 07:51:08 PM PDT 24 |
| Finished | Jul 03 08:18:51 PM PDT 24 |
| Peak memory | 610092 kb |
| Host | smart-db45712e-5c85-4a6c-9bc4-bfe7cb52cec3 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_all_wake_ups:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 197929653 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_deep_sleep_all_wake_ups.197929653 |
| Directory | /workspace/0.chip_sw_pwrmgr_deep_sleep_all_wake_ups/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_por_reset.181227285 |
| Short name | T984 |
| Test name | |
| Test status | |
| Simulation time | 9722797642 ps |
| CPU time | 964.69 seconds |
| Started | Jul 03 07:49:25 PM PDT 24 |
| Finished | Jul 03 08:05:31 PM PDT 24 |
| Peak memory | 611056 kb |
| Host | smart-6900689b-f8f4-48c6-93c9-cfade66d1795 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_por_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=181227285 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_por_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/ default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_deep_sleep_por_reset.181227285 |
| Directory | /workspace/0.chip_sw_pwrmgr_deep_sleep_por_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.2535863568 |
| Short name | T1284 |
| Test name | |
| Test status | |
| Simulation time | 8299932020 ps |
| CPU time | 521.56 seconds |
| Started | Jul 03 07:48:00 PM PDT 24 |
| Finished | Jul 03 07:56:42 PM PDT 24 |
| Peak memory | 615792 kb |
| Host | smart-77a78202-43a8-4b95-8c94-4e627d177a3b |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_power_glitch_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2535863568 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.2535863568 |
| Directory | /workspace/0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.2817044079 |
| Short name | T1104 |
| Test name | |
| Test status | |
| Simulation time | 13300016510 ps |
| CPU time | 1568.2 seconds |
| Started | Jul 03 07:47:44 PM PDT 24 |
| Finished | Jul 03 08:13:53 PM PDT 24 |
| Peak memory | 610720 kb |
| Host | smart-a4b83273-2e33-48bc-8a7a-4ce2a7031040 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2817044079 -assert nop ostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.2817044079 |
| Directory | /workspace/0.chip_sw_pwrmgr_normal_sleep_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_wake_ups.102277529 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 6952357388 ps |
| CPU time | 469.05 seconds |
| Started | Jul 03 07:50:01 PM PDT 24 |
| Finished | Jul 03 07:57:51 PM PDT 24 |
| Peak memory | 608496 kb |
| Host | smart-bbd51022-0f18-43ee-8c5a-527e263d1603 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_all_wake_ups:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102277529 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work space/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_normal_sleep_all_wake_ups.102277529 |
| Directory | /workspace/0.chip_sw_pwrmgr_normal_sleep_all_wake_ups/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_por_reset.2162126959 |
| Short name | T1281 |
| Test name | |
| Test status | |
| Simulation time | 6592929559 ps |
| CPU time | 674.09 seconds |
| Started | Jul 03 07:48:15 PM PDT 24 |
| Finished | Jul 03 07:59:30 PM PDT 24 |
| Peak memory | 610676 kb |
| Host | smart-d45c5033-07a3-4885-bb77-0d3a0fd0b791 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_por_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162126959 -assert nopostpr oc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_por_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_normal_sleep_por_reset.2162126959 |
| Directory | /workspace/0.chip_sw_pwrmgr_normal_sleep_por_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_reset_reqs.3224740273 |
| Short name | T907 |
| Test name | |
| Test status | |
| Simulation time | 24326508710 ps |
| CPU time | 3092.73 seconds |
| Started | Jul 03 07:47:55 PM PDT 24 |
| Finished | Jul 03 08:39:28 PM PDT 24 |
| Peak memory | 610248 kb |
| Host | smart-c0d6410c-ca6c-4c6d-978b-83a83f99af8b |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_all_reset_reqs_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3224740273 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_random_sleep_all_reset_reqs.3224740273 |
| Directory | /workspace/0.chip_sw_pwrmgr_random_sleep_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_wake_ups.315057283 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 22724126220 ps |
| CPU time | 2263.07 seconds |
| Started | Jul 03 07:52:25 PM PDT 24 |
| Finished | Jul 03 08:30:09 PM PDT 24 |
| Peak memory | 610160 kb |
| Host | smart-0ffbd42e-e283-444f-af65-cc265d8b30b2 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_all_wake_ups:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=315057283 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_random_sleep_all_wake_ups.315057283 |
| Directory | /workspace/0.chip_sw_pwrmgr_random_sleep_all_wake_ups/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_power_glitch_reset.2301999394 |
| Short name | T1112 |
| Test name | |
| Test status | |
| Simulation time | 34761717948 ps |
| CPU time | 3317.93 seconds |
| Started | Jul 03 07:49:56 PM PDT 24 |
| Finished | Jul 03 08:45:15 PM PDT 24 |
| Peak memory | 611536 kb |
| Host | smart-17789785-f52d-4f5f-a502-425512d3f583 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_test_timeout_ns=24_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_power _glitch_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2301999394 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_random_power_glit ch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_random_s leep_power_glitch_reset.2301999394 |
| Directory | /workspace/0.chip_sw_pwrmgr_random_sleep_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_disabled.610078289 |
| Short name | T636 |
| Test name | |
| Test status | |
| Simulation time | 3633103690 ps |
| CPU time | 274.89 seconds |
| Started | Jul 03 07:48:14 PM PDT 24 |
| Finished | Jul 03 07:52:50 PM PDT 24 |
| Peak memory | 607656 kb |
| Host | smart-de602251-7e32-4c51-898f-46fd970cfc2b |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_disabled_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=610078289 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 0.chip_sw_pwrmgr_sleep_disabled.610078289 |
| Directory | /workspace/0.chip_sw_pwrmgr_sleep_disabled/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_power_glitch_reset.2704167717 |
| Short name | T1245 |
| Test name | |
| Test status | |
| Simulation time | 4467761248 ps |
| CPU time | 514.64 seconds |
| Started | Jul 03 07:51:23 PM PDT 24 |
| Finished | Jul 03 07:59:59 PM PDT 24 |
| Peak memory | 616584 kb |
| Host | smart-ad132a7c-5860-4f96-9e3b-88818d52c2f5 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_power_glitch_test:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s eed=2704167717 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_main_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_sleep_power_glitch_reset.2704167717 |
| Directory | /workspace/0.chip_sw_pwrmgr_sleep_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_wake_5_bug.2218692491 |
| Short name | T934 |
| Test name | |
| Test status | |
| Simulation time | 5587123712 ps |
| CPU time | 599.11 seconds |
| Started | Jul 03 07:52:06 PM PDT 24 |
| Finished | Jul 03 08:02:06 PM PDT 24 |
| Peak memory | 610772 kb |
| Host | smart-84e29dcf-89ee-4b82-bb81-9f504c94091c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_wake_5_bug_test:1:new_rules,test_r om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=2218692491 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_sleep_wake_5_bug.2218692491 |
| Directory | /workspace/0.chip_sw_pwrmgr_sleep_wake_5_bug/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_smoketest.3923084891 |
| Short name | T998 |
| Test name | |
| Test status | |
| Simulation time | 5129910034 ps |
| CPU time | 395.24 seconds |
| Started | Jul 03 07:56:57 PM PDT 24 |
| Finished | Jul 03 08:03:33 PM PDT 24 |
| Peak memory | 610672 kb |
| Host | smart-57cc1170-5955-4930-9f76-3969c89b4e1f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=10000000 +sw_build_device=sim_dv +sw_images=pwrmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3923084891 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_smoketest.3923084891 |
| Directory | /workspace/0.chip_sw_pwrmgr_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_sysrst_ctrl_reset.57916548 |
| Short name | T1138 |
| Test name | |
| Test status | |
| Simulation time | 7814345805 ps |
| CPU time | 1454.33 seconds |
| Started | Jul 03 07:49:46 PM PDT 24 |
| Finished | Jul 03 08:14:02 PM PDT 24 |
| Peak memory | 609840 kb |
| Host | smart-b209b7dc-1a32-481b-903d-d0723494275a |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_sysrst_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57916548 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c m_log /dev/null -cm_name 0.chip_sw_pwrmgr_sysrst_ctrl_reset.57916548 |
| Directory | /workspace/0.chip_sw_pwrmgr_sysrst_ctrl_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_usb_clk_disabled_when_active.2470178077 |
| Short name | T874 |
| Test name | |
| Test status | |
| Simulation time | 5440529184 ps |
| CPU time | 710.8 seconds |
| Started | Jul 03 07:49:34 PM PDT 24 |
| Finished | Jul 03 08:01:25 PM PDT 24 |
| Peak memory | 609300 kb |
| Host | smart-c123a8af-3f3b-4733-8f63-f9e73d8614c8 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_usb_clk_disabled_when_active_test:1:new_rules,test_rom:0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2470178077 -assert no postproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_usb_clk_disabled_when_active.2470178077 |
| Directory | /workspace/0.chip_sw_pwrmgr_usb_clk_disabled_when_active/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_usbdev_smoketest.3849666030 |
| Short name | T1277 |
| Test name | |
| Test status | |
| Simulation time | 6396262944 ps |
| CPU time | 313.98 seconds |
| Started | Jul 03 07:52:11 PM PDT 24 |
| Finished | Jul 03 07:57:25 PM PDT 24 |
| Peak memory | 609296 kb |
| Host | smart-52c8a1e6-b9a7-485e-8f45-68e98b6d6d55 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_usbdev_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3849666030 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_usbdev_smoketest.3849666030 |
| Directory | /workspace/0.chip_sw_pwrmgr_usbdev_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_wdog_reset.117397825 |
| Short name | T1042 |
| Test name | |
| Test status | |
| Simulation time | 3812459320 ps |
| CPU time | 483.52 seconds |
| Started | Jul 03 07:49:32 PM PDT 24 |
| Finished | Jul 03 07:57:36 PM PDT 24 |
| Peak memory | 608228 kb |
| Host | smart-a2aa4243-f2bf-4539-a4dd-8c8a1d7897d6 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_wdog_reset_reqs_test:1:new_rules,test_rom:0 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=117 397825 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work space/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_wdog_reset.117397825 |
| Directory | /workspace/0.chip_sw_pwrmgr_wdog_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rom_ctrl_integrity_check.2438519255 |
| Short name | T398 |
| Test name | |
| Test status | |
| Simulation time | 9526464482 ps |
| CPU time | 453.99 seconds |
| Started | Jul 03 07:50:55 PM PDT 24 |
| Finished | Jul 03 07:58:30 PM PDT 24 |
| Peak memory | 609708 kb |
| Host | smart-9bddd2ee-fa7c-45dc-9fc8-12c62261dd91 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rom_ctrl_integrity_check_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2438519255 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_ctrl_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rom_ctrl_integrity_check.2438519255 |
| Directory | /workspace/0.chip_sw_rom_ctrl_integrity_check/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rstmgr_cpu_info.2833814174 |
| Short name | T243 |
| Test name | |
| Test status | |
| Simulation time | 4725347856 ps |
| CPU time | 552.3 seconds |
| Started | Jul 03 07:50:03 PM PDT 24 |
| Finished | Jul 03 07:59:17 PM PDT 24 |
| Peak memory | 610652 kb |
| Host | smart-3e96cd52-16ce-48b3-a829-faafb41cfbce |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_cpu_info_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2833814174 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 0.chip_sw_rstmgr_cpu_info.2833814174 |
| Directory | /workspace/0.chip_sw_rstmgr_cpu_info/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rstmgr_rst_cnsty_escalation.2233093377 |
| Short name | T649 |
| Test name | |
| Test status | |
| Simulation time | 4554731652 ps |
| CPU time | 878.37 seconds |
| Started | Jul 03 07:49:09 PM PDT 24 |
| Finished | Jul 03 08:03:48 PM PDT 24 |
| Peak memory | 641184 kb |
| Host | smart-6c06c648-b480-4fec-aaca-84d9dc973ae2 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2233093377 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rstmgr_cnsty_fault_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rstmgr_rst_cnsty_escalation.2233093377 |
| Directory | /workspace/0.chip_sw_rstmgr_rst_cnsty_escalation/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rstmgr_smoketest.967268543 |
| Short name | T1186 |
| Test name | |
| Test status | |
| Simulation time | 2445399688 ps |
| CPU time | 255 seconds |
| Started | Jul 03 07:51:34 PM PDT 24 |
| Finished | Jul 03 07:55:50 PM PDT 24 |
| Peak memory | 607768 kb |
| Host | smart-dd6c1c39-1752-44a7-832a-26645340fe12 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=967268543 -assert nopostproc +UVM_TESTNAME=ch ip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 0.chip_sw_rstmgr_smoketest.967268543 |
| Directory | /workspace/0.chip_sw_rstmgr_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rstmgr_sw_req.520943970 |
| Short name | T1231 |
| Test name | |
| Test status | |
| Simulation time | 5318239150 ps |
| CPU time | 438.06 seconds |
| Started | Jul 03 07:49:04 PM PDT 24 |
| Finished | Jul 03 07:56:23 PM PDT 24 |
| Peak memory | 608276 kb |
| Host | smart-2ded3e21-7d73-4b85-b378-6e47be35ea6a |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_sw_req_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=520943970 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 0.chip_sw_rstmgr_sw_req.520943970 |
| Directory | /workspace/0.chip_sw_rstmgr_sw_req/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rstmgr_sw_rst.383724148 |
| Short name | T206 |
| Test name | |
| Test status | |
| Simulation time | 2905181758 ps |
| CPU time | 278.31 seconds |
| Started | Jul 03 07:48:18 PM PDT 24 |
| Finished | Jul 03 07:52:58 PM PDT 24 |
| Peak memory | 610588 kb |
| Host | smart-7170e4d9-bbe4-4142-9b63-1cf58f6f9bd6 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_sw_rst_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=383724148 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rstmgr_sw_rst.383724148 |
| Directory | /workspace/0.chip_sw_rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rv_core_ibex_icache_invalidate.2148421639 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 2747763333 ps |
| CPU time | 331.03 seconds |
| Started | Jul 03 07:51:21 PM PDT 24 |
| Finished | Jul 03 07:56:52 PM PDT 24 |
| Peak memory | 610636 kb |
| Host | smart-a86bbb0d-e2f8-43dc-8d23-7dc9a6e0ae32 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_core_ibex_icache_invalidate_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2148421639 -assert nopostp roc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_core_ibex_icache_invalidate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_core_ibex_icache_invalidate.2148421639 |
| Directory | /workspace/0.chip_sw_rv_core_ibex_icache_invalidate/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rv_core_ibex_rnd.4205650941 |
| Short name | T918 |
| Test name | |
| Test status | |
| Simulation time | 6118310174 ps |
| CPU time | 1011.8 seconds |
| Started | Jul 03 07:49:21 PM PDT 24 |
| Finished | Jul 03 08:06:13 PM PDT 24 |
| Peak memory | 610560 kb |
| Host | smart-2ee845e8-b562-4987-aa69-94423206bded |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +rng_srate_value_max=32 +sw_build_device=sim_dv +sw_images=rv_core_ibex_rnd_test:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=4205650941 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_core_ibex_rnd.4205650941 |
| Directory | /workspace/0.chip_sw_rv_core_ibex_rnd/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rv_plic_smoketest.2032600372 |
| Short name | T1015 |
| Test name | |
| Test status | |
| Simulation time | 3150646000 ps |
| CPU time | 245.62 seconds |
| Started | Jul 03 07:55:04 PM PDT 24 |
| Finished | Jul 03 07:59:10 PM PDT 24 |
| Peak memory | 610712 kb |
| Host | smart-2f372c8e-ef42-4eb7-a8be-0e65d69508c3 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_plic_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2032600372 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 0.chip_sw_rv_plic_smoketest.2032600372 |
| Directory | /workspace/0.chip_sw_rv_plic_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rv_timer_irq.1122642436 |
| Short name | T255 |
| Test name | |
| Test status | |
| Simulation time | 2636475470 ps |
| CPU time | 278.57 seconds |
| Started | Jul 03 07:48:31 PM PDT 24 |
| Finished | Jul 03 07:53:10 PM PDT 24 |
| Peak memory | 610576 kb |
| Host | smart-eeeaafc4-a1cb-4606-bc91-1f00b2331fd5 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1122642436 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 0.chip_sw_rv_timer_irq.1122642436 |
| Directory | /workspace/0.chip_sw_rv_timer_irq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rv_timer_smoketest.3935390715 |
| Short name | T1227 |
| Test name | |
| Test status | |
| Simulation time | 3113516024 ps |
| CPU time | 249.25 seconds |
| Started | Jul 03 07:51:39 PM PDT 24 |
| Finished | Jul 03 07:55:49 PM PDT 24 |
| Peak memory | 610624 kb |
| Host | smart-6127a231-fd2d-4ee5-92c2-896290ecd04c |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3935390715 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 0.chip_sw_rv_timer_smoketest.3935390715 |
| Directory | /workspace/0.chip_sw_rv_timer_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sensor_ctrl_status.1317676977 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 2710066105 ps |
| CPU time | 296.67 seconds |
| Started | Jul 03 07:50:57 PM PDT 24 |
| Finished | Jul 03 07:55:54 PM PDT 24 |
| Peak memory | 609780 kb |
| Host | smart-3b116ed6-bc64-4a9c-949d-51c865e804f0 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_status_test:1:new_rules,test_rom:0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1317676 977 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sensor_ctrl_status_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sensor_ctrl_status.1317676977 |
| Directory | /workspace/0.chip_sw_sensor_ctrl_status/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sleep_pin_retention.356552255 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 4682452456 ps |
| CPU time | 369.22 seconds |
| Started | Jul 03 07:50:00 PM PDT 24 |
| Finished | Jul 03 07:56:11 PM PDT 24 |
| Peak memory | 610692 kb |
| Host | smart-5749f673-9906-4de5-a590-7eba382feed1 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sleep_pin_retention_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=356552255 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_retention_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa ult.vdb -cm_log /dev/null -cm_name 0.chip_sw_sleep_pin_retention.356552255 |
| Directory | /workspace/0.chip_sw_sleep_pin_retention/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sleep_pwm_pulses.2976019446 |
| Short name | T214 |
| Test name | |
| Test status | |
| Simulation time | 9464019382 ps |
| CPU time | 1490.4 seconds |
| Started | Jul 03 07:47:34 PM PDT 24 |
| Finished | Jul 03 08:12:25 PM PDT 24 |
| Peak memory | 609984 kb |
| Host | smart-408d6943-cfa4-4987-b4d8-29544c71d493 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sleep_pwm_pulses_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976019446 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwm_pulses_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 0.chip_sw_sleep_pwm_pulses.2976019446 |
| Directory | /workspace/0.chip_sw_sleep_pwm_pulses/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_no_scramble.41442902 |
| Short name | T1184 |
| Test name | |
| Test status | |
| Simulation time | 6468421780 ps |
| CPU time | 785.26 seconds |
| Started | Jul 03 07:50:04 PM PDT 24 |
| Finished | Jul 03 08:03:10 PM PDT 24 |
| Peak memory | 610640 kb |
| Host | smart-ff4034c1-9079-4526-9a77-1e9daf77a3b7 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_sleep_sram_ret_contents_no_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41442902 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_slee p_sram_ret_contents_no_scramble.41442902 |
| Directory | /workspace/0.chip_sw_sleep_sram_ret_contents_no_scramble/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_scramble.1855828291 |
| Short name | T1009 |
| Test name | |
| Test status | |
| Simulation time | 8418961740 ps |
| CPU time | 728.32 seconds |
| Started | Jul 03 07:50:30 PM PDT 24 |
| Finished | Jul 03 08:02:39 PM PDT 24 |
| Peak memory | 609796 kb |
| Host | smart-f9ef30c7-8d66-438c-b1d2-fc1c73e98560 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_sleep_sram_ret_contents_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1855828291 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sleep _sram_ret_contents_scramble.1855828291 |
| Directory | /workspace/0.chip_sw_sleep_sram_ret_contents_scramble/latest |
| Test location | /workspace/coverage/default/0.chip_sw_spi_device_pass_through.1432626751 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 5882325284 ps |
| CPU time | 625.38 seconds |
| Started | Jul 03 07:48:05 PM PDT 24 |
| Finished | Jul 03 07:58:32 PM PDT 24 |
| Peak memory | 624960 kb |
| Host | smart-ff2ba0ff-c154-4805-9102-94efb6d3af04 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_passthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1432626751 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_passthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_spi_device_pass_through.1432626751 |
| Directory | /workspace/0.chip_sw_spi_device_pass_through/latest |
| Test location | /workspace/coverage/default/0.chip_sw_spi_device_tpm.2944137399 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 3501010862 ps |
| CPU time | 393.71 seconds |
| Started | Jul 03 07:48:37 PM PDT 24 |
| Finished | Jul 03 07:55:12 PM PDT 24 |
| Peak memory | 618488 kb |
| Host | smart-4d4ec410-242c-45bc-bd48-6c924d95ca97 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_device_tpm_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2944137399 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_device_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default .vdb -cm_log /dev/null -cm_name 0.chip_sw_spi_device_tpm.2944137399 |
| Directory | /workspace/0.chip_sw_spi_device_tpm/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sram_ctrl_execution_main.119248114 |
| Short name | T294 |
| Test name | |
| Test status | |
| Simulation time | 8008535634 ps |
| CPU time | 904.76 seconds |
| Started | Jul 03 07:51:41 PM PDT 24 |
| Finished | Jul 03 08:06:48 PM PDT 24 |
| Peak memory | 610712 kb |
| Host | smart-658ce76a-77bf-4cae-b357-d2b14d335f29 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sram_ctrl_execution_main_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=119248114 -assert nopostproc +UV M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_execution_main_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sram_ctrl_execution_main.119248114 |
| Directory | /workspace/0.chip_sw_sram_ctrl_execution_main/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en.4237344873 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 5495982344 ps |
| CPU time | 591.38 seconds |
| Started | Jul 03 07:50:06 PM PDT 24 |
| Finished | Jul 03 07:59:58 PM PDT 24 |
| Peak memory | 609220 kb |
| Host | smart-c8d234aa-4d64-4c76-9130-c0b51ec1c606 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=12_000_000 +bypass_alert_ready_to_end_check=1 +en_jitter=1 +en_scb_tl_err_chk=0 +sw_build_device=sim_dv +s w_images=sram_ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4237344873 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chi p_sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 0.chip_sw_sram_ctrl_scrambled_access_jitter_en.4237344873 |
| Directory | /workspace/0.chip_sw_sram_ctrl_scrambled_access_jitter_en/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.2864948954 |
| Short name | T1099 |
| Test name | |
| Test status | |
| Simulation time | 4500053317 ps |
| CPU time | 539.77 seconds |
| Started | Jul 03 07:50:01 PM PDT 24 |
| Finished | Jul 03 07:59:02 PM PDT 24 |
| Peak memory | 610076 kb |
| Host | smart-78cb9fc0-e06d-4f62-9c58-545175f88d4b |
| User | root |
| Command | /workspace/default/simv +mem_sel=main +sw_test_timeout_ns=12_000_000 +bypass_alert_ready_to_end_check=1 +en_jitter=1 +en_scb_tl_err_chk=0 +cal_sys_clk _70mhz=1 +sw_build_device=sim_dv +sw_images=sram_ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2864948954 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/ default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.2864948954 |
| Directory | /workspace/0.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sram_ctrl_smoketest.3507689769 |
| Short name | T1187 |
| Test name | |
| Test status | |
| Simulation time | 2947433520 ps |
| CPU time | 164.44 seconds |
| Started | Jul 03 07:52:18 PM PDT 24 |
| Finished | Jul 03 07:55:03 PM PDT 24 |
| Peak memory | 610656 kb |
| Host | smart-552bcd06-d622-4d14-a73c-501136210f2a |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sram_ctrl_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3507689769 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 0.chip_sw_sram_ctrl_smoketest.3507689769 |
| Directory | /workspace/0.chip_sw_sram_ctrl_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sysrst_ctrl_ec_rst_l.4167992149 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 21257182252 ps |
| CPU time | 3661.5 seconds |
| Started | Jul 03 07:47:50 PM PDT 24 |
| Finished | Jul 03 08:48:53 PM PDT 24 |
| Peak memory | 610588 kb |
| Host | smart-f0dd2ecc-d8f2-41a8-961b-be692ecf978e |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_ec_rst_l_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4167992149 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_ec_rst_l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d efault.vdb -cm_log /dev/null -cm_name 0.chip_sw_sysrst_ctrl_ec_rst_l.4167992149 |
| Directory | /workspace/0.chip_sw_sysrst_ctrl_ec_rst_l/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sysrst_ctrl_in_irq.3676323256 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 4863014561 ps |
| CPU time | 798.31 seconds |
| Started | Jul 03 07:49:16 PM PDT 24 |
| Finished | Jul 03 08:02:37 PM PDT 24 |
| Peak memory | 612948 kb |
| Host | smart-028b89bf-ecd3-451d-bcce-5ae6f4ee11c9 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_in_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3676323256 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_in_irq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 0.chip_sw_sysrst_ctrl_in_irq.3676323256 |
| Directory | /workspace/0.chip_sw_sysrst_ctrl_in_irq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sysrst_ctrl_outputs.804993117 |
| Short name | T1150 |
| Test name | |
| Test status | |
| Simulation time | 4055003752 ps |
| CPU time | 465.45 seconds |
| Started | Jul 03 07:51:13 PM PDT 24 |
| Finished | Jul 03 07:58:59 PM PDT 24 |
| Peak memory | 608084 kb |
| Host | smart-3005335c-9d60-4764-b882-fabcc109bf03 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_outputs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804993117 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_outputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa ult.vdb -cm_log /dev/null -cm_name 0.chip_sw_sysrst_ctrl_outputs.804993117 |
| Directory | /workspace/0.chip_sw_sysrst_ctrl_outputs/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sysrst_ctrl_reset.3922905164 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 21920130852 ps |
| CPU time | 1474.48 seconds |
| Started | Jul 03 07:48:46 PM PDT 24 |
| Finished | Jul 03 08:13:22 PM PDT 24 |
| Peak memory | 614064 kb |
| Host | smart-6351f591-b1b7-4746-a661-b57c35816a32 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=36_000_000 +sw_build_device=sim_dv +sw_images=sysrst_ctrl_reset_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39229051 64 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sysrst_ctrl_reset.3922905164 |
| Directory | /workspace/0.chip_sw_sysrst_ctrl_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sysrst_ctrl_ulp_z3_wakeup.3024481042 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 5678629034 ps |
| CPU time | 468.71 seconds |
| Started | Jul 03 07:48:05 PM PDT 24 |
| Finished | Jul 03 07:55:55 PM PDT 24 |
| Peak memory | 610788 kb |
| Host | smart-069a41b6-1309-4867-b9e8-c9cf4335290d |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_ulp_z3_wakeup_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3024481042 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_ulp_z3_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/ coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sysrst_ctrl_ulp_z3_wakeup.3024481042 |
| Directory | /workspace/0.chip_sw_sysrst_ctrl_ulp_z3_wakeup/latest |
| Test location | /workspace/coverage/default/0.chip_sw_uart_rand_baudrate.2656326526 |
| Short name | T1077 |
| Test name | |
| Test status | |
| Simulation time | 3846083144 ps |
| CPU time | 672.88 seconds |
| Started | Jul 03 07:52:01 PM PDT 24 |
| Finished | Jul 03 08:03:16 PM PDT 24 |
| Peak memory | 621848 kb |
| Host | smart-7a57de20-d8f7-4d4b-8609-29c58e59e54f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=2656326526 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_rand_baudrate.2656326526 |
| Directory | /workspace/0.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/0.chip_sw_uart_smoketest.2451858747 |
| Short name | T1229 |
| Test name | |
| Test status | |
| Simulation time | 2952770348 ps |
| CPU time | 281.52 seconds |
| Started | Jul 03 07:55:17 PM PDT 24 |
| Finished | Jul 03 08:00:01 PM PDT 24 |
| Peak memory | 611104 kb |
| Host | smart-8dd00f05-d61c-4d95-9e31-7aeb37e3a7ce |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=uart_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2451858747 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 0.chip_sw_uart_smoketest.2451858747 |
| Directory | /workspace/0.chip_sw_uart_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_uart_tx_rx.945537284 |
| Short name | T1088 |
| Test name | |
| Test status | |
| Simulation time | 3876712260 ps |
| CPU time | 773.49 seconds |
| Started | Jul 03 07:49:02 PM PDT 24 |
| Finished | Jul 03 08:01:57 PM PDT 24 |
| Peak memory | 621728 kb |
| Host | smart-8a1b5f8b-db32-4f2c-b52a-5de9ed660042 |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=945537284 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx.945537284 |
| Directory | /workspace/0.chip_sw_uart_tx_rx/latest |
| Test location | /workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.3017800053 |
| Short name | T932 |
| Test name | |
| Test status | |
| Simulation time | 4999375455 ps |
| CPU time | 634.77 seconds |
| Started | Jul 03 07:47:31 PM PDT 24 |
| Finished | Jul 03 07:58:07 PM PDT 24 |
| Peak memory | 618060 kb |
| Host | smart-af7017b6-54d1-478f-94bd-d58f1f1c56e5 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3017800053 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_b audrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx _alt_clk_freq_low_speed.3017800053 |
| Directory | /workspace/0.chip_sw_uart_tx_rx_alt_clk_freq_low_speed/latest |
| Test location | /workspace/coverage/default/0.chip_sw_uart_tx_rx_bootstrap.4047488671 |
| Short name | T1052 |
| Test name | |
| Test status | |
| Simulation time | 78517767450 ps |
| CPU time | 13034.7 seconds |
| Started | Jul 03 07:48:15 PM PDT 24 |
| Finished | Jul 03 11:25:31 PM PDT 24 |
| Peak memory | 633184 kb |
| Host | smart-cf25e60c-861d-43a2-af23-038b87a60a63 |
| User | root |
| Command | /workspace/default/simv +use_spi_load_bootstrap=1 +calibrate_usb_clk=1 +test_timeout_ns=160_000_000 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=4047488671 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx_bootstrap.4047488671 |
| Directory | /workspace/0.chip_sw_uart_tx_rx_bootstrap/latest |
| Test location | /workspace/coverage/default/0.chip_sw_uart_tx_rx_idx1.3122254516 |
| Short name | T876 |
| Test name | |
| Test status | |
| Simulation time | 3886697418 ps |
| CPU time | 744.02 seconds |
| Started | Jul 03 07:47:10 PM PDT 24 |
| Finished | Jul 03 07:59:34 PM PDT 24 |
| Peak memory | 621936 kb |
| Host | smart-411fe7e1-c898-4788-8af0-0675e5d44981 |
| User | root |
| Command | /workspace/default/simv +uart_idx=1 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3122254516 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx_idx1.3122254516 |
| Directory | /workspace/0.chip_sw_uart_tx_rx_idx1/latest |
| Test location | /workspace/coverage/default/0.chip_sw_uart_tx_rx_idx2.4107496202 |
| Short name | T1151 |
| Test name | |
| Test status | |
| Simulation time | 4298719312 ps |
| CPU time | 689.12 seconds |
| Started | Jul 03 07:48:03 PM PDT 24 |
| Finished | Jul 03 07:59:32 PM PDT 24 |
| Peak memory | 622228 kb |
| Host | smart-00e67ef5-1dd1-4243-bfa1-73550fd61e0d |
| User | root |
| Command | /workspace/default/simv +uart_idx=2 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4107496202 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx_idx2.4107496202 |
| Directory | /workspace/0.chip_sw_uart_tx_rx_idx2/latest |
| Test location | /workspace/coverage/default/0.chip_sw_usb_ast_clk_calib.4143287417 |
| Short name | T957 |
| Test name | |
| Test status | |
| Simulation time | 3904613795 ps |
| CPU time | 319.78 seconds |
| Started | Jul 03 07:49:24 PM PDT 24 |
| Finished | Jul 03 07:54:45 PM PDT 24 |
| Peak memory | 607896 kb |
| Host | smart-409a9165-a8a0-4d77-ab8a-497e9d07a839 |
| User | root |
| Command | /workspace/default/simv +usb_max_drift=1 +usb_fast_sof=1 +sw_build_device=sim_dv +sw_images=ast_usb_clk_calib:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4143287417 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usb_ast_clk_calib_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usb_ast_clk_calib.4143287417 |
| Directory | /workspace/0.chip_sw_usb_ast_clk_calib/latest |
| Test location | /workspace/coverage/default/0.chip_sw_usbdev_dpi.2045136005 |
| Short name | T410 |
| Test name | |
| Test status | |
| Simulation time | 12816229760 ps |
| CPU time | 3110.97 seconds |
| Started | Jul 03 07:46:55 PM PDT 24 |
| Finished | Jul 03 08:38:47 PM PDT 24 |
| Peak memory | 610500 kb |
| Host | smart-bf5277a0-0d2c-4dc9-87f9-0f24569c7dad |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_test_timeout_ns=30_000_000 +sw_build_device=sim_dv +sw_images=usbdev_test:1:new_rules,tes t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=2045136005 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_dpi.2045136005 |
| Directory | /workspace/0.chip_sw_usbdev_dpi/latest |
| Test location | /workspace/coverage/default/0.chip_sw_usbdev_pincfg.3149001347 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 31988505994 ps |
| CPU time | 6609.18 seconds |
| Started | Jul 03 07:47:22 PM PDT 24 |
| Finished | Jul 03 09:37:33 PM PDT 24 |
| Peak memory | 610616 kb |
| Host | smart-835cc1de-2b52-4f26-b3fe-100551e93acc |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_test_timeout_ns=100_000_000 +sw_build_device=sim_dv +sw_images=usbdev_pincfg_test:1:new_r ules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim .tcl +ntb_random_seed=3149001347 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_pincfg.3149001347 |
| Directory | /workspace/0.chip_sw_usbdev_pincfg/latest |
| Test location | /workspace/coverage/default/0.chip_sw_usbdev_pullup.3523587976 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 3199095594 ps |
| CPU time | 301.82 seconds |
| Started | Jul 03 07:47:01 PM PDT 24 |
| Finished | Jul 03 07:52:03 PM PDT 24 |
| Peak memory | 608848 kb |
| Host | smart-648139e1-1ce9-48b7-a3ad-50802eb58d67 |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=usbdev_pullup_test:1:new_rules,test_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3523587976 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work space/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_pullup.3523587976 |
| Directory | /workspace/0.chip_sw_usbdev_pullup/latest |
| Test location | /workspace/coverage/default/0.chip_sw_usbdev_setuprx.147103353 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 3891648600 ps |
| CPU time | 587.27 seconds |
| Started | Jul 03 07:47:26 PM PDT 24 |
| Finished | Jul 03 07:57:14 PM PDT 24 |
| Peak memory | 607732 kb |
| Host | smart-1594ab2a-8039-4069-9bb1-e8fe65e67f43 |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=usbdev_setuprx_test:1:new_rules,test_rom:0 +cdc_instrument ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=147103353 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work space/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_setuprx.147103353 |
| Directory | /workspace/0.chip_sw_usbdev_setuprx/latest |
| Test location | /workspace/coverage/default/0.chip_sw_usbdev_stream.3306160042 |
| Short name | T383 |
| Test name | |
| Test status | |
| Simulation time | 19114320684 ps |
| CPU time | 4699.53 seconds |
| Started | Jul 03 07:49:15 PM PDT 24 |
| Finished | Jul 03 09:07:36 PM PDT 24 |
| Peak memory | 610612 kb |
| Host | smart-80cfc3e1-b31b-4a10-85f5-8e7ceef0f145 |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_test_timeout_ns=60_000_000 +sw_build_device=sim_dv +sw_images=usbdev_stream_test:1:new_ru les,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim. tcl +ntb_random_seed=3306160042 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_stream_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_stream.3306160042 |
| Directory | /workspace/0.chip_sw_usbdev_stream/latest |
| Test location | /workspace/coverage/default/0.chip_sw_usbdev_vbus.243271946 |
| Short name | T1199 |
| Test name | |
| Test status | |
| Simulation time | 2771290396 ps |
| CPU time | 302.34 seconds |
| Started | Jul 03 07:48:23 PM PDT 24 |
| Finished | Jul 03 07:53:26 PM PDT 24 |
| Peak memory | 610672 kb |
| Host | smart-058ef66d-aa00-4bf5-a9ab-3c4f19df50bc |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=usbdev_vbus_test:1:new_rules,test_rom:0 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=243271946 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_vbus.243271946 |
| Directory | /workspace/0.chip_sw_usbdev_vbus/latest |
| Test location | /workspace/coverage/default/0.chip_tap_straps_dev.1417508783 |
| Short name | T996 |
| Test name | |
| Test status | |
| Simulation time | 5906883650 ps |
| CPU time | 571.82 seconds |
| Started | Jul 03 07:49:33 PM PDT 24 |
| Finished | Jul 03 07:59:06 PM PDT 24 |
| Peak memory | 623948 kb |
| Host | smart-14a81a34-faca-4857-842b-101edfead126 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStDev +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom: new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1417508783 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_tap_straps_dev.1417508783 |
| Directory | /workspace/0.chip_tap_straps_dev/latest |
| Test location | /workspace/coverage/default/0.chip_tap_straps_prod.329508013 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 11039469468 ps |
| CPU time | 1280.37 seconds |
| Started | Jul 03 07:53:33 PM PDT 24 |
| Finished | Jul 03 08:14:54 PM PDT 24 |
| Peak memory | 623980 kb |
| Host | smart-e86302a6-9750-43bb-b0fa-32627e482898 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom :new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=329508013 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_tap_straps_prod.329508013 |
| Directory | /workspace/0.chip_tap_straps_prod/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_asm_init_dev.3944229536 |
| Short name | T1271 |
| Test name | |
| Test status | |
| Simulation time | 15061916320 ps |
| CPU time | 3508.55 seconds |
| Started | Jul 03 07:57:39 PM PDT 24 |
| Finished | Jul 03 08:56:08 PM PDT 24 |
| Peak memory | 610804 kb |
| Host | smart-a8a89336-273e-4b38-b4f8-4505540d284c |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_dev:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3944229536 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S EQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_asm_init_dev.3944229536 |
| Directory | /workspace/0.rom_e2e_asm_init_dev/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_asm_init_prod.2657383853 |
| Short name | T365 |
| Test name | |
| Test status | |
| Simulation time | 15935804693 ps |
| CPU time | 3035.68 seconds |
| Started | Jul 03 07:55:44 PM PDT 24 |
| Finished | Jul 03 08:46:21 PM PDT 24 |
| Peak memory | 610776 kb |
| Host | smart-37e3181d-b49d-4587-a5a8-566280272df7 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2657383853 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_ SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_asm_init_prod.2657383853 |
| Directory | /workspace/0.rom_e2e_asm_init_prod/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_asm_init_prod_end.2608737438 |
| Short name | T1095 |
| Test name | |
| Test status | |
| Simulation time | 15183045022 ps |
| CPU time | 3191.96 seconds |
| Started | Jul 03 07:55:37 PM PDT 24 |
| Finished | Jul 03 08:48:50 PM PDT 24 |
| Peak memory | 610780 kb |
| Host | smart-071f2fee-9be3-4744-9d95-aeafe7a56706 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_prod_end:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2608737438 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_T EST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 0.rom_e2e_asm_init_prod_end.2608737438 |
| Directory | /workspace/0.rom_e2e_asm_init_prod_end/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_asm_init_rma.1772458049 |
| Short name | T1026 |
| Test name | |
| Test status | |
| Simulation time | 14904625760 ps |
| CPU time | 3826.97 seconds |
| Started | Jul 03 07:56:45 PM PDT 24 |
| Finished | Jul 03 09:00:33 PM PDT 24 |
| Peak memory | 610868 kb |
| Host | smart-dac09816-ea2d-443d-b79a-f78369b7ea55 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1772458049 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S EQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_asm_init_rma.1772458049 |
| Directory | /workspace/0.rom_e2e_asm_init_rma/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_asm_init_test_unlocked0.2097939021 |
| Short name | T862 |
| Test name | |
| Test status | |
| Simulation time | 11901763996 ps |
| CPU time | 3339.61 seconds |
| Started | Jul 03 07:58:38 PM PDT 24 |
| Finished | Jul 03 08:54:18 PM PDT 24 |
| Peak memory | 610856 kb |
| Host | smart-23b83ee4-e9fa-4715-8a2e-beeed7542701 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=410_000_000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2097939021 -assert nopostproc +UVM_TESTNAME=chip_base_te st +UVM_TEST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 0.rom_e2e_asm_init_test_unlocked0.2097939021 |
| Directory | /workspace/0.rom_e2e_asm_init_test_unlocked0/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.1223610677 |
| Short name | T1164 |
| Test name | |
| Test status | |
| Simulation time | 24457671318 ps |
| CPU time | 5962.52 seconds |
| Started | Jul 03 08:00:52 PM PDT 24 |
| Finished | Jul 03 09:40:15 PM PDT 24 |
| Peak memory | 608780 kb |
| Host | smart-b3439bc8-0046-434c-ab76-7786f1a32a36 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_dev:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=1223610677 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.1223610677 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.293427402 |
| Short name | T304 |
| Test name | |
| Test status | |
| Simulation time | 24529578252 ps |
| CPU time | 5968.3 seconds |
| Started | Jul 03 07:55:22 PM PDT 24 |
| Finished | Jul 03 09:34:52 PM PDT 24 |
| Peak memory | 608912 kb |
| Host | smart-754ce643-e06a-4f1a-a17d-593893850c0c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_prod_end:4,mask_r om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=293427402 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.293427402 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.2291900587 |
| Short name | T373 |
| Test name | |
| Test status | |
| Simulation time | 22806263896 ps |
| CPU time | 5653.67 seconds |
| Started | Jul 03 07:56:27 PM PDT 24 |
| Finished | Jul 03 09:30:42 PM PDT 24 |
| Peak memory | 608784 kb |
| Host | smart-87f3e40a-41bd-4e51-9fd0-0dca356c5d6a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=2291900587 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.2291900587 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.3505330116 |
| Short name | T1028 |
| Test name | |
| Test status | |
| Simulation time | 18040125280 ps |
| CPU time | 6407.74 seconds |
| Started | Jul 03 07:59:16 PM PDT 24 |
| Finished | Jul 03 09:46:06 PM PDT 24 |
| Peak memory | 608292 kb |
| Host | smart-3e9bc70a-e89b-40b7-931d-15adaa644870 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=410_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_test_unlocked0:4, mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3505330116 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.3505330116 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.2598743725 |
| Short name | T992 |
| Test name | |
| Test status | |
| Simulation time | 15781783416 ps |
| CPU time | 4245.19 seconds |
| Started | Jul 03 08:00:17 PM PDT 24 |
| Finished | Jul 03 09:11:03 PM PDT 24 |
| Peak memory | 608828 kb |
| Host | smart-ef14909b-1f6d-49ab-9c1c-77953d74e377 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_boot_policy_valid_dev:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=2598743725 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.2598743725 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.3922860715 |
| Short name | T978 |
| Test name | |
| Test status | |
| Simulation time | 15068258730 ps |
| CPU time | 4618.63 seconds |
| Started | Jul 03 08:02:14 PM PDT 24 |
| Finished | Jul 03 09:19:14 PM PDT 24 |
| Peak memory | 608984 kb |
| Host | smart-1334ad9f-de59-4d46-b34d-24e4353eefd9 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_boot_policy_valid_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3922860715 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.3922860715 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.3320056973 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 15505669064 ps |
| CPU time | 3795.72 seconds |
| Started | Jul 03 07:57:00 PM PDT 24 |
| Finished | Jul 03 09:00:17 PM PDT 24 |
| Peak memory | 608768 kb |
| Host | smart-8051be14-4850-4813-a251-1eaed33f9bdc |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_boot_policy_valid_prod_end:4,mask_r om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=3320056973 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.3320056973 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.201212407 |
| Short name | T1155 |
| Test name | |
| Test status | |
| Simulation time | 14866830486 ps |
| CPU time | 3502.49 seconds |
| Started | Jul 03 07:55:17 PM PDT 24 |
| Finished | Jul 03 08:53:40 PM PDT 24 |
| Peak memory | 608668 kb |
| Host | smart-68319052-a80f-4807-bf1d-6f5b503bb331 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_boot_policy_valid_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=201212407 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.201212407 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.2127155510 |
| Short name | T1170 |
| Test name | |
| Test status | |
| Simulation time | 11084953706 ps |
| CPU time | 2917.36 seconds |
| Started | Jul 03 07:57:13 PM PDT 24 |
| Finished | Jul 03 08:45:52 PM PDT 24 |
| Peak memory | 608364 kb |
| Host | smart-7f294d50-8734-40ed-ae4e-d19677d2bae7 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=410_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_boot_policy_valid_test_unlocked0:4, mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2127155510 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.2127155510 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_dev.2242770039 |
| Short name | T1254 |
| Test name | |
| Test status | |
| Simulation time | 15425309680 ps |
| CPU time | 3701.28 seconds |
| Started | Jul 03 07:58:54 PM PDT 24 |
| Finished | Jul 03 09:00:36 PM PDT 24 |
| Peak memory | 608924 kb |
| Host | smart-0d1b0370-383c-48c2-94c6-34a2b8643442 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_dev:4,mask_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2242770039 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_good_dev.2242770039 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_good_b_good_dev/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_prod.3815882045 |
| Short name | T972 |
| Test name | |
| Test status | |
| Simulation time | 15406803440 ps |
| CPU time | 4722.83 seconds |
| Started | Jul 03 08:02:18 PM PDT 24 |
| Finished | Jul 03 09:21:03 PM PDT 24 |
| Peak memory | 608940 kb |
| Host | smart-bb2c07f3-904e-4e44-a872-e27eb7b23cd8 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_prod:4,mask_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3815882045 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/ coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_good_prod.3815882045 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_good_b_good_prod/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_prod_end.2226454335 |
| Short name | T1206 |
| Test name | |
| Test status | |
| Simulation time | 15804490600 ps |
| CPU time | 3958.42 seconds |
| Started | Jul 03 07:56:24 PM PDT 24 |
| Finished | Jul 03 09:02:23 PM PDT 24 |
| Peak memory | 608780 kb |
| Host | smart-68f0b2cb-e2a9-44eb-be30-5ad9775015a2 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_prod_end:4,mask_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=222645 4335 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_good_prod_end.2226454335 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_good_b_good_prod_end/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_rma.3353532933 |
| Short name | T1100 |
| Test name | |
| Test status | |
| Simulation time | 14877745680 ps |
| CPU time | 3892.3 seconds |
| Started | Jul 03 07:59:12 PM PDT 24 |
| Finished | Jul 03 09:04:05 PM PDT 24 |
| Peak memory | 609420 kb |
| Host | smart-bf88d285-6b91-4600-b486-033800b27270 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_rma:4,mask_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3353532933 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_good_rma.3353532933 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_good_b_good_rma/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0.230782417 |
| Short name | T265 |
| Test name | |
| Test status | |
| Simulation time | 11515907620 ps |
| CPU time | 2887.71 seconds |
| Started | Jul 03 07:56:12 PM PDT 24 |
| Finished | Jul 03 08:44:20 PM PDT 24 |
| Peak memory | 609316 kb |
| Host | smart-5da9a4eb-9732-4a55-9d61-ee83ffe3d6b4 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=410_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_test_unlocked0:4,mask_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 230782417 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0.230782417 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_jtag_inject_dev.3008165888 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 23988869029 ps |
| CPU time | 2972.57 seconds |
| Started | Jul 03 07:52:37 PM PDT 24 |
| Finished | Jul 03 08:42:10 PM PDT 24 |
| Peak memory | 618384 kb |
| Host | smart-81d2030b-5f82-4bb6-a178-5db29949dfeb |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_jtag_dmi=1 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=img_dev_exec_di sabled:4,sram_program:5,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3008165888 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_jtag_inject_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_jtag_inject_dev.3008165888 |
| Directory | /workspace/0.rom_e2e_jtag_inject_dev/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_jtag_inject_rma.2596256326 |
| Short name | T256 |
| Test name | |
| Test status | |
| Simulation time | 24291381339 ps |
| CPU time | 2258.19 seconds |
| Started | Jul 03 07:55:36 PM PDT 24 |
| Finished | Jul 03 08:33:15 PM PDT 24 |
| Peak memory | 618300 kb |
| Host | smart-82e65d81-b474-40b0-a715-9e1a26bec5e2 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_jtag_dmi=1 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=img_rma_exec_di sabled:4,sram_program:5,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2596256326 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_jtag_inject_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_jtag_inject_rma.2596256326 |
| Directory | /workspace/0.rom_e2e_jtag_inject_rma/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_jtag_inject_test_unlocked0.2154396741 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 32295396377 ps |
| CPU time | 2407.46 seconds |
| Started | Jul 03 07:51:15 PM PDT 24 |
| Finished | Jul 03 08:31:24 PM PDT 24 |
| Peak memory | 619316 kb |
| Host | smart-4ac161a9-9d4c-4e57-80c1-32afdfb922ac |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_jtag_dmi=1 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=img_test_unlock ed0_exec_disabled:4,sram_program:5,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2154396741 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_jtag_ inject_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_jtag_inject _test_unlocked0.2154396741 |
| Directory | /workspace/0.rom_e2e_jtag_inject_test_unlocked0/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_invalid_meas.904294760 |
| Short name | T897 |
| Test name | |
| Test status | |
| Simulation time | 14795240500 ps |
| CPU time | 3667.17 seconds |
| Started | Jul 03 07:58:34 PM PDT 24 |
| Finished | Jul 03 08:59:42 PM PDT 24 |
| Peak memory | 610796 kb |
| Host | smart-e3955c79-b978-4187-968d-d09015dae351 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_invalid _meas:1:new_rules,otp_img_keymgr_otp_invalid_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=904294760 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_ sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_keymgr_ini t_rom_ext_invalid_meas.904294760 |
| Directory | /workspace/0.rom_e2e_keymgr_init_rom_ext_invalid_meas/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_meas.1474017937 |
| Short name | T1133 |
| Test name | |
| Test status | |
| Simulation time | 14968480000 ps |
| CPU time | 3805.28 seconds |
| Started | Jul 03 07:56:35 PM PDT 24 |
| Finished | Jul 03 09:00:01 PM PDT 24 |
| Peak memory | 608460 kb |
| Host | smart-ec386e0e-89c7-4707-92e9-fbee08076165 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_meas:1: new_rules,otp_img_keymgr_otp_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1474017937 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_keymgr_init_rom_ext_meas.1474017937 |
| Directory | /workspace/0.rom_e2e_keymgr_init_rom_ext_meas/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_no_meas.3748303251 |
| Short name | T983 |
| Test name | |
| Test status | |
| Simulation time | 14892199166 ps |
| CPU time | 3717.19 seconds |
| Started | Jul 03 07:57:24 PM PDT 24 |
| Finished | Jul 03 08:59:22 PM PDT 24 |
| Peak memory | 608480 kb |
| Host | smart-a2d51cbd-8f41-4298-8267-35185f205b3c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_no_meas :1:new_rules,otp_img_keymgr_otp_no_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3748303251 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_keymgr_init_rom_ext _no_meas.3748303251 |
| Directory | /workspace/0.rom_e2e_keymgr_init_rom_ext_no_meas/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_shutdown_exception_c.2720578888 |
| Short name | T860 |
| Test name | |
| Test status | |
| Simulation time | 14982748488 ps |
| CPU time | 3673.1 seconds |
| Started | Jul 03 07:57:05 PM PDT 24 |
| Finished | Jul 03 08:58:19 PM PDT 24 |
| Peak memory | 611180 kb |
| Host | smart-cdd1b919-966e-4966-b7d2-533ba872cf7c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_shutdown_exception_c:1:ne w_rules,otp_img_secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2720578888 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_shu tdown_exception_c_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_ shutdown_exception_c.2720578888 |
| Directory | /workspace/0.rom_e2e_shutdown_exception_c/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_shutdown_output.392113293 |
| Short name | T1008 |
| Test name | |
| Test status | |
| Simulation time | 28001482560 ps |
| CPU time | 3700.62 seconds |
| Started | Jul 03 07:55:31 PM PDT 24 |
| Finished | Jul 03 08:57:12 PM PDT 24 |
| Peak memory | 611140 kb |
| Host | smart-3caff0ef-3573-45eb-b6d7-9dd99fcba595 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_unsigned:1:ot_f lash_binary,otp_img_shutdown_output_test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=392113293 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip _sw_rom_e2e_shutdown_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_shutdown_output.392113293 |
| Directory | /workspace/0.rom_e2e_shutdown_output/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_dev.4017588752 |
| Short name | T933 |
| Test name | |
| Test status | |
| Simulation time | 23357964050 ps |
| CPU time | 5799.33 seconds |
| Started | Jul 03 07:59:39 PM PDT 24 |
| Finished | Jul 03 09:36:19 PM PDT 24 |
| Peak memory | 609552 kb |
| Host | smart-d4349968-0060-45a3-bbbc-7e53e19d6306 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_dev_key_0,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_dev_key_0,otp_img_sigverify_always_dev :4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=4017588752 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b_b ad_dev.4017588752 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_bad_b_bad_dev/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_prod.1776533062 |
| Short name | T1081 |
| Test name | |
| Test status | |
| Simulation time | 23337674802 ps |
| CPU time | 5694.44 seconds |
| Started | Jul 03 07:59:56 PM PDT 24 |
| Finished | Jul 03 09:34:52 PM PDT 24 |
| Peak memory | 609752 kb |
| Host | smart-cf4d397b-4e87-4f37-af4c-b13f4b67bdc6 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_p rod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si m.tcl +ntb_random_seed=1776533062 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_ b_bad_prod.1776533062 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_bad_b_bad_prod/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_prod_end.609628151 |
| Short name | T406 |
| Test name | |
| Test status | |
| Simulation time | 23628341294 ps |
| CPU time | 6464.87 seconds |
| Started | Jul 03 07:59:14 PM PDT 24 |
| Finished | Jul 03 09:47:00 PM PDT 24 |
| Peak memory | 609524 kb |
| Host | smart-59cefefe-411e-486f-b88c-3fcba68165ec |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_p rod_end:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tool s/sim.tcl +ntb_random_seed=609628151 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_b ad_b_bad_prod_end.609628151 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_bad_b_bad_prod_end/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_rma.3171392217 |
| Short name | T977 |
| Test name | |
| Test status | |
| Simulation time | 23108901000 ps |
| CPU time | 6261.96 seconds |
| Started | Jul 03 07:57:57 PM PDT 24 |
| Finished | Jul 03 09:42:20 PM PDT 24 |
| Peak memory | 609744 kb |
| Host | smart-1408f10d-7308-414c-babb-46185bbc2229 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_r ma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim .tcl +ntb_random_seed=3171392217 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b _bad_rma.3171392217 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_bad_b_bad_rma/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0.1184198206 |
| Short name | T1232 |
| Test name | |
| Test status | |
| Simulation time | 17311901059 ps |
| CPU time | 4996.93 seconds |
| Started | Jul 03 08:02:29 PM PDT 24 |
| Finished | Jul 03 09:25:47 PM PDT 24 |
| Peak memory | 609884 kb |
| Host | smart-46095a9a-c93d-4ce0-a4ee-f6c8adaf68cc |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=600_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_test_key_0,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_test_key_0,otp_img_sigverify_always_t est_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d v/tools/sim.tcl +ntb_random_seed=1184198206 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b _bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_alw ays_a_bad_b_bad_test_unlocked0.1184198206 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_dev.4006825052 |
| Short name | T973 |
| Test name | |
| Test status | |
| Simulation time | 14739233962 ps |
| CPU time | 3852.64 seconds |
| Started | Jul 03 07:56:41 PM PDT 24 |
| Finished | Jul 03 09:00:54 PM PDT 24 |
| Peak memory | 610852 kb |
| Host | smart-a7e03aa6-78e1-4213-973d-37d1b8dab00b |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_dev_key_0,otp_img_sigverify_always_dev:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4006825052 -assert nopostproc +UVM_TESTNAME=chip_base_ test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b_nothing_dev.4006825052 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_bad_b_nothing_dev/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod.3717150858 |
| Short name | T1029 |
| Test name | |
| Test status | |
| Simulation time | 14784414671 ps |
| CPU time | 4195.63 seconds |
| Started | Jul 03 08:01:24 PM PDT 24 |
| Finished | Jul 03 09:11:21 PM PDT 24 |
| Peak memory | 610832 kb |
| Host | smart-83d57377-18a0-43e5-96e7-c77286ec77fa |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3717150858 -assert nopostproc +UVM_TESTNAME=chip_bas e_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d efault.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b_nothing_prod.3717150858 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod_end.837146871 |
| Short name | T896 |
| Test name | |
| Test status | |
| Simulation time | 14679732525 ps |
| CPU time | 3507.2 seconds |
| Started | Jul 03 07:56:39 PM PDT 24 |
| Finished | Jul 03 08:55:07 PM PDT 24 |
| Peak memory | 610728 kb |
| Host | smart-32dd2fa7-d8ca-48c3-90fc-6c635606365a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_prod_end:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=837146871 -assert nopostproc +UVM_TESTNAME=chip_ base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b_nothing_prod_end.837146871 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod_end/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_rma.1691392428 |
| Short name | T268 |
| Test name | |
| Test status | |
| Simulation time | 14319759852 ps |
| CPU time | 3476.22 seconds |
| Started | Jul 03 07:57:35 PM PDT 24 |
| Finished | Jul 03 08:55:32 PM PDT 24 |
| Peak memory | 609344 kb |
| Host | smart-a4f28cca-e76a-4858-8b33-09ec1beb17aa |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1691392428 -assert nopostproc +UVM_TESTNAME=chip_base _test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b_nothing_rma.1691392428 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_bad_b_nothing_rma/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.1843470751 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 12117206922 ps |
| CPU time | 2543.46 seconds |
| Started | Jul 03 07:55:12 PM PDT 24 |
| Finished | Jul 03 08:37:36 PM PDT 24 |
| Peak memory | 608444 kb |
| Host | smart-ec570a85-b6ef-41e4-8db8-3e492c040f69 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=410_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_test_key_0:new_rules,otp_img_sigverify_always_test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1843470751 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.1843470751 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.425452936 |
| Short name | T952 |
| Test name | |
| Test status | |
| Simulation time | 14457899691 ps |
| CPU time | 3486.98 seconds |
| Started | Jul 03 07:55:56 PM PDT 24 |
| Finished | Jul 03 08:54:04 PM PDT 24 |
| Peak memory | 610716 kb |
| Host | smart-4a7e5231-3e4a-45b3-8f05-af3b265d3cfd |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_b_corrupted:1: ot_flash_binary:signed:fake_ecdsa_dev_key_0,otp_img_sigverify_always_dev:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425452936 -assert nopostproc +UVM_TESTNAME=chip_base_t est +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa ult.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.425452936 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.357792421 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 15537642564 ps |
| CPU time | 4403.25 seconds |
| Started | Jul 03 08:01:45 PM PDT 24 |
| Finished | Jul 03 09:15:10 PM PDT 24 |
| Peak memory | 610844 kb |
| Host | smart-66f16688-41bc-4386-9742-fbfdcbe285ce |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_b_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=357792421 -assert nopostproc +UVM_TESTNAME=chip_base _test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.357792421 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.3027288280 |
| Short name | T267 |
| Test name | |
| Test status | |
| Simulation time | 14565020675 ps |
| CPU time | 4268.06 seconds |
| Started | Jul 03 08:00:38 PM PDT 24 |
| Finished | Jul 03 09:11:47 PM PDT 24 |
| Peak memory | 610740 kb |
| Host | smart-66209733-2310-4edc-8816-ee244ea4f912 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_b_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_prod_end:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3027288280 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.3027288280 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_rma.545449541 |
| Short name | T890 |
| Test name | |
| Test status | |
| Simulation time | 13431233548 ps |
| CPU time | 3465.25 seconds |
| Started | Jul 03 08:02:10 PM PDT 24 |
| Finished | Jul 03 08:59:56 PM PDT 24 |
| Peak memory | 610740 kb |
| Host | smart-0057e63a-a5a9-4bc5-a485-3a7ff993fe72 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_b_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=545449541 -assert nopostproc +UVM_TESTNAME=chip_base_ test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_nothing_b_bad_rma.545449541 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_nothing_b_bad_rma/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0.3299237523 |
| Short name | T935 |
| Test name | |
| Test status | |
| Simulation time | 11313309043 ps |
| CPU time | 3055.39 seconds |
| Started | Jul 03 07:56:07 PM PDT 24 |
| Finished | Jul 03 08:47:03 PM PDT 24 |
| Peak memory | 609536 kb |
| Host | smart-906283a9-148d-45c2-8a61-4f3914e0df42 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=410_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_b_corrupted:1: ot_flash_binary:signed:fake_ecdsa_test_key_0,otp_img_sigverify_always_test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3299237523 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/ coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0.3299237523 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_smoke.1143061668 |
| Short name | T910 |
| Test name | |
| Test status | |
| Simulation time | 15083641612 ps |
| CPU time | 3614.46 seconds |
| Started | Jul 03 07:54:43 PM PDT 24 |
| Finished | Jul 03 08:54:59 PM PDT 24 |
| Peak memory | 608460 kb |
| Host | smart-128c91d1-808d-4124-9cc3-4a104a831459 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_smoke:1:new_rules,otp_img _secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_to p/hw/dv/tools/sim.tcl +ntb_random_seed=1143061668 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_smoke.1143061668 |
| Directory | /workspace/0.rom_e2e_smoke/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_static_critical.2605910318 |
| Short name | T1111 |
| Test name | |
| Test status | |
| Simulation time | 17652879408 ps |
| CPU time | 4784.92 seconds |
| Started | Jul 03 07:58:17 PM PDT 24 |
| Finished | Jul 03 09:18:04 PM PDT 24 |
| Peak memory | 608532 kb |
| Host | smart-1fe9ac15-b559-45ce-8586-c469e5cb7d31 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_static_critical:1:new_rul es,otp_img_secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2605910318 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_static_critical.2605910318 |
| Directory | /workspace/0.rom_e2e_static_critical/latest |
| Test location | /workspace/coverage/default/0.rom_keymgr_functest.4002596294 |
| Short name | T870 |
| Test name | |
| Test status | |
| Simulation time | 5664805450 ps |
| CPU time | 696.31 seconds |
| Started | Jul 03 07:55:07 PM PDT 24 |
| Finished | Jul 03 08:06:44 PM PDT 24 |
| Peak memory | 610628 kb |
| Host | smart-cef7035b-a231-4854-95b4-9d78716d3907 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=10_000_000 +sw_build_device=sim_dv +sw_images=keymgr_functest:1:new_rules,test_rom:0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4002596294 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 0.rom_keymgr_functest.4002596294 |
| Directory | /workspace/0.rom_keymgr_functest/latest |
| Test location | /workspace/coverage/default/0.rom_volatile_raw_unlock.578144967 |
| Short name | T1262 |
| Test name | |
| Test status | |
| Simulation time | 2442905324 ps |
| CPU time | 126.14 seconds |
| Started | Jul 03 07:55:43 PM PDT 24 |
| Finished | Jul 03 07:57:50 PM PDT 24 |
| Peak memory | 614920 kb |
| Host | smart-13f614d5-e853-4da6-a1ea-85f128239d61 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceExternal48Mhz +rom_prod_mode=1 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_test_key_0:1:ot_flash_binary,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=578144967 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage /default.vdb -cm_log /dev/null -cm_name 0.rom_volatile_raw_unlock.578144967 |
| Directory | /workspace/0.rom_volatile_raw_unlock/latest |
| Test location | /workspace/coverage/default/1.chip_jtag_csr_rw.621470333 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 18972154420 ps |
| CPU time | 2512.3 seconds |
| Started | Jul 03 07:53:31 PM PDT 24 |
| Finished | Jul 03 08:35:24 PM PDT 24 |
| Peak memory | 607988 kb |
| Host | smart-a662c69b-c9a9-44fe-9711-514fd21a805f |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +csr_rw +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=621470333 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_jtag_csr_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.ch ip_jtag_csr_rw.621470333 |
| Directory | /workspace/1.chip_jtag_csr_rw/latest |
| Test location | /workspace/coverage/default/1.chip_jtag_mem_access.1029055885 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 13720609040 ps |
| CPU time | 1693.63 seconds |
| Started | Jul 03 07:53:37 PM PDT 24 |
| Finished | Jul 03 08:21:51 PM PDT 24 |
| Peak memory | 607788 kb |
| Host | smart-10d5d526-8460-41de-b029-e3bfd21b59d4 |
| User | root |
| Command | /workspace/default/simv +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1029055885 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_jtag_ mem_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_jtag_mem_access.1 029055885 |
| Directory | /workspace/1.chip_jtag_mem_access/latest |
| Test location | /workspace/coverage/default/1.chip_rv_dm_ndm_reset_req.3719752883 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 4513445200 ps |
| CPU time | 627.68 seconds |
| Started | Jul 03 08:01:14 PM PDT 24 |
| Finished | Jul 03 08:11:42 PM PDT 24 |
| Peak memory | 618228 kb |
| Host | smart-4bdd5648-bc2b-4584-b4e2-898fa8a0ce2f |
| User | root |
| Command | /workspace/default/simv +en_scb_tl_err_chk=0 +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_ndm_reset_req_rma:1:new_rules,test_rom:0 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3 719752883 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_rv_dm_ndm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_rv_dm_ndm_reset_req.3719752883 |
| Directory | /workspace/1.chip_rv_dm_ndm_reset_req/latest |
| Test location | /workspace/coverage/default/1.chip_sival_flash_info_access.994217210 |
| Short name | T332 |
| Test name | |
| Test status | |
| Simulation time | 3571525932 ps |
| CPU time | 334.19 seconds |
| Started | Jul 03 07:52:07 PM PDT 24 |
| Finished | Jul 03 07:57:42 PM PDT 24 |
| Peak memory | 610628 kb |
| Host | smart-7c735372-4274-4045-bbdd-a3c40fd42e4d |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +sw_build_device=sim_dv +sw_images=flash_ctrl_info_access_lc:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s eed=994217210 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sival_flash_info_access.994217210 |
| Directory | /workspace/1.chip_sival_flash_info_access/latest |
| Test location | /workspace/coverage/default/1.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.3399889038 |
| Short name | T1241 |
| Test name | |
| Test status | |
| Simulation time | 19022938320 ps |
| CPU time | 569.38 seconds |
| Started | Jul 03 07:56:46 PM PDT 24 |
| Finished | Jul 03 08:06:16 PM PDT 24 |
| Peak memory | 618996 kb |
| Host | smart-c2d189b1-62f8-4321-82db-cb9b778c73b3 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=adc_ctrl_sleep_debug_cable_wakeup_test:1:new_rules,test_rom: 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=3399889038 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.3399889038 |
| Directory | /workspace/1.chip_sw_adc_ctrl_sleep_debug_cable_wakeup/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aes_enc.3468610264 |
| Short name | T928 |
| Test name | |
| Test status | |
| Simulation time | 3434343630 ps |
| CPU time | 234.98 seconds |
| Started | Jul 03 08:03:20 PM PDT 24 |
| Finished | Jul 03 08:07:17 PM PDT 24 |
| Peak memory | 610652 kb |
| Host | smart-73ac0e80-3fee-43c5-9177-8f3a7d193b19 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=22_000_000 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3468610264 -asser t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aes_enc.3468610264 |
| Directory | /workspace/1.chip_sw_aes_enc/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aes_enc_jitter_en.1738083739 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 3086173534 ps |
| CPU time | 295.45 seconds |
| Started | Jul 03 07:55:34 PM PDT 24 |
| Finished | Jul 03 08:00:30 PM PDT 24 |
| Peak memory | 610660 kb |
| Host | smart-d67ab8f5-a866-40c0-8f20-d8f171355458 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=26_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1738 083739 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work space/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aes_enc_jitter_en.1738083739 |
| Directory | /workspace/1.chip_sw_aes_enc_jitter_en/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aes_enc_jitter_en_reduced_freq.565591702 |
| Short name | T1195 |
| Test name | |
| Test status | |
| Simulation time | 3507529205 ps |
| CPU time | 313.63 seconds |
| Started | Jul 03 08:03:06 PM PDT 24 |
| Finished | Jul 03 08:08:20 PM PDT 24 |
| Peak memory | 608896 kb |
| Host | smart-7ebbd7bd-a589-4d71-9b1d-86a70f2ca286 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=26_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules, test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=565591702 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aes_enc_jitter_en_reduced_freq.565591702 |
| Directory | /workspace/1.chip_sw_aes_enc_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aes_entropy.2047702358 |
| Short name | T1266 |
| Test name | |
| Test status | |
| Simulation time | 3054759460 ps |
| CPU time | 364.59 seconds |
| Started | Jul 03 08:00:15 PM PDT 24 |
| Finished | Jul 03 08:06:21 PM PDT 24 |
| Peak memory | 610580 kb |
| Host | smart-7b719cde-33de-46c5-b3e7-11469f2348bc |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=aes_entropy_test:1:new_rules,test_rom:0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2047702358 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove rage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aes_entropy.2047702358 |
| Directory | /workspace/1.chip_sw_aes_entropy/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aes_idle.35159254 |
| Short name | T1160 |
| Test name | |
| Test status | |
| Simulation time | 3262348508 ps |
| CPU time | 245.06 seconds |
| Started | Jul 03 07:58:13 PM PDT 24 |
| Finished | Jul 03 08:02:18 PM PDT 24 |
| Peak memory | 610640 kb |
| Host | smart-3b298b62-60bc-47e1-8fcc-193d32ca46d6 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=25_000_000 +sw_build_device=sim_dv +sw_images=aes_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35159254 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/ default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aes_idle.35159254 |
| Directory | /workspace/1.chip_sw_aes_idle/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aes_masking_off.3986267719 |
| Short name | T943 |
| Test name | |
| Test status | |
| Simulation time | 2660770878 ps |
| CPU time | 408.42 seconds |
| Started | Jul 03 07:57:14 PM PDT 24 |
| Finished | Jul 03 08:04:03 PM PDT 24 |
| Peak memory | 610716 kb |
| Host | smart-c7371248-3d93-45d9-a953-f488a001aa6f |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=aes_masking_off_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3986267719 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_aes_masking_off_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aes_masking_off.3986267719 |
| Directory | /workspace/1.chip_sw_aes_masking_off/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aes_smoketest.5366323 |
| Short name | T881 |
| Test name | |
| Test status | |
| Simulation time | 3278208680 ps |
| CPU time | 331.96 seconds |
| Started | Jul 03 08:03:43 PM PDT 24 |
| Finished | Jul 03 08:09:16 PM PDT 24 |
| Peak memory | 608660 kb |
| Host | smart-dd357a6a-9730-451c-8552-3242e89683b6 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5366323 -assert nopostproc +UVM_TESTNAME=chip_ba se_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 1.chip_sw_aes_smoketest.5366323 |
| Directory | /workspace/1.chip_sw_aes_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_alert_handler_entropy.1240942253 |
| Short name | T1128 |
| Test name | |
| Test status | |
| Simulation time | 3748265848 ps |
| CPU time | 290.48 seconds |
| Started | Jul 03 07:56:48 PM PDT 24 |
| Finished | Jul 03 08:01:39 PM PDT 24 |
| Peak memory | 609128 kb |
| Host | smart-af865240-2895-497d-aa2f-b37a230946c4 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler_entropy_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1240942253 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_entropy.1240942253 |
| Directory | /workspace/1.chip_sw_alert_handler_entropy/latest |
| Test location | /workspace/coverage/default/1.chip_sw_alert_handler_escalation.1615059912 |
| Short name | T941 |
| Test name | |
| Test status | |
| Simulation time | 5303806408 ps |
| CPU time | 605.1 seconds |
| Started | Jul 03 07:58:47 PM PDT 24 |
| Finished | Jul 03 08:08:53 PM PDT 24 |
| Peak memory | 618720 kb |
| Host | smart-0e693023-7392-4662-8b7b-f36d83f9e268 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler_escalation_test:1:new_rules,test _rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb _random_seed=1615059912 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_escalation_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_escalation.1615059912 |
| Directory | /workspace/1.chip_sw_alert_handler_escalation/latest |
| Test location | /workspace/coverage/default/1.chip_sw_alert_handler_lpg_clkoff.2121906305 |
| Short name | T1257 |
| Test name | |
| Test status | |
| Simulation time | 5902185240 ps |
| CPU time | 1595.82 seconds |
| Started | Jul 03 07:57:14 PM PDT 24 |
| Finished | Jul 03 08:23:50 PM PDT 24 |
| Peak memory | 609360 kb |
| Host | smart-a6210d22-1f62-4604-b5e1-5d6fa62f116a |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_lpg_clkoff_test:1:new_rules,test_r om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=2121906305 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_lpg_clkoff_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_lpg_clkoff.2121906305 |
| Directory | /workspace/1.chip_sw_alert_handler_lpg_clkoff/latest |
| Test location | /workspace/coverage/default/1.chip_sw_alert_handler_lpg_reset_toggle.3943475881 |
| Short name | T1048 |
| Test name | |
| Test status | |
| Simulation time | 7017685992 ps |
| CPU time | 1646.86 seconds |
| Started | Jul 03 07:56:36 PM PDT 24 |
| Finished | Jul 03 08:24:04 PM PDT 24 |
| Peak memory | 608376 kb |
| Host | smart-eb786aa7-a76b-4434-a1bf-7c970c4b3a99 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_lpg_reset_toggle_test:1:new_rules, test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3943475881 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_shorten_ping_wait_cycle_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_lpg_reset_togg le.3943475881 |
| Directory | /workspace/1.chip_sw_alert_handler_lpg_reset_toggle/latest |
| Test location | /workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_pings.2049657684 |
| Short name | T1204 |
| Test name | |
| Test status | |
| Simulation time | 11820016036 ps |
| CPU time | 1672.49 seconds |
| Started | Jul 03 07:58:10 PM PDT 24 |
| Finished | Jul 03 08:26:03 PM PDT 24 |
| Peak memory | 610284 kb |
| Host | smart-3e939569-eca8-4af5-a719-c7a877952880 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler _lpg_sleep_mode_pings_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2049657684 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_han dler_shorten_ping_wait_cycle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_lpg_sleep_mode_pings.2049657684 |
| Directory | /workspace/1.chip_sw_alert_handler_lpg_sleep_mode_pings/latest |
| Test location | /workspace/coverage/default/1.chip_sw_alert_handler_ping_ok.3007948105 |
| Short name | T1220 |
| Test name | |
| Test status | |
| Simulation time | 7453856560 ps |
| CPU time | 1505.82 seconds |
| Started | Jul 03 07:57:08 PM PDT 24 |
| Finished | Jul 03 08:22:14 PM PDT 24 |
| Peak memory | 609768 kb |
| Host | smart-78784878-67d1-4eae-8d32-5d2ce75d735e |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=24000000 +sw_build_device=sim_dv +sw_images=alert_handler_ping_ok_test:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s eed=3007948105 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_ping_ok.3007948105 |
| Directory | /workspace/1.chip_sw_alert_handler_ping_ok/latest |
| Test location | /workspace/coverage/default/1.chip_sw_alert_handler_ping_timeout.1471388921 |
| Short name | T341 |
| Test name | |
| Test status | |
| Simulation time | 3537837576 ps |
| CPU time | 336.85 seconds |
| Started | Jul 03 08:01:54 PM PDT 24 |
| Finished | Jul 03 08:07:33 PM PDT 24 |
| Peak memory | 608152 kb |
| Host | smart-7a79e520-f9f2-48a2-9f17-b2306bb5d3c4 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=24000000 +sw_build_device=sim_dv +sw_images=alert_handler_ping_timeout_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1471388921 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_ping_timeout.1471388921 |
| Directory | /workspace/1.chip_sw_alert_handler_ping_timeout/latest |
| Test location | /workspace/coverage/default/1.chip_sw_alert_handler_reverse_ping_in_deep_sleep.2044586970 |
| Short name | T241 |
| Test name | |
| Test status | |
| Simulation time | 255703617300 ps |
| CPU time | 12322.9 seconds |
| Started | Jul 03 07:57:19 PM PDT 24 |
| Finished | Jul 03 11:22:44 PM PDT 24 |
| Peak memory | 609900 kb |
| Host | smart-c8f4c1a4-1bd5-4b8b-9392-5a681199b6f6 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=300_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_reverse_ping_in_deep_sleep_test:1:n ew_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2044586970 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_reverse_ping_in_deep_sleep.2044586970 |
| Directory | /workspace/1.chip_sw_alert_handler_reverse_ping_in_deep_sleep/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aon_timer_irq.2078706697 |
| Short name | T889 |
| Test name | |
| Test status | |
| Simulation time | 3956322704 ps |
| CPU time | 340.9 seconds |
| Started | Jul 03 07:57:38 PM PDT 24 |
| Finished | Jul 03 08:03:20 PM PDT 24 |
| Peak memory | 610584 kb |
| Host | smart-57f0a718-cc83-4343-ae2a-a949b5f45ddb |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_irq_test:1:new_rules,test_rom:0 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2078706697 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aon_timer_irq.2078706697 |
| Directory | /workspace/1.chip_sw_aon_timer_irq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aon_timer_sleep_wdog_sleep_pause.4047393027 |
| Short name | T894 |
| Test name | |
| Test status | |
| Simulation time | 7526255528 ps |
| CPU time | 565.85 seconds |
| Started | Jul 03 07:59:33 PM PDT 24 |
| Finished | Jul 03 08:09:01 PM PDT 24 |
| Peak memory | 610712 kb |
| Host | smart-bbac6d87-b656-4d8d-b480-a59852d7ceb4 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_sleep_wdog_sleep_pause_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=4047393027 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aon_timer_sleep_wdog_sleep_pause.4047393027 |
| Directory | /workspace/1.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aon_timer_smoketest.2589972692 |
| Short name | T1101 |
| Test name | |
| Test status | |
| Simulation time | 3261130270 ps |
| CPU time | 282.07 seconds |
| Started | Jul 03 08:04:51 PM PDT 24 |
| Finished | Jul 03 08:09:34 PM PDT 24 |
| Peak memory | 610612 kb |
| Host | smart-5ac397e6-d64b-4ac8-907b-41ceb3a15034 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=aon_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2589972692 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 1.chip_sw_aon_timer_smoketest.2589972692 |
| Directory | /workspace/1.chip_sw_aon_timer_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aon_timer_wdog_bite_reset.4277076160 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 7333008600 ps |
| CPU time | 721.93 seconds |
| Started | Jul 03 07:57:41 PM PDT 24 |
| Finished | Jul 03 08:09:44 PM PDT 24 |
| Peak memory | 608636 kb |
| Host | smart-88e6bd9f-86ff-4aaa-bf04-11fe591f9c8b |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_wdog_bite_reset_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 4277076160 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aon_timer_wdog_bite_reset.4277076160 |
| Directory | /workspace/1.chip_sw_aon_timer_wdog_bite_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aon_timer_wdog_lc_escalate.2320659799 |
| Short name | T620 |
| Test name | |
| Test status | |
| Simulation time | 5362234830 ps |
| CPU time | 504.73 seconds |
| Started | Jul 03 08:03:34 PM PDT 24 |
| Finished | Jul 03 08:12:00 PM PDT 24 |
| Peak memory | 608660 kb |
| Host | smart-1e09f609-2973-49c4-a42f-0f6c90655d9c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_wdog_lc_escalate_test:1:new_rules,test_rom:0 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed =2320659799 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aon_timer_wdog_lc_escalate.2320659799 |
| Directory | /workspace/1.chip_sw_aon_timer_wdog_lc_escalate/latest |
| Test location | /workspace/coverage/default/1.chip_sw_ast_clk_outputs.2304430423 |
| Short name | T1236 |
| Test name | |
| Test status | |
| Simulation time | 8007133996 ps |
| CPU time | 1102.66 seconds |
| Started | Jul 03 08:02:12 PM PDT 24 |
| Finished | Jul 03 08:20:35 PM PDT 24 |
| Peak memory | 616168 kb |
| Host | smart-50531d18-a672-4602-942c-dce9e1906838 |
| User | root |
| Command | /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=ast_clk_outs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2304430423 -assert nopo stproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ast_clk_outputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_ast_clk_outputs.2304430423 |
| Directory | /workspace/1.chip_sw_ast_clk_outputs/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_lc.3849967746 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 7950461577 ps |
| CPU time | 561.2 seconds |
| Started | Jul 03 08:00:00 PM PDT 24 |
| Finished | Jul 03 08:09:22 PM PDT 24 |
| Peak memory | 620492 kb |
| Host | smart-a952cd48-8deb-4441-8748-6fa95f4af62c |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +sw_images=clkmgr_external_clk_src_for_lc_test:1:new_r ules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim .tcl +ntb_random_seed=3849967746 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_clkmgr_external_clk_src_for_lc.3849967746 |
| Directory | /workspace/1.chip_sw_clkmgr_external_clk_src_for_lc/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.3002408803 |
| Short name | T909 |
| Test name | |
| Test status | |
| Simulation time | 3576824036 ps |
| CPU time | 618.18 seconds |
| Started | Jul 03 08:00:10 PM PDT 24 |
| Finished | Jul 03 08:10:29 PM PDT 24 |
| Peak memory | 613180 kb |
| Host | smart-4598caa5-ff46-4680-9988-7fd03380d933 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStDev +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3002408803 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_c lkmgr_external_clk_src_for_sw_fast_dev.3002408803 |
| Directory | /workspace/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.3592981007 |
| Short name | T946 |
| Test name | |
| Test status | |
| Simulation time | 3781674520 ps |
| CPU time | 636.22 seconds |
| Started | Jul 03 08:00:47 PM PDT 24 |
| Finished | Jul 03 08:11:24 PM PDT 24 |
| Peak memory | 613176 kb |
| Host | smart-ab63110e-5922-403e-832c-d76a1a6d4d0d |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3592981007 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_c lkmgr_external_clk_src_for_sw_fast_rma.3592981007 |
| Directory | /workspace/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.2715745508 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 3595783110 ps |
| CPU time | 793.3 seconds |
| Started | Jul 03 07:59:43 PM PDT 24 |
| Finished | Jul 03 08:12:57 PM PDT 24 |
| Peak memory | 611924 kb |
| Host | smart-e95b449f-bb64-40aa-8e05-4c514635bd2f |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStTestUnlocked0 +sw_build_device=sim_ dv +sw_images=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2715745508 -assert nopostproc +UVM_TESTNAME=chip_base_test +UV M_TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 .chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.2715745508 |
| Directory | /workspace/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.2198864438 |
| Short name | T1202 |
| Test name | |
| Test status | |
| Simulation time | 4373652718 ps |
| CPU time | 863.53 seconds |
| Started | Jul 03 08:00:13 PM PDT 24 |
| Finished | Jul 03 08:14:37 PM PDT 24 |
| Peak memory | 613184 kb |
| Host | smart-fa507ebd-901a-4fce-b5ee-e69883fb3499 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStDev +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198864438 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_c lkmgr_external_clk_src_for_sw_slow_dev.2198864438 |
| Directory | /workspace/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.541093191 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 4520667940 ps |
| CPU time | 543.08 seconds |
| Started | Jul 03 08:00:36 PM PDT 24 |
| Finished | Jul 03 08:09:39 PM PDT 24 |
| Peak memory | 613188 kb |
| Host | smart-7e692db9-8aac-49f6-aa2c-372ee4a81dfa |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=541093191 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_cl kmgr_external_clk_src_for_sw_slow_rma.541093191 |
| Directory | /workspace/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.2101018723 |
| Short name | T1259 |
| Test name | |
| Test status | |
| Simulation time | 5072538408 ps |
| CPU time | 622.26 seconds |
| Started | Jul 03 08:02:02 PM PDT 24 |
| Finished | Jul 03 08:12:25 PM PDT 24 |
| Peak memory | 612284 kb |
| Host | smart-1869122a-2486-4f96-a3bc-5fdefa646696 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStTestUnlocked0 +sw_build_device=sim_ dv +sw_images=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2101018723 -assert nopostproc +UVM_TESTNAME=chip_base_test +UV M_TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 .chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.2101018723 |
| Directory | /workspace/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_jitter.2890732194 |
| Short name | T1293 |
| Test name | |
| Test status | |
| Simulation time | 2385436098 ps |
| CPU time | 173.14 seconds |
| Started | Jul 03 08:01:00 PM PDT 24 |
| Finished | Jul 03 08:03:54 PM PDT 24 |
| Peak memory | 610720 kb |
| Host | smart-8ea6d148-ac6a-4d73-87d2-f47d3ddc0dcf |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_jitter_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2890732194 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 1.chip_sw_clkmgr_jitter.2890732194 |
| Directory | /workspace/1.chip_sw_clkmgr_jitter/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_jitter_frequency.1949196580 |
| Short name | T1193 |
| Test name | |
| Test status | |
| Simulation time | 3901792020 ps |
| CPU time | 458.69 seconds |
| Started | Jul 03 07:59:55 PM PDT 24 |
| Finished | Jul 03 08:07:35 PM PDT 24 |
| Peak memory | 610588 kb |
| Host | smart-4868eb5b-7a1c-45e3-accb-29093e2382ef |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_jitter_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1949196580 -assert nopostproc +UV M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c m_log /dev/null -cm_name 1.chip_sw_clkmgr_jitter_frequency.1949196580 |
| Directory | /workspace/1.chip_sw_clkmgr_jitter_frequency/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_jitter_reduced_freq.1619185240 |
| Short name | T965 |
| Test name | |
| Test status | |
| Simulation time | 2414106964 ps |
| CPU time | 264.6 seconds |
| Started | Jul 03 08:01:24 PM PDT 24 |
| Finished | Jul 03 08:05:49 PM PDT 24 |
| Peak memory | 607716 kb |
| Host | smart-c6eb59a4-b76f-460a-a728-df5378ef5248 |
| User | root |
| Command | /workspace/default/simv +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=clkmgr_jitter_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619185240 -assert nop ostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 1.chip_sw_clkmgr_jitter_reduced_freq.1619185240 |
| Directory | /workspace/1.chip_sw_clkmgr_jitter_reduced_freq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_off_aes_trans.2478833471 |
| Short name | T1055 |
| Test name | |
| Test status | |
| Simulation time | 4426648068 ps |
| CPU time | 537.71 seconds |
| Started | Jul 03 08:00:41 PM PDT 24 |
| Finished | Jul 03 08:09:39 PM PDT 24 |
| Peak memory | 609292 kb |
| Host | smart-5a8e904f-9093-4fc4-9954-c9d3091c49ef |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_aes_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2478833471 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 1.chip_sw_clkmgr_off_aes_trans.2478833471 |
| Directory | /workspace/1.chip_sw_clkmgr_off_aes_trans/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_off_hmac_trans.598152474 |
| Short name | T829 |
| Test name | |
| Test status | |
| Simulation time | 5453711838 ps |
| CPU time | 446.07 seconds |
| Started | Jul 03 07:59:25 PM PDT 24 |
| Finished | Jul 03 08:06:52 PM PDT 24 |
| Peak memory | 610648 kb |
| Host | smart-46b81891-1542-4845-9bc2-7273fc3f47ba |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_hmac_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=598152474 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 1.chip_sw_clkmgr_off_hmac_trans.598152474 |
| Directory | /workspace/1.chip_sw_clkmgr_off_hmac_trans/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_off_kmac_trans.1221855526 |
| Short name | T1127 |
| Test name | |
| Test status | |
| Simulation time | 4085891720 ps |
| CPU time | 632.88 seconds |
| Started | Jul 03 07:59:59 PM PDT 24 |
| Finished | Jul 03 08:10:33 PM PDT 24 |
| Peak memory | 610624 kb |
| Host | smart-1070d99a-d624-46bf-916b-853b69e84782 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_kmac_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221855526 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 1.chip_sw_clkmgr_off_kmac_trans.1221855526 |
| Directory | /workspace/1.chip_sw_clkmgr_off_kmac_trans/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_off_otbn_trans.4173027005 |
| Short name | T1221 |
| Test name | |
| Test status | |
| Simulation time | 4889409616 ps |
| CPU time | 531.13 seconds |
| Started | Jul 03 07:59:41 PM PDT 24 |
| Finished | Jul 03 08:08:32 PM PDT 24 |
| Peak memory | 608292 kb |
| Host | smart-edabaa16-10ca-4283-acae-7a22a7708e4f |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_otbn_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4173027005 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 1.chip_sw_clkmgr_off_otbn_trans.4173027005 |
| Directory | /workspace/1.chip_sw_clkmgr_off_otbn_trans/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_off_peri.2094036381 |
| Short name | T401 |
| Test name | |
| Test status | |
| Simulation time | 10436408908 ps |
| CPU time | 1643.08 seconds |
| Started | Jul 03 08:00:58 PM PDT 24 |
| Finished | Jul 03 08:28:22 PM PDT 24 |
| Peak memory | 608676 kb |
| Host | smart-c1d4c7b2-7f54-4645-b1e6-c4ba92d34f10 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=30_000_000 +sw_build_device=sim_dv +sw_images=clkmgr_off_peri_test:1:new_rules,test_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2094036381 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/ coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_clkmgr_off_peri.2094036381 |
| Directory | /workspace/1.chip_sw_clkmgr_off_peri/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_reset_frequency.530322765 |
| Short name | T1057 |
| Test name | |
| Test status | |
| Simulation time | 3748000084 ps |
| CPU time | 542.62 seconds |
| Started | Jul 03 08:00:31 PM PDT 24 |
| Finished | Jul 03 08:09:34 PM PDT 24 |
| Peak memory | 610604 kb |
| Host | smart-82fdd3a6-53db-4bf1-bf69-9306e2970023 |
| User | root |
| Command | /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=clkmgr_reset_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=530322765 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove rage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_clkmgr_reset_frequency.530322765 |
| Directory | /workspace/1.chip_sw_clkmgr_reset_frequency/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_sleep_frequency.1504081056 |
| Short name | T1295 |
| Test name | |
| Test status | |
| Simulation time | 4720887688 ps |
| CPU time | 621.86 seconds |
| Started | Jul 03 08:00:19 PM PDT 24 |
| Finished | Jul 03 08:10:42 PM PDT 24 |
| Peak memory | 609168 kb |
| Host | smart-6c0bd46c-89b9-42ca-bc9a-949bd052d7c8 |
| User | root |
| Command | /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=clkmgr_sleep_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1504081056 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_clkmgr_sleep_frequency.1504081056 |
| Directory | /workspace/1.chip_sw_clkmgr_sleep_frequency/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_smoketest.2240158494 |
| Short name | T827 |
| Test name | |
| Test status | |
| Simulation time | 2636614938 ps |
| CPU time | 324.8 seconds |
| Started | Jul 03 08:04:48 PM PDT 24 |
| Finished | Jul 03 08:10:14 PM PDT 24 |
| Peak memory | 610596 kb |
| Host | smart-2fbbd371-6802-4847-98be-973c66f69dda |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2240158494 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 1.chip_sw_clkmgr_smoketest.2240158494 |
| Directory | /workspace/1.chip_sw_clkmgr_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_csrng_edn_concurrency.2322108519 |
| Short name | T405 |
| Test name | |
| Test status | |
| Simulation time | 26914387312 ps |
| CPU time | 7216.66 seconds |
| Started | Jul 03 07:58:35 PM PDT 24 |
| Finished | Jul 03 09:58:53 PM PDT 24 |
| Peak memory | 608484 kb |
| Host | smart-3160e378-9c47-4299-a00a-d24a6680f761 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +accelerate_cold_power_up_time=3 +accelerate_r egulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2322108519 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 1.chip_sw_csrng_edn_concurrency.2322108519 |
| Directory | /workspace/1.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspace/coverage/default/1.chip_sw_csrng_fuse_en_sw_app_read_test.1480976888 |
| Short name | T1000 |
| Test name | |
| Test status | |
| Simulation time | 4130952476 ps |
| CPU time | 527.37 seconds |
| Started | Jul 03 07:59:23 PM PDT 24 |
| Finished | Jul 03 08:08:12 PM PDT 24 |
| Peak memory | 610712 kb |
| Host | smart-8fb86feb-63b5-4ffc-8951-2bb92d135c68 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=csrng_fuse_en_sw_app_read:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14809 76888 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_entropy_src_fuse_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_csrng_fuse_en_sw_app_read_test.1480976888 |
| Directory | /workspace/1.chip_sw_csrng_fuse_en_sw_app_read_test/latest |
| Test location | /workspace/coverage/default/1.chip_sw_csrng_kat_test.4017993069 |
| Short name | T1208 |
| Test name | |
| Test status | |
| Simulation time | 3170248462 ps |
| CPU time | 291.72 seconds |
| Started | Jul 03 07:58:54 PM PDT 24 |
| Finished | Jul 03 08:03:47 PM PDT 24 |
| Peak memory | 610640 kb |
| Host | smart-18bc6f8c-d93a-4967-ae41-4cdde1d37243 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=csrng_kat_test:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4017993069 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_csrng_kat_test.4017993069 |
| Directory | /workspace/1.chip_sw_csrng_kat_test/latest |
| Test location | /workspace/coverage/default/1.chip_sw_csrng_smoketest.1018100436 |
| Short name | T841 |
| Test name | |
| Test status | |
| Simulation time | 3025807832 ps |
| CPU time | 278 seconds |
| Started | Jul 03 08:04:59 PM PDT 24 |
| Finished | Jul 03 08:09:38 PM PDT 24 |
| Peak memory | 610588 kb |
| Host | smart-492ebff8-a3a0-417c-bf94-50c42278a313 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=csrng_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1018100436 -assert nopostproc +UVM_TESTNAME=ch ip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 1.chip_sw_csrng_smoketest.1018100436 |
| Directory | /workspace/1.chip_sw_csrng_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_data_integrity_escalation.1610532553 |
| Short name | T269 |
| Test name | |
| Test status | |
| Simulation time | 4990768000 ps |
| CPU time | 794.48 seconds |
| Started | Jul 03 07:57:00 PM PDT 24 |
| Finished | Jul 03 08:10:15 PM PDT 24 |
| Peak memory | 610704 kb |
| Host | smart-a362453c-8f36-4f11-a15e-af4b355dd53d |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=data_integrity_escalation_reset_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1610532553 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_data_integrity_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_data_integrity_escalation.1610532553 |
| Directory | /workspace/1.chip_sw_data_integrity_escalation/latest |
| Test location | /workspace/coverage/default/1.chip_sw_edn_auto_mode.3941098646 |
| Short name | T1264 |
| Test name | |
| Test status | |
| Simulation time | 4184385712 ps |
| CPU time | 998.76 seconds |
| Started | Jul 03 07:59:03 PM PDT 24 |
| Finished | Jul 03 08:15:43 PM PDT 24 |
| Peak memory | 609192 kb |
| Host | smart-2b32c8df-04ef-476c-89d7-519560d06861 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_ build_device=sim_dv +sw_images=edn_auto_mode:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3941098646 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_edn_ auto_mode.3941098646 |
| Directory | /workspace/1.chip_sw_edn_auto_mode/latest |
| Test location | /workspace/coverage/default/1.chip_sw_edn_boot_mode.1526018650 |
| Short name | T611 |
| Test name | |
| Test status | |
| Simulation time | 3233186172 ps |
| CPU time | 528.58 seconds |
| Started | Jul 03 07:57:16 PM PDT 24 |
| Finished | Jul 03 08:06:06 PM PDT 24 |
| Peak memory | 609120 kb |
| Host | smart-8d4709c9-5e86-4395-951b-4bd9650b91c1 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_ build_device=sim_dv +sw_images=edn_boot_mode:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1526018650 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_edn_ boot_mode.1526018650 |
| Directory | /workspace/1.chip_sw_edn_boot_mode/latest |
| Test location | /workspace/coverage/default/1.chip_sw_edn_entropy_reqs.1731139755 |
| Short name | T425 |
| Test name | |
| Test status | |
| Simulation time | 7250724396 ps |
| CPU time | 1203.88 seconds |
| Started | Jul 03 07:57:58 PM PDT 24 |
| Finished | Jul 03 08:18:02 PM PDT 24 |
| Peak memory | 609992 kb |
| Host | smart-f462a8e3-5fe0-4a91-bd11-af71f957fdae |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15000000 +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_ed n_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1731139755 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_edn_entropy_reqs.1731139755 |
| Directory | /workspace/1.chip_sw_edn_entropy_reqs/latest |
| Test location | /workspace/coverage/default/1.chip_sw_edn_kat.918197119 |
| Short name | T1292 |
| Test name | |
| Test status | |
| Simulation time | 3378493170 ps |
| CPU time | 710.41 seconds |
| Started | Jul 03 07:59:05 PM PDT 24 |
| Finished | Jul 03 08:10:56 PM PDT 24 |
| Peak memory | 614604 kb |
| Host | smart-42ed0bdf-33a3-41aa-b3e1-30ffba64e802 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +disable_assert_edn_output_diff_from_prev=1 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=edn_kat:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=918197119 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 1.chip_sw_edn_kat.918197119 |
| Directory | /workspace/1.chip_sw_edn_kat/latest |
| Test location | /workspace/coverage/default/1.chip_sw_edn_sw_mode.788517638 |
| Short name | T853 |
| Test name | |
| Test status | |
| Simulation time | 10009663592 ps |
| CPU time | 2515.14 seconds |
| Started | Jul 03 07:57:56 PM PDT 24 |
| Finished | Jul 03 08:39:52 PM PDT 24 |
| Peak memory | 610484 kb |
| Host | smart-911b3a2b-a33b-41a3-ab8e-c01cb8284c56 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=edn_sw_mode:1:new_rules,test_rom:0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=788517638 -assert n opostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d efault.vdb -cm_log /dev/null -cm_name 1.chip_sw_edn_sw_mode.788517638 |
| Directory | /workspace/1.chip_sw_edn_sw_mode/latest |
| Test location | /workspace/coverage/default/1.chip_sw_entropy_src_ast_rng_req.2286280907 |
| Short name | T828 |
| Test name | |
| Test status | |
| Simulation time | 2546304612 ps |
| CPU time | 334.78 seconds |
| Started | Jul 03 07:57:43 PM PDT 24 |
| Finished | Jul 03 08:03:18 PM PDT 24 |
| Peak memory | 608052 kb |
| Host | smart-de1cb4c7-7a84-4d07-9268-c8996d0a96be |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=entropy_src_ast_rng_req_test:1:new_rules,test_rom:0 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22 86280907 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_entropy_src_ast_rng_req.2286280907 |
| Directory | /workspace/1.chip_sw_entropy_src_ast_rng_req/latest |
| Test location | /workspace/coverage/default/1.chip_sw_entropy_src_kat_test.2274546712 |
| Short name | T1234 |
| Test name | |
| Test status | |
| Simulation time | 2737986662 ps |
| CPU time | 219.13 seconds |
| Started | Jul 03 07:56:45 PM PDT 24 |
| Finished | Jul 03 08:00:25 PM PDT 24 |
| Peak memory | 610556 kb |
| Host | smart-3d99118c-d5db-4405-86de-92b6aad16a35 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=entropy_src_kat_test:1:new_rules,test_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2274546712 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/ coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_entropy_src_kat_test.2274546712 |
| Directory | /workspace/1.chip_sw_entropy_src_kat_test/latest |
| Test location | /workspace/coverage/default/1.chip_sw_entropy_src_smoketest.2201392711 |
| Short name | T1084 |
| Test name | |
| Test status | |
| Simulation time | 3521142536 ps |
| CPU time | 427.34 seconds |
| Started | Jul 03 08:05:20 PM PDT 24 |
| Finished | Jul 03 08:12:28 PM PDT 24 |
| Peak memory | 610648 kb |
| Host | smart-828d7898-281b-4f90-8f7d-ae1b991593ff |
| User | root |
| Command | /workspace/default/simv +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_smoketest:1:new_rules,test_rom: 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=2201392711 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_entropy_src_smoketest.2201392711 |
| Directory | /workspace/1.chip_sw_entropy_src_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_example_concurrency.4077867256 |
| Short name | T830 |
| Test name | |
| Test status | |
| Simulation time | 2347879664 ps |
| CPU time | 288.36 seconds |
| Started | Jul 03 07:52:54 PM PDT 24 |
| Finished | Jul 03 07:57:43 PM PDT 24 |
| Peak memory | 607644 kb |
| Host | smart-25518fa2-86bf-43c9-b613-893a1940aca4 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4077867256 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo g /dev/null -cm_name 1.chip_sw_example_concurrency.4077867256 |
| Directory | /workspace/1.chip_sw_example_concurrency/latest |
| Test location | /workspace/coverage/default/1.chip_sw_example_flash.1137905211 |
| Short name | T1006 |
| Test name | |
| Test status | |
| Simulation time | 3064156712 ps |
| CPU time | 211.27 seconds |
| Started | Jul 03 07:53:26 PM PDT 24 |
| Finished | Jul 03 07:56:58 PM PDT 24 |
| Peak memory | 607664 kb |
| Host | smart-1a7f1db6-89d1-46b6-9cf6-bd9c77234c01 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test_from_flash:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1137905211 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_example_flash.1137905211 |
| Directory | /workspace/1.chip_sw_example_flash/latest |
| Test location | /workspace/coverage/default/1.chip_sw_example_manufacturer.4092429112 |
| Short name | T1238 |
| Test name | |
| Test status | |
| Simulation time | 2687006952 ps |
| CPU time | 189.17 seconds |
| Started | Jul 03 07:54:00 PM PDT 24 |
| Finished | Jul 03 07:57:10 PM PDT 24 |
| Peak memory | 607752 kb |
| Host | smart-7fe6eba8-a14a-4fff-83eb-4448d8345a2a |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4092429112 -assert nopostproc +UVM_TESTNAME=chip_ base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_example_manufacturer.4092429112 |
| Directory | /workspace/1.chip_sw_example_manufacturer/latest |
| Test location | /workspace/coverage/default/1.chip_sw_example_rom.513681299 |
| Short name | T1054 |
| Test name | |
| Test status | |
| Simulation time | 1981661190 ps |
| CPU time | 107.34 seconds |
| Started | Jul 03 07:52:55 PM PDT 24 |
| Finished | Jul 03 07:54:43 PM PDT 24 |
| Peak memory | 607408 kb |
| Host | smart-4984dfaf-a412-4562-8132-a88331c64af8 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=513681299 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 1.chip_sw_example_rom.513681299 |
| Directory | /workspace/1.chip_sw_example_rom/latest |
| Test location | /workspace/coverage/default/1.chip_sw_exit_test_unlocked_bootstrap.3908626556 |
| Short name | T1110 |
| Test name | |
| Test status | |
| Simulation time | 59327966984 ps |
| CPU time | 10506 seconds |
| Started | Jul 03 07:55:05 PM PDT 24 |
| Finished | Jul 03 10:50:12 PM PDT 24 |
| Peak memory | 624828 kb |
| Host | smart-2318fec9-3895-40e1-a62f-71a919ae3ca0 |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=exit_test_unlocked_bootstrap:1:new _rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/s im.tcl +ntb_random_seed=3908626556 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_exit_test_unlocked_bootstrap_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_exit_test_unlocked_bootstrap.3908626556 |
| Directory | /workspace/1.chip_sw_exit_test_unlocked_bootstrap/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_crash_alert.3674188644 |
| Short name | T296 |
| Test name | |
| Test status | |
| Simulation time | 5192613980 ps |
| CPU time | 585.32 seconds |
| Started | Jul 03 08:03:10 PM PDT 24 |
| Finished | Jul 03 08:12:56 PM PDT 24 |
| Peak memory | 610780 kb |
| Host | smart-a59382ed-be00-42b1-aceb-a2b010634300 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=8_000_000 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1: new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tool s/sim.tcl +ntb_random_seed=3674188644 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_host_gnt_err_inj_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_crash_alert.3674188644 |
| Directory | /workspace/1.chip_sw_flash_crash_alert/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_ctrl_access.2930715790 |
| Short name | T1056 |
| Test name | |
| Test status | |
| Simulation time | 4977914352 ps |
| CPU time | 896.54 seconds |
| Started | Jul 03 07:56:28 PM PDT 24 |
| Finished | Jul 03 08:11:26 PM PDT 24 |
| Peak memory | 610680 kb |
| Host | smart-8ee9e82d-9e51-466f-af12-fd9c4cd0bc3c |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2930715790 -assert nopostproc +UVM_TESTNAME=ch ip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 1.chip_sw_flash_ctrl_access.2930715790 |
| Directory | /workspace/1.chip_sw_flash_ctrl_access/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en.3095102228 |
| Short name | T861 |
| Test name | |
| Test status | |
| Simulation time | 6181661017 ps |
| CPU time | 1112.96 seconds |
| Started | Jul 03 07:58:31 PM PDT 24 |
| Finished | Jul 03 08:17:04 PM PDT 24 |
| Peak memory | 610616 kb |
| Host | smart-950c7441-c238-4818-aa19-5e58219822d2 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3095102228 -assert nopostproc +UV M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c m_log /dev/null -cm_name 1.chip_sw_flash_ctrl_access_jitter_en.3095102228 |
| Directory | /workspace/1.chip_sw_flash_ctrl_access_jitter_en/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.3535177014 |
| Short name | T926 |
| Test name | |
| Test status | |
| Simulation time | 7359800546 ps |
| CPU time | 1527.95 seconds |
| Started | Jul 03 08:05:33 PM PDT 24 |
| Finished | Jul 03 08:31:02 PM PDT 24 |
| Peak memory | 609108 kb |
| Host | smart-94a1814f-15a3-4a20-8ab6-c79b3e9ef370 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3535177014 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.3535177014 |
| Directory | /workspace/1.chip_sw_flash_ctrl_access_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_ctrl_clock_freqs.3539903354 |
| Short name | T1102 |
| Test name | |
| Test status | |
| Simulation time | 6303159688 ps |
| CPU time | 1300.1 seconds |
| Started | Jul 03 07:54:34 PM PDT 24 |
| Finished | Jul 03 08:16:14 PM PDT 24 |
| Peak memory | 607996 kb |
| Host | smart-4837556d-1747-41e9-a0bc-68a9ca88bc21 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_clock_freqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3539903354 -assert nopostproc +UVM _TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 1.chip_sw_flash_ctrl_clock_freqs.3539903354 |
| Directory | /workspace/1.chip_sw_flash_ctrl_clock_freqs/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_ctrl_idle_low_power.1260434001 |
| Short name | T893 |
| Test name | |
| Test status | |
| Simulation time | 3433006696 ps |
| CPU time | 468.32 seconds |
| Started | Jul 03 07:54:42 PM PDT 24 |
| Finished | Jul 03 08:02:30 PM PDT 24 |
| Peak memory | 608736 kb |
| Host | smart-4ae792a9-9298-479d-beb5-2713f2b81789 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_idle_low_power_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1260434001 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_idle_low_power.1260434001 |
| Directory | /workspace/1.chip_sw_flash_ctrl_idle_low_power/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_ctrl_lc_rw_en.3860755893 |
| Short name | T236 |
| Test name | |
| Test status | |
| Simulation time | 5915187788 ps |
| CPU time | 424.19 seconds |
| Started | Jul 03 07:52:49 PM PDT 24 |
| Finished | Jul 03 07:59:54 PM PDT 24 |
| Peak memory | 608660 kb |
| Host | smart-c40035ed-4cff-43ec-becf-e2b458e7a11c |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_lc_rw_en_test:1:new_rules,test_rom:0 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38 60755893 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_ctrl_lc_rw_en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_lc_rw_en.3860755893 |
| Directory | /workspace/1.chip_sw_flash_ctrl_lc_rw_en/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_ctrl_mem_protection.1780238496 |
| Short name | T989 |
| Test name | |
| Test status | |
| Simulation time | 5423263428 ps |
| CPU time | 1175.45 seconds |
| Started | Jul 03 08:02:51 PM PDT 24 |
| Finished | Jul 03 08:22:27 PM PDT 24 |
| Peak memory | 610608 kb |
| Host | smart-1649924f-7864-43c7-b529-8c30ae75d58f |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_mem_protection_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1780238496 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_mem_protection.1780238496 |
| Directory | /workspace/1.chip_sw_flash_ctrl_mem_protection/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_ctrl_ops.178547758 |
| Short name | T326 |
| Test name | |
| Test status | |
| Simulation time | 4299593992 ps |
| CPU time | 656.09 seconds |
| Started | Jul 03 07:53:43 PM PDT 24 |
| Finished | Jul 03 08:04:39 PM PDT 24 |
| Peak memory | 610620 kb |
| Host | smart-2a2e6b2b-080a-4e03-b28c-beec42648e47 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=178547758 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_ops.178547758 |
| Directory | /workspace/1.chip_sw_flash_ctrl_ops/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en.182676926 |
| Short name | T337 |
| Test name | |
| Test status | |
| Simulation time | 4396847273 ps |
| CPU time | 712.06 seconds |
| Started | Jul 03 07:54:28 PM PDT 24 |
| Finished | Jul 03 08:06:20 PM PDT 24 |
| Peak memory | 608272 kb |
| Host | smart-5a3c906c-4399-474a-ae97-b3a244fdbbd5 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_rules,test_rom:0 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=182676926 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_ops_jitter_en.182676926 |
| Directory | /workspace/1.chip_sw_flash_ctrl_ops_jitter_en/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_ctrl_write_clear.809082334 |
| Short name | T847 |
| Test name | |
| Test status | |
| Simulation time | 3426863014 ps |
| CPU time | 396.28 seconds |
| Started | Jul 03 08:01:17 PM PDT 24 |
| Finished | Jul 03 08:07:55 PM PDT 24 |
| Peak memory | 610584 kb |
| Host | smart-391e235b-4eca-487d-867c-d2b9ab485999 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=8_000_000 +sw_build_device=sim_dv +sw_images=flash_ctrl_write_clear_test:1:new_rules,test_rom:0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8090823 34 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_write_clear.809082334 |
| Directory | /workspace/1.chip_sw_flash_ctrl_write_clear/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_init_reduced_freq.1362364568 |
| Short name | T1185 |
| Test name | |
| Test status | |
| Simulation time | 21484510362 ps |
| CPU time | 1970.71 seconds |
| Started | Jul 03 08:02:14 PM PDT 24 |
| Finished | Jul 03 08:35:06 PM PDT 24 |
| Peak memory | 616368 kb |
| Host | smart-127aefba-e513-48d7-aa8c-a5a97bb52ce4 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=25_000_000 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_init_test:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1362364568 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_init_reduced_freq.1362364568 |
| Directory | /workspace/1.chip_sw_flash_init_reduced_freq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_scrambling_smoketest.4077327791 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 2721124388 ps |
| CPU time | 225.29 seconds |
| Started | Jul 03 08:07:22 PM PDT 24 |
| Finished | Jul 03 08:11:08 PM PDT 24 |
| Peak memory | 607868 kb |
| Host | smart-83eafa8a-dae5-484f-8bd4-32653605eb99 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=flash_scrambling_smoketest:1:new_rules,flash_scrambling_smoket est_otp_img_rma:4,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=4077327791 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_scrambling_smoketest.4077327791 |
| Directory | /workspace/1.chip_sw_flash_scrambling_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_gpio_smoketest.1459328304 |
| Short name | T1267 |
| Test name | |
| Test status | |
| Simulation time | 2418695730 ps |
| CPU time | 253.82 seconds |
| Started | Jul 03 08:04:05 PM PDT 24 |
| Finished | Jul 03 08:08:20 PM PDT 24 |
| Peak memory | 609648 kb |
| Host | smart-36917a78-e69f-4772-8b7a-22b96fd7ae7b |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=gpio_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1459328304 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 1.chip_sw_gpio_smoketest.1459328304 |
| Directory | /workspace/1.chip_sw_gpio_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_hmac_enc_idle.3452118747 |
| Short name | T1072 |
| Test name | |
| Test status | |
| Simulation time | 2958932200 ps |
| CPU time | 424.94 seconds |
| Started | Jul 03 07:57:52 PM PDT 24 |
| Finished | Jul 03 08:04:58 PM PDT 24 |
| Peak memory | 610620 kb |
| Host | smart-88e36692-b7eb-49d9-a742-f07d3e2329c0 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_enc_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3452118747 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 1.chip_sw_hmac_enc_idle.3452118747 |
| Directory | /workspace/1.chip_sw_hmac_enc_idle/latest |
| Test location | /workspace/coverage/default/1.chip_sw_hmac_enc_jitter_en.258523682 |
| Short name | T824 |
| Test name | |
| Test status | |
| Simulation time | 3772480837 ps |
| CPU time | 334.06 seconds |
| Started | Jul 03 07:58:36 PM PDT 24 |
| Finished | Jul 03 08:04:11 PM PDT 24 |
| Peak memory | 610644 kb |
| Host | smart-5b4e584f-e6bf-467c-a2e4-907ec9d786fa |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=258523682 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 1.chip_sw_hmac_enc_jitter_en.258523682 |
| Directory | /workspace/1.chip_sw_hmac_enc_jitter_en/latest |
| Test location | /workspace/coverage/default/1.chip_sw_hmac_enc_jitter_en_reduced_freq.3194010516 |
| Short name | T921 |
| Test name | |
| Test status | |
| Simulation time | 3014747953 ps |
| CPU time | 269.2 seconds |
| Started | Jul 03 08:01:29 PM PDT 24 |
| Finished | Jul 03 08:05:58 PM PDT 24 |
| Peak memory | 610636 kb |
| Host | smart-b77007e6-e6eb-4493-95cd-bfc3a822f962 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3194010516 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove rage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_hmac_enc_jitter_en_reduced_freq.3194010516 |
| Directory | /workspace/1.chip_sw_hmac_enc_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_hmac_multistream.2784926527 |
| Short name | T906 |
| Test name | |
| Test status | |
| Simulation time | 7539066608 ps |
| CPU time | 1748.91 seconds |
| Started | Jul 03 07:59:03 PM PDT 24 |
| Finished | Jul 03 08:28:13 PM PDT 24 |
| Peak memory | 607956 kb |
| Host | smart-b1693b10-8ff3-4250-b0ba-28aeabd3b121 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_multistream_functest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2784926527 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 1.chip_sw_hmac_multistream.2784926527 |
| Directory | /workspace/1.chip_sw_hmac_multistream/latest |
| Test location | /workspace/coverage/default/1.chip_sw_hmac_oneshot.1484263862 |
| Short name | T1098 |
| Test name | |
| Test status | |
| Simulation time | 3131168896 ps |
| CPU time | 352.36 seconds |
| Started | Jul 03 07:58:38 PM PDT 24 |
| Finished | Jul 03 08:04:31 PM PDT 24 |
| Peak memory | 607700 kb |
| Host | smart-58e72c32-03f0-4338-9a8b-46ff506f55c1 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_functest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1484263862 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_hmac_oneshot.1484263862 |
| Directory | /workspace/1.chip_sw_hmac_oneshot/latest |
| Test location | /workspace/coverage/default/1.chip_sw_hmac_smoketest.4282590294 |
| Short name | T1147 |
| Test name | |
| Test status | |
| Simulation time | 2762637808 ps |
| CPU time | 281.45 seconds |
| Started | Jul 03 08:04:00 PM PDT 24 |
| Finished | Jul 03 08:08:42 PM PDT 24 |
| Peak memory | 610584 kb |
| Host | smart-bab82a10-59cf-4ba7-8e0a-f83e95a75469 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4282590294 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 1.chip_sw_hmac_smoketest.4282590294 |
| Directory | /workspace/1.chip_sw_hmac_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_i2c_device_tx_rx.2370530977 |
| Short name | T322 |
| Test name | |
| Test status | |
| Simulation time | 3899310040 ps |
| CPU time | 542.61 seconds |
| Started | Jul 03 07:56:20 PM PDT 24 |
| Finished | Jul 03 08:05:24 PM PDT 24 |
| Peak memory | 609836 kb |
| Host | smart-2e61cbb8-5ebf-4ee7-8922-66148d25a99e |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=i2c_device_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2370530977 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_device_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 1.chip_sw_i2c_device_tx_rx.2370530977 |
| Directory | /workspace/1.chip_sw_i2c_device_tx_rx/latest |
| Test location | /workspace/coverage/default/1.chip_sw_i2c_host_tx_rx.3273038908 |
| Short name | T368 |
| Test name | |
| Test status | |
| Simulation time | 5321620096 ps |
| CPU time | 751.69 seconds |
| Started | Jul 03 07:53:30 PM PDT 24 |
| Finished | Jul 03 08:06:03 PM PDT 24 |
| Peak memory | 608184 kb |
| Host | smart-5a278f5f-812d-4885-99be-667058d3a2c2 |
| User | root |
| Command | /workspace/default/simv +i2c_idx=0 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3273038908 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 1.chip_sw_i2c_host_tx_rx.3273038908 |
| Directory | /workspace/1.chip_sw_i2c_host_tx_rx/latest |
| Test location | /workspace/coverage/default/1.chip_sw_i2c_host_tx_rx_idx1.3445319916 |
| Short name | T369 |
| Test name | |
| Test status | |
| Simulation time | 5691294868 ps |
| CPU time | 1041.68 seconds |
| Started | Jul 03 07:53:20 PM PDT 24 |
| Finished | Jul 03 08:10:42 PM PDT 24 |
| Peak memory | 609432 kb |
| Host | smart-0e7a90ab-524e-4107-a48b-491c3f895ec1 |
| User | root |
| Command | /workspace/default/simv +i2c_idx=1 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445319916 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 1.chip_sw_i2c_host_tx_rx_idx1.3445319916 |
| Directory | /workspace/1.chip_sw_i2c_host_tx_rx_idx1/latest |
| Test location | /workspace/coverage/default/1.chip_sw_i2c_host_tx_rx_idx2.3191653249 |
| Short name | T317 |
| Test name | |
| Test status | |
| Simulation time | 5330644856 ps |
| CPU time | 1046.37 seconds |
| Started | Jul 03 07:56:03 PM PDT 24 |
| Finished | Jul 03 08:13:30 PM PDT 24 |
| Peak memory | 608172 kb |
| Host | smart-ce89df03-c5c6-4913-8f1a-1b14851d1797 |
| User | root |
| Command | /workspace/default/simv +i2c_idx=2 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3191653249 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 1.chip_sw_i2c_host_tx_rx_idx2.3191653249 |
| Directory | /workspace/1.chip_sw_i2c_host_tx_rx_idx2/latest |
| Test location | /workspace/coverage/default/1.chip_sw_inject_scramble_seed.1057406979 |
| Short name | T1049 |
| Test name | |
| Test status | |
| Simulation time | 65835253338 ps |
| CPU time | 12143.1 seconds |
| Started | Jul 03 07:52:17 PM PDT 24 |
| Finished | Jul 03 11:14:42 PM PDT 24 |
| Peak memory | 625060 kb |
| Host | smart-8f06ece3-609f-470a-b99e-0e0fa97a1287 |
| User | root |
| Command | /workspace/default/simv +lc_at_prod=1 +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=inject_scramble_seed :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1057406979 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_inject_scramble_seed_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_inject_scramble_seed.1057406979 |
| Directory | /workspace/1.chip_sw_inject_scramble_seed/latest |
| Test location | /workspace/coverage/default/1.chip_sw_keymgr_key_derivation.1002961114 |
| Short name | T1093 |
| Test name | |
| Test status | |
| Simulation time | 9545983206 ps |
| CPU time | 1892.98 seconds |
| Started | Jul 03 07:59:05 PM PDT 24 |
| Finished | Jul 03 08:30:39 PM PDT 24 |
| Peak memory | 616700 kb |
| Host | smart-758fe26e-58b3-4eee-85f1-2484bdf28da0 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1002 961114 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_key_derivation.1002961114 |
| Directory | /workspace/1.chip_sw_keymgr_key_derivation/latest |
| Test location | /workspace/coverage/default/1.chip_sw_keymgr_key_derivation_jitter_en.535641482 |
| Short name | T885 |
| Test name | |
| Test status | |
| Simulation time | 11802571269 ps |
| CPU time | 2827.54 seconds |
| Started | Jul 03 07:59:10 PM PDT 24 |
| Finished | Jul 03 08:46:19 PM PDT 24 |
| Peak memory | 615988 kb |
| Host | smart-77d4c2b0-1744-4abd-a719-f2138b036e36 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=535641482 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_key_derivation_jitter_en.535641482 |
| Directory | /workspace/1.chip_sw_keymgr_key_derivation_jitter_en/latest |
| Test location | /workspace/coverage/default/1.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.2565667767 |
| Short name | T939 |
| Test name | |
| Test status | |
| Simulation time | 9153905537 ps |
| CPU time | 1348.92 seconds |
| Started | Jul 03 08:02:26 PM PDT 24 |
| Finished | Jul 03 08:24:57 PM PDT 24 |
| Peak memory | 616040 kb |
| Host | smart-b7c4a332-efb5-4298-8d18-b666ec54e048 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2565667767 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_key_derivation_jitter_en _reduced_freq.2565667767 |
| Directory | /workspace/1.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_keymgr_key_derivation_prod.3959377434 |
| Short name | T221 |
| Test name | |
| Test status | |
| Simulation time | 7935703490 ps |
| CPU time | 1650.91 seconds |
| Started | Jul 03 07:57:32 PM PDT 24 |
| Finished | Jul 03 08:25:03 PM PDT 24 |
| Peak memory | 616768 kb |
| Host | smart-5fdc47a0-70dc-4bc6-b887-fe200bf60859 |
| User | root |
| Command | /workspace/default/simv +lc_at_prod=1 +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3959377434 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_key_derivation_prod.3959377434 |
| Directory | /workspace/1.chip_sw_keymgr_key_derivation_prod/latest |
| Test location | /workspace/coverage/default/1.chip_sw_keymgr_sideload_aes.1809471163 |
| Short name | T224 |
| Test name | |
| Test status | |
| Simulation time | 11201020420 ps |
| CPU time | 2252.46 seconds |
| Started | Jul 03 08:06:41 PM PDT 24 |
| Finished | Jul 03 08:44:15 PM PDT 24 |
| Peak memory | 610764 kb |
| Host | smart-9eb1cce4-f6e0-425d-b6fa-74ceb32a64cc |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_aes_test:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=180947 1163 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_sideload_aes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_sideload_aes.1809471163 |
| Directory | /workspace/1.chip_sw_keymgr_sideload_aes/latest |
| Test location | /workspace/coverage/default/1.chip_sw_keymgr_sideload_kmac.1360097530 |
| Short name | T362 |
| Test name | |
| Test status | |
| Simulation time | 8056936104 ps |
| CPU time | 1779.49 seconds |
| Started | Jul 03 07:58:37 PM PDT 24 |
| Finished | Jul 03 08:28:17 PM PDT 24 |
| Peak memory | 610668 kb |
| Host | smart-6c3433aa-8d30-4faa-931b-493303eb45a3 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_kmac_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13600 97530 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_sideload_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_sideload_kmac.1360097530 |
| Directory | /workspace/1.chip_sw_keymgr_sideload_kmac/latest |
| Test location | /workspace/coverage/default/1.chip_sw_keymgr_sideload_otbn.3462050924 |
| Short name | T226 |
| Test name | |
| Test status | |
| Simulation time | 12747605356 ps |
| CPU time | 3166.48 seconds |
| Started | Jul 03 07:58:56 PM PDT 24 |
| Finished | Jul 03 08:51:43 PM PDT 24 |
| Peak memory | 610732 kb |
| Host | smart-908f05ae-e7fc-4281-9800-f183412a04cd |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_otbn_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34620 50924 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_sideload_otbn.3462050924 |
| Directory | /workspace/1.chip_sw_keymgr_sideload_otbn/latest |
| Test location | /workspace/coverage/default/1.chip_sw_kmac_app_rom.649377567 |
| Short name | T384 |
| Test name | |
| Test status | |
| Simulation time | 2994659792 ps |
| CPU time | 233.86 seconds |
| Started | Jul 03 08:00:40 PM PDT 24 |
| Finished | Jul 03 08:04:35 PM PDT 24 |
| Peak memory | 610664 kb |
| Host | smart-b37d9097-0cf3-4809-b0f0-2a641b630e29 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_app_rom_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=649377567 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 1.chip_sw_kmac_app_rom.649377567 |
| Directory | /workspace/1.chip_sw_kmac_app_rom/latest |
| Test location | /workspace/coverage/default/1.chip_sw_kmac_entropy.1824028370 |
| Short name | T402 |
| Test name | |
| Test status | |
| Simulation time | 2616552570 ps |
| CPU time | 260.06 seconds |
| Started | Jul 03 07:52:20 PM PDT 24 |
| Finished | Jul 03 07:56:41 PM PDT 24 |
| Peak memory | 610624 kb |
| Host | smart-c299110a-b39b-4d99-a98b-0db2308b827a |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_entropy_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1824028370 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 1.chip_sw_kmac_entropy.1824028370 |
| Directory | /workspace/1.chip_sw_kmac_entropy/latest |
| Test location | /workspace/coverage/default/1.chip_sw_kmac_mode_cshake.4225723452 |
| Short name | T888 |
| Test name | |
| Test status | |
| Simulation time | 3423180952 ps |
| CPU time | 320.87 seconds |
| Started | Jul 03 07:58:15 PM PDT 24 |
| Finished | Jul 03 08:03:37 PM PDT 24 |
| Peak memory | 610604 kb |
| Host | smart-0d1fd60a-93ca-457f-9f5e-5ab2e0e2c3bf |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_mode_cshake_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4225723452 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 1.chip_sw_kmac_mode_cshake.4225723452 |
| Directory | /workspace/1.chip_sw_kmac_mode_cshake/latest |
| Test location | /workspace/coverage/default/1.chip_sw_kmac_mode_kmac.1369239698 |
| Short name | T987 |
| Test name | |
| Test status | |
| Simulation time | 3040636048 ps |
| CPU time | 461.25 seconds |
| Started | Jul 03 07:58:59 PM PDT 24 |
| Finished | Jul 03 08:06:41 PM PDT 24 |
| Peak memory | 607692 kb |
| Host | smart-6bd0a278-c68b-425f-af5d-5a34cc9dfd04 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1369239698 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 1.chip_sw_kmac_mode_kmac.1369239698 |
| Directory | /workspace/1.chip_sw_kmac_mode_kmac/latest |
| Test location | /workspace/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en.2029939754 |
| Short name | T1094 |
| Test name | |
| Test status | |
| Simulation time | 2959227318 ps |
| CPU time | 392.3 seconds |
| Started | Jul 03 08:00:30 PM PDT 24 |
| Finished | Jul 03 08:07:03 PM PDT 24 |
| Peak memory | 610604 kb |
| Host | smart-b7eff942-ee06-417b-a0dc-4c81b775bca5 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029939754 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 1.chip_sw_kmac_mode_kmac_jitter_en.2029939754 |
| Directory | /workspace/1.chip_sw_kmac_mode_kmac_jitter_en/latest |
| Test location | /workspace/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.2383449646 |
| Short name | T1228 |
| Test name | |
| Test status | |
| Simulation time | 3151782581 ps |
| CPU time | 315.47 seconds |
| Started | Jul 03 08:01:41 PM PDT 24 |
| Finished | Jul 03 08:06:57 PM PDT 24 |
| Peak memory | 610620 kb |
| Host | smart-14d02a01-090b-40aa-843c-ab3be5324ae7 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23834496 46 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.2383449646 |
| Directory | /workspace/1.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_kmac_smoketest.3617673361 |
| Short name | T899 |
| Test name | |
| Test status | |
| Simulation time | 3216905352 ps |
| CPU time | 286.77 seconds |
| Started | Jul 03 08:04:06 PM PDT 24 |
| Finished | Jul 03 08:08:54 PM PDT 24 |
| Peak memory | 610644 kb |
| Host | smart-a8c365a5-84fc-4c61-a133-ca1ba48c26b2 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3617673361 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 1.chip_sw_kmac_smoketest.3617673361 |
| Directory | /workspace/1.chip_sw_kmac_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_lc_ctrl_otp_hw_cfg0.40723399 |
| Short name | T1279 |
| Test name | |
| Test status | |
| Simulation time | 3150963690 ps |
| CPU time | 233.74 seconds |
| Started | Jul 03 07:53:55 PM PDT 24 |
| Finished | Jul 03 07:57:50 PM PDT 24 |
| Peak memory | 610596 kb |
| Host | smart-3f7f2b3b-794e-439e-b8c4-3207e410e4e2 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_otp_hw_cfg0_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40723399 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_ctrl_otp_hw_cfg0.40723399 |
| Directory | /workspace/1.chip_sw_lc_ctrl_otp_hw_cfg0/latest |
| Test location | /workspace/coverage/default/1.chip_sw_lc_ctrl_program_error.493860175 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 4478843692 ps |
| CPU time | 595.65 seconds |
| Started | Jul 03 08:00:49 PM PDT 24 |
| Finished | Jul 03 08:10:46 PM PDT 24 |
| Peak memory | 610116 kb |
| Host | smart-fe1c5486-ccd7-488a-983f-8e272a76f4bb |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=lc_ctrl_program_error:1:new_rules,test_rom:0 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=493860175 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_program_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_ctrl_program_error.493860175 |
| Directory | /workspace/1.chip_sw_lc_ctrl_program_error/latest |
| Test location | /workspace/coverage/default/1.chip_sw_lc_ctrl_rand_to_scrap.2453703695 |
| Short name | T628 |
| Test name | |
| Test status | |
| Simulation time | 3188086623 ps |
| CPU time | 136.05 seconds |
| Started | Jul 03 07:53:28 PM PDT 24 |
| Finished | Jul 03 07:55:45 PM PDT 24 |
| Peak memory | 619036 kb |
| Host | smart-ee2d25a5-3fc0-4d1b-99cb-85539ab829be |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=lc_ctrl_scrap_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24537036 95 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_scrap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_ctrl_rand_to_scrap.2453703695 |
| Directory | /workspace/1.chip_sw_lc_ctrl_rand_to_scrap/latest |
| Test location | /workspace/coverage/default/1.chip_sw_lc_ctrl_transition.3091464478 |
| Short name | T1168 |
| Test name | |
| Test status | |
| Simulation time | 4769508535 ps |
| CPU time | 388.86 seconds |
| Started | Jul 03 07:58:21 PM PDT 24 |
| Finished | Jul 03 08:04:50 PM PDT 24 |
| Peak memory | 624896 kb |
| Host | smart-78abc774-42a3-451e-91ec-48582d7f1503 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3091464478 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_ctrl_transition.3091464478 |
| Directory | /workspace/1.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock.706024005 |
| Short name | T1035 |
| Test name | |
| Test status | |
| Simulation time | 2344634255 ps |
| CPU time | 108.29 seconds |
| Started | Jul 03 07:54:18 PM PDT 24 |
| Finished | Jul 03 07:56:07 PM PDT 24 |
| Peak memory | 613980 kb |
| Host | smart-04edd360-a6cf-495e-a7ad-73fe6308f8cb |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +exp_volatile_raw_unlock_en=0 +sw_build_device=sim_dv +sw_images=lc_ctrl_volatile_raw_unlock_tes t:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=706024005 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_ctrl_volatile_raw_unlock.706024005 |
| Directory | /workspace/1.chip_sw_lc_ctrl_volatile_raw_unlock/latest |
| Test location | /workspace/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.552501741 |
| Short name | T627 |
| Test name | |
| Test status | |
| Simulation time | 2191819013 ps |
| CPU time | 124.79 seconds |
| Started | Jul 03 07:57:07 PM PDT 24 |
| Finished | Jul 03 07:59:12 PM PDT 24 |
| Peak memory | 616904 kb |
| Host | smart-8e3b6408-a3cf-4860-ba79-7efcd3ca8981 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceExternal48Mhz +exp_volatile_raw_unlock_en=0 +sw_build_device=s im_dv +sw_images=lc_ctrl_volatile_raw_unlock_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=552501741 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST _SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 1.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.552501741 |
| Directory | /workspace/1.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz/latest |
| Test location | /workspace/coverage/default/1.chip_sw_lc_walkthrough_prod.1253049091 |
| Short name | T1174 |
| Test name | |
| Test status | |
| Simulation time | 50313755797 ps |
| CPU time | 5455.38 seconds |
| Started | Jul 03 07:55:37 PM PDT 24 |
| Finished | Jul 03 09:26:34 PM PDT 24 |
| Peak memory | 624172 kb |
| Host | smart-093cad63-3edf-4b51-95d0-0e1ea2efedd2 |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStProd +sw_test_timeout_ns=200_000_000 +sw_build_d evice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1253049091 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chi p_sw_lc_walkthrough_prod.1253049091 |
| Directory | /workspace/1.chip_sw_lc_walkthrough_prod/latest |
| Test location | /workspace/coverage/default/1.chip_sw_lc_walkthrough_prodend.2455043397 |
| Short name | T1061 |
| Test name | |
| Test status | |
| Simulation time | 10011657856 ps |
| CPU time | 932.32 seconds |
| Started | Jul 03 07:54:01 PM PDT 24 |
| Finished | Jul 03 08:09:34 PM PDT 24 |
| Peak memory | 618368 kb |
| Host | smart-ed39fa4a-7112-405c-b7d9-874a5aab04d4 |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStProdEnd +sw_build_device=sim_dv +sw_images=lc_wa lkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2455043397 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_walkthrough_prodend.2455043397 |
| Directory | /workspace/1.chip_sw_lc_walkthrough_prodend/latest |
| Test location | /workspace/coverage/default/1.chip_sw_lc_walkthrough_rma.218244908 |
| Short name | T230 |
| Test name | |
| Test status | |
| Simulation time | 45860205000 ps |
| CPU time | 4783.39 seconds |
| Started | Jul 03 07:54:56 PM PDT 24 |
| Finished | Jul 03 09:14:41 PM PDT 24 |
| Peak memory | 619272 kb |
| Host | smart-b12b487a-818d-432a-a1fa-647dd20d9056 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStRma +flash_program_latency=5 +sw_test_timeout_ns=200_000_000 +sw_build_de vice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218244908 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=ch ip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_ sw_lc_walkthrough_rma.218244908 |
| Directory | /workspace/1.chip_sw_lc_walkthrough_rma/latest |
| Test location | /workspace/coverage/default/1.chip_sw_lc_walkthrough_testunlocks.2282552246 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 27748090810 ps |
| CPU time | 2314.98 seconds |
| Started | Jul 03 07:54:12 PM PDT 24 |
| Finished | Jul 03 08:32:47 PM PDT 24 |
| Peak memory | 619188 kb |
| Host | smart-8de868d1-09fd-40ed-bdac-9d4bd0bb8810 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStTestUnlock7 +sw_build_device=sim_dv +sw_images=lc_walkthrough_testunlocks _test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2282552246 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_testunlocks_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_walkthrough_testun locks.2282552246 |
| Directory | /workspace/1.chip_sw_lc_walkthrough_testunlocks/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq.1441307198 |
| Short name | T1218 |
| Test name | |
| Test status | |
| Simulation time | 17097130384 ps |
| CPU time | 3488.85 seconds |
| Started | Jul 03 08:03:40 PM PDT 24 |
| Finished | Jul 03 09:01:51 PM PDT 24 |
| Peak memory | 610792 kb |
| Host | smart-b770ebc1-7b66-4f08-b8ff-9cb86540b166 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=28_000_000 +rng_srate_value=30 +sw_build_device=sim_dv +sw_images=otbn_ecdsa_op_irq_test:1:new_rules,test_ rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ random_seed=1441307198 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otbn_ecdsa_op_irq.1441307198 |
| Directory | /workspace/1.chip_sw_otbn_ecdsa_op_irq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en.2611568399 |
| Short name | T1196 |
| Test name | |
| Test status | |
| Simulation time | 18328237685 ps |
| CPU time | 4169.62 seconds |
| Started | Jul 03 07:59:25 PM PDT 24 |
| Finished | Jul 03 09:08:57 PM PDT 24 |
| Peak memory | 609480 kb |
| Host | smart-9b02e045-7e47-452a-a6e9-62e2ce6abf6d |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=33_000_000 +rng_srate_value=30 +en_jitter=1 +sw_build_device=sim_dv +sw_images=otbn_ecdsa_op_irq_test:1:ne w_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=2611568399 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otbn_ecdsa_op_irq_jitter_en.2611568399 |
| Directory | /workspace/1.chip_sw_otbn_ecdsa_op_irq_jitter_en/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.2347986020 |
| Short name | T908 |
| Test name | |
| Test status | |
| Simulation time | 24884973539 ps |
| CPU time | 3473.08 seconds |
| Started | Jul 03 08:00:59 PM PDT 24 |
| Finished | Jul 03 08:58:53 PM PDT 24 |
| Peak memory | 610796 kb |
| Host | smart-206818d8-219a-4e05-8d34-318546ca5d00 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=33_000_000 +rng_srate_value=30 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=otbn_e cdsa_op_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2347986020 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otbn_ecdsa_op_irq_jitter_en_redu ced_freq.2347986020 |
| Directory | /workspace/1.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otbn_mem_scramble.1387272494 |
| Short name | T1181 |
| Test name | |
| Test status | |
| Simulation time | 3743015382 ps |
| CPU time | 490.16 seconds |
| Started | Jul 03 07:55:42 PM PDT 24 |
| Finished | Jul 03 08:03:53 PM PDT 24 |
| Peak memory | 608936 kb |
| Host | smart-d25c3991-3579-4a45-9b1d-5da85ca0ac9b |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=otbn _mem_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387272494 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otbn_mem_scramble.1387272494 |
| Directory | /workspace/1.chip_sw_otbn_mem_scramble/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otbn_randomness.4140445032 |
| Short name | T971 |
| Test name | |
| Test status | |
| Simulation time | 6180736750 ps |
| CPU time | 977.14 seconds |
| Started | Jul 03 07:57:42 PM PDT 24 |
| Finished | Jul 03 08:13:59 PM PDT 24 |
| Peak memory | 610868 kb |
| Host | smart-2f02ab72-537f-493e-bd11-49856f9a1b68 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=30 +sw_build_device=sim_dv +sw_images=otbn_randomness_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=4140445032 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otbn_randomness.4140445032 |
| Directory | /workspace/1.chip_sw_otbn_randomness/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otbn_smoketest.1750145163 |
| Short name | T1223 |
| Test name | |
| Test status | |
| Simulation time | 8400829892 ps |
| CPU time | 1771.8 seconds |
| Started | Jul 03 08:04:10 PM PDT 24 |
| Finished | Jul 03 08:33:43 PM PDT 24 |
| Peak memory | 610712 kb |
| Host | smart-9c03654b-6ef7-4bf4-9fb9-96ccacd09e50 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otbn_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1750145163 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 1.chip_sw_otbn_smoketest.1750145163 |
| Directory | /workspace/1.chip_sw_otbn_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otp_ctrl_ecc_error_vendor_test.2100165452 |
| Short name | T271 |
| Test name | |
| Test status | |
| Simulation time | 3362670595 ps |
| CPU time | 271.41 seconds |
| Started | Jul 03 07:55:23 PM PDT 24 |
| Finished | Jul 03 07:59:55 PM PDT 24 |
| Peak memory | 610596 kb |
| Host | smart-2d4815fe-7bc2-433d-8fb8-9928d1036f0b |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_vendor_test_ecc_error_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2100165452 -assert nopostp roc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_vendor_test_ecc_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otp_ctrl_ecc_error_vendor_test.2100165452 |
| Directory | /workspace/1.chip_sw_otp_ctrl_ecc_error_vendor_test/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_dev.975580973 |
| Short name | T1156 |
| Test name | |
| Test status | |
| Simulation time | 8435511916 ps |
| CPU time | 1396.33 seconds |
| Started | Jul 03 07:54:32 PM PDT 24 |
| Finished | Jul 03 08:17:48 PM PDT 24 |
| Peak memory | 610648 kb |
| Host | smart-63b282a9-325e-4111-b358-91348b2dbe9a |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStDev +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,tes t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=975580973 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otp_ctrl_lc_signals_dev.975580973 |
| Directory | /workspace/1.chip_sw_otp_ctrl_lc_signals_dev/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_prod.4126148278 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 7056403256 ps |
| CPU time | 1449.08 seconds |
| Started | Jul 03 07:53:51 PM PDT 24 |
| Finished | Jul 03 08:18:01 PM PDT 24 |
| Peak memory | 610644 kb |
| Host | smart-e3d7956c-6284-4ab7-8e5f-a107dfb6a55f |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=4126148278 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otp_ctrl_lc_signals_prod.4126148278 |
| Directory | /workspace/1.chip_sw_otp_ctrl_lc_signals_prod/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_rma.955891932 |
| Short name | T1255 |
| Test name | |
| Test status | |
| Simulation time | 8637823198 ps |
| CPU time | 1572.52 seconds |
| Started | Jul 03 07:55:14 PM PDT 24 |
| Finished | Jul 03 08:21:28 PM PDT 24 |
| Peak memory | 609484 kb |
| Host | smart-87e21b12-1ab0-4291-b605-245e19f9e2ec |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRma +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,tes t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=955891932 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otp_ctrl_lc_signals_rma.955891932 |
| Directory | /workspace/1.chip_sw_otp_ctrl_lc_signals_rma/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_test_unlocked0.3825225888 |
| Short name | T1205 |
| Test name | |
| Test status | |
| Simulation time | 3762437390 ps |
| CPU time | 743.21 seconds |
| Started | Jul 03 07:55:45 PM PDT 24 |
| Finished | Jul 03 08:08:10 PM PDT 24 |
| Peak memory | 610660 kb |
| Host | smart-2ff8c78e-be51-4e15-a3e0-5df398b22228 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new _rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/s im.tcl +ntb_random_seed=3825225888 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otp_ctrl_lc_signals_test_unlocked0.3825225888 |
| Directory | /workspace/1.chip_sw_otp_ctrl_lc_signals_test_unlocked0/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otp_ctrl_smoketest.3202884606 |
| Short name | T1067 |
| Test name | |
| Test status | |
| Simulation time | 2780898630 ps |
| CPU time | 283.61 seconds |
| Started | Jul 03 08:05:25 PM PDT 24 |
| Finished | Jul 03 08:10:09 PM PDT 24 |
| Peak memory | 610652 kb |
| Host | smart-dac2c21a-a464-4561-abd9-b19739967da6 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3202884606 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 1.chip_sw_otp_ctrl_smoketest.3202884606 |
| Directory | /workspace/1.chip_sw_otp_ctrl_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pattgen_ios.3341049446 |
| Short name | T212 |
| Test name | |
| Test status | |
| Simulation time | 3492222460 ps |
| CPU time | 267.85 seconds |
| Started | Jul 03 07:53:24 PM PDT 24 |
| Finished | Jul 03 07:57:53 PM PDT 24 |
| Peak memory | 610440 kb |
| Host | smart-936e2941-fd92-41bc-9653-c291bfdee18c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=5_000_000 +sw_build_device=sim_dv +sw_images=pattgen_ios_test:1:new_rules,test_rom:0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3341049446 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_patt_ios_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pattgen_ios.3341049446 |
| Directory | /workspace/1.chip_sw_pattgen_ios/latest |
| Test location | /workspace/coverage/default/1.chip_sw_plic_sw_irq.2753917186 |
| Short name | T252 |
| Test name | |
| Test status | |
| Simulation time | 2296017104 ps |
| CPU time | 237.59 seconds |
| Started | Jul 03 07:59:43 PM PDT 24 |
| Finished | Jul 03 08:03:41 PM PDT 24 |
| Peak memory | 610636 kb |
| Host | smart-7f9ee31b-f650-4706-9385-e7e02f7d9dc1 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_sw_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2753917186 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 1.chip_sw_plic_sw_irq.2753917186 |
| Directory | /workspace/1.chip_sw_plic_sw_irq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_power_idle_load.3770050831 |
| Short name | T1005 |
| Test name | |
| Test status | |
| Simulation time | 3706301320 ps |
| CPU time | 486.69 seconds |
| Started | Jul 03 08:00:58 PM PDT 24 |
| Finished | Jul 03 08:09:06 PM PDT 24 |
| Peak memory | 609584 kb |
| Host | smart-ffcaa677-aa20-43d3-a58a-6da8aa4e17f1 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=chip_power_idle_load:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3770050831 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_idle_load_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_power_idle_load.3770050831 |
| Directory | /workspace/1.chip_sw_power_idle_load/latest |
| Test location | /workspace/coverage/default/1.chip_sw_power_sleep_load.493990356 |
| Short name | T1113 |
| Test name | |
| Test status | |
| Simulation time | 10800804904 ps |
| CPU time | 578.55 seconds |
| Started | Jul 03 08:01:33 PM PDT 24 |
| Finished | Jul 03 08:11:12 PM PDT 24 |
| Peak memory | 610292 kb |
| Host | smart-95a4b3c3-8a09-41e9-9f11-492676d6b0ac |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=chip_power_sleep_load:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=493990356 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_sleep_load_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 1.chip_sw_power_sleep_load.493990356 |
| Directory | /workspace/1.chip_sw_power_sleep_load/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_b2b_sleep_reset_req.937732109 |
| Short name | T652 |
| Test name | |
| Test status | |
| Simulation time | 22235465238 ps |
| CPU time | 2091.74 seconds |
| Started | Jul 03 07:58:56 PM PDT 24 |
| Finished | Jul 03 08:33:49 PM PDT 24 |
| Peak memory | 610744 kb |
| Host | smart-f21c7ece-8d21-4421-a995-aa816c2e718e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=35_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_b2b_sleep_reset_test:1:new_rules,test_rom:0 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=937 732109 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_repeat_reset_wkup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_b2b_sleep_reset_req.937732109 |
| Directory | /workspace/1.chip_sw_pwrmgr_b2b_sleep_reset_req/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.3757557214 |
| Short name | T264 |
| Test name | |
| Test status | |
| Simulation time | 18077512821 ps |
| CPU time | 1750.4 seconds |
| Started | Jul 03 07:55:21 PM PDT 24 |
| Finished | Jul 03 08:24:32 PM PDT 24 |
| Peak memory | 610384 kb |
| Host | smart-74483b48-e806-480d-af00-296ace92f321 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3757557214 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.3757557214 |
| Directory | /workspace/1.chip_sw_pwrmgr_deep_sleep_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_wake_ups.3556945614 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 26056201742 ps |
| CPU time | 1747.36 seconds |
| Started | Jul 03 08:01:17 PM PDT 24 |
| Finished | Jul 03 08:30:25 PM PDT 24 |
| Peak memory | 609656 kb |
| Host | smart-2e9c290a-ffc4-4835-8ae5-81e61db7b6a0 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_all_wake_ups:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3556945614 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_deep_sleep_all_wake_ups.3556945614 |
| Directory | /workspace/1.chip_sw_pwrmgr_deep_sleep_all_wake_ups/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_por_reset.1798738677 |
| Short name | T927 |
| Test name | |
| Test status | |
| Simulation time | 8601324812 ps |
| CPU time | 696.87 seconds |
| Started | Jul 03 07:58:45 PM PDT 24 |
| Finished | Jul 03 08:10:22 PM PDT 24 |
| Peak memory | 610784 kb |
| Host | smart-285714d3-62b1-4414-87d8-0eb6a55905b1 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_por_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1798738677 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_por_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage /default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_deep_sleep_por_reset.1798738677 |
| Directory | /workspace/1.chip_sw_pwrmgr_deep_sleep_por_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.1722538954 |
| Short name | T1167 |
| Test name | |
| Test status | |
| Simulation time | 7949592624 ps |
| CPU time | 353.28 seconds |
| Started | Jul 03 07:58:38 PM PDT 24 |
| Finished | Jul 03 08:04:32 PM PDT 24 |
| Peak memory | 615760 kb |
| Host | smart-745f5116-4931-489c-8c64-2448f118a842 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_power_glitch_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1722538954 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.1722538954 |
| Directory | /workspace/1.chip_sw_pwrmgr_deep_sleep_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_full_aon_reset.203664100 |
| Short name | T1091 |
| Test name | |
| Test status | |
| Simulation time | 6989253118 ps |
| CPU time | 470.62 seconds |
| Started | Jul 03 07:55:41 PM PDT 24 |
| Finished | Jul 03 08:03:32 PM PDT 24 |
| Peak memory | 610616 kb |
| Host | smart-89eca868-cda5-4398-a012-548227491727 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=203664100 -assert nopostproc +UVM_TESTNAME=ch ip_base_test +UVM_TEST_SEQ=chip_sw_full_aon_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 1.chip_sw_pwrmgr_full_aon_reset.203664100 |
| Directory | /workspace/1.chip_sw_pwrmgr_full_aon_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_lowpower_cancel.2584976015 |
| Short name | T325 |
| Test name | |
| Test status | |
| Simulation time | 3422548240 ps |
| CPU time | 359.77 seconds |
| Started | Jul 03 08:00:34 PM PDT 24 |
| Finished | Jul 03 08:06:34 PM PDT 24 |
| Peak memory | 610712 kb |
| Host | smart-db73ceb0-11fe-47b9-aba1-27b5a62a3920 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_lowpower_cancel_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2584976015 -assert nopostproc +UVM _TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 1.chip_sw_pwrmgr_lowpower_cancel.2584976015 |
| Directory | /workspace/1.chip_sw_pwrmgr_lowpower_cancel/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_main_power_glitch_reset.1004935199 |
| Short name | T1132 |
| Test name | |
| Test status | |
| Simulation time | 3961292912 ps |
| CPU time | 290.86 seconds |
| Started | Jul 03 07:55:35 PM PDT 24 |
| Finished | Jul 03 08:00:26 PM PDT 24 |
| Peak memory | 615308 kb |
| Host | smart-30724344-7358-4e76-9953-83b3e38b6302 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_main_power_glitch_test:1:new_rules,test_rom:0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=1004935199 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_main_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_main_power_glitch_reset.1004935199 |
| Directory | /workspace/1.chip_sw_pwrmgr_main_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.1421779167 |
| Short name | T883 |
| Test name | |
| Test status | |
| Simulation time | 14771191019 ps |
| CPU time | 1591.14 seconds |
| Started | Jul 03 07:55:13 PM PDT 24 |
| Finished | Jul 03 08:21:45 PM PDT 24 |
| Peak memory | 610880 kb |
| Host | smart-c35b2d73-7c02-4c20-9c8c-9f4a72808290 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421779167 -assert nop ostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.1421779167 |
| Directory | /workspace/1.chip_sw_pwrmgr_normal_sleep_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_por_reset.1385821789 |
| Short name | T1183 |
| Test name | |
| Test status | |
| Simulation time | 8309551186 ps |
| CPU time | 804.71 seconds |
| Started | Jul 03 07:55:02 PM PDT 24 |
| Finished | Jul 03 08:08:28 PM PDT 24 |
| Peak memory | 610568 kb |
| Host | smart-bfb452c8-3d84-4d9d-959b-cf23c1fdedcd |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_por_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385821789 -assert nopostpr oc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_por_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_normal_sleep_por_reset.1385821789 |
| Directory | /workspace/1.chip_sw_pwrmgr_normal_sleep_por_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_reset_reqs.2255541504 |
| Short name | T878 |
| Test name | |
| Test status | |
| Simulation time | 22017610575 ps |
| CPU time | 2513.43 seconds |
| Started | Jul 03 07:56:08 PM PDT 24 |
| Finished | Jul 03 08:38:02 PM PDT 24 |
| Peak memory | 610860 kb |
| Host | smart-b1ae84b4-1777-4b4a-8b18-e5efe394d31e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_all_reset_reqs_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2255541504 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_random_sleep_all_reset_reqs.2255541504 |
| Directory | /workspace/1.chip_sw_pwrmgr_random_sleep_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_power_glitch_reset.1806453517 |
| Short name | T1275 |
| Test name | |
| Test status | |
| Simulation time | 33212756286 ps |
| CPU time | 2851.27 seconds |
| Started | Jul 03 07:56:24 PM PDT 24 |
| Finished | Jul 03 08:43:57 PM PDT 24 |
| Peak memory | 611356 kb |
| Host | smart-acb74114-fda4-48a1-a556-854b9e8080d2 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_test_timeout_ns=24_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_power _glitch_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1806453517 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_random_power_glit ch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_random_s leep_power_glitch_reset.1806453517 |
| Directory | /workspace/1.chip_sw_pwrmgr_random_sleep_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.3962428589 |
| Short name | T355 |
| Test name | |
| Test status | |
| Simulation time | 5602497320 ps |
| CPU time | 369.79 seconds |
| Started | Jul 03 08:01:02 PM PDT 24 |
| Finished | Jul 03 08:07:13 PM PDT 24 |
| Peak memory | 610728 kb |
| Host | smart-0f69e73e-dba4-469b-870d-87dd308ece0d |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sensor_ctrl_deep_sleep_wake_up:1:new_rul es,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=3962428589 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_sensor_ctrl_deep_s leep_wake_up.3962428589 |
| Directory | /workspace/1.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_disabled.2586548043 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 2906390456 ps |
| CPU time | 300.27 seconds |
| Started | Jul 03 07:57:27 PM PDT 24 |
| Finished | Jul 03 08:02:28 PM PDT 24 |
| Peak memory | 610640 kb |
| Host | smart-28f185a6-72d0-4a9b-bab3-74a48c64f47b |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_disabled_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2586548043 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 1.chip_sw_pwrmgr_sleep_disabled.2586548043 |
| Directory | /workspace/1.chip_sw_pwrmgr_sleep_disabled/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_power_glitch_reset.3600273393 |
| Short name | T1096 |
| Test name | |
| Test status | |
| Simulation time | 4956048373 ps |
| CPU time | 427.06 seconds |
| Started | Jul 03 07:56:05 PM PDT 24 |
| Finished | Jul 03 08:03:12 PM PDT 24 |
| Peak memory | 615564 kb |
| Host | smart-73e6ca51-a973-4c15-b480-683407742905 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_power_glitch_test:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s eed=3600273393 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_main_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_sleep_power_glitch_reset.3600273393 |
| Directory | /workspace/1.chip_sw_pwrmgr_sleep_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.2796756998 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 5098013856 ps |
| CPU time | 509.21 seconds |
| Started | Jul 03 07:59:11 PM PDT 24 |
| Finished | Jul 03 08:07:40 PM PDT 24 |
| Peak memory | 608144 kb |
| Host | smart-01afb8c4-77e0-4ec0-8c74-9b2a8bec041d |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=8_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_wakeup_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27967569 98 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.2796756998 |
| Directory | /workspace/1.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_wake_5_bug.3855509487 |
| Short name | T1172 |
| Test name | |
| Test status | |
| Simulation time | 6586375976 ps |
| CPU time | 669.12 seconds |
| Started | Jul 03 08:01:22 PM PDT 24 |
| Finished | Jul 03 08:12:32 PM PDT 24 |
| Peak memory | 610700 kb |
| Host | smart-13db9e39-8d75-4951-be84-6f6b92e4c78a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_wake_5_bug_test:1:new_rules,test_r om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=3855509487 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_sleep_wake_5_bug.3855509487 |
| Directory | /workspace/1.chip_sw_pwrmgr_sleep_wake_5_bug/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_smoketest.669883533 |
| Short name | T911 |
| Test name | |
| Test status | |
| Simulation time | 6418183392 ps |
| CPU time | 525.38 seconds |
| Started | Jul 03 08:04:17 PM PDT 24 |
| Finished | Jul 03 08:13:03 PM PDT 24 |
| Peak memory | 610700 kb |
| Host | smart-ec5c24a7-c2e3-45ee-bffa-a907b7e4457c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=10000000 +sw_build_device=sim_dv +sw_images=pwrmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=669883533 -asser t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_smoketest.669883533 |
| Directory | /workspace/1.chip_sw_pwrmgr_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_sysrst_ctrl_reset.4005336073 |
| Short name | T1173 |
| Test name | |
| Test status | |
| Simulation time | 6768525804 ps |
| CPU time | 1198.44 seconds |
| Started | Jul 03 07:55:03 PM PDT 24 |
| Finished | Jul 03 08:15:02 PM PDT 24 |
| Peak memory | 608960 kb |
| Host | smart-8f46251d-fdda-4844-aa3b-3a231687cb57 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_sysrst_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4005336073 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_sysrst_ctrl_reset.4005336073 |
| Directory | /workspace/1.chip_sw_pwrmgr_sysrst_ctrl_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_usb_clk_disabled_when_active.2415888001 |
| Short name | T1144 |
| Test name | |
| Test status | |
| Simulation time | 4807607082 ps |
| CPU time | 454.87 seconds |
| Started | Jul 03 08:02:42 PM PDT 24 |
| Finished | Jul 03 08:10:19 PM PDT 24 |
| Peak memory | 608284 kb |
| Host | smart-cea1f116-fa9e-4fbc-a015-78130dc283de |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_usb_clk_disabled_when_active_test:1:new_rules,test_rom:0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2415888001 -assert no postproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_usb_clk_disabled_when_active.2415888001 |
| Directory | /workspace/1.chip_sw_pwrmgr_usb_clk_disabled_when_active/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_usbdev_smoketest.3595414204 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 5069139580 ps |
| CPU time | 501.2 seconds |
| Started | Jul 03 08:04:18 PM PDT 24 |
| Finished | Jul 03 08:12:41 PM PDT 24 |
| Peak memory | 610716 kb |
| Host | smart-912d329e-1a5e-4630-a27b-853864688bce |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_usbdev_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3595414204 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_usbdev_smoketest.3595414204 |
| Directory | /workspace/1.chip_sw_pwrmgr_usbdev_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_wdog_reset.1828967110 |
| Short name | T1034 |
| Test name | |
| Test status | |
| Simulation time | 4880066920 ps |
| CPU time | 560.25 seconds |
| Started | Jul 03 07:55:53 PM PDT 24 |
| Finished | Jul 03 08:05:14 PM PDT 24 |
| Peak memory | 610628 kb |
| Host | smart-5d6cca6d-2fa4-4276-be08-85dd018450f2 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_wdog_reset_reqs_test:1:new_rules,test_rom:0 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=182 8967110 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_wdog_reset.1828967110 |
| Directory | /workspace/1.chip_sw_pwrmgr_wdog_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rom_ctrl_integrity_check.3566887126 |
| Short name | T386 |
| Test name | |
| Test status | |
| Simulation time | 9065851668 ps |
| CPU time | 665.88 seconds |
| Started | Jul 03 07:58:54 PM PDT 24 |
| Finished | Jul 03 08:10:01 PM PDT 24 |
| Peak memory | 611592 kb |
| Host | smart-784e76d7-700c-4206-900d-d243fe55f04a |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rom_ctrl_integrity_check_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3566887126 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_ctrl_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rom_ctrl_integrity_check.3566887126 |
| Directory | /workspace/1.chip_sw_rom_ctrl_integrity_check/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rstmgr_cpu_info.2380410875 |
| Short name | T260 |
| Test name | |
| Test status | |
| Simulation time | 5251334420 ps |
| CPU time | 758.62 seconds |
| Started | Jul 03 07:54:25 PM PDT 24 |
| Finished | Jul 03 08:07:05 PM PDT 24 |
| Peak memory | 608396 kb |
| Host | smart-95385f55-8552-4ee0-9478-d256503a0f1f |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_cpu_info_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2380410875 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 1.chip_sw_rstmgr_cpu_info.2380410875 |
| Directory | /workspace/1.chip_sw_rstmgr_cpu_info/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rstmgr_rst_cnsty_escalation.1203214997 |
| Short name | T1114 |
| Test name | |
| Test status | |
| Simulation time | 4982816040 ps |
| CPU time | 780.11 seconds |
| Started | Jul 03 07:52:39 PM PDT 24 |
| Finished | Jul 03 08:05:39 PM PDT 24 |
| Peak memory | 640876 kb |
| Host | smart-429b3316-1223-48df-b694-124d87657bd2 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1203214997 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rstmgr_cnsty_fault_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rstmgr_rst_cnsty_escalation.1203214997 |
| Directory | /workspace/1.chip_sw_rstmgr_rst_cnsty_escalation/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rstmgr_smoketest.3073925804 |
| Short name | T1108 |
| Test name | |
| Test status | |
| Simulation time | 2734547472 ps |
| CPU time | 230.02 seconds |
| Started | Jul 03 08:04:44 PM PDT 24 |
| Finished | Jul 03 08:08:35 PM PDT 24 |
| Peak memory | 610632 kb |
| Host | smart-ff06d9af-b8b8-4e06-b585-e04f362af55a |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3073925804 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 1.chip_sw_rstmgr_smoketest.3073925804 |
| Directory | /workspace/1.chip_sw_rstmgr_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rstmgr_sw_req.3852993838 |
| Short name | T836 |
| Test name | |
| Test status | |
| Simulation time | 4311055448 ps |
| CPU time | 354.29 seconds |
| Started | Jul 03 07:54:06 PM PDT 24 |
| Finished | Jul 03 08:00:01 PM PDT 24 |
| Peak memory | 609272 kb |
| Host | smart-ae415ca7-5ea2-45dc-9b5d-0f4f423968d4 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_sw_req_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3852993838 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 1.chip_sw_rstmgr_sw_req.3852993838 |
| Directory | /workspace/1.chip_sw_rstmgr_sw_req/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rstmgr_sw_rst.3722471384 |
| Short name | T1240 |
| Test name | |
| Test status | |
| Simulation time | 2952982784 ps |
| CPU time | 307.56 seconds |
| Started | Jul 03 07:54:37 PM PDT 24 |
| Finished | Jul 03 07:59:46 PM PDT 24 |
| Peak memory | 610640 kb |
| Host | smart-73eff7fc-c45b-4945-9a39-be72ba4ae39a |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_sw_rst_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3722471384 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rstmgr_sw_rst.3722471384 |
| Directory | /workspace/1.chip_sw_rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rv_core_ibex_address_translation.1851838557 |
| Short name | T285 |
| Test name | |
| Test status | |
| Simulation time | 2935411608 ps |
| CPU time | 287.01 seconds |
| Started | Jul 03 08:01:46 PM PDT 24 |
| Finished | Jul 03 08:06:34 PM PDT 24 |
| Peak memory | 610568 kb |
| Host | smart-c6cfa247-aa34-41cb-a6e7-e5b48792b2e2 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=7_000_000 +sw_build_device=sim_dv +sw_images=rv_core_ibex_address_translation_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=1851838557 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_core_ibex_address_translation.1851838557 |
| Directory | /workspace/1.chip_sw_rv_core_ibex_address_translation/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rv_core_ibex_icache_invalidate.2783591250 |
| Short name | T202 |
| Test name | |
| Test status | |
| Simulation time | 2911961063 ps |
| CPU time | 298.91 seconds |
| Started | Jul 03 08:01:34 PM PDT 24 |
| Finished | Jul 03 08:06:33 PM PDT 24 |
| Peak memory | 610960 kb |
| Host | smart-5d814e25-f54a-43a8-987e-2030ab926748 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_core_ibex_icache_invalidate_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2783591250 -assert nopostp roc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_core_ibex_icache_invalidate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_core_ibex_icache_invalidate.2783591250 |
| Directory | /workspace/1.chip_sw_rv_core_ibex_icache_invalidate/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rv_core_ibex_nmi_irq.4289200722 |
| Short name | T498 |
| Test name | |
| Test status | |
| Simulation time | 4763274318 ps |
| CPU time | 821.75 seconds |
| Started | Jul 03 07:55:45 PM PDT 24 |
| Finished | Jul 03 08:09:28 PM PDT 24 |
| Peak memory | 608064 kb |
| Host | smart-5fb246f1-f94d-4edb-bce0-3617fecc150f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=10_000_000 +sw_build_device=sim_dv +sw_images=rv_core_ibex_nmi_irq_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42892 00722 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_core_ibex_nmi_irq.4289200722 |
| Directory | /workspace/1.chip_sw_rv_core_ibex_nmi_irq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rv_core_ibex_rnd.1879924806 |
| Short name | T966 |
| Test name | |
| Test status | |
| Simulation time | 5789191852 ps |
| CPU time | 1012.29 seconds |
| Started | Jul 03 07:55:29 PM PDT 24 |
| Finished | Jul 03 08:12:22 PM PDT 24 |
| Peak memory | 610560 kb |
| Host | smart-ce85462a-4663-484b-b8cf-dfc8d66841fc |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +rng_srate_value_max=32 +sw_build_device=sim_dv +sw_images=rv_core_ibex_rnd_test:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=1879924806 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_core_ibex_rnd.1879924806 |
| Directory | /workspace/1.chip_sw_rv_core_ibex_rnd/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rv_dm_access_after_escalation_reset.2358844421 |
| Short name | T621 |
| Test name | |
| Test status | |
| Simulation time | 4917118909 ps |
| CPU time | 572.04 seconds |
| Started | Jul 03 08:01:09 PM PDT 24 |
| Finished | Jul 03 08:10:42 PM PDT 24 |
| Peak memory | 624312 kb |
| Host | smart-bd709ccc-9e7c-4c56-a05e-a7e92a601e8a |
| User | root |
| Command | /workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=alert_handler_escalation_test:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2358844421 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_access_after_escalation_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_dm_access_after_escalation_reset.2358844421 |
| Directory | /workspace/1.chip_sw_rv_dm_access_after_escalation_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.3044838482 |
| Short name | T350 |
| Test name | |
| Test status | |
| Simulation time | 5074677500 ps |
| CPU time | 700.31 seconds |
| Started | Jul 03 08:02:08 PM PDT 24 |
| Finished | Jul 03 08:13:49 PM PDT 24 |
| Peak memory | 618332 kb |
| Host | smart-4c39be63-fde5-4489-97cb-11358a376953 |
| User | root |
| Command | /workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_ndm_reset_req_when_cpu_halted_rma:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=304483 8482 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_ndm_reset_when_cpu_halted_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.3044838482 |
| Directory | /workspace/1.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rv_plic_smoketest.178181325 |
| Short name | T1258 |
| Test name | |
| Test status | |
| Simulation time | 3236786140 ps |
| CPU time | 239.08 seconds |
| Started | Jul 03 08:02:33 PM PDT 24 |
| Finished | Jul 03 08:06:33 PM PDT 24 |
| Peak memory | 610648 kb |
| Host | smart-62d51ab6-b853-45e3-a5e7-ab4ca73280c9 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_plic_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=178181325 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 1.chip_sw_rv_plic_smoketest.178181325 |
| Directory | /workspace/1.chip_sw_rv_plic_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rv_timer_irq.1568149503 |
| Short name | T1002 |
| Test name | |
| Test status | |
| Simulation time | 2347977512 ps |
| CPU time | 236.05 seconds |
| Started | Jul 03 08:02:42 PM PDT 24 |
| Finished | Jul 03 08:06:40 PM PDT 24 |
| Peak memory | 608660 kb |
| Host | smart-ab472047-0e15-4d85-bc28-d498c42dc011 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1568149503 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 1.chip_sw_rv_timer_irq.1568149503 |
| Directory | /workspace/1.chip_sw_rv_timer_irq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rv_timer_smoketest.2654024879 |
| Short name | T254 |
| Test name | |
| Test status | |
| Simulation time | 3214070280 ps |
| CPU time | 254.57 seconds |
| Started | Jul 03 08:03:26 PM PDT 24 |
| Finished | Jul 03 08:07:41 PM PDT 24 |
| Peak memory | 610632 kb |
| Host | smart-905ee15a-1f43-422a-b7aa-0453ba55c6c8 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2654024879 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 1.chip_sw_rv_timer_smoketest.2654024879 |
| Directory | /workspace/1.chip_sw_rv_timer_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sensor_ctrl_alert.1069753423 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 6647048488 ps |
| CPU time | 613.51 seconds |
| Started | Jul 03 07:59:08 PM PDT 24 |
| Finished | Jul 03 08:09:23 PM PDT 24 |
| Peak memory | 610640 kb |
| Host | smart-8f6761c8-e3e8-4d5c-844a-5e8ca8faa80d |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_alert_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10697534 23 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sensor_ctrl_alert.1069753423 |
| Directory | /workspace/1.chip_sw_sensor_ctrl_alert/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sensor_ctrl_status.4143165402 |
| Short name | T1273 |
| Test name | |
| Test status | |
| Simulation time | 3285635067 ps |
| CPU time | 208.3 seconds |
| Started | Jul 03 07:58:45 PM PDT 24 |
| Finished | Jul 03 08:02:14 PM PDT 24 |
| Peak memory | 609400 kb |
| Host | smart-59ef34a6-743b-40cf-a8b0-d6baa614a737 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_status_test:1:new_rules,test_rom:0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4143165 402 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sensor_ctrl_status_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sensor_ctrl_status.4143165402 |
| Directory | /workspace/1.chip_sw_sensor_ctrl_status/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sleep_pwm_pulses.1709031647 |
| Short name | T1086 |
| Test name | |
| Test status | |
| Simulation time | 9205435504 ps |
| CPU time | 1630.15 seconds |
| Started | Jul 03 07:54:36 PM PDT 24 |
| Finished | Jul 03 08:21:47 PM PDT 24 |
| Peak memory | 609932 kb |
| Host | smart-6195c61b-f3eb-46a5-94d2-8b9355e7553f |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sleep_pwm_pulses_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1709031647 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwm_pulses_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 1.chip_sw_sleep_pwm_pulses.1709031647 |
| Directory | /workspace/1.chip_sw_sleep_pwm_pulses/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sleep_sram_ret_contents_no_scramble.152700339 |
| Short name | T1065 |
| Test name | |
| Test status | |
| Simulation time | 6043379832 ps |
| CPU time | 532.62 seconds |
| Started | Jul 03 07:59:34 PM PDT 24 |
| Finished | Jul 03 08:08:27 PM PDT 24 |
| Peak memory | 610700 kb |
| Host | smart-6d98d692-a495-4ce0-8ef6-3d0b2c7032b0 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_sleep_sram_ret_contents_no_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=152700339 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SE Q=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sle ep_sram_ret_contents_no_scramble.152700339 |
| Directory | /workspace/1.chip_sw_sleep_sram_ret_contents_no_scramble/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sleep_sram_ret_contents_scramble.864553659 |
| Short name | T959 |
| Test name | |
| Test status | |
| Simulation time | 8634146760 ps |
| CPU time | 891.24 seconds |
| Started | Jul 03 08:00:34 PM PDT 24 |
| Finished | Jul 03 08:15:26 PM PDT 24 |
| Peak memory | 610696 kb |
| Host | smart-1bec770d-cabf-412e-8766-2dc245b6bf91 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_sleep_sram_ret_contents_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=864553659 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=c hip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sleep_ sram_ret_contents_scramble.864553659 |
| Directory | /workspace/1.chip_sw_sleep_sram_ret_contents_scramble/latest |
| Test location | /workspace/coverage/default/1.chip_sw_spi_device_pass_through.3219173649 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 7011413589 ps |
| CPU time | 821.19 seconds |
| Started | Jul 03 07:53:36 PM PDT 24 |
| Finished | Jul 03 08:07:17 PM PDT 24 |
| Peak memory | 624960 kb |
| Host | smart-6068a5c6-0300-4763-a654-23760845426c |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_passthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219173649 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_passthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_spi_device_pass_through.3219173649 |
| Directory | /workspace/1.chip_sw_spi_device_pass_through/latest |
| Test location | /workspace/coverage/default/1.chip_sw_spi_device_pass_through_collision.1678064791 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 3341395106 ps |
| CPU time | 495.3 seconds |
| Started | Jul 03 07:56:16 PM PDT 24 |
| Finished | Jul 03 08:04:32 PM PDT 24 |
| Peak memory | 624004 kb |
| Host | smart-24576467-2bb6-48cb-ac3d-768d2fa39621 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_passthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1678064791 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_passthrough_collision_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d efault.vdb -cm_log /dev/null -cm_name 1.chip_sw_spi_device_pass_through_collision.1678064791 |
| Directory | /workspace/1.chip_sw_spi_device_pass_through_collision/latest |
| Test location | /workspace/coverage/default/1.chip_sw_spi_device_tpm.4265509650 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 3418251520 ps |
| CPU time | 368.44 seconds |
| Started | Jul 03 07:52:47 PM PDT 24 |
| Finished | Jul 03 07:58:56 PM PDT 24 |
| Peak memory | 617984 kb |
| Host | smart-091698de-b6b8-4713-870f-10157a424bea |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_device_tpm_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4265509650 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_device_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default .vdb -cm_log /dev/null -cm_name 1.chip_sw_spi_device_tpm.4265509650 |
| Directory | /workspace/1.chip_sw_spi_device_tpm/latest |
| Test location | /workspace/coverage/default/1.chip_sw_spi_host_tx_rx.3494347835 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 3599343420 ps |
| CPU time | 326.17 seconds |
| Started | Jul 03 07:53:52 PM PDT 24 |
| Finished | Jul 03 07:59:18 PM PDT 24 |
| Peak memory | 610720 kb |
| Host | smart-cad34ac4-87ae-4a3c-ad2b-619a6f36cd85 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3494347835 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 1.chip_sw_spi_host_tx_rx.3494347835 |
| Directory | /workspace/1.chip_sw_spi_host_tx_rx/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sram_ctrl_execution_main.3682332882 |
| Short name | T293 |
| Test name | |
| Test status | |
| Simulation time | 7186814595 ps |
| CPU time | 700.61 seconds |
| Started | Jul 03 07:59:41 PM PDT 24 |
| Finished | Jul 03 08:11:23 PM PDT 24 |
| Peak memory | 610656 kb |
| Host | smart-39ecd211-4dec-4a45-b553-d139b0b5d13f |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sram_ctrl_execution_main_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3682332882 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_execution_main_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sram_ctrl_execution_main.3682332882 |
| Directory | /workspace/1.chip_sw_sram_ctrl_execution_main/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access.2018147398 |
| Short name | T274 |
| Test name | |
| Test status | |
| Simulation time | 4751476594 ps |
| CPU time | 624.48 seconds |
| Started | Jul 03 08:00:42 PM PDT 24 |
| Finished | Jul 03 08:11:07 PM PDT 24 |
| Peak memory | 610680 kb |
| Host | smart-d09c318e-e591-453f-9a8b-de105e5d0b15 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=12_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018147398 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctr l_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw _sram_ctrl_scrambled_access.2018147398 |
| Directory | /workspace/1.chip_sw_sram_ctrl_scrambled_access/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en.2213789980 |
| Short name | T1203 |
| Test name | |
| Test status | |
| Simulation time | 5284624621 ps |
| CPU time | 665.25 seconds |
| Started | Jul 03 08:00:08 PM PDT 24 |
| Finished | Jul 03 08:11:14 PM PDT 24 |
| Peak memory | 609216 kb |
| Host | smart-e2de8777-4a8f-4158-b9fd-5599d2fc10ba |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=12_000_000 +bypass_alert_ready_to_end_check=1 +en_jitter=1 +en_scb_tl_err_chk=0 +sw_build_device=sim_dv +s w_images=sram_ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2213789980 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chi p_sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 1.chip_sw_sram_ctrl_scrambled_access_jitter_en.2213789980 |
| Directory | /workspace/1.chip_sw_sram_ctrl_scrambled_access_jitter_en/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.3014931082 |
| Short name | T1272 |
| Test name | |
| Test status | |
| Simulation time | 5009397007 ps |
| CPU time | 667.93 seconds |
| Started | Jul 03 08:02:04 PM PDT 24 |
| Finished | Jul 03 08:13:13 PM PDT 24 |
| Peak memory | 609224 kb |
| Host | smart-2b14712f-3602-49f0-8a87-3b1001286f51 |
| User | root |
| Command | /workspace/default/simv +mem_sel=main +sw_test_timeout_ns=12_000_000 +bypass_alert_ready_to_end_check=1 +en_jitter=1 +en_scb_tl_err_chk=0 +cal_sys_clk _70mhz=1 +sw_build_device=sim_dv +sw_images=sram_ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3014931082 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/ default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.3014931082 |
| Directory | /workspace/1.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sram_ctrl_smoketest.2861893840 |
| Short name | T1158 |
| Test name | |
| Test status | |
| Simulation time | 2884436618 ps |
| CPU time | 209.9 seconds |
| Started | Jul 03 08:04:47 PM PDT 24 |
| Finished | Jul 03 08:08:18 PM PDT 24 |
| Peak memory | 610600 kb |
| Host | smart-5d1cc1a8-bb38-4767-b92e-6f1c41543aa7 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sram_ctrl_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2861893840 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 1.chip_sw_sram_ctrl_smoketest.2861893840 |
| Directory | /workspace/1.chip_sw_sram_ctrl_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sysrst_ctrl_ec_rst_l.3496177442 |
| Short name | T960 |
| Test name | |
| Test status | |
| Simulation time | 20207522313 ps |
| CPU time | 3545.53 seconds |
| Started | Jul 03 07:56:26 PM PDT 24 |
| Finished | Jul 03 08:55:33 PM PDT 24 |
| Peak memory | 610736 kb |
| Host | smart-78ca9c5b-9343-40eb-ad0b-9bdfe181970f |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_ec_rst_l_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3496177442 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_ec_rst_l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d efault.vdb -cm_log /dev/null -cm_name 1.chip_sw_sysrst_ctrl_ec_rst_l.3496177442 |
| Directory | /workspace/1.chip_sw_sysrst_ctrl_ec_rst_l/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sysrst_ctrl_in_irq.3884269681 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 3790951619 ps |
| CPU time | 656.92 seconds |
| Started | Jul 03 08:02:37 PM PDT 24 |
| Finished | Jul 03 08:13:38 PM PDT 24 |
| Peak memory | 612460 kb |
| Host | smart-f990c562-6f21-4f2e-bcf4-ef60daaec66b |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_in_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3884269681 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_in_irq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 1.chip_sw_sysrst_ctrl_in_irq.3884269681 |
| Directory | /workspace/1.chip_sw_sysrst_ctrl_in_irq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sysrst_ctrl_inputs.175623442 |
| Short name | T396 |
| Test name | |
| Test status | |
| Simulation time | 3735633560 ps |
| CPU time | 331.92 seconds |
| Started | Jul 03 07:55:29 PM PDT 24 |
| Finished | Jul 03 08:01:03 PM PDT 24 |
| Peak memory | 612720 kb |
| Host | smart-7531d339-9f3b-4567-98ec-ae95b380053a |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_inputs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=175623442 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_inputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul t.vdb -cm_log /dev/null -cm_name 1.chip_sw_sysrst_ctrl_inputs.175623442 |
| Directory | /workspace/1.chip_sw_sysrst_ctrl_inputs/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sysrst_ctrl_outputs.2242885406 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 3076043568 ps |
| CPU time | 336.74 seconds |
| Started | Jul 03 07:56:11 PM PDT 24 |
| Finished | Jul 03 08:01:48 PM PDT 24 |
| Peak memory | 610504 kb |
| Host | smart-cbc428b7-43ac-4e00-bc13-2ddcd7c530e9 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_outputs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2242885406 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_outputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 1.chip_sw_sysrst_ctrl_outputs.2242885406 |
| Directory | /workspace/1.chip_sw_sysrst_ctrl_outputs/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sysrst_ctrl_reset.2584792729 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 23056419520 ps |
| CPU time | 1927.19 seconds |
| Started | Jul 03 08:00:28 PM PDT 24 |
| Finished | Jul 03 08:32:36 PM PDT 24 |
| Peak memory | 613328 kb |
| Host | smart-8e83412c-08a0-4744-b38a-7c092403c8f6 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=36_000_000 +sw_build_device=sim_dv +sw_images=sysrst_ctrl_reset_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25847927 29 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sysrst_ctrl_reset.2584792729 |
| Directory | /workspace/1.chip_sw_sysrst_ctrl_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sysrst_ctrl_ulp_z3_wakeup.2333736586 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 5567727880 ps |
| CPU time | 420.97 seconds |
| Started | Jul 03 07:55:18 PM PDT 24 |
| Finished | Jul 03 08:02:20 PM PDT 24 |
| Peak memory | 609688 kb |
| Host | smart-0c920bd9-1566-4ead-a172-a0292561c5f3 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_ulp_z3_wakeup_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2333736586 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_ulp_z3_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/ coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sysrst_ctrl_ulp_z3_wakeup.2333736586 |
| Directory | /workspace/1.chip_sw_sysrst_ctrl_ulp_z3_wakeup/latest |
| Test location | /workspace/coverage/default/1.chip_sw_uart_smoketest.846730952 |
| Short name | T1224 |
| Test name | |
| Test status | |
| Simulation time | 2772524872 ps |
| CPU time | 281.3 seconds |
| Started | Jul 03 08:03:13 PM PDT 24 |
| Finished | Jul 03 08:07:55 PM PDT 24 |
| Peak memory | 612336 kb |
| Host | smart-24ea12c9-ab8c-4720-819e-bb76bd87588c |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=uart_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=846730952 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 1.chip_sw_uart_smoketest.846730952 |
| Directory | /workspace/1.chip_sw_uart_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_uart_tx_rx.1349656568 |
| Short name | T290 |
| Test name | |
| Test status | |
| Simulation time | 4100143784 ps |
| CPU time | 629.12 seconds |
| Started | Jul 03 07:55:02 PM PDT 24 |
| Finished | Jul 03 08:05:32 PM PDT 24 |
| Peak memory | 621656 kb |
| Host | smart-de3e1c33-65e7-4b10-8db9-dbc6231a730f |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1349656568 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx.1349656568 |
| Directory | /workspace/1.chip_sw_uart_tx_rx/latest |
| Test location | /workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq.1281475740 |
| Short name | T1031 |
| Test name | |
| Test status | |
| Simulation time | 9129065480 ps |
| CPU time | 1874.7 seconds |
| Started | Jul 03 07:52:40 PM PDT 24 |
| Finished | Jul 03 08:23:56 PM PDT 24 |
| Peak memory | 621376 kb |
| Host | smart-712af49a-bcfb-4104-8453-c3e9c0012a51 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1281475740 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_b audrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx _alt_clk_freq.1281475740 |
| Directory | /workspace/1.chip_sw_uart_tx_rx_alt_clk_freq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.2501376033 |
| Short name | T832 |
| Test name | |
| Test status | |
| Simulation time | 8946769935 ps |
| CPU time | 1453.53 seconds |
| Started | Jul 03 07:52:49 PM PDT 24 |
| Finished | Jul 03 08:17:04 PM PDT 24 |
| Peak memory | 621064 kb |
| Host | smart-43fdd119-af61-44d1-8af8-e1953512e538 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2501376033 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_b audrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx _alt_clk_freq_low_speed.2501376033 |
| Directory | /workspace/1.chip_sw_uart_tx_rx_alt_clk_freq_low_speed/latest |
| Test location | /workspace/coverage/default/1.chip_sw_uart_tx_rx_bootstrap.1426639682 |
| Short name | T352 |
| Test name | |
| Test status | |
| Simulation time | 78601209440 ps |
| CPU time | 13000.8 seconds |
| Started | Jul 03 07:53:11 PM PDT 24 |
| Finished | Jul 03 11:29:54 PM PDT 24 |
| Peak memory | 634192 kb |
| Host | smart-5c70533e-c636-496d-9140-cc156e231572 |
| User | root |
| Command | /workspace/default/simv +use_spi_load_bootstrap=1 +calibrate_usb_clk=1 +test_timeout_ns=160_000_000 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1426639682 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx_bootstrap.1426639682 |
| Directory | /workspace/1.chip_sw_uart_tx_rx_bootstrap/latest |
| Test location | /workspace/coverage/default/1.chip_sw_uart_tx_rx_idx1.1209460968 |
| Short name | T1030 |
| Test name | |
| Test status | |
| Simulation time | 3862075730 ps |
| CPU time | 730.23 seconds |
| Started | Jul 03 07:55:08 PM PDT 24 |
| Finished | Jul 03 08:07:20 PM PDT 24 |
| Peak memory | 621924 kb |
| Host | smart-944b39c6-c738-4034-90da-7c0ebf72d26d |
| User | root |
| Command | /workspace/default/simv +uart_idx=1 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1209460968 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx_idx1.1209460968 |
| Directory | /workspace/1.chip_sw_uart_tx_rx_idx1/latest |
| Test location | /workspace/coverage/default/1.chip_sw_uart_tx_rx_idx2.1981136247 |
| Short name | T1290 |
| Test name | |
| Test status | |
| Simulation time | 4095990838 ps |
| CPU time | 695.45 seconds |
| Started | Jul 03 07:54:50 PM PDT 24 |
| Finished | Jul 03 08:06:26 PM PDT 24 |
| Peak memory | 621956 kb |
| Host | smart-04fe8eee-6cd4-47b3-b945-09aea095f1d8 |
| User | root |
| Command | /workspace/default/simv +uart_idx=2 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1981136247 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx_idx2.1981136247 |
| Directory | /workspace/1.chip_sw_uart_tx_rx_idx2/latest |
| Test location | /workspace/coverage/default/1.chip_sw_uart_tx_rx_idx3.551611670 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 3980483576 ps |
| CPU time | 636.5 seconds |
| Started | Jul 03 07:53:46 PM PDT 24 |
| Finished | Jul 03 08:04:23 PM PDT 24 |
| Peak memory | 621996 kb |
| Host | smart-2cac5660-6432-4022-9644-b19d6def2f0b |
| User | root |
| Command | /workspace/default/simv +uart_idx=3 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=551611670 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx_idx3.551611670 |
| Directory | /workspace/1.chip_sw_uart_tx_rx_idx3/latest |
| Test location | /workspace/coverage/default/1.chip_tap_straps_dev.905431545 |
| Short name | T1044 |
| Test name | |
| Test status | |
| Simulation time | 8174753310 ps |
| CPU time | 832.78 seconds |
| Started | Jul 03 08:00:15 PM PDT 24 |
| Finished | Jul 03 08:14:09 PM PDT 24 |
| Peak memory | 623936 kb |
| Host | smart-bbd49868-3104-4839-9691-ec78e8a2bdc3 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStDev +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom: new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=905431545 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_tap_straps_dev.905431545 |
| Directory | /workspace/1.chip_tap_straps_dev/latest |
| Test location | /workspace/coverage/default/1.chip_tap_straps_prod.4252612691 |
| Short name | T1169 |
| Test name | |
| Test status | |
| Simulation time | 8703245018 ps |
| CPU time | 1065.67 seconds |
| Started | Jul 03 08:00:32 PM PDT 24 |
| Finished | Jul 03 08:18:19 PM PDT 24 |
| Peak memory | 622660 kb |
| Host | smart-f6aad1a1-3846-42cb-aaa8-274187f9d377 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom :new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4252612691 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_tap_straps_prod.4252612691 |
| Directory | /workspace/1.chip_tap_straps_prod/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_asm_init_dev.352181823 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 15408352791 ps |
| CPU time | 3562.44 seconds |
| Started | Jul 03 08:07:00 PM PDT 24 |
| Finished | Jul 03 09:06:23 PM PDT 24 |
| Peak memory | 610900 kb |
| Host | smart-c04a175e-83b8-4121-b6a7-a15cc86f89ae |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_dev:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352181823 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SE Q=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 .rom_e2e_asm_init_dev.352181823 |
| Directory | /workspace/1.rom_e2e_asm_init_dev/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_asm_init_prod.1233051076 |
| Short name | T289 |
| Test name | |
| Test status | |
| Simulation time | 15547555080 ps |
| CPU time | 3157.77 seconds |
| Started | Jul 03 08:07:40 PM PDT 24 |
| Finished | Jul 03 09:00:18 PM PDT 24 |
| Peak memory | 610816 kb |
| Host | smart-51d06604-d4ae-49a0-a240-c37188150084 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233051076 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_ SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_asm_init_prod.1233051076 |
| Directory | /workspace/1.rom_e2e_asm_init_prod/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_asm_init_prod_end.316470909 |
| Short name | T895 |
| Test name | |
| Test status | |
| Simulation time | 14970322100 ps |
| CPU time | 3899.44 seconds |
| Started | Jul 03 08:06:47 PM PDT 24 |
| Finished | Jul 03 09:11:47 PM PDT 24 |
| Peak memory | 608360 kb |
| Host | smart-749e7a65-8273-47c4-acc0-656d5de5173d |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_prod_end:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=316470909 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 1.rom_e2e_asm_init_prod_end.316470909 |
| Directory | /workspace/1.rom_e2e_asm_init_prod_end/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_asm_init_rma.2313219459 |
| Short name | T850 |
| Test name | |
| Test status | |
| Simulation time | 15417743747 ps |
| CPU time | 3229.75 seconds |
| Started | Jul 03 08:07:48 PM PDT 24 |
| Finished | Jul 03 09:01:39 PM PDT 24 |
| Peak memory | 610860 kb |
| Host | smart-c0dda7d4-cd3c-4c99-b46b-a5c8b836651d |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313219459 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S EQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_asm_init_rma.2313219459 |
| Directory | /workspace/1.rom_e2e_asm_init_rma/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_asm_init_test_unlocked0.2738206444 |
| Short name | T1190 |
| Test name | |
| Test status | |
| Simulation time | 11954066280 ps |
| CPU time | 2816.25 seconds |
| Started | Jul 03 08:06:35 PM PDT 24 |
| Finished | Jul 03 08:53:32 PM PDT 24 |
| Peak memory | 610848 kb |
| Host | smart-99144bca-6cd3-4036-8694-f1af8214fdfc |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=410_000_000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2738206444 -assert nopostproc +UVM_TESTNAME=chip_base_te st +UVM_TEST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 1.rom_e2e_asm_init_test_unlocked0.2738206444 |
| Directory | /workspace/1.rom_e2e_asm_init_test_unlocked0/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_invalid_meas.3804538916 |
| Short name | T826 |
| Test name | |
| Test status | |
| Simulation time | 15445938990 ps |
| CPU time | 3347.42 seconds |
| Started | Jul 03 08:09:44 PM PDT 24 |
| Finished | Jul 03 09:05:32 PM PDT 24 |
| Peak memory | 610796 kb |
| Host | smart-cb188e00-256a-4ea4-bf3d-8b5ed6b51a49 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_invalid _meas:1:new_rules,otp_img_keymgr_otp_invalid_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3804538916 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip _sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_keymgr_in it_rom_ext_invalid_meas.3804538916 |
| Directory | /workspace/1.rom_e2e_keymgr_init_rom_ext_invalid_meas/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_meas.1657535336 |
| Short name | T1178 |
| Test name | |
| Test status | |
| Simulation time | 15073708134 ps |
| CPU time | 3277.35 seconds |
| Started | Jul 03 08:07:58 PM PDT 24 |
| Finished | Jul 03 09:02:36 PM PDT 24 |
| Peak memory | 610796 kb |
| Host | smart-b3cc48a9-f669-4d1b-8a2c-be88d8f1115e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_meas:1: new_rules,otp_img_keymgr_otp_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1657535336 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_keymgr_init_rom_ext_meas.1657535336 |
| Directory | /workspace/1.rom_e2e_keymgr_init_rom_ext_meas/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_no_meas.2267652164 |
| Short name | T1047 |
| Test name | |
| Test status | |
| Simulation time | 14598919570 ps |
| CPU time | 4263.36 seconds |
| Started | Jul 03 08:10:52 PM PDT 24 |
| Finished | Jul 03 09:21:57 PM PDT 24 |
| Peak memory | 608496 kb |
| Host | smart-cd5ba627-d5ef-4f0b-ae5a-5a24d5bda799 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_no_meas :1:new_rules,otp_img_keymgr_otp_no_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2267652164 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_keymgr_init_rom_ext _no_meas.2267652164 |
| Directory | /workspace/1.rom_e2e_keymgr_init_rom_ext_no_meas/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_shutdown_exception_c.1543716420 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 14840787224 ps |
| CPU time | 3188.57 seconds |
| Started | Jul 03 08:08:06 PM PDT 24 |
| Finished | Jul 03 09:01:15 PM PDT 24 |
| Peak memory | 609360 kb |
| Host | smart-0aaaf1cc-a7c3-4763-ad1c-6c12290a4dfd |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_shutdown_exception_c:1:ne w_rules,otp_img_secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1543716420 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_shu tdown_exception_c_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_ shutdown_exception_c.1543716420 |
| Directory | /workspace/1.rom_e2e_shutdown_exception_c/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_smoke.374796314 |
| Short name | T1024 |
| Test name | |
| Test status | |
| Simulation time | 15342185190 ps |
| CPU time | 3558.38 seconds |
| Started | Jul 03 08:06:07 PM PDT 24 |
| Finished | Jul 03 09:05:27 PM PDT 24 |
| Peak memory | 608412 kb |
| Host | smart-1dd3eb11-fcef-4038-a78b-9ffa2fd79fe5 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_smoke:1:new_rules,otp_img _secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_to p/hw/dv/tools/sim.tcl +ntb_random_seed=374796314 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_smoke.374796314 |
| Directory | /workspace/1.rom_e2e_smoke/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_static_critical.3338214797 |
| Short name | T848 |
| Test name | |
| Test status | |
| Simulation time | 16974041272 ps |
| CPU time | 4719.63 seconds |
| Started | Jul 03 08:06:22 PM PDT 24 |
| Finished | Jul 03 09:25:02 PM PDT 24 |
| Peak memory | 608488 kb |
| Host | smart-8cd6435e-8cea-49b7-b7d5-ef2ee5a8bde3 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_static_critical:1:new_rul es,otp_img_secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338214797 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_static_critical.3338214797 |
| Directory | /workspace/1.rom_e2e_static_critical/latest |
| Test location | /workspace/coverage/default/1.rom_keymgr_functest.1323152944 |
| Short name | T282 |
| Test name | |
| Test status | |
| Simulation time | 4199412184 ps |
| CPU time | 563.02 seconds |
| Started | Jul 03 08:03:17 PM PDT 24 |
| Finished | Jul 03 08:12:41 PM PDT 24 |
| Peak memory | 608176 kb |
| Host | smart-6c7d0eba-55af-49c0-9b7f-9358a8872f79 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=10_000_000 +sw_build_device=sim_dv +sw_images=keymgr_functest:1:new_rules,test_rom:0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323152944 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 1.rom_keymgr_functest.1323152944 |
| Directory | /workspace/1.rom_keymgr_functest/latest |
| Test location | /workspace/coverage/default/1.rom_volatile_raw_unlock.108129209 |
| Short name | T626 |
| Test name | |
| Test status | |
| Simulation time | 2079496507 ps |
| CPU time | 115.53 seconds |
| Started | Jul 03 08:04:05 PM PDT 24 |
| Finished | Jul 03 08:06:02 PM PDT 24 |
| Peak memory | 614884 kb |
| Host | smart-fb085f48-93b3-4afa-8e07-ae8cc709f357 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceExternal48Mhz +rom_prod_mode=1 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_test_key_0:1:ot_flash_binary,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108129209 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage /default.vdb -cm_log /dev/null -cm_name 1.rom_volatile_raw_unlock.108129209 |
| Directory | /workspace/1.rom_volatile_raw_unlock/latest |
| Test location | /workspace/coverage/default/10.chip_sw_alert_handler_lpg_sleep_mode_alerts.2040381690 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 4160621036 ps |
| CPU time | 468.31 seconds |
| Started | Jul 03 08:16:42 PM PDT 24 |
| Finished | Jul 03 08:24:31 PM PDT 24 |
| Peak memory | 640492 kb |
| Host | smart-565ddfa0-d7ad-4271-8a92-c156e0824e6d |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040381690 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2040381690 |
| Directory | /workspace/10.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/10.chip_sw_lc_ctrl_transition.1156508059 |
| Short name | T986 |
| Test name | |
| Test status | |
| Simulation time | 13075778161 ps |
| CPU time | 940.97 seconds |
| Started | Jul 03 08:16:48 PM PDT 24 |
| Finished | Jul 03 08:32:29 PM PDT 24 |
| Peak memory | 622568 kb |
| Host | smart-5277a874-e666-41fc-aecf-03c24a010ff5 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1156508059 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 10.chip_sw_lc_ctrl_transition.1156508059 |
| Directory | /workspace/10.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/10.chip_sw_uart_rand_baudrate.453409164 |
| Short name | T930 |
| Test name | |
| Test status | |
| Simulation time | 7793022582 ps |
| CPU time | 1877.58 seconds |
| Started | Jul 03 08:16:56 PM PDT 24 |
| Finished | Jul 03 08:48:15 PM PDT 24 |
| Peak memory | 620016 kb |
| Host | smart-46ad42e7-cdfa-4958-a88e-63409e6d271e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=453409164 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.chip_sw_uart_rand_baudrate.453409164 |
| Directory | /workspace/10.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/11.chip_sw_all_escalation_resets.4025551458 |
| Short name | T1280 |
| Test name | |
| Test status | |
| Simulation time | 5265588498 ps |
| CPU time | 608.72 seconds |
| Started | Jul 03 08:16:56 PM PDT 24 |
| Finished | Jul 03 08:27:05 PM PDT 24 |
| Peak memory | 649656 kb |
| Host | smart-313891a9-a5c0-4afd-a322-29d6a6833831 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 4025551458 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.chip_sw_all_escalation_resets.4025551458 |
| Directory | /workspace/11.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/11.chip_sw_lc_ctrl_transition.1116545125 |
| Short name | T1217 |
| Test name | |
| Test status | |
| Simulation time | 6245110466 ps |
| CPU time | 609.65 seconds |
| Started | Jul 03 08:16:35 PM PDT 24 |
| Finished | Jul 03 08:26:45 PM PDT 24 |
| Peak memory | 625044 kb |
| Host | smart-79885f7d-47e4-4445-a706-b85ee6ddc461 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1116545125 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 11.chip_sw_lc_ctrl_transition.1116545125 |
| Directory | /workspace/11.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/11.chip_sw_uart_rand_baudrate.662128251 |
| Short name | T404 |
| Test name | |
| Test status | |
| Simulation time | 3979905024 ps |
| CPU time | 430.28 seconds |
| Started | Jul 03 08:15:31 PM PDT 24 |
| Finished | Jul 03 08:22:42 PM PDT 24 |
| Peak memory | 622180 kb |
| Host | smart-800dac02-7d55-4e73-8bc9-17a8252b8d1c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=662128251 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.chip_sw_uart_rand_baudrate.662128251 |
| Directory | /workspace/11.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/12.chip_sw_lc_ctrl_transition.3646248295 |
| Short name | T901 |
| Test name | |
| Test status | |
| Simulation time | 5756953928 ps |
| CPU time | 417.58 seconds |
| Started | Jul 03 08:16:16 PM PDT 24 |
| Finished | Jul 03 08:23:15 PM PDT 24 |
| Peak memory | 619468 kb |
| Host | smart-54276437-7d1a-48db-89be-1d226dccbbb5 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3646248295 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 12.chip_sw_lc_ctrl_transition.3646248295 |
| Directory | /workspace/12.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/12.chip_sw_uart_rand_baudrate.2124249929 |
| Short name | T333 |
| Test name | |
| Test status | |
| Simulation time | 8278847960 ps |
| CPU time | 1385.56 seconds |
| Started | Jul 03 08:16:15 PM PDT 24 |
| Finished | Jul 03 08:39:22 PM PDT 24 |
| Peak memory | 622068 kb |
| Host | smart-83aa3ca9-53b6-44e5-b6a2-ee65d4cc6955 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=2124249929 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.chip_sw_uart_rand_baudrate.2124249929 |
| Directory | /workspace/12.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/13.chip_sw_lc_ctrl_transition.2781770744 |
| Short name | T1265 |
| Test name | |
| Test status | |
| Simulation time | 11738297553 ps |
| CPU time | 1139.1 seconds |
| Started | Jul 03 08:16:42 PM PDT 24 |
| Finished | Jul 03 08:35:41 PM PDT 24 |
| Peak memory | 622780 kb |
| Host | smart-45c43748-1fa0-442d-90f7-7b6bf7306179 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2781770744 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 13.chip_sw_lc_ctrl_transition.2781770744 |
| Directory | /workspace/13.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/13.chip_sw_uart_rand_baudrate.526238089 |
| Short name | T1191 |
| Test name | |
| Test status | |
| Simulation time | 4303693920 ps |
| CPU time | 656.51 seconds |
| Started | Jul 03 08:15:20 PM PDT 24 |
| Finished | Jul 03 08:26:17 PM PDT 24 |
| Peak memory | 620316 kb |
| Host | smart-0e04a58c-d044-4390-aa1e-e3bf36f7283a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=526238089 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.chip_sw_uart_rand_baudrate.526238089 |
| Directory | /workspace/13.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/14.chip_sw_alert_handler_lpg_sleep_mode_alerts.1852816328 |
| Short name | T372 |
| Test name | |
| Test status | |
| Simulation time | 4351948600 ps |
| CPU time | 393.72 seconds |
| Started | Jul 03 08:15:59 PM PDT 24 |
| Finished | Jul 03 08:22:34 PM PDT 24 |
| Peak memory | 649000 kb |
| Host | smart-aac795cc-9328-4e62-bc45-750192445163 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1852816328 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1852816328 |
| Directory | /workspace/14.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/14.chip_sw_lc_ctrl_transition.2034843228 |
| Short name | T1068 |
| Test name | |
| Test status | |
| Simulation time | 8012241558 ps |
| CPU time | 520.14 seconds |
| Started | Jul 03 08:16:31 PM PDT 24 |
| Finished | Jul 03 08:25:12 PM PDT 24 |
| Peak memory | 623800 kb |
| Host | smart-1681da77-664a-43c1-a410-7ebf70ea7bf8 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2034843228 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 14.chip_sw_lc_ctrl_transition.2034843228 |
| Directory | /workspace/14.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/14.chip_sw_uart_rand_baudrate.932123269 |
| Short name | T924 |
| Test name | |
| Test status | |
| Simulation time | 8297453176 ps |
| CPU time | 1526.9 seconds |
| Started | Jul 03 08:17:31 PM PDT 24 |
| Finished | Jul 03 08:42:59 PM PDT 24 |
| Peak memory | 620060 kb |
| Host | smart-27653e85-46f5-45e7-a666-abe49550e9ea |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=932123269 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.chip_sw_uart_rand_baudrate.932123269 |
| Directory | /workspace/14.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/15.chip_sw_alert_handler_lpg_sleep_mode_alerts.3680312988 |
| Short name | T678 |
| Test name | |
| Test status | |
| Simulation time | 3862728120 ps |
| CPU time | 453.25 seconds |
| Started | Jul 03 08:16:49 PM PDT 24 |
| Finished | Jul 03 08:24:23 PM PDT 24 |
| Peak memory | 641204 kb |
| Host | smart-c15325c9-b320-411e-af52-81d7fa5529e2 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3680312988 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3680312988 |
| Directory | /workspace/15.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/15.chip_sw_all_escalation_resets.4250729273 |
| Short name | T994 |
| Test name | |
| Test status | |
| Simulation time | 5732284350 ps |
| CPU time | 607.72 seconds |
| Started | Jul 03 08:18:07 PM PDT 24 |
| Finished | Jul 03 08:28:16 PM PDT 24 |
| Peak memory | 615796 kb |
| Host | smart-6080b774-a538-4e50-aff2-ddc6481bc238 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 4250729273 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.chip_sw_all_escalation_resets.4250729273 |
| Directory | /workspace/15.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/15.chip_sw_uart_rand_baudrate.1812337070 |
| Short name | T1283 |
| Test name | |
| Test status | |
| Simulation time | 4053819976 ps |
| CPU time | 607.84 seconds |
| Started | Jul 03 08:15:50 PM PDT 24 |
| Finished | Jul 03 08:25:59 PM PDT 24 |
| Peak memory | 620340 kb |
| Host | smart-0681d619-280b-4813-8187-4ce6b04d0b94 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=1812337070 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.chip_sw_uart_rand_baudrate.1812337070 |
| Directory | /workspace/15.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/16.chip_sw_uart_rand_baudrate.237933039 |
| Short name | T980 |
| Test name | |
| Test status | |
| Simulation time | 8712127880 ps |
| CPU time | 1877.74 seconds |
| Started | Jul 03 08:16:02 PM PDT 24 |
| Finished | Jul 03 08:47:21 PM PDT 24 |
| Peak memory | 620076 kb |
| Host | smart-121ca59a-a04f-44de-9430-568a1f34b439 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=237933039 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.chip_sw_uart_rand_baudrate.237933039 |
| Directory | /workspace/16.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/17.chip_sw_uart_rand_baudrate.1115962199 |
| Short name | T1137 |
| Test name | |
| Test status | |
| Simulation time | 12765881736 ps |
| CPU time | 2424.96 seconds |
| Started | Jul 03 08:19:15 PM PDT 24 |
| Finished | Jul 03 08:59:42 PM PDT 24 |
| Peak memory | 620056 kb |
| Host | smart-fc4bc1cf-d814-4da3-830a-b9e637c1c46f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=1115962199 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.chip_sw_uart_rand_baudrate.1115962199 |
| Directory | /workspace/17.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/18.chip_sw_uart_rand_baudrate.1469945123 |
| Short name | T1291 |
| Test name | |
| Test status | |
| Simulation time | 8413840666 ps |
| CPU time | 1843.83 seconds |
| Started | Jul 03 08:17:21 PM PDT 24 |
| Finished | Jul 03 08:48:06 PM PDT 24 |
| Peak memory | 619984 kb |
| Host | smart-9b98e29e-bc79-420a-b5c3-419a593124f8 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=1469945123 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.chip_sw_uart_rand_baudrate.1469945123 |
| Directory | /workspace/18.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/19.chip_sw_uart_rand_baudrate.3453000588 |
| Short name | T1060 |
| Test name | |
| Test status | |
| Simulation time | 4332141824 ps |
| CPU time | 466.65 seconds |
| Started | Jul 03 08:18:07 PM PDT 24 |
| Finished | Jul 03 08:25:54 PM PDT 24 |
| Peak memory | 620284 kb |
| Host | smart-9faf01b5-4b63-43e8-8ab5-826f241a94c5 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=3453000588 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.chip_sw_uart_rand_baudrate.3453000588 |
| Directory | /workspace/19.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/2.chip_jtag_mem_access.268216875 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 13701045605 ps |
| CPU time | 1493.64 seconds |
| Started | Jul 03 08:02:36 PM PDT 24 |
| Finished | Jul 03 08:27:31 PM PDT 24 |
| Peak memory | 607940 kb |
| Host | smart-3c9e8119-cd8e-4042-a16c-80472482d07b |
| User | root |
| Command | /workspace/default/simv +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=268216875 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_jtag_m em_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_jtag_mem_access.268216875 |
| Directory | /workspace/2.chip_jtag_mem_access/latest |
| Test location | /workspace/coverage/default/2.chip_rv_dm_ndm_reset_req.2424548900 |
| Short name | T389 |
| Test name | |
| Test status | |
| Simulation time | 4298412980 ps |
| CPU time | 555.98 seconds |
| Started | Jul 03 08:11:36 PM PDT 24 |
| Finished | Jul 03 08:20:53 PM PDT 24 |
| Peak memory | 619068 kb |
| Host | smart-8c1da17d-a1f3-40d1-b735-275485766ec3 |
| User | root |
| Command | /workspace/default/simv +en_scb_tl_err_chk=0 +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_ndm_reset_req_rma:1:new_rules,test_rom:0 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2 424548900 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_rv_dm_ndm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_rv_dm_ndm_reset_req.2424548900 |
| Directory | /workspace/2.chip_rv_dm_ndm_reset_req/latest |
| Test location | /workspace/coverage/default/2.chip_sival_flash_info_access.2301225223 |
| Short name | T1120 |
| Test name | |
| Test status | |
| Simulation time | 3353456728 ps |
| CPU time | 336.77 seconds |
| Started | Jul 03 08:05:43 PM PDT 24 |
| Finished | Jul 03 08:11:21 PM PDT 24 |
| Peak memory | 610656 kb |
| Host | smart-0f23e174-1022-4497-bef5-6fb56a3cf454 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +sw_build_device=sim_dv +sw_images=flash_ctrl_info_access_lc:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s eed=2301225223 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sival_flash_info_access.2301225223 |
| Directory | /workspace/2.chip_sival_flash_info_access/latest |
| Test location | /workspace/coverage/default/2.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.3749496915 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 18838739546 ps |
| CPU time | 666.36 seconds |
| Started | Jul 03 08:09:34 PM PDT 24 |
| Finished | Jul 03 08:20:42 PM PDT 24 |
| Peak memory | 615696 kb |
| Host | smart-fef1a1cc-3fbf-42c1-a5e3-551cb270d9f2 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=adc_ctrl_sleep_debug_cable_wakeup_test:1:new_rules,test_rom: 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=3749496915 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.3749496915 |
| Directory | /workspace/2.chip_sw_adc_ctrl_sleep_debug_cable_wakeup/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aes_enc.1726579973 |
| Short name | T1043 |
| Test name | |
| Test status | |
| Simulation time | 2436701896 ps |
| CPU time | 261.08 seconds |
| Started | Jul 03 08:07:35 PM PDT 24 |
| Finished | Jul 03 08:11:57 PM PDT 24 |
| Peak memory | 607960 kb |
| Host | smart-890a9fe8-bb14-473c-af11-905d38d38acf |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=22_000_000 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1726579973 -asser t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_enc.1726579973 |
| Directory | /workspace/2.chip_sw_aes_enc/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aes_enc_jitter_en.3065195635 |
| Short name | T961 |
| Test name | |
| Test status | |
| Simulation time | 3291104915 ps |
| CPU time | 269.01 seconds |
| Started | Jul 03 08:09:30 PM PDT 24 |
| Finished | Jul 03 08:13:59 PM PDT 24 |
| Peak memory | 610640 kb |
| Host | smart-1ab31add-c23d-4459-9cee-7fc014dcb079 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=26_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065 195635 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work space/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_enc_jitter_en.3065195635 |
| Directory | /workspace/2.chip_sw_aes_enc_jitter_en/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aes_enc_jitter_en_reduced_freq.2931675776 |
| Short name | T1297 |
| Test name | |
| Test status | |
| Simulation time | 3505196462 ps |
| CPU time | 259.97 seconds |
| Started | Jul 03 08:10:48 PM PDT 24 |
| Finished | Jul 03 08:15:09 PM PDT 24 |
| Peak memory | 610588 kb |
| Host | smart-9971c8c6-b244-41c0-9934-3d748c436807 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=26_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules, test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2931675776 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_enc_jitter_en_reduced_freq.2931675776 |
| Directory | /workspace/2.chip_sw_aes_enc_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aes_entropy.955398488 |
| Short name | T872 |
| Test name | |
| Test status | |
| Simulation time | 3392392008 ps |
| CPU time | 404.19 seconds |
| Started | Jul 03 08:08:34 PM PDT 24 |
| Finished | Jul 03 08:15:20 PM PDT 24 |
| Peak memory | 607944 kb |
| Host | smart-98819292-bc9e-4785-8e38-403d8876fd8d |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=aes_entropy_test:1:new_rules,test_rom:0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=955398488 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_entropy.955398488 |
| Directory | /workspace/2.chip_sw_aes_entropy/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aes_idle.2005927224 |
| Short name | T419 |
| Test name | |
| Test status | |
| Simulation time | 3026890120 ps |
| CPU time | 363.62 seconds |
| Started | Jul 03 08:08:27 PM PDT 24 |
| Finished | Jul 03 08:14:31 PM PDT 24 |
| Peak memory | 610628 kb |
| Host | smart-054c676a-676c-4c74-b7d6-d2c1e71dfa2f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=25_000_000 +sw_build_device=sim_dv +sw_images=aes_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2005927224 -asser t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_idle.2005927224 |
| Directory | /workspace/2.chip_sw_aes_idle/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aes_masking_off.920428454 |
| Short name | T1079 |
| Test name | |
| Test status | |
| Simulation time | 2815161043 ps |
| CPU time | 334.02 seconds |
| Started | Jul 03 08:07:22 PM PDT 24 |
| Finished | Jul 03 08:12:57 PM PDT 24 |
| Peak memory | 609528 kb |
| Host | smart-5cd6d303-71ca-466a-ae47-cd92793c1bc1 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=aes_masking_off_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=920428454 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_aes_masking_off_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_masking_off.920428454 |
| Directory | /workspace/2.chip_sw_aes_masking_off/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aes_smoketest.804018473 |
| Short name | T1083 |
| Test name | |
| Test status | |
| Simulation time | 2239884776 ps |
| CPU time | 248.2 seconds |
| Started | Jul 03 08:12:30 PM PDT 24 |
| Finished | Jul 03 08:16:39 PM PDT 24 |
| Peak memory | 610656 kb |
| Host | smart-8a379e48-4d5d-4dda-8078-922a1e29ff09 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804018473 -assert nopostproc +UVM_TESTNAME=chip_ base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_smoketest.804018473 |
| Directory | /workspace/2.chip_sw_aes_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_alert_handler_entropy.306624793 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 3281097446 ps |
| CPU time | 258.25 seconds |
| Started | Jul 03 08:07:29 PM PDT 24 |
| Finished | Jul 03 08:11:48 PM PDT 24 |
| Peak memory | 609168 kb |
| Host | smart-1f39a0f9-3773-43d0-a6c8-2f61829ec29a |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler_entropy_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=306624793 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_entropy.306624793 |
| Directory | /workspace/2.chip_sw_alert_handler_entropy/latest |
| Test location | /workspace/coverage/default/2.chip_sw_alert_handler_escalation.2493884337 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 5281676230 ps |
| CPU time | 647.42 seconds |
| Started | Jul 03 08:07:18 PM PDT 24 |
| Finished | Jul 03 08:18:06 PM PDT 24 |
| Peak memory | 618748 kb |
| Host | smart-c539e3eb-a070-45d2-93cc-8f111f535208 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler_escalation_test:1:new_rules,test _rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb _random_seed=2493884337 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_escalation_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_escalation.2493884337 |
| Directory | /workspace/2.chip_sw_alert_handler_escalation/latest |
| Test location | /workspace/coverage/default/2.chip_sw_alert_handler_lpg_clkoff.1188084119 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 8031310488 ps |
| CPU time | 1939.64 seconds |
| Started | Jul 03 08:08:20 PM PDT 24 |
| Finished | Jul 03 08:40:40 PM PDT 24 |
| Peak memory | 609368 kb |
| Host | smart-b1dbb723-e09f-4286-97fe-50ac47424518 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_lpg_clkoff_test:1:new_rules,test_r om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=1188084119 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_lpg_clkoff_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_lpg_clkoff.1188084119 |
| Directory | /workspace/2.chip_sw_alert_handler_lpg_clkoff/latest |
| Test location | /workspace/coverage/default/2.chip_sw_alert_handler_lpg_reset_toggle.1256976682 |
| Short name | T208 |
| Test name | |
| Test status | |
| Simulation time | 7669816640 ps |
| CPU time | 1885.65 seconds |
| Started | Jul 03 08:08:50 PM PDT 24 |
| Finished | Jul 03 08:40:16 PM PDT 24 |
| Peak memory | 609588 kb |
| Host | smart-b6f3a0df-a219-4bf4-b98d-d0c5539bdb37 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_lpg_reset_toggle_test:1:new_rules, test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1256976682 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_shorten_ping_wait_cycle_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_lpg_reset_togg le.1256976682 |
| Directory | /workspace/2.chip_sw_alert_handler_lpg_reset_toggle/latest |
| Test location | /workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_alerts.2667670090 |
| Short name | T395 |
| Test name | |
| Test status | |
| Simulation time | 3660190380 ps |
| CPU time | 392.54 seconds |
| Started | Jul 03 08:07:17 PM PDT 24 |
| Finished | Jul 03 08:13:50 PM PDT 24 |
| Peak memory | 639884 kb |
| Host | smart-e2e7363a-3867-4ebe-ba54-2de6c5cedb49 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2667670090 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_s w_alert_handler_lpg_sleep_mode_alerts.2667670090 |
| Directory | /workspace/2.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_pings.1937142422 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 14198920990 ps |
| CPU time | 1516.88 seconds |
| Started | Jul 03 08:07:59 PM PDT 24 |
| Finished | Jul 03 08:33:17 PM PDT 24 |
| Peak memory | 609988 kb |
| Host | smart-c1afb4f3-9bdc-4c7f-ba31-d83df67fc918 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler _lpg_sleep_mode_pings_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1937142422 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_han dler_shorten_ping_wait_cycle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_lpg_sleep_mode_pings.1937142422 |
| Directory | /workspace/2.chip_sw_alert_handler_lpg_sleep_mode_pings/latest |
| Test location | /workspace/coverage/default/2.chip_sw_alert_handler_ping_ok.2817706981 |
| Short name | T416 |
| Test name | |
| Test status | |
| Simulation time | 7797001228 ps |
| CPU time | 1275.52 seconds |
| Started | Jul 03 08:09:01 PM PDT 24 |
| Finished | Jul 03 08:30:18 PM PDT 24 |
| Peak memory | 608780 kb |
| Host | smart-94f9d07e-e561-4ca0-9939-014257af0d1d |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=24000000 +sw_build_device=sim_dv +sw_images=alert_handler_ping_ok_test:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s eed=2817706981 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_ping_ok.2817706981 |
| Directory | /workspace/2.chip_sw_alert_handler_ping_ok/latest |
| Test location | /workspace/coverage/default/2.chip_sw_alert_handler_ping_timeout.3407048748 |
| Short name | T1192 |
| Test name | |
| Test status | |
| Simulation time | 4012794400 ps |
| CPU time | 536.11 seconds |
| Started | Jul 03 08:10:58 PM PDT 24 |
| Finished | Jul 03 08:19:55 PM PDT 24 |
| Peak memory | 609420 kb |
| Host | smart-7018f5ad-8a50-405c-9b15-2ccd3806b71c |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=24000000 +sw_build_device=sim_dv +sw_images=alert_handler_ping_timeout_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3407048748 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_ping_timeout.3407048748 |
| Directory | /workspace/2.chip_sw_alert_handler_ping_timeout/latest |
| Test location | /workspace/coverage/default/2.chip_sw_alert_handler_reverse_ping_in_deep_sleep.3948964304 |
| Short name | T1288 |
| Test name | |
| Test status | |
| Simulation time | 255706183824 ps |
| CPU time | 12040.1 seconds |
| Started | Jul 03 08:09:18 PM PDT 24 |
| Finished | Jul 03 11:30:00 PM PDT 24 |
| Peak memory | 609808 kb |
| Host | smart-83bdf376-961e-48ab-b3a6-15f32a5d6903 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=300_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_reverse_ping_in_deep_sleep_test:1:n ew_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3948964304 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_reverse_ping_in_deep_sleep.3948964304 |
| Directory | /workspace/2.chip_sw_alert_handler_reverse_ping_in_deep_sleep/latest |
| Test location | /workspace/coverage/default/2.chip_sw_alert_test.577211726 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 2747412472 ps |
| CPU time | 320.16 seconds |
| Started | Jul 03 08:06:42 PM PDT 24 |
| Finished | Jul 03 08:12:03 PM PDT 24 |
| Peak memory | 610660 kb |
| Host | smart-77c067b7-faad-4a26-a061-5464c4a2bcf0 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=alert_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=577211726 -assert nopostproc +UVM_TESTNAME=chip_bas e_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 2.chip_sw_alert_test.577211726 |
| Directory | /workspace/2.chip_sw_alert_test/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aon_timer_irq.1264411298 |
| Short name | T947 |
| Test name | |
| Test status | |
| Simulation time | 3402679032 ps |
| CPU time | 442.31 seconds |
| Started | Jul 03 08:06:22 PM PDT 24 |
| Finished | Jul 03 08:13:45 PM PDT 24 |
| Peak memory | 610616 kb |
| Host | smart-87b7b79d-c728-479e-a8ce-e2c058f6b6ff |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_irq_test:1:new_rules,test_rom:0 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1264411298 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aon_timer_irq.1264411298 |
| Directory | /workspace/2.chip_sw_aon_timer_irq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aon_timer_sleep_wdog_sleep_pause.3870450516 |
| Short name | T856 |
| Test name | |
| Test status | |
| Simulation time | 6888671848 ps |
| CPU time | 348.73 seconds |
| Started | Jul 03 08:07:01 PM PDT 24 |
| Finished | Jul 03 08:12:51 PM PDT 24 |
| Peak memory | 610692 kb |
| Host | smart-83e8f377-d213-4f35-8bd0-e6f613087e3d |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_sleep_wdog_sleep_pause_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3870450516 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aon_timer_sleep_wdog_sleep_pause.3870450516 |
| Directory | /workspace/2.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aon_timer_smoketest.3472172917 |
| Short name | T407 |
| Test name | |
| Test status | |
| Simulation time | 2770985592 ps |
| CPU time | 256.41 seconds |
| Started | Jul 03 08:12:02 PM PDT 24 |
| Finished | Jul 03 08:16:20 PM PDT 24 |
| Peak memory | 610656 kb |
| Host | smart-5e835cb9-75fe-4439-a539-8f73766525eb |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=aon_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3472172917 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 2.chip_sw_aon_timer_smoketest.3472172917 |
| Directory | /workspace/2.chip_sw_aon_timer_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aon_timer_wdog_bite_reset.3698614497 |
| Short name | T917 |
| Test name | |
| Test status | |
| Simulation time | 7198115160 ps |
| CPU time | 751.76 seconds |
| Started | Jul 03 08:07:39 PM PDT 24 |
| Finished | Jul 03 08:20:12 PM PDT 24 |
| Peak memory | 610652 kb |
| Host | smart-d8a67aba-2252-4c22-824f-38f9acb1baa1 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_wdog_bite_reset_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3698614497 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aon_timer_wdog_bite_reset.3698614497 |
| Directory | /workspace/2.chip_sw_aon_timer_wdog_bite_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aon_timer_wdog_lc_escalate.2256547359 |
| Short name | T1013 |
| Test name | |
| Test status | |
| Simulation time | 6317369608 ps |
| CPU time | 667.91 seconds |
| Started | Jul 03 08:06:16 PM PDT 24 |
| Finished | Jul 03 08:17:24 PM PDT 24 |
| Peak memory | 608708 kb |
| Host | smart-d5799121-91d7-4f48-8f0e-bb5f3142c8ee |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_wdog_lc_escalate_test:1:new_rules,test_rom:0 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed =2256547359 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aon_timer_wdog_lc_escalate.2256547359 |
| Directory | /workspace/2.chip_sw_aon_timer_wdog_lc_escalate/latest |
| Test location | /workspace/coverage/default/2.chip_sw_ast_clk_outputs.1047272938 |
| Short name | T1180 |
| Test name | |
| Test status | |
| Simulation time | 8214323928 ps |
| CPU time | 1155.28 seconds |
| Started | Jul 03 08:09:53 PM PDT 24 |
| Finished | Jul 03 08:29:09 PM PDT 24 |
| Peak memory | 616516 kb |
| Host | smart-2fa2659d-63d0-4708-ba94-26ac65f1e483 |
| User | root |
| Command | /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=ast_clk_outs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1047272938 -assert nopo stproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ast_clk_outputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_ast_clk_outputs.1047272938 |
| Directory | /workspace/2.chip_sw_ast_clk_outputs/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_lc.3610074982 |
| Short name | T1053 |
| Test name | |
| Test status | |
| Simulation time | 6493989025 ps |
| CPU time | 588.65 seconds |
| Started | Jul 03 08:08:47 PM PDT 24 |
| Finished | Jul 03 08:18:36 PM PDT 24 |
| Peak memory | 621736 kb |
| Host | smart-472b2614-f824-411d-b3bd-64f365379ebb |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +sw_images=clkmgr_external_clk_src_for_lc_test:1:new_r ules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim .tcl +ntb_random_seed=3610074982 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_clkmgr_external_clk_src_for_lc.3610074982 |
| Directory | /workspace/2.chip_sw_clkmgr_external_clk_src_for_lc/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.1883908686 |
| Short name | T868 |
| Test name | |
| Test status | |
| Simulation time | 3783768168 ps |
| CPU time | 686.17 seconds |
| Started | Jul 03 08:08:27 PM PDT 24 |
| Finished | Jul 03 08:19:54 PM PDT 24 |
| Peak memory | 613196 kb |
| Host | smart-9c0799b5-e2a7-4ea3-9f61-ca067219b845 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStDev +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1883908686 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_c lkmgr_external_clk_src_for_sw_fast_dev.1883908686 |
| Directory | /workspace/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.375920435 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 4289312040 ps |
| CPU time | 634.57 seconds |
| Started | Jul 03 08:09:59 PM PDT 24 |
| Finished | Jul 03 08:20:34 PM PDT 24 |
| Peak memory | 610896 kb |
| Host | smart-d59b492f-6174-4d98-a441-03657b9ac122 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=375920435 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_cl kmgr_external_clk_src_for_sw_fast_rma.375920435 |
| Directory | /workspace/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.2775273060 |
| Short name | T1124 |
| Test name | |
| Test status | |
| Simulation time | 3620335992 ps |
| CPU time | 609.15 seconds |
| Started | Jul 03 08:09:32 PM PDT 24 |
| Finished | Jul 03 08:19:42 PM PDT 24 |
| Peak memory | 610920 kb |
| Host | smart-db29eb63-d54a-4eb7-8bfe-13f4d0dffaa7 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStTestUnlocked0 +sw_build_device=sim_ dv +sw_images=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2775273060 -assert nopostproc +UVM_TESTNAME=chip_base_test +UV M_TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 .chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.2775273060 |
| Directory | /workspace/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.362081463 |
| Short name | T886 |
| Test name | |
| Test status | |
| Simulation time | 5158555240 ps |
| CPU time | 623.51 seconds |
| Started | Jul 03 08:10:35 PM PDT 24 |
| Finished | Jul 03 08:20:59 PM PDT 24 |
| Peak memory | 610876 kb |
| Host | smart-b713f7cb-52f3-4702-b632-946217a50c88 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStDev +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=362081463 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_cl kmgr_external_clk_src_for_sw_slow_dev.362081463 |
| Directory | /workspace/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.2695816366 |
| Short name | T1022 |
| Test name | |
| Test status | |
| Simulation time | 4707780096 ps |
| CPU time | 671.56 seconds |
| Started | Jul 03 08:09:39 PM PDT 24 |
| Finished | Jul 03 08:20:51 PM PDT 24 |
| Peak memory | 613180 kb |
| Host | smart-7ab9c3b0-7632-4726-9581-2674f5299356 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2695816366 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_c lkmgr_external_clk_src_for_sw_slow_rma.2695816366 |
| Directory | /workspace/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.3440156293 |
| Short name | T1070 |
| Test name | |
| Test status | |
| Simulation time | 4357788276 ps |
| CPU time | 587.33 seconds |
| Started | Jul 03 08:08:58 PM PDT 24 |
| Finished | Jul 03 08:18:46 PM PDT 24 |
| Peak memory | 614300 kb |
| Host | smart-54450f1e-21f6-4879-a8e3-451bf8f61db7 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStTestUnlocked0 +sw_build_device=sim_ dv +sw_images=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3440156293 -assert nopostproc +UVM_TESTNAME=chip_base_test +UV M_TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 .chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.3440156293 |
| Directory | /workspace/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_jitter.1998011089 |
| Short name | T1130 |
| Test name | |
| Test status | |
| Simulation time | 2648930891 ps |
| CPU time | 224 seconds |
| Started | Jul 03 08:10:08 PM PDT 24 |
| Finished | Jul 03 08:13:53 PM PDT 24 |
| Peak memory | 610608 kb |
| Host | smart-d0786da4-06cd-444f-aa7b-cc68b1b71fda |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_jitter_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1998011089 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 2.chip_sw_clkmgr_jitter.1998011089 |
| Directory | /workspace/2.chip_sw_clkmgr_jitter/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_jitter_frequency.4148615352 |
| Short name | T839 |
| Test name | |
| Test status | |
| Simulation time | 3893205450 ps |
| CPU time | 502.36 seconds |
| Started | Jul 03 08:10:45 PM PDT 24 |
| Finished | Jul 03 08:19:08 PM PDT 24 |
| Peak memory | 610616 kb |
| Host | smart-10367d54-2b9f-45f6-990d-c2c06cc7ba89 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_jitter_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4148615352 -assert nopostproc +UV M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c m_log /dev/null -cm_name 2.chip_sw_clkmgr_jitter_frequency.4148615352 |
| Directory | /workspace/2.chip_sw_clkmgr_jitter_frequency/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_jitter_reduced_freq.790039567 |
| Short name | T851 |
| Test name | |
| Test status | |
| Simulation time | 3126666149 ps |
| CPU time | 238.02 seconds |
| Started | Jul 03 08:12:41 PM PDT 24 |
| Finished | Jul 03 08:16:40 PM PDT 24 |
| Peak memory | 610624 kb |
| Host | smart-7e38ba96-ee29-4380-afe3-62dbe3c9766a |
| User | root |
| Command | /workspace/default/simv +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=clkmgr_jitter_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=790039567 -assert nopo stproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa ult.vdb -cm_log /dev/null -cm_name 2.chip_sw_clkmgr_jitter_reduced_freq.790039567 |
| Directory | /workspace/2.chip_sw_clkmgr_jitter_reduced_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_off_aes_trans.2133660343 |
| Short name | T284 |
| Test name | |
| Test status | |
| Simulation time | 4977872010 ps |
| CPU time | 553.12 seconds |
| Started | Jul 03 08:08:22 PM PDT 24 |
| Finished | Jul 03 08:17:36 PM PDT 24 |
| Peak memory | 610676 kb |
| Host | smart-e7ede527-43f2-4c0e-a327-29613e0d0271 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_aes_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2133660343 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 2.chip_sw_clkmgr_off_aes_trans.2133660343 |
| Directory | /workspace/2.chip_sw_clkmgr_off_aes_trans/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_off_hmac_trans.2758948551 |
| Short name | T1165 |
| Test name | |
| Test status | |
| Simulation time | 3780121360 ps |
| CPU time | 535.75 seconds |
| Started | Jul 03 08:09:59 PM PDT 24 |
| Finished | Jul 03 08:18:55 PM PDT 24 |
| Peak memory | 610652 kb |
| Host | smart-a4a0cf42-489a-4119-ae28-20a2e8338c66 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_hmac_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2758948551 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 2.chip_sw_clkmgr_off_hmac_trans.2758948551 |
| Directory | /workspace/2.chip_sw_clkmgr_off_hmac_trans/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_off_kmac_trans.315678176 |
| Short name | T948 |
| Test name | |
| Test status | |
| Simulation time | 4477725616 ps |
| CPU time | 432.22 seconds |
| Started | Jul 03 08:08:31 PM PDT 24 |
| Finished | Jul 03 08:15:44 PM PDT 24 |
| Peak memory | 610640 kb |
| Host | smart-9936234b-1e16-4217-b066-ab0544b03b91 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_kmac_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=315678176 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 2.chip_sw_clkmgr_off_kmac_trans.315678176 |
| Directory | /workspace/2.chip_sw_clkmgr_off_kmac_trans/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_off_otbn_trans.1124978045 |
| Short name | T840 |
| Test name | |
| Test status | |
| Simulation time | 5287463732 ps |
| CPU time | 579.7 seconds |
| Started | Jul 03 08:09:17 PM PDT 24 |
| Finished | Jul 03 08:18:57 PM PDT 24 |
| Peak memory | 609252 kb |
| Host | smart-5feb9a8b-61ef-4acc-8430-c85055c3883a |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_otbn_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1124978045 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 2.chip_sw_clkmgr_off_otbn_trans.1124978045 |
| Directory | /workspace/2.chip_sw_clkmgr_off_otbn_trans/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_off_peri.3065539570 |
| Short name | T1090 |
| Test name | |
| Test status | |
| Simulation time | 10014553080 ps |
| CPU time | 1212.75 seconds |
| Started | Jul 03 08:08:39 PM PDT 24 |
| Finished | Jul 03 08:28:53 PM PDT 24 |
| Peak memory | 610624 kb |
| Host | smart-d2dcc055-0c14-4279-ab60-450010672168 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=30_000_000 +sw_build_device=sim_dv +sw_images=clkmgr_off_peri_test:1:new_rules,test_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065539570 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/ coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_clkmgr_off_peri.3065539570 |
| Directory | /workspace/2.chip_sw_clkmgr_off_peri/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_reset_frequency.3069978820 |
| Short name | T1210 |
| Test name | |
| Test status | |
| Simulation time | 4015596616 ps |
| CPU time | 510.17 seconds |
| Started | Jul 03 08:10:43 PM PDT 24 |
| Finished | Jul 03 08:19:14 PM PDT 24 |
| Peak memory | 610660 kb |
| Host | smart-6710c422-c001-4118-9693-ea6111d5d1b1 |
| User | root |
| Command | /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=clkmgr_reset_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3069978820 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_clkmgr_reset_frequency.3069978820 |
| Directory | /workspace/2.chip_sw_clkmgr_reset_frequency/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_sleep_frequency.2172444569 |
| Short name | T859 |
| Test name | |
| Test status | |
| Simulation time | 4600698402 ps |
| CPU time | 657.38 seconds |
| Started | Jul 03 08:09:33 PM PDT 24 |
| Finished | Jul 03 08:20:31 PM PDT 24 |
| Peak memory | 609132 kb |
| Host | smart-f610ac0f-2f46-4b2a-8afd-48cb52f82e0a |
| User | root |
| Command | /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=clkmgr_sleep_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2172444569 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_clkmgr_sleep_frequency.2172444569 |
| Directory | /workspace/2.chip_sw_clkmgr_sleep_frequency/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_smoketest.2557026617 |
| Short name | T1126 |
| Test name | |
| Test status | |
| Simulation time | 2836544484 ps |
| CPU time | 218.48 seconds |
| Started | Jul 03 08:12:34 PM PDT 24 |
| Finished | Jul 03 08:16:13 PM PDT 24 |
| Peak memory | 610624 kb |
| Host | smart-8982e9bb-bc67-4c6f-b9ea-96243d8c7b7e |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2557026617 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 2.chip_sw_clkmgr_smoketest.2557026617 |
| Directory | /workspace/2.chip_sw_clkmgr_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_csrng_edn_concurrency.1003779318 |
| Short name | T1064 |
| Test name | |
| Test status | |
| Simulation time | 13350406700 ps |
| CPU time | 2732.07 seconds |
| Started | Jul 03 08:08:15 PM PDT 24 |
| Finished | Jul 03 08:53:48 PM PDT 24 |
| Peak memory | 609812 kb |
| Host | smart-7d138062-cdb9-4249-a4ca-687d73e44397 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +accelerate_cold_power_up_time=3 +accelerate_r egulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1003779318 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 2.chip_sw_csrng_edn_concurrency.1003779318 |
| Directory | /workspace/2.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspace/coverage/default/2.chip_sw_csrng_edn_concurrency_reduced_freq.3470875341 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 19509743067 ps |
| CPU time | 3668.67 seconds |
| Started | Jul 03 08:17:12 PM PDT 24 |
| Finished | Jul 03 09:18:22 PM PDT 24 |
| Peak memory | 609788 kb |
| Host | smart-b89b67af-8815-471e-b8fc-908002990e84 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=360_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +cal_sys_clk_70mhz=1 +en_jitter=1 +accelerate_ cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=3470875341 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_csrng_edn_concurrency_reduced_freq.3470875341 |
| Directory | /workspace/2.chip_sw_csrng_edn_concurrency_reduced_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_csrng_fuse_en_sw_app_read_test.514265147 |
| Short name | T1066 |
| Test name | |
| Test status | |
| Simulation time | 4330720944 ps |
| CPU time | 498.15 seconds |
| Started | Jul 03 08:08:19 PM PDT 24 |
| Finished | Jul 03 08:16:38 PM PDT 24 |
| Peak memory | 610648 kb |
| Host | smart-4dfc921b-4749-4f0b-82b4-bee5c7f2e0cd |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=csrng_fuse_en_sw_app_read:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51426 5147 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_entropy_src_fuse_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_csrng_fuse_en_sw_app_read_test.514265147 |
| Directory | /workspace/2.chip_sw_csrng_fuse_en_sw_app_read_test/latest |
| Test location | /workspace/coverage/default/2.chip_sw_csrng_kat_test.2809436061 |
| Short name | T858 |
| Test name | |
| Test status | |
| Simulation time | 3333885664 ps |
| CPU time | 247.67 seconds |
| Started | Jul 03 08:06:38 PM PDT 24 |
| Finished | Jul 03 08:10:47 PM PDT 24 |
| Peak memory | 610588 kb |
| Host | smart-cd5ed523-71ef-4397-884a-b7e80c8c05d0 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=csrng_kat_test:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809436061 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_csrng_kat_test.2809436061 |
| Directory | /workspace/2.chip_sw_csrng_kat_test/latest |
| Test location | /workspace/coverage/default/2.chip_sw_csrng_lc_hw_debug_en_test.2598605123 |
| Short name | T1038 |
| Test name | |
| Test status | |
| Simulation time | 7384655500 ps |
| CPU time | 663.45 seconds |
| Started | Jul 03 08:07:21 PM PDT 24 |
| Finished | Jul 03 08:18:26 PM PDT 24 |
| Peak memory | 610916 kb |
| Host | smart-56f6c437-e690-4d91-96d6-0eb1dd8cf8dd |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +rng_srate_value_min=15 +use_otp_image=OtpTypeLcStTestUnlocked0 +sw_build_device=sim_dv +sw_ima ges=csrng_lc_hw_debug_en_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2598605123 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_csrng_ lc_hw_debug_en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_csr ng_lc_hw_debug_en_test.2598605123 |
| Directory | /workspace/2.chip_sw_csrng_lc_hw_debug_en_test/latest |
| Test location | /workspace/coverage/default/2.chip_sw_csrng_smoketest.3305533142 |
| Short name | T303 |
| Test name | |
| Test status | |
| Simulation time | 2854253224 ps |
| CPU time | 291.64 seconds |
| Started | Jul 03 08:13:24 PM PDT 24 |
| Finished | Jul 03 08:18:16 PM PDT 24 |
| Peak memory | 610636 kb |
| Host | smart-340a9fd2-54bf-431d-a3ab-1a95051a47e5 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=csrng_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3305533142 -assert nopostproc +UVM_TESTNAME=ch ip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 2.chip_sw_csrng_smoketest.3305533142 |
| Directory | /workspace/2.chip_sw_csrng_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_data_integrity_escalation.1317297004 |
| Short name | T279 |
| Test name | |
| Test status | |
| Simulation time | 4687387800 ps |
| CPU time | 711.63 seconds |
| Started | Jul 03 08:05:20 PM PDT 24 |
| Finished | Jul 03 08:17:12 PM PDT 24 |
| Peak memory | 610740 kb |
| Host | smart-7a8f9b6b-a443-480c-8188-87938bd22c22 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=data_integrity_escalation_reset_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1317297004 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_data_integrity_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_data_integrity_escalation.1317297004 |
| Directory | /workspace/2.chip_sw_data_integrity_escalation/latest |
| Test location | /workspace/coverage/default/2.chip_sw_edn_auto_mode.2951056094 |
| Short name | T1089 |
| Test name | |
| Test status | |
| Simulation time | 3120425716 ps |
| CPU time | 734.35 seconds |
| Started | Jul 03 08:07:49 PM PDT 24 |
| Finished | Jul 03 08:20:04 PM PDT 24 |
| Peak memory | 610716 kb |
| Host | smart-bc096410-4350-4295-93eb-edd4b7a58786 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_ build_device=sim_dv +sw_images=edn_auto_mode:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2951056094 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_edn_ auto_mode.2951056094 |
| Directory | /workspace/2.chip_sw_edn_auto_mode/latest |
| Test location | /workspace/coverage/default/2.chip_sw_edn_boot_mode.188875241 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 3125612942 ps |
| CPU time | 630.86 seconds |
| Started | Jul 03 08:07:53 PM PDT 24 |
| Finished | Jul 03 08:18:24 PM PDT 24 |
| Peak memory | 610788 kb |
| Host | smart-a6aa24b6-ab96-40f7-99c2-2d0c4b3d153a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_ build_device=sim_dv +sw_images=edn_boot_mode:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=188875241 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_edn_b oot_mode.188875241 |
| Directory | /workspace/2.chip_sw_edn_boot_mode/latest |
| Test location | /workspace/coverage/default/2.chip_sw_edn_entropy_reqs.1314538758 |
| Short name | T1197 |
| Test name | |
| Test status | |
| Simulation time | 4971289186 ps |
| CPU time | 931.06 seconds |
| Started | Jul 03 08:09:22 PM PDT 24 |
| Finished | Jul 03 08:24:54 PM PDT 24 |
| Peak memory | 610808 kb |
| Host | smart-c9ec5697-d509-4d53-8938-5a39b9d5d75f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15000000 +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_ed n_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1314538758 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_edn_entropy_reqs.1314538758 |
| Directory | /workspace/2.chip_sw_edn_entropy_reqs/latest |
| Test location | /workspace/coverage/default/2.chip_sw_edn_entropy_reqs_jitter.2971191762 |
| Short name | T1019 |
| Test name | |
| Test status | |
| Simulation time | 7229622707 ps |
| CPU time | 1122.91 seconds |
| Started | Jul 03 08:09:30 PM PDT 24 |
| Finished | Jul 03 08:28:14 PM PDT 24 |
| Peak memory | 610768 kb |
| Host | smart-c114e1f3-8738-4dea-aca5-2cf5ecf35894 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15000000 +rng_srate_value_min=15 +rng_srate_value_max=30 +en_jitter=1 +sw_build_device=sim_dv +sw_images=e ntropy_src_edn_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2971191762 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_edn_entropy_reqs_jitter.2971191762 |
| Directory | /workspace/2.chip_sw_edn_entropy_reqs_jitter/latest |
| Test location | /workspace/coverage/default/2.chip_sw_edn_kat.451268109 |
| Short name | T974 |
| Test name | |
| Test status | |
| Simulation time | 3466635408 ps |
| CPU time | 637.05 seconds |
| Started | Jul 03 08:08:38 PM PDT 24 |
| Finished | Jul 03 08:19:16 PM PDT 24 |
| Peak memory | 614804 kb |
| Host | smart-779d4db8-a215-473a-a895-2a15e563684c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +disable_assert_edn_output_diff_from_prev=1 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=edn_kat:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=451268109 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 2.chip_sw_edn_kat.451268109 |
| Directory | /workspace/2.chip_sw_edn_kat/latest |
| Test location | /workspace/coverage/default/2.chip_sw_edn_sw_mode.1413009191 |
| Short name | T408 |
| Test name | |
| Test status | |
| Simulation time | 8948852352 ps |
| CPU time | 1915.05 seconds |
| Started | Jul 03 08:08:43 PM PDT 24 |
| Finished | Jul 03 08:40:38 PM PDT 24 |
| Peak memory | 608272 kb |
| Host | smart-1d5cd6d4-3f33-4f94-a311-ce5b2894cccc |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=edn_sw_mode:1:new_rules,test_rom:0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1413009191 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/ default.vdb -cm_log /dev/null -cm_name 2.chip_sw_edn_sw_mode.1413009191 |
| Directory | /workspace/2.chip_sw_edn_sw_mode/latest |
| Test location | /workspace/coverage/default/2.chip_sw_entropy_src_ast_rng_req.828721648 |
| Short name | T1106 |
| Test name | |
| Test status | |
| Simulation time | 2491720694 ps |
| CPU time | 249.26 seconds |
| Started | Jul 03 08:08:27 PM PDT 24 |
| Finished | Jul 03 08:12:37 PM PDT 24 |
| Peak memory | 608072 kb |
| Host | smart-f64ab59c-f4d1-47c8-8714-53442383934b |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=entropy_src_ast_rng_req_test:1:new_rules,test_rom:0 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82 8721648 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_entropy_src_ast_rng_req.828721648 |
| Directory | /workspace/2.chip_sw_entropy_src_ast_rng_req/latest |
| Test location | /workspace/coverage/default/2.chip_sw_entropy_src_csrng.2257967850 |
| Short name | T315 |
| Test name | |
| Test status | |
| Simulation time | 7031440664 ps |
| CPU time | 2229.09 seconds |
| Started | Jul 03 08:10:04 PM PDT 24 |
| Finished | Jul 03 08:47:13 PM PDT 24 |
| Peak memory | 610808 kb |
| Host | smart-abcd65cf-f0c7-4b05-be4a-cb5ff36a1894 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_ csrng_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2257967850 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_entropy_src_csrng.2257967850 |
| Directory | /workspace/2.chip_sw_entropy_src_csrng/latest |
| Test location | /workspace/coverage/default/2.chip_sw_entropy_src_kat_test.3226474059 |
| Short name | T869 |
| Test name | |
| Test status | |
| Simulation time | 2353794150 ps |
| CPU time | 186.02 seconds |
| Started | Jul 03 08:07:01 PM PDT 24 |
| Finished | Jul 03 08:10:08 PM PDT 24 |
| Peak memory | 610600 kb |
| Host | smart-70717f20-40f1-4d81-9561-415f6faef82f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=entropy_src_kat_test:1:new_rules,test_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3226474059 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/ coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_entropy_src_kat_test.3226474059 |
| Directory | /workspace/2.chip_sw_entropy_src_kat_test/latest |
| Test location | /workspace/coverage/default/2.chip_sw_entropy_src_smoketest.628653044 |
| Short name | T1145 |
| Test name | |
| Test status | |
| Simulation time | 3414508380 ps |
| CPU time | 614.19 seconds |
| Started | Jul 03 08:13:26 PM PDT 24 |
| Finished | Jul 03 08:23:41 PM PDT 24 |
| Peak memory | 610612 kb |
| Host | smart-bbd4581a-ef5d-44cc-b568-fb4c9e12e9e4 |
| User | root |
| Command | /workspace/default/simv +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_smoketest:1:new_rules,test_rom: 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=628653044 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_entropy_src_smoketest.628653044 |
| Directory | /workspace/2.chip_sw_entropy_src_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_example_concurrency.2346970740 |
| Short name | T999 |
| Test name | |
| Test status | |
| Simulation time | 2603212564 ps |
| CPU time | 222.8 seconds |
| Started | Jul 03 08:04:07 PM PDT 24 |
| Finished | Jul 03 08:07:51 PM PDT 24 |
| Peak memory | 610608 kb |
| Host | smart-c9791902-6397-4ec2-a590-09450372dec2 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2346970740 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo g /dev/null -cm_name 2.chip_sw_example_concurrency.2346970740 |
| Directory | /workspace/2.chip_sw_example_concurrency/latest |
| Test location | /workspace/coverage/default/2.chip_sw_example_flash.2822746567 |
| Short name | T1278 |
| Test name | |
| Test status | |
| Simulation time | 2120348240 ps |
| CPU time | 162.39 seconds |
| Started | Jul 03 08:04:23 PM PDT 24 |
| Finished | Jul 03 08:07:07 PM PDT 24 |
| Peak memory | 608632 kb |
| Host | smart-44065c46-dc9e-42f7-a4f9-a29f893680b9 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test_from_flash:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2822746567 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_example_flash.2822746567 |
| Directory | /workspace/2.chip_sw_example_flash/latest |
| Test location | /workspace/coverage/default/2.chip_sw_example_manufacturer.1373881110 |
| Short name | T891 |
| Test name | |
| Test status | |
| Simulation time | 1883898840 ps |
| CPU time | 179.5 seconds |
| Started | Jul 03 08:05:37 PM PDT 24 |
| Finished | Jul 03 08:08:37 PM PDT 24 |
| Peak memory | 610580 kb |
| Host | smart-3a8c2e44-f64f-4e15-80ec-a0fe66c9ee28 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1373881110 -assert nopostproc +UVM_TESTNAME=chip_ base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_example_manufacturer.1373881110 |
| Directory | /workspace/2.chip_sw_example_manufacturer/latest |
| Test location | /workspace/coverage/default/2.chip_sw_example_rom.3586409801 |
| Short name | T887 |
| Test name | |
| Test status | |
| Simulation time | 2001191856 ps |
| CPU time | 129.66 seconds |
| Started | Jul 03 08:04:26 PM PDT 24 |
| Finished | Jul 03 08:06:36 PM PDT 24 |
| Peak memory | 610296 kb |
| Host | smart-652e0850-2c71-4acc-bbbc-b83b440d7d0c |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586409801 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_example_rom.3586409801 |
| Directory | /workspace/2.chip_sw_example_rom/latest |
| Test location | /workspace/coverage/default/2.chip_sw_exit_test_unlocked_bootstrap.2531211058 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 58675676213 ps |
| CPU time | 12500 seconds |
| Started | Jul 03 08:05:09 PM PDT 24 |
| Finished | Jul 03 11:33:31 PM PDT 24 |
| Peak memory | 624796 kb |
| Host | smart-738acd86-033a-4cbf-8f70-1a6df0788cb8 |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=exit_test_unlocked_bootstrap:1:new _rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/s im.tcl +ntb_random_seed=2531211058 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_exit_test_unlocked_bootstrap_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_exit_test_unlocked_bootstrap.2531211058 |
| Directory | /workspace/2.chip_sw_exit_test_unlocked_bootstrap/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_crash_alert.968240698 |
| Short name | T1062 |
| Test name | |
| Test status | |
| Simulation time | 6046189784 ps |
| CPU time | 685.74 seconds |
| Started | Jul 03 08:11:39 PM PDT 24 |
| Finished | Jul 03 08:23:05 PM PDT 24 |
| Peak memory | 609872 kb |
| Host | smart-93612038-74ed-4a06-b893-ac9888ddb387 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=8_000_000 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1: new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tool s/sim.tcl +ntb_random_seed=968240698 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_host_gnt_err_inj_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_crash_alert.968240698 |
| Directory | /workspace/2.chip_sw_flash_crash_alert/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_ctrl_access.3082592687 |
| Short name | T1074 |
| Test name | |
| Test status | |
| Simulation time | 5550222632 ps |
| CPU time | 1125.2 seconds |
| Started | Jul 03 08:06:01 PM PDT 24 |
| Finished | Jul 03 08:24:47 PM PDT 24 |
| Peak memory | 610652 kb |
| Host | smart-44400ac6-bc21-4c4d-a855-46d9a0bc0ddb |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3082592687 -assert nopostproc +UVM_TESTNAME=ch ip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 2.chip_sw_flash_ctrl_access.3082592687 |
| Directory | /workspace/2.chip_sw_flash_ctrl_access/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en.2205981903 |
| Short name | T864 |
| Test name | |
| Test status | |
| Simulation time | 5999291963 ps |
| CPU time | 1096.94 seconds |
| Started | Jul 03 08:05:15 PM PDT 24 |
| Finished | Jul 03 08:23:33 PM PDT 24 |
| Peak memory | 610596 kb |
| Host | smart-428c90ae-5a66-4dba-9e97-faabca32324d |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2205981903 -assert nopostproc +UV M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c m_log /dev/null -cm_name 2.chip_sw_flash_ctrl_access_jitter_en.2205981903 |
| Directory | /workspace/2.chip_sw_flash_ctrl_access_jitter_en/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.1753761774 |
| Short name | T919 |
| Test name | |
| Test status | |
| Simulation time | 7376342487 ps |
| CPU time | 955.86 seconds |
| Started | Jul 03 08:11:25 PM PDT 24 |
| Finished | Jul 03 08:27:22 PM PDT 24 |
| Peak memory | 610624 kb |
| Host | smart-80741015-6247-4134-a3c1-85ea4c7c8dc6 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1753761774 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.1753761774 |
| Directory | /workspace/2.chip_sw_flash_ctrl_access_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_ctrl_clock_freqs.187421745 |
| Short name | T1025 |
| Test name | |
| Test status | |
| Simulation time | 5623330890 ps |
| CPU time | 1142.77 seconds |
| Started | Jul 03 08:08:20 PM PDT 24 |
| Finished | Jul 03 08:27:24 PM PDT 24 |
| Peak memory | 609008 kb |
| Host | smart-7caba1a9-37f9-4512-96c6-b4df42f002b3 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_clock_freqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=187421745 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 2.chip_sw_flash_ctrl_clock_freqs.187421745 |
| Directory | /workspace/2.chip_sw_flash_ctrl_clock_freqs/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_ctrl_idle_low_power.1684693865 |
| Short name | T1045 |
| Test name | |
| Test status | |
| Simulation time | 3519569124 ps |
| CPU time | 360.05 seconds |
| Started | Jul 03 08:05:01 PM PDT 24 |
| Finished | Jul 03 08:11:01 PM PDT 24 |
| Peak memory | 610808 kb |
| Host | smart-3a6814d6-a30a-4eeb-bb0d-ec4add605825 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_idle_low_power_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1684693865 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_idle_low_power.1684693865 |
| Directory | /workspace/2.chip_sw_flash_ctrl_idle_low_power/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_ctrl_mem_protection.4179247667 |
| Short name | T920 |
| Test name | |
| Test status | |
| Simulation time | 5532695324 ps |
| CPU time | 1278.55 seconds |
| Started | Jul 03 08:18:20 PM PDT 24 |
| Finished | Jul 03 08:39:40 PM PDT 24 |
| Peak memory | 610592 kb |
| Host | smart-f06b7531-0748-414d-ae78-83bd45c1c2ef |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_mem_protection_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4179247667 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_mem_protection.4179247667 |
| Directory | /workspace/2.chip_sw_flash_ctrl_mem_protection/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en.1398736130 |
| Short name | T345 |
| Test name | |
| Test status | |
| Simulation time | 3406282272 ps |
| CPU time | 537.99 seconds |
| Started | Jul 03 08:05:12 PM PDT 24 |
| Finished | Jul 03 08:14:11 PM PDT 24 |
| Peak memory | 608168 kb |
| Host | smart-1ac06ea8-ce7e-4661-b8f5-3ad6c87c46c4 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_rules,test_rom:0 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=1398736130 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_ops_jitter_en.1398736130 |
| Directory | /workspace/2.chip_sw_flash_ctrl_ops_jitter_en/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.1852383691 |
| Short name | T331 |
| Test name | |
| Test status | |
| Simulation time | 4735954230 ps |
| CPU time | 582.46 seconds |
| Started | Jul 03 08:11:35 PM PDT 24 |
| Finished | Jul 03 08:21:18 PM PDT 24 |
| Peak memory | 610604 kb |
| Host | smart-e9287947-159f-4294-bd9e-f3bb725d2140 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_ rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si m.tcl +ntb_random_seed=1852383691 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.1852383691 |
| Directory | /workspace/2.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_ctrl_write_clear.4223651843 |
| Short name | T1216 |
| Test name | |
| Test status | |
| Simulation time | 2570488832 ps |
| CPU time | 368.09 seconds |
| Started | Jul 03 08:11:52 PM PDT 24 |
| Finished | Jul 03 08:18:01 PM PDT 24 |
| Peak memory | 610536 kb |
| Host | smart-5ce37d7d-4b91-4b9b-bd98-81a484f86a07 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=8_000_000 +sw_build_device=sim_dv +sw_images=flash_ctrl_write_clear_test:1:new_rules,test_rom:0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4223651 843 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_write_clear.4223651843 |
| Directory | /workspace/2.chip_sw_flash_ctrl_write_clear/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_init.3563254598 |
| Short name | T237 |
| Test name | |
| Test status | |
| Simulation time | 20890391448 ps |
| CPU time | 2139.96 seconds |
| Started | Jul 03 08:04:44 PM PDT 24 |
| Finished | Jul 03 08:40:25 PM PDT 24 |
| Peak memory | 612644 kb |
| Host | smart-369d5f78-b4c4-4a59-9688-afb3482ab508 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=25_000_000 +sw_build_device=sim_dv +sw_images=flash_init_test:0:test_in_rom:new_rules +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3563254598 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_init.3563254598 |
| Directory | /workspace/2.chip_sw_flash_init/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_init_reduced_freq.2559110996 |
| Short name | T233 |
| Test name | |
| Test status | |
| Simulation time | 21655373831 ps |
| CPU time | 1494.22 seconds |
| Started | Jul 03 08:11:43 PM PDT 24 |
| Finished | Jul 03 08:36:38 PM PDT 24 |
| Peak memory | 615572 kb |
| Host | smart-ce474145-b20e-4ee7-8652-6e7b3053c026 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=25_000_000 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_init_test:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2559110996 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_init_reduced_freq.2559110996 |
| Directory | /workspace/2.chip_sw_flash_init_reduced_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_scrambling_smoketest.2353329472 |
| Short name | T1274 |
| Test name | |
| Test status | |
| Simulation time | 2858972056 ps |
| CPU time | 217.74 seconds |
| Started | Jul 03 08:18:17 PM PDT 24 |
| Finished | Jul 03 08:21:57 PM PDT 24 |
| Peak memory | 610568 kb |
| Host | smart-090a75f5-3859-4edc-84fd-c972df6cfd71 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=flash_scrambling_smoketest:1:new_rules,flash_scrambling_smoket est_otp_img_rma:4,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2353329472 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_scrambling_smoketest.2353329472 |
| Directory | /workspace/2.chip_sw_flash_scrambling_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_gpio.1934256800 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 4271300996 ps |
| CPU time | 518.68 seconds |
| Started | Jul 03 08:07:02 PM PDT 24 |
| Finished | Jul 03 08:15:42 PM PDT 24 |
| Peak memory | 609248 kb |
| Host | smart-b92943a0-ec9c-4fda-af30-3f27902d2272 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=gpio_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934256800 -assert nopostproc +UVM_TESTNAME=chip_bas e_test +UVM_TEST_SEQ=chip_sw_gpio_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 2.chip_sw_gpio.1934256800 |
| Directory | /workspace/2.chip_sw_gpio/latest |
| Test location | /workspace/coverage/default/2.chip_sw_gpio_smoketest.2484423965 |
| Short name | T1115 |
| Test name | |
| Test status | |
| Simulation time | 3424620904 ps |
| CPU time | 363.93 seconds |
| Started | Jul 03 08:11:33 PM PDT 24 |
| Finished | Jul 03 08:17:38 PM PDT 24 |
| Peak memory | 609584 kb |
| Host | smart-a22fa920-1b3f-4761-91ac-cb3107f5fc1b |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=gpio_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2484423965 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 2.chip_sw_gpio_smoketest.2484423965 |
| Directory | /workspace/2.chip_sw_gpio_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_hmac_enc.2864429954 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 2997149738 ps |
| CPU time | 268.66 seconds |
| Started | Jul 03 08:08:24 PM PDT 24 |
| Finished | Jul 03 08:12:53 PM PDT 24 |
| Peak memory | 610656 kb |
| Host | smart-1901f13b-ae13-49e5-a89d-764f7f4c6e45 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2864429954 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_hmac_enc.2864429954 |
| Directory | /workspace/2.chip_sw_hmac_enc/latest |
| Test location | /workspace/coverage/default/2.chip_sw_hmac_enc_idle.3275429321 |
| Short name | T951 |
| Test name | |
| Test status | |
| Simulation time | 2939492528 ps |
| CPU time | 320.1 seconds |
| Started | Jul 03 08:07:41 PM PDT 24 |
| Finished | Jul 03 08:13:02 PM PDT 24 |
| Peak memory | 607648 kb |
| Host | smart-52ddbd31-c4cf-4534-9d11-09fb9ab7e66b |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_enc_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3275429321 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 2.chip_sw_hmac_enc_idle.3275429321 |
| Directory | /workspace/2.chip_sw_hmac_enc_idle/latest |
| Test location | /workspace/coverage/default/2.chip_sw_hmac_enc_jitter_en_reduced_freq.1870320405 |
| Short name | T347 |
| Test name | |
| Test status | |
| Simulation time | 3070042022 ps |
| CPU time | 335.71 seconds |
| Started | Jul 03 08:11:52 PM PDT 24 |
| Finished | Jul 03 08:17:28 PM PDT 24 |
| Peak memory | 608692 kb |
| Host | smart-4fee39c8-c225-4305-a738-3523f972572d |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1870320405 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove rage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_hmac_enc_jitter_en_reduced_freq.1870320405 |
| Directory | /workspace/2.chip_sw_hmac_enc_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_hmac_multistream.561395969 |
| Short name | T1117 |
| Test name | |
| Test status | |
| Simulation time | 7966795412 ps |
| CPU time | 1600.66 seconds |
| Started | Jul 03 08:08:27 PM PDT 24 |
| Finished | Jul 03 08:35:09 PM PDT 24 |
| Peak memory | 610624 kb |
| Host | smart-5347b81a-f6fc-4072-a4c1-ee2307f3732c |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_multistream_functest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=561395969 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo g /dev/null -cm_name 2.chip_sw_hmac_multistream.561395969 |
| Directory | /workspace/2.chip_sw_hmac_multistream/latest |
| Test location | /workspace/coverage/default/2.chip_sw_hmac_oneshot.2510331412 |
| Short name | T1294 |
| Test name | |
| Test status | |
| Simulation time | 3276168220 ps |
| CPU time | 306.71 seconds |
| Started | Jul 03 08:07:18 PM PDT 24 |
| Finished | Jul 03 08:12:25 PM PDT 24 |
| Peak memory | 608668 kb |
| Host | smart-532fcb45-9a06-45f5-903e-98e75a4c1f98 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_functest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2510331412 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_hmac_oneshot.2510331412 |
| Directory | /workspace/2.chip_sw_hmac_oneshot/latest |
| Test location | /workspace/coverage/default/2.chip_sw_hmac_smoketest.2199868914 |
| Short name | T1161 |
| Test name | |
| Test status | |
| Simulation time | 3505792712 ps |
| CPU time | 316.73 seconds |
| Started | Jul 03 08:12:36 PM PDT 24 |
| Finished | Jul 03 08:17:54 PM PDT 24 |
| Peak memory | 610632 kb |
| Host | smart-70511380-82e9-4c34-bd19-4727275fe8fa |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2199868914 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 2.chip_sw_hmac_smoketest.2199868914 |
| Directory | /workspace/2.chip_sw_hmac_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_i2c_device_tx_rx.2623810842 |
| Short name | T321 |
| Test name | |
| Test status | |
| Simulation time | 4093180264 ps |
| CPU time | 496.19 seconds |
| Started | Jul 03 08:05:41 PM PDT 24 |
| Finished | Jul 03 08:13:58 PM PDT 24 |
| Peak memory | 609484 kb |
| Host | smart-1c8b8ed8-bcb0-4198-97e4-c0275a293f1f |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=i2c_device_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2623810842 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_device_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 2.chip_sw_i2c_device_tx_rx.2623810842 |
| Directory | /workspace/2.chip_sw_i2c_device_tx_rx/latest |
| Test location | /workspace/coverage/default/2.chip_sw_i2c_host_tx_rx.2415002212 |
| Short name | T209 |
| Test name | |
| Test status | |
| Simulation time | 5841918426 ps |
| CPU time | 920.68 seconds |
| Started | Jul 03 08:06:53 PM PDT 24 |
| Finished | Jul 03 08:22:14 PM PDT 24 |
| Peak memory | 608684 kb |
| Host | smart-14554529-502c-43ce-be21-b57cf37068a2 |
| User | root |
| Command | /workspace/default/simv +i2c_idx=0 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2415002212 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 2.chip_sw_i2c_host_tx_rx.2415002212 |
| Directory | /workspace/2.chip_sw_i2c_host_tx_rx/latest |
| Test location | /workspace/coverage/default/2.chip_sw_i2c_host_tx_rx_idx1.797466986 |
| Short name | T316 |
| Test name | |
| Test status | |
| Simulation time | 5337739720 ps |
| CPU time | 815.31 seconds |
| Started | Jul 03 08:05:28 PM PDT 24 |
| Finished | Jul 03 08:19:04 PM PDT 24 |
| Peak memory | 608652 kb |
| Host | smart-917c4a0d-a051-49ac-ba2c-a992dc934bdb |
| User | root |
| Command | /workspace/default/simv +i2c_idx=1 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=797466986 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 2.chip_sw_i2c_host_tx_rx_idx1.797466986 |
| Directory | /workspace/2.chip_sw_i2c_host_tx_rx_idx1/latest |
| Test location | /workspace/coverage/default/2.chip_sw_i2c_host_tx_rx_idx2.795307584 |
| Short name | T215 |
| Test name | |
| Test status | |
| Simulation time | 4756591344 ps |
| CPU time | 976.22 seconds |
| Started | Jul 03 08:05:49 PM PDT 24 |
| Finished | Jul 03 08:22:06 PM PDT 24 |
| Peak memory | 609136 kb |
| Host | smart-2a31ad52-010e-4e84-8196-854859214fc3 |
| User | root |
| Command | /workspace/default/simv +i2c_idx=2 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=795307584 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 2.chip_sw_i2c_host_tx_rx_idx2.795307584 |
| Directory | /workspace/2.chip_sw_i2c_host_tx_rx_idx2/latest |
| Test location | /workspace/coverage/default/2.chip_sw_inject_scramble_seed.211373479 |
| Short name | T1249 |
| Test name | |
| Test status | |
| Simulation time | 64728646732 ps |
| CPU time | 11403.3 seconds |
| Started | Jul 03 08:04:28 PM PDT 24 |
| Finished | Jul 03 11:14:34 PM PDT 24 |
| Peak memory | 624912 kb |
| Host | smart-90181cce-e53f-452e-926b-fd9d62fdcaaf |
| User | root |
| Command | /workspace/default/simv +lc_at_prod=1 +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=inject_scramble_seed :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=211373479 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_inject_scramble_seed_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_inject_scramble_seed.211373479 |
| Directory | /workspace/2.chip_sw_inject_scramble_seed/latest |
| Test location | /workspace/coverage/default/2.chip_sw_keymgr_key_derivation.3907982578 |
| Short name | T866 |
| Test name | |
| Test status | |
| Simulation time | 12801704280 ps |
| CPU time | 2286.3 seconds |
| Started | Jul 03 08:08:29 PM PDT 24 |
| Finished | Jul 03 08:46:36 PM PDT 24 |
| Peak memory | 615988 kb |
| Host | smart-750e9537-56cd-48a2-a2b4-8b5d9f0ccb55 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3907 982578 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_key_derivation.3907982578 |
| Directory | /workspace/2.chip_sw_keymgr_key_derivation/latest |
| Test location | /workspace/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en.1684456980 |
| Short name | T912 |
| Test name | |
| Test status | |
| Simulation time | 11940099644 ps |
| CPU time | 2493.67 seconds |
| Started | Jul 03 08:10:26 PM PDT 24 |
| Finished | Jul 03 08:52:03 PM PDT 24 |
| Peak memory | 615972 kb |
| Host | smart-c4b6aa7b-77c2-48cf-920a-50b8d4258e24 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1684456980 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_key_derivation_jitter_en.1684456980 |
| Directory | /workspace/2.chip_sw_keymgr_key_derivation_jitter_en/latest |
| Test location | /workspace/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.1905353101 |
| Short name | T898 |
| Test name | |
| Test status | |
| Simulation time | 8028817230 ps |
| CPU time | 1364.34 seconds |
| Started | Jul 03 08:11:20 PM PDT 24 |
| Finished | Jul 03 08:34:05 PM PDT 24 |
| Peak memory | 617040 kb |
| Host | smart-c2b3d180-4403-4a97-b0dc-6f2f80229ef5 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1905353101 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_key_derivation_jitter_en _reduced_freq.1905353101 |
| Directory | /workspace/2.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_keymgr_key_derivation_prod.3233227533 |
| Short name | T219 |
| Test name | |
| Test status | |
| Simulation time | 9918719620 ps |
| CPU time | 2553.2 seconds |
| Started | Jul 03 08:08:58 PM PDT 24 |
| Finished | Jul 03 08:51:32 PM PDT 24 |
| Peak memory | 616760 kb |
| Host | smart-8dffbc2f-cb0a-4085-a753-3100e3d66506 |
| User | root |
| Command | /workspace/default/simv +lc_at_prod=1 +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3233227533 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_key_derivation_prod.3233227533 |
| Directory | /workspace/2.chip_sw_keymgr_key_derivation_prod/latest |
| Test location | /workspace/coverage/default/2.chip_sw_keymgr_sideload_kmac.3282200398 |
| Short name | T222 |
| Test name | |
| Test status | |
| Simulation time | 7964668580 ps |
| CPU time | 1186.96 seconds |
| Started | Jul 03 08:07:39 PM PDT 24 |
| Finished | Jul 03 08:27:26 PM PDT 24 |
| Peak memory | 610740 kb |
| Host | smart-3c596dab-9349-4930-bfb1-89c9047a83d1 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_kmac_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32822 00398 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_sideload_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_sideload_kmac.3282200398 |
| Directory | /workspace/2.chip_sw_keymgr_sideload_kmac/latest |
| Test location | /workspace/coverage/default/2.chip_sw_keymgr_sideload_otbn.1673538262 |
| Short name | T227 |
| Test name | |
| Test status | |
| Simulation time | 15204620912 ps |
| CPU time | 3733.21 seconds |
| Started | Jul 03 08:07:25 PM PDT 24 |
| Finished | Jul 03 09:09:39 PM PDT 24 |
| Peak memory | 610764 kb |
| Host | smart-f5698b56-95b0-49ee-b093-9c23cc5d21d5 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_otbn_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16735 38262 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_sideload_otbn.1673538262 |
| Directory | /workspace/2.chip_sw_keymgr_sideload_otbn/latest |
| Test location | /workspace/coverage/default/2.chip_sw_kmac_app_rom.4093404872 |
| Short name | T913 |
| Test name | |
| Test status | |
| Simulation time | 2409546904 ps |
| CPU time | 170.2 seconds |
| Started | Jul 03 08:12:24 PM PDT 24 |
| Finished | Jul 03 08:15:15 PM PDT 24 |
| Peak memory | 610660 kb |
| Host | smart-3f15bc4d-08ba-46d9-91c8-3de12a08b4eb |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_app_rom_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4093404872 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 2.chip_sw_kmac_app_rom.4093404872 |
| Directory | /workspace/2.chip_sw_kmac_app_rom/latest |
| Test location | /workspace/coverage/default/2.chip_sw_kmac_entropy.1264828678 |
| Short name | T1222 |
| Test name | |
| Test status | |
| Simulation time | 2845164052 ps |
| CPU time | 220.65 seconds |
| Started | Jul 03 08:05:46 PM PDT 24 |
| Finished | Jul 03 08:09:27 PM PDT 24 |
| Peak memory | 610624 kb |
| Host | smart-045f1c3a-e52d-43ae-b394-89109c3c580a |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_entropy_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1264828678 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 2.chip_sw_kmac_entropy.1264828678 |
| Directory | /workspace/2.chip_sw_kmac_entropy/latest |
| Test location | /workspace/coverage/default/2.chip_sw_kmac_idle.2941346993 |
| Short name | T825 |
| Test name | |
| Test status | |
| Simulation time | 2190515644 ps |
| CPU time | 231.12 seconds |
| Started | Jul 03 08:09:32 PM PDT 24 |
| Finished | Jul 03 08:13:24 PM PDT 24 |
| Peak memory | 610656 kb |
| Host | smart-ca10a5f4-d329-4f9a-a90b-0b2b7f1b1402 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2941346993 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 2.chip_sw_kmac_idle.2941346993 |
| Directory | /workspace/2.chip_sw_kmac_idle/latest |
| Test location | /workspace/coverage/default/2.chip_sw_kmac_mode_cshake.4051891336 |
| Short name | T1017 |
| Test name | |
| Test status | |
| Simulation time | 2808337634 ps |
| CPU time | 334.31 seconds |
| Started | Jul 03 08:08:09 PM PDT 24 |
| Finished | Jul 03 08:13:44 PM PDT 24 |
| Peak memory | 610656 kb |
| Host | smart-f23a0336-d793-4ff4-9ef3-d87930caf40e |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_mode_cshake_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4051891336 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 2.chip_sw_kmac_mode_cshake.4051891336 |
| Directory | /workspace/2.chip_sw_kmac_mode_cshake/latest |
| Test location | /workspace/coverage/default/2.chip_sw_kmac_mode_kmac.3234471249 |
| Short name | T1007 |
| Test name | |
| Test status | |
| Simulation time | 3469668080 ps |
| CPU time | 333.95 seconds |
| Started | Jul 03 08:07:30 PM PDT 24 |
| Finished | Jul 03 08:13:04 PM PDT 24 |
| Peak memory | 610952 kb |
| Host | smart-35c5aaa9-6425-46ef-bce4-ef703c388be1 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3234471249 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 2.chip_sw_kmac_mode_kmac.3234471249 |
| Directory | /workspace/2.chip_sw_kmac_mode_kmac/latest |
| Test location | /workspace/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en.2030852622 |
| Short name | T1041 |
| Test name | |
| Test status | |
| Simulation time | 3175040208 ps |
| CPU time | 302.53 seconds |
| Started | Jul 03 08:08:16 PM PDT 24 |
| Finished | Jul 03 08:13:19 PM PDT 24 |
| Peak memory | 610552 kb |
| Host | smart-419b037d-084b-4074-936d-dac0eab00fc6 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2030852622 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 2.chip_sw_kmac_mode_kmac_jitter_en.2030852622 |
| Directory | /workspace/2.chip_sw_kmac_mode_kmac_jitter_en/latest |
| Test location | /workspace/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.274280342 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 3295815366 ps |
| CPU time | 283.99 seconds |
| Started | Jul 03 08:11:42 PM PDT 24 |
| Finished | Jul 03 08:16:27 PM PDT 24 |
| Peak memory | 610544 kb |
| Host | smart-cad02de1-53f8-4964-a3e8-d5658206e5ee |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27428034 2 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace /coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.274280342 |
| Directory | /workspace/2.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_kmac_smoketest.4212956707 |
| Short name | T1179 |
| Test name | |
| Test status | |
| Simulation time | 2871300120 ps |
| CPU time | 324.07 seconds |
| Started | Jul 03 08:11:53 PM PDT 24 |
| Finished | Jul 03 08:17:18 PM PDT 24 |
| Peak memory | 608704 kb |
| Host | smart-10f38c4f-c248-4a22-a7de-5138d92730b2 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4212956707 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 2.chip_sw_kmac_smoketest.4212956707 |
| Directory | /workspace/2.chip_sw_kmac_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_lc_ctrl_otp_hw_cfg0.900066225 |
| Short name | T849 |
| Test name | |
| Test status | |
| Simulation time | 2811333220 ps |
| CPU time | 203.88 seconds |
| Started | Jul 03 08:04:15 PM PDT 24 |
| Finished | Jul 03 08:07:39 PM PDT 24 |
| Peak memory | 610572 kb |
| Host | smart-4f4c8361-f742-451f-99e4-5afbf0fd39df |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_otp_hw_cfg0_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=900066225 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_ctrl_otp_hw_cfg0.900066225 |
| Directory | /workspace/2.chip_sw_lc_ctrl_otp_hw_cfg0/latest |
| Test location | /workspace/coverage/default/2.chip_sw_lc_ctrl_program_error.1163194389 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 5094221222 ps |
| CPU time | 633.59 seconds |
| Started | Jul 03 08:10:25 PM PDT 24 |
| Finished | Jul 03 08:21:00 PM PDT 24 |
| Peak memory | 609444 kb |
| Host | smart-64951aac-72b8-4301-980e-d85d1ca84bf3 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=lc_ctrl_program_error:1:new_rules,test_rom:0 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=1163194389 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_program_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_ctrl_program_error.1163194389 |
| Directory | /workspace/2.chip_sw_lc_ctrl_program_error/latest |
| Test location | /workspace/coverage/default/2.chip_sw_lc_ctrl_rand_to_scrap.1483588518 |
| Short name | T1097 |
| Test name | |
| Test status | |
| Simulation time | 3039975979 ps |
| CPU time | 140 seconds |
| Started | Jul 03 08:06:53 PM PDT 24 |
| Finished | Jul 03 08:09:14 PM PDT 24 |
| Peak memory | 619040 kb |
| Host | smart-80bfaea3-a9fc-461d-9d47-ca61531c1269 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=lc_ctrl_scrap_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14835885 18 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_scrap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_ctrl_rand_to_scrap.1483588518 |
| Directory | /workspace/2.chip_sw_lc_ctrl_rand_to_scrap/latest |
| Test location | /workspace/coverage/default/2.chip_sw_lc_ctrl_transition.520955328 |
| Short name | T931 |
| Test name | |
| Test status | |
| Simulation time | 6467807368 ps |
| CPU time | 714.29 seconds |
| Started | Jul 03 08:06:30 PM PDT 24 |
| Finished | Jul 03 08:18:25 PM PDT 24 |
| Peak memory | 624900 kb |
| Host | smart-69ee2345-738b-4f8a-887b-117a42640c60 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=520955328 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul t.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_ctrl_transition.520955328 |
| Directory | /workspace/2.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock.3296869876 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 2261533878 ps |
| CPU time | 116.51 seconds |
| Started | Jul 03 08:06:08 PM PDT 24 |
| Finished | Jul 03 08:08:05 PM PDT 24 |
| Peak memory | 616908 kb |
| Host | smart-9799ade1-8f30-43a6-bae2-b839192a009f |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +exp_volatile_raw_unlock_en=0 +sw_build_device=sim_dv +sw_images=lc_ctrl_volatile_raw_unlock_tes t:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=3296869876 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_ctrl_volatile_raw_unlock.3296869876 |
| Directory | /workspace/2.chip_sw_lc_ctrl_volatile_raw_unlock/latest |
| Test location | /workspace/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.3122902513 |
| Short name | T1299 |
| Test name | |
| Test status | |
| Simulation time | 2540491125 ps |
| CPU time | 119.53 seconds |
| Started | Jul 03 08:05:30 PM PDT 24 |
| Finished | Jul 03 08:07:30 PM PDT 24 |
| Peak memory | 613936 kb |
| Host | smart-48779afe-b560-4099-9fb5-b2c45ff6b55e |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceExternal48Mhz +exp_volatile_raw_unlock_en=0 +sw_build_device=s im_dv +sw_images=lc_ctrl_volatile_raw_unlock_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3122902513 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TES T_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.3122902513 |
| Directory | /workspace/2.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz/latest |
| Test location | /workspace/coverage/default/2.chip_sw_lc_walkthrough_dev.2640808229 |
| Short name | T239 |
| Test name | |
| Test status | |
| Simulation time | 47572120770 ps |
| CPU time | 5037.23 seconds |
| Started | Jul 03 08:06:12 PM PDT 24 |
| Finished | Jul 03 09:30:11 PM PDT 24 |
| Peak memory | 615836 kb |
| Host | smart-85d3c9ec-b89a-43ee-b5e5-914971fcdcdf |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStDev +sw_test_timeout_ns=200_000_000 +sw_build_de vice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2640808229 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=c hip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip _sw_lc_walkthrough_dev.2640808229 |
| Directory | /workspace/2.chip_sw_lc_walkthrough_dev/latest |
| Test location | /workspace/coverage/default/2.chip_sw_lc_walkthrough_prodend.2911218533 |
| Short name | T1109 |
| Test name | |
| Test status | |
| Simulation time | 10328007370 ps |
| CPU time | 1160.28 seconds |
| Started | Jul 03 08:05:08 PM PDT 24 |
| Finished | Jul 03 08:24:29 PM PDT 24 |
| Peak memory | 619384 kb |
| Host | smart-431f9a5c-88e2-42f6-803c-336a29ae1724 |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStProdEnd +sw_build_device=sim_dv +sw_images=lc_wa lkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2911218533 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_walkthrough_prodend.2911218533 |
| Directory | /workspace/2.chip_sw_lc_walkthrough_prodend/latest |
| Test location | /workspace/coverage/default/2.chip_sw_lc_walkthrough_rma.3380360742 |
| Short name | T231 |
| Test name | |
| Test status | |
| Simulation time | 49584841700 ps |
| CPU time | 5459.67 seconds |
| Started | Jul 03 08:05:36 PM PDT 24 |
| Finished | Jul 03 09:36:37 PM PDT 24 |
| Peak memory | 618304 kb |
| Host | smart-22afe072-5689-47e9-a406-d1dc2d91094b |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStRma +flash_program_latency=5 +sw_test_timeout_ns=200_000_000 +sw_build_de vice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3380360742 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=c hip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip _sw_lc_walkthrough_rma.3380360742 |
| Directory | /workspace/2.chip_sw_lc_walkthrough_rma/latest |
| Test location | /workspace/coverage/default/2.chip_sw_lc_walkthrough_testunlocks.2325137930 |
| Short name | T945 |
| Test name | |
| Test status | |
| Simulation time | 25935398391 ps |
| CPU time | 2362.1 seconds |
| Started | Jul 03 08:05:35 PM PDT 24 |
| Finished | Jul 03 08:44:58 PM PDT 24 |
| Peak memory | 619156 kb |
| Host | smart-ed2bea40-547a-49e0-8ad7-595bc4a43646 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStTestUnlock7 +sw_build_device=sim_dv +sw_images=lc_walkthrough_testunlocks _test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2325137930 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_testunlocks_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_walkthrough_testun locks.2325137930 |
| Directory | /workspace/2.chip_sw_lc_walkthrough_testunlocks/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq.3791179798 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 17717577796 ps |
| CPU time | 3506.66 seconds |
| Started | Jul 03 08:08:32 PM PDT 24 |
| Finished | Jul 03 09:07:00 PM PDT 24 |
| Peak memory | 609468 kb |
| Host | smart-63564ef0-c945-4858-bd8a-5bac374000ae |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=28_000_000 +rng_srate_value=30 +sw_build_device=sim_dv +sw_images=otbn_ecdsa_op_irq_test:1:new_rules,test_ rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ random_seed=3791179798 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otbn_ecdsa_op_irq.3791179798 |
| Directory | /workspace/2.chip_sw_otbn_ecdsa_op_irq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en.394316889 |
| Short name | T1219 |
| Test name | |
| Test status | |
| Simulation time | 18896310598 ps |
| CPU time | 3280.72 seconds |
| Started | Jul 03 08:07:13 PM PDT 24 |
| Finished | Jul 03 09:01:54 PM PDT 24 |
| Peak memory | 610748 kb |
| Host | smart-8b670088-093f-40da-ae64-627bd0b55181 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=33_000_000 +rng_srate_value=30 +en_jitter=1 +sw_build_device=sim_dv +sw_images=otbn_ecdsa_op_irq_test:1:ne w_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=394316889 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otbn_ecdsa_op_irq_jitter_en.394316889 |
| Directory | /workspace/2.chip_sw_otbn_ecdsa_op_irq_jitter_en/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.1820672663 |
| Short name | T940 |
| Test name | |
| Test status | |
| Simulation time | 25362119765 ps |
| CPU time | 4793.1 seconds |
| Started | Jul 03 08:11:50 PM PDT 24 |
| Finished | Jul 03 09:31:44 PM PDT 24 |
| Peak memory | 610868 kb |
| Host | smart-640944d4-9832-406d-9ac4-17f8ad56d716 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=33_000_000 +rng_srate_value=30 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=otbn_e cdsa_op_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1820672663 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otbn_ecdsa_op_irq_jitter_en_redu ced_freq.1820672663 |
| Directory | /workspace/2.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otbn_mem_scramble.1607429581 |
| Short name | T276 |
| Test name | |
| Test status | |
| Simulation time | 3395642600 ps |
| CPU time | 621.79 seconds |
| Started | Jul 03 08:06:57 PM PDT 24 |
| Finished | Jul 03 08:17:20 PM PDT 24 |
| Peak memory | 610552 kb |
| Host | smart-8a2a62b4-0ca6-41e9-9e00-711c029b9d6c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=otbn _mem_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1607429581 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otbn_mem_scramble.1607429581 |
| Directory | /workspace/2.chip_sw_otbn_mem_scramble/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otbn_randomness.327738011 |
| Short name | T1166 |
| Test name | |
| Test status | |
| Simulation time | 5844886492 ps |
| CPU time | 1104.73 seconds |
| Started | Jul 03 08:06:59 PM PDT 24 |
| Finished | Jul 03 08:25:24 PM PDT 24 |
| Peak memory | 609452 kb |
| Host | smart-f6ce8d04-9c2c-4761-a163-f983aa61b187 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=30 +sw_build_device=sim_dv +sw_images=otbn_randomness_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=327738011 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otbn_randomness.327738011 |
| Directory | /workspace/2.chip_sw_otbn_randomness/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otbn_smoketest.4023942237 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 7530408850 ps |
| CPU time | 1295.71 seconds |
| Started | Jul 03 08:12:55 PM PDT 24 |
| Finished | Jul 03 08:34:32 PM PDT 24 |
| Peak memory | 610780 kb |
| Host | smart-b14ab29c-1d45-471c-b517-9a431c389cc7 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otbn_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4023942237 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 2.chip_sw_otbn_smoketest.4023942237 |
| Directory | /workspace/2.chip_sw_otbn_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otp_ctrl_ecc_error_vendor_test.1883052527 |
| Short name | T963 |
| Test name | |
| Test status | |
| Simulation time | 2637371404 ps |
| CPU time | 285.59 seconds |
| Started | Jul 03 08:05:17 PM PDT 24 |
| Finished | Jul 03 08:10:03 PM PDT 24 |
| Peak memory | 610652 kb |
| Host | smart-97995040-6817-480e-a2cb-ca1f8360a77b |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_vendor_test_ecc_error_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1883052527 -assert nopostp roc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_vendor_test_ecc_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otp_ctrl_ecc_error_vendor_test.1883052527 |
| Directory | /workspace/2.chip_sw_otp_ctrl_ecc_error_vendor_test/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_dev.4154184513 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 8634562666 ps |
| CPU time | 1455.66 seconds |
| Started | Jul 03 08:05:28 PM PDT 24 |
| Finished | Jul 03 08:29:45 PM PDT 24 |
| Peak memory | 610672 kb |
| Host | smart-9ce0ec5b-3a1a-48c3-911b-0b39c77b3a5c |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStDev +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,tes t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=4154184513 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otp_ctrl_lc_signals_dev.4154184513 |
| Directory | /workspace/2.chip_sw_otp_ctrl_lc_signals_dev/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_prod.634038279 |
| Short name | T842 |
| Test name | |
| Test status | |
| Simulation time | 9636126060 ps |
| CPU time | 1445.55 seconds |
| Started | Jul 03 08:07:35 PM PDT 24 |
| Finished | Jul 03 08:31:42 PM PDT 24 |
| Peak memory | 610676 kb |
| Host | smart-04752c8b-9ed7-4165-8552-65bf1200217c |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=634038279 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otp_ctrl_lc_signals_prod.634038279 |
| Directory | /workspace/2.chip_sw_otp_ctrl_lc_signals_prod/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_rma.2467391190 |
| Short name | T1182 |
| Test name | |
| Test status | |
| Simulation time | 8465608052 ps |
| CPU time | 1295.82 seconds |
| Started | Jul 03 08:05:37 PM PDT 24 |
| Finished | Jul 03 08:27:13 PM PDT 24 |
| Peak memory | 610668 kb |
| Host | smart-a160a591-511f-40ae-bfc5-f537a226d308 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRma +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,tes t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=2467391190 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otp_ctrl_lc_signals_rma.2467391190 |
| Directory | /workspace/2.chip_sw_otp_ctrl_lc_signals_rma/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_test_unlocked0.3619730107 |
| Short name | T914 |
| Test name | |
| Test status | |
| Simulation time | 4535132972 ps |
| CPU time | 820.79 seconds |
| Started | Jul 03 08:06:34 PM PDT 24 |
| Finished | Jul 03 08:20:16 PM PDT 24 |
| Peak memory | 610640 kb |
| Host | smart-5314933f-663a-46d6-b74e-995ffe27d209 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new _rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/s im.tcl +ntb_random_seed=3619730107 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otp_ctrl_lc_signals_test_unlocked0.3619730107 |
| Directory | /workspace/2.chip_sw_otp_ctrl_lc_signals_test_unlocked0/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otp_ctrl_smoketest.417022794 |
| Short name | T417 |
| Test name | |
| Test status | |
| Simulation time | 2855609352 ps |
| CPU time | 252.2 seconds |
| Started | Jul 03 08:12:23 PM PDT 24 |
| Finished | Jul 03 08:16:36 PM PDT 24 |
| Peak memory | 610648 kb |
| Host | smart-c4ce0f38-ba7f-448c-83e1-d5615d60634f |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=417022794 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 2.chip_sw_otp_ctrl_smoketest.417022794 |
| Directory | /workspace/2.chip_sw_otp_ctrl_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pattgen_ios.1034279197 |
| Short name | T213 |
| Test name | |
| Test status | |
| Simulation time | 3307274092 ps |
| CPU time | 290.57 seconds |
| Started | Jul 03 08:05:19 PM PDT 24 |
| Finished | Jul 03 08:10:12 PM PDT 24 |
| Peak memory | 613460 kb |
| Host | smart-2a774189-2c73-4226-9e36-ae565a839345 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=5_000_000 +sw_build_device=sim_dv +sw_images=pattgen_ios_test:1:new_rules,test_rom:0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034279197 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_patt_ios_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pattgen_ios.1034279197 |
| Directory | /workspace/2.chip_sw_pattgen_ios/latest |
| Test location | /workspace/coverage/default/2.chip_sw_plic_sw_irq.2500554986 |
| Short name | T251 |
| Test name | |
| Test status | |
| Simulation time | 2520874000 ps |
| CPU time | 187.36 seconds |
| Started | Jul 03 08:08:11 PM PDT 24 |
| Finished | Jul 03 08:11:19 PM PDT 24 |
| Peak memory | 610588 kb |
| Host | smart-36031520-7391-4c34-ab81-54a84469abfb |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_sw_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2500554986 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 2.chip_sw_plic_sw_irq.2500554986 |
| Directory | /workspace/2.chip_sw_plic_sw_irq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_power_idle_load.713168392 |
| Short name | T631 |
| Test name | |
| Test status | |
| Simulation time | 4789346600 ps |
| CPU time | 699.95 seconds |
| Started | Jul 03 08:11:30 PM PDT 24 |
| Finished | Jul 03 08:23:11 PM PDT 24 |
| Peak memory | 609604 kb |
| Host | smart-7dcbf26f-5a7c-4e6c-bb98-3812247b1d9f |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=chip_power_idle_load:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=713168392 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_power_idle_load_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_power_idle_load.713168392 |
| Directory | /workspace/2.chip_sw_power_idle_load/latest |
| Test location | /workspace/coverage/default/2.chip_sw_power_sleep_load.4097655903 |
| Short name | T413 |
| Test name | |
| Test status | |
| Simulation time | 10172914590 ps |
| CPU time | 669.21 seconds |
| Started | Jul 03 08:11:07 PM PDT 24 |
| Finished | Jul 03 08:22:17 PM PDT 24 |
| Peak memory | 610260 kb |
| Host | smart-e17925b1-8d1a-459c-bd26-8273e33cb775 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=chip_power_sleep_load:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4097655903 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_sleep_load_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 2.chip_sw_power_sleep_load.4097655903 |
| Directory | /workspace/2.chip_sw_power_sleep_load/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_all_reset_reqs.2738828204 |
| Short name | T916 |
| Test name | |
| Test status | |
| Simulation time | 12011743436 ps |
| CPU time | 1469.59 seconds |
| Started | Jul 03 08:06:23 PM PDT 24 |
| Finished | Jul 03 08:30:53 PM PDT 24 |
| Peak memory | 610820 kb |
| Host | smart-5ebb3b31-7c06-46e3-acbf-9941c6d7c7bc |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2738 828204 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_all_reset_reqs.2738828204 |
| Directory | /workspace/2.chip_sw_pwrmgr_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_b2b_sleep_reset_req.2182613920 |
| Short name | T1269 |
| Test name | |
| Test status | |
| Simulation time | 25110437461 ps |
| CPU time | 1987.51 seconds |
| Started | Jul 03 08:07:53 PM PDT 24 |
| Finished | Jul 03 08:41:01 PM PDT 24 |
| Peak memory | 610696 kb |
| Host | smart-f3beed01-d3ae-4d73-b841-db6b858ba5ff |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=35_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_b2b_sleep_reset_test:1:new_rules,test_rom:0 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218 2613920 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_repeat_reset_wkup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_b2b_sleep_reset_req.2182613920 |
| Directory | /workspace/2.chip_sw_pwrmgr_b2b_sleep_reset_req/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.2564849195 |
| Short name | T982 |
| Test name | |
| Test status | |
| Simulation time | 17379614687 ps |
| CPU time | 1648.3 seconds |
| Started | Jul 03 08:06:01 PM PDT 24 |
| Finished | Jul 03 08:33:29 PM PDT 24 |
| Peak memory | 610280 kb |
| Host | smart-c59364b1-8a07-44fe-ba4d-e34d3702281f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2564849195 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.2564849195 |
| Directory | /workspace/2.chip_sw_pwrmgr_deep_sleep_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_wake_ups.3123560050 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 25358312042 ps |
| CPU time | 1886.43 seconds |
| Started | Jul 03 08:11:09 PM PDT 24 |
| Finished | Jul 03 08:42:36 PM PDT 24 |
| Peak memory | 610084 kb |
| Host | smart-b3330831-cad0-4b18-b4df-67dbd5b8308f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_all_wake_ups:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3123560050 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_deep_sleep_all_wake_ups.3123560050 |
| Directory | /workspace/2.chip_sw_pwrmgr_deep_sleep_all_wake_ups/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_por_reset.763423407 |
| Short name | T1105 |
| Test name | |
| Test status | |
| Simulation time | 8734149000 ps |
| CPU time | 951.53 seconds |
| Started | Jul 03 08:05:30 PM PDT 24 |
| Finished | Jul 03 08:21:22 PM PDT 24 |
| Peak memory | 610676 kb |
| Host | smart-b8a2b276-2b3e-42b6-b510-b769e10c9c0d |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_por_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=763423407 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_por_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/ default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_deep_sleep_por_reset.763423407 |
| Directory | /workspace/2.chip_sw_pwrmgr_deep_sleep_por_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.763966343 |
| Short name | T852 |
| Test name | |
| Test status | |
| Simulation time | 5713720510 ps |
| CPU time | 426.37 seconds |
| Started | Jul 03 08:06:49 PM PDT 24 |
| Finished | Jul 03 08:13:56 PM PDT 24 |
| Peak memory | 616148 kb |
| Host | smart-201b2068-0ec3-4fd9-ad7f-475aca26c97d |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_power_glitch_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=763966343 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.763966343 |
| Directory | /workspace/2.chip_sw_pwrmgr_deep_sleep_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_full_aon_reset.1690493757 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 9023320280 ps |
| CPU time | 430.34 seconds |
| Started | Jul 03 08:06:15 PM PDT 24 |
| Finished | Jul 03 08:13:26 PM PDT 24 |
| Peak memory | 610688 kb |
| Host | smart-9f880d97-7bad-4434-ab51-1fdbddf9b5b7 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1690493757 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_full_aon_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 2.chip_sw_pwrmgr_full_aon_reset.1690493757 |
| Directory | /workspace/2.chip_sw_pwrmgr_full_aon_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_main_power_glitch_reset.3549192915 |
| Short name | T1050 |
| Test name | |
| Test status | |
| Simulation time | 4108319574 ps |
| CPU time | 432.66 seconds |
| Started | Jul 03 08:08:27 PM PDT 24 |
| Finished | Jul 03 08:15:40 PM PDT 24 |
| Peak memory | 616424 kb |
| Host | smart-4e9f07b2-2af3-4ba7-a7c0-0b1066000d40 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_main_power_glitch_test:1:new_rules,test_rom:0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=3549192915 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_main_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_main_power_glitch_reset.3549192915 |
| Directory | /workspace/2.chip_sw_pwrmgr_main_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.1058865680 |
| Short name | T956 |
| Test name | |
| Test status | |
| Simulation time | 11919839141 ps |
| CPU time | 1319.41 seconds |
| Started | Jul 03 08:06:07 PM PDT 24 |
| Finished | Jul 03 08:28:07 PM PDT 24 |
| Peak memory | 610824 kb |
| Host | smart-98630ea6-789d-48a4-9e1c-537803675910 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1058865680 -assert nop ostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.1058865680 |
| Directory | /workspace/2.chip_sw_pwrmgr_normal_sleep_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_por_reset.463979766 |
| Short name | T360 |
| Test name | |
| Test status | |
| Simulation time | 7360500644 ps |
| CPU time | 544.8 seconds |
| Started | Jul 03 08:05:27 PM PDT 24 |
| Finished | Jul 03 08:14:33 PM PDT 24 |
| Peak memory | 610636 kb |
| Host | smart-0007bd92-3914-4507-9568-76dcbccd3527 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_por_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=463979766 -assert nopostpro c +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_por_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_normal_sleep_por_reset.463979766 |
| Directory | /workspace/2.chip_sw_pwrmgr_normal_sleep_por_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_reset_reqs.2537152916 |
| Short name | T1051 |
| Test name | |
| Test status | |
| Simulation time | 26686078013 ps |
| CPU time | 2956.3 seconds |
| Started | Jul 03 08:06:28 PM PDT 24 |
| Finished | Jul 03 08:55:45 PM PDT 24 |
| Peak memory | 610908 kb |
| Host | smart-a22fb795-e35f-4ae9-9aaa-5fbc466238d2 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_all_reset_reqs_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2537152916 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_random_sleep_all_reset_reqs.2537152916 |
| Directory | /workspace/2.chip_sw_pwrmgr_random_sleep_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_wake_ups.3672555632 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 25465364100 ps |
| CPU time | 2067.58 seconds |
| Started | Jul 03 08:11:48 PM PDT 24 |
| Finished | Jul 03 08:46:17 PM PDT 24 |
| Peak memory | 610044 kb |
| Host | smart-b68ee2ba-7ed5-42ef-8c6f-326834ff7b3d |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_all_wake_ups:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=3672555632 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_random_sleep_all_wake_ups.3672555632 |
| Directory | /workspace/2.chip_sw_pwrmgr_random_sleep_all_wake_ups/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_power_glitch_reset.1366762547 |
| Short name | T875 |
| Test name | |
| Test status | |
| Simulation time | 31892491355 ps |
| CPU time | 3004.86 seconds |
| Started | Jul 03 08:08:28 PM PDT 24 |
| Finished | Jul 03 08:58:34 PM PDT 24 |
| Peak memory | 611216 kb |
| Host | smart-0054c6bb-68d2-42d6-ad40-fcbc87da9495 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_test_timeout_ns=24_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_power _glitch_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1366762547 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_random_power_glit ch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_random_s leep_power_glitch_reset.1366762547 |
| Directory | /workspace/2.chip_sw_pwrmgr_random_sleep_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.3059904244 |
| Short name | T353 |
| Test name | |
| Test status | |
| Simulation time | 4806733296 ps |
| CPU time | 338.16 seconds |
| Started | Jul 03 08:10:22 PM PDT 24 |
| Finished | Jul 03 08:16:00 PM PDT 24 |
| Peak memory | 610088 kb |
| Host | smart-63b2e476-c39d-4e49-a378-9400ac453190 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sensor_ctrl_deep_sleep_wake_up:1:new_rul es,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=3059904244 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_sensor_ctrl_deep_s leep_wake_up.3059904244 |
| Directory | /workspace/2.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_disabled.678172504 |
| Short name | T637 |
| Test name | |
| Test status | |
| Simulation time | 3419154060 ps |
| CPU time | 398.18 seconds |
| Started | Jul 03 08:06:38 PM PDT 24 |
| Finished | Jul 03 08:13:17 PM PDT 24 |
| Peak memory | 610648 kb |
| Host | smart-4a375784-e4d8-4045-95c7-2d61f5fbdc63 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_disabled_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=678172504 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 2.chip_sw_pwrmgr_sleep_disabled.678172504 |
| Directory | /workspace/2.chip_sw_pwrmgr_sleep_disabled/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_power_glitch_reset.3504468767 |
| Short name | T1139 |
| Test name | |
| Test status | |
| Simulation time | 5816519352 ps |
| CPU time | 580.09 seconds |
| Started | Jul 03 08:06:29 PM PDT 24 |
| Finished | Jul 03 08:16:10 PM PDT 24 |
| Peak memory | 615648 kb |
| Host | smart-4cdb41b5-fcb8-4de3-b9dc-97d3dfc9c1af |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_power_glitch_test:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s eed=3504468767 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_main_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_sleep_power_glitch_reset.3504468767 |
| Directory | /workspace/2.chip_sw_pwrmgr_sleep_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.1864408454 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 5379080750 ps |
| CPU time | 450.37 seconds |
| Started | Jul 03 08:12:45 PM PDT 24 |
| Finished | Jul 03 08:20:16 PM PDT 24 |
| Peak memory | 608100 kb |
| Host | smart-63ffb175-96bd-4818-b077-0bf1c1ad33dc |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=8_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_wakeup_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18644084 54 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.1864408454 |
| Directory | /workspace/2.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_wake_5_bug.1863672624 |
| Short name | T1263 |
| Test name | |
| Test status | |
| Simulation time | 7306923356 ps |
| CPU time | 686.27 seconds |
| Started | Jul 03 08:10:28 PM PDT 24 |
| Finished | Jul 03 08:21:55 PM PDT 24 |
| Peak memory | 609860 kb |
| Host | smart-82f392ce-8796-4c29-a202-c687b7ec27c7 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_wake_5_bug_test:1:new_rules,test_r om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=1863672624 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_sleep_wake_5_bug.1863672624 |
| Directory | /workspace/2.chip_sw_pwrmgr_sleep_wake_5_bug/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_smoketest.1921502766 |
| Short name | T1027 |
| Test name | |
| Test status | |
| Simulation time | 7119245384 ps |
| CPU time | 575.75 seconds |
| Started | Jul 03 08:12:58 PM PDT 24 |
| Finished | Jul 03 08:22:35 PM PDT 24 |
| Peak memory | 610812 kb |
| Host | smart-a6c54055-d3fb-422d-9978-7870983d2bae |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=10000000 +sw_build_device=sim_dv +sw_images=pwrmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921502766 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_smoketest.1921502766 |
| Directory | /workspace/2.chip_sw_pwrmgr_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_sysrst_ctrl_reset.3729080824 |
| Short name | T1135 |
| Test name | |
| Test status | |
| Simulation time | 9110846160 ps |
| CPU time | 1559.12 seconds |
| Started | Jul 03 08:06:21 PM PDT 24 |
| Finished | Jul 03 08:32:21 PM PDT 24 |
| Peak memory | 609200 kb |
| Host | smart-57a2fc8f-cb0c-4c80-9988-20539b4746d1 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_sysrst_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3729080824 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_sysrst_ctrl_reset.3729080824 |
| Directory | /workspace/2.chip_sw_pwrmgr_sysrst_ctrl_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_usb_clk_disabled_when_active.427046104 |
| Short name | T970 |
| Test name | |
| Test status | |
| Simulation time | 4159203836 ps |
| CPU time | 460.9 seconds |
| Started | Jul 03 08:05:51 PM PDT 24 |
| Finished | Jul 03 08:13:33 PM PDT 24 |
| Peak memory | 610988 kb |
| Host | smart-010b9d14-b518-4375-8960-73b262fbc7bb |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_usb_clk_disabled_when_active_test:1:new_rules,test_rom:0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427046104 -assert nop ostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_usb_clk_disabled_when_active.427046104 |
| Directory | /workspace/2.chip_sw_pwrmgr_usb_clk_disabled_when_active/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_usbdev_smoketest.1474546955 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 4875631472 ps |
| CPU time | 383.3 seconds |
| Started | Jul 03 08:12:45 PM PDT 24 |
| Finished | Jul 03 08:19:09 PM PDT 24 |
| Peak memory | 610696 kb |
| Host | smart-65b0c6ec-b84e-4d97-8b3a-37c8d93792d2 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_usbdev_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1474546955 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_usbdev_smoketest.1474546955 |
| Directory | /workspace/2.chip_sw_pwrmgr_usbdev_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_wdog_reset.494989230 |
| Short name | T831 |
| Test name | |
| Test status | |
| Simulation time | 4597336266 ps |
| CPU time | 679.87 seconds |
| Started | Jul 03 08:06:15 PM PDT 24 |
| Finished | Jul 03 08:17:36 PM PDT 24 |
| Peak memory | 608628 kb |
| Host | smart-22d526d8-2db1-4f5f-b9d9-c5e3a30ea98d |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_wdog_reset_reqs_test:1:new_rules,test_rom:0 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=494 989230 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work space/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_wdog_reset.494989230 |
| Directory | /workspace/2.chip_sw_pwrmgr_wdog_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rom_ctrl_integrity_check.3402673316 |
| Short name | T388 |
| Test name | |
| Test status | |
| Simulation time | 9722585784 ps |
| CPU time | 513.6 seconds |
| Started | Jul 03 08:07:42 PM PDT 24 |
| Finished | Jul 03 08:16:16 PM PDT 24 |
| Peak memory | 611596 kb |
| Host | smart-5459293d-7737-4d65-9ce1-cc5e397bc6d8 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rom_ctrl_integrity_check_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3402673316 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_ctrl_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rom_ctrl_integrity_check.3402673316 |
| Directory | /workspace/2.chip_sw_rom_ctrl_integrity_check/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rstmgr_alert_info.215663190 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 14727620110 ps |
| CPU time | 2043.87 seconds |
| Started | Jul 03 08:08:31 PM PDT 24 |
| Finished | Jul 03 08:42:36 PM PDT 24 |
| Peak memory | 609988 kb |
| Host | smart-13ec12ad-51d9-4485-ae59-7f759d2b52ab |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=30_000_000 +en_scb_tl_err_chk=0 +sw_build_device=sim_dv +sw_images=rstmgr_alert_info_test:1:new_rules,test _rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb _random_seed=215663190 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rstmgr_alert_info.215663190 |
| Directory | /workspace/2.chip_sw_rstmgr_alert_info/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rstmgr_cpu_info.2305336270 |
| Short name | T261 |
| Test name | |
| Test status | |
| Simulation time | 5880060200 ps |
| CPU time | 520.88 seconds |
| Started | Jul 03 08:07:03 PM PDT 24 |
| Finished | Jul 03 08:15:44 PM PDT 24 |
| Peak memory | 610684 kb |
| Host | smart-dc7d83e9-e6fc-47c4-b967-44303caae935 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_cpu_info_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2305336270 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 2.chip_sw_rstmgr_cpu_info.2305336270 |
| Directory | /workspace/2.chip_sw_rstmgr_cpu_info/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rstmgr_rst_cnsty_escalation.4007100583 |
| Short name | T1154 |
| Test name | |
| Test status | |
| Simulation time | 4972639814 ps |
| CPU time | 787.26 seconds |
| Started | Jul 03 08:05:43 PM PDT 24 |
| Finished | Jul 03 08:18:51 PM PDT 24 |
| Peak memory | 641168 kb |
| Host | smart-de26d768-4bb2-4143-b1dc-713babfcc269 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 4007100583 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rstmgr_cnsty_fault_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rstmgr_rst_cnsty_escalation.4007100583 |
| Directory | /workspace/2.chip_sw_rstmgr_rst_cnsty_escalation/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rstmgr_smoketest.2820466906 |
| Short name | T904 |
| Test name | |
| Test status | |
| Simulation time | 3085038062 ps |
| CPU time | 335.05 seconds |
| Started | Jul 03 08:13:19 PM PDT 24 |
| Finished | Jul 03 08:18:55 PM PDT 24 |
| Peak memory | 607836 kb |
| Host | smart-93bddd1a-2f4f-4127-9cdd-059b10ef8a65 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2820466906 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 2.chip_sw_rstmgr_smoketest.2820466906 |
| Directory | /workspace/2.chip_sw_rstmgr_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rstmgr_sw_req.2459431299 |
| Short name | T1063 |
| Test name | |
| Test status | |
| Simulation time | 3535314760 ps |
| CPU time | 503.95 seconds |
| Started | Jul 03 08:06:15 PM PDT 24 |
| Finished | Jul 03 08:14:40 PM PDT 24 |
| Peak memory | 608968 kb |
| Host | smart-4827a4af-cd77-4d61-84a2-4b8638537ef6 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_sw_req_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2459431299 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 2.chip_sw_rstmgr_sw_req.2459431299 |
| Directory | /workspace/2.chip_sw_rstmgr_sw_req/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rstmgr_sw_rst.3784146792 |
| Short name | T962 |
| Test name | |
| Test status | |
| Simulation time | 2780031982 ps |
| CPU time | 245.42 seconds |
| Started | Jul 03 08:05:43 PM PDT 24 |
| Finished | Jul 03 08:09:48 PM PDT 24 |
| Peak memory | 608688 kb |
| Host | smart-e2b3afc6-33d0-46ba-8d05-d2fae25067c8 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_sw_rst_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3784146792 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rstmgr_sw_rst.3784146792 |
| Directory | /workspace/2.chip_sw_rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rv_core_ibex_address_translation.3523063299 |
| Short name | T287 |
| Test name | |
| Test status | |
| Simulation time | 3154297720 ps |
| CPU time | 269.18 seconds |
| Started | Jul 03 08:11:01 PM PDT 24 |
| Finished | Jul 03 08:15:31 PM PDT 24 |
| Peak memory | 610616 kb |
| Host | smart-3fc3fffd-6265-47b1-8a68-1401f4d63e33 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=7_000_000 +sw_build_device=sim_dv +sw_images=rv_core_ibex_address_translation_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=3523063299 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_core_ibex_address_translation.3523063299 |
| Directory | /workspace/2.chip_sw_rv_core_ibex_address_translation/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rv_core_ibex_icache_invalidate.3074090878 |
| Short name | T286 |
| Test name | |
| Test status | |
| Simulation time | 2830031833 ps |
| CPU time | 218.7 seconds |
| Started | Jul 03 08:11:59 PM PDT 24 |
| Finished | Jul 03 08:15:39 PM PDT 24 |
| Peak memory | 610612 kb |
| Host | smart-3d69fcdc-a125-48ea-a49e-bf0bfec2a59f |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_core_ibex_icache_invalidate_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3074090878 -assert nopostp roc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_core_ibex_icache_invalidate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_core_ibex_icache_invalidate.3074090878 |
| Directory | /workspace/2.chip_sw_rv_core_ibex_icache_invalidate/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rv_core_ibex_nmi_irq.1933071091 |
| Short name | T655 |
| Test name | |
| Test status | |
| Simulation time | 5608123310 ps |
| CPU time | 861 seconds |
| Started | Jul 03 08:09:36 PM PDT 24 |
| Finished | Jul 03 08:23:57 PM PDT 24 |
| Peak memory | 608096 kb |
| Host | smart-949770c2-9541-445f-99ac-34922e738f19 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=10_000_000 +sw_build_device=sim_dv +sw_images=rv_core_ibex_nmi_irq_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19330 71091 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_core_ibex_nmi_irq.1933071091 |
| Directory | /workspace/2.chip_sw_rv_core_ibex_nmi_irq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rv_core_ibex_rnd.606853497 |
| Short name | T1143 |
| Test name | |
| Test status | |
| Simulation time | 5299438712 ps |
| CPU time | 1083.02 seconds |
| Started | Jul 03 08:08:17 PM PDT 24 |
| Finished | Jul 03 08:26:21 PM PDT 24 |
| Peak memory | 610600 kb |
| Host | smart-be5f1c2d-2084-4016-a06e-df867d98e0c8 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +rng_srate_value_max=32 +sw_build_device=sim_dv +sw_images=rv_core_ibex_rnd_test:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=606853497 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_core_ibex_rnd.606853497 |
| Directory | /workspace/2.chip_sw_rv_core_ibex_rnd/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rv_dm_access_after_escalation_reset.3661866557 |
| Short name | T400 |
| Test name | |
| Test status | |
| Simulation time | 4783963205 ps |
| CPU time | 608.05 seconds |
| Started | Jul 03 08:11:01 PM PDT 24 |
| Finished | Jul 03 08:21:10 PM PDT 24 |
| Peak memory | 624368 kb |
| Host | smart-75678885-479d-4b61-a203-8130fc87b164 |
| User | root |
| Command | /workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=alert_handler_escalation_test:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3661866557 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_access_after_escalation_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_dm_access_after_escalation_reset.3661866557 |
| Directory | /workspace/2.chip_sw_rv_dm_access_after_escalation_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.2254214187 |
| Short name | T349 |
| Test name | |
| Test status | |
| Simulation time | 5661440524 ps |
| CPU time | 567.34 seconds |
| Started | Jul 03 08:10:43 PM PDT 24 |
| Finished | Jul 03 08:20:11 PM PDT 24 |
| Peak memory | 618508 kb |
| Host | smart-24120179-af67-4b87-be63-85442223d88f |
| User | root |
| Command | /workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_ndm_reset_req_when_cpu_halted_rma:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=225421 4187 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_ndm_reset_when_cpu_halted_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.2254214187 |
| Directory | /workspace/2.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rv_plic_smoketest.726280024 |
| Short name | T1188 |
| Test name | |
| Test status | |
| Simulation time | 2810079246 ps |
| CPU time | 337.91 seconds |
| Started | Jul 03 08:12:29 PM PDT 24 |
| Finished | Jul 03 08:18:07 PM PDT 24 |
| Peak memory | 610672 kb |
| Host | smart-be44b4ea-bee8-40e7-8ae3-5a3e8bad216a |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_plic_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=726280024 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 2.chip_sw_rv_plic_smoketest.726280024 |
| Directory | /workspace/2.chip_sw_rv_plic_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rv_timer_irq.1704988979 |
| Short name | T1032 |
| Test name | |
| Test status | |
| Simulation time | 2758336078 ps |
| CPU time | 293.69 seconds |
| Started | Jul 03 08:05:53 PM PDT 24 |
| Finished | Jul 03 08:10:47 PM PDT 24 |
| Peak memory | 610580 kb |
| Host | smart-bd35b839-b3eb-4b9b-803c-a018054d4f27 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1704988979 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 2.chip_sw_rv_timer_irq.1704988979 |
| Directory | /workspace/2.chip_sw_rv_timer_irq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rv_timer_smoketest.3338126974 |
| Short name | T253 |
| Test name | |
| Test status | |
| Simulation time | 3352243524 ps |
| CPU time | 285.21 seconds |
| Started | Jul 03 08:12:42 PM PDT 24 |
| Finished | Jul 03 08:17:28 PM PDT 24 |
| Peak memory | 610616 kb |
| Host | smart-a8599c52-fa48-4f0a-bab1-65d8af3dc308 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338126974 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 2.chip_sw_rv_timer_smoketest.3338126974 |
| Directory | /workspace/2.chip_sw_rv_timer_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sensor_ctrl_status.3601654800 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 3173277481 ps |
| CPU time | 290.22 seconds |
| Started | Jul 03 08:09:47 PM PDT 24 |
| Finished | Jul 03 08:14:38 PM PDT 24 |
| Peak memory | 609364 kb |
| Host | smart-fb3b9875-0d16-40c9-b713-58b0a01608dc |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_status_test:1:new_rules,test_rom:0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3601654 800 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sensor_ctrl_status_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sensor_ctrl_status.3601654800 |
| Directory | /workspace/2.chip_sw_sensor_ctrl_status/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sleep_pin_retention.473949408 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 4101278932 ps |
| CPU time | 328.35 seconds |
| Started | Jul 03 08:04:11 PM PDT 24 |
| Finished | Jul 03 08:09:40 PM PDT 24 |
| Peak memory | 608136 kb |
| Host | smart-9ee16d61-8d30-45e5-8a08-c8464a7cf335 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sleep_pin_retention_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473949408 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_retention_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa ult.vdb -cm_log /dev/null -cm_name 2.chip_sw_sleep_pin_retention.473949408 |
| Directory | /workspace/2.chip_sw_sleep_pin_retention/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sleep_pwm_pulses.565914361 |
| Short name | T976 |
| Test name | |
| Test status | |
| Simulation time | 9323726032 ps |
| CPU time | 1226.86 seconds |
| Started | Jul 03 08:05:04 PM PDT 24 |
| Finished | Jul 03 08:25:32 PM PDT 24 |
| Peak memory | 610076 kb |
| Host | smart-fbae8d92-1ba5-41e1-aea4-5678e6fe3088 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sleep_pwm_pulses_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=565914361 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwm_pulses_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 2.chip_sw_sleep_pwm_pulses.565914361 |
| Directory | /workspace/2.chip_sw_sleep_pwm_pulses/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_no_scramble.3210668493 |
| Short name | T1194 |
| Test name | |
| Test status | |
| Simulation time | 8326405520 ps |
| CPU time | 463.93 seconds |
| Started | Jul 03 08:08:51 PM PDT 24 |
| Finished | Jul 03 08:16:35 PM PDT 24 |
| Peak memory | 609776 kb |
| Host | smart-a1a050d8-5b48-4425-9640-c0b174b9fee4 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_sleep_sram_ret_contents_no_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210668493 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S EQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sl eep_sram_ret_contents_no_scramble.3210668493 |
| Directory | /workspace/2.chip_sw_sleep_sram_ret_contents_no_scramble/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_scramble.3153340899 |
| Short name | T1285 |
| Test name | |
| Test status | |
| Simulation time | 8359262504 ps |
| CPU time | 995.16 seconds |
| Started | Jul 03 08:08:32 PM PDT 24 |
| Finished | Jul 03 08:25:08 PM PDT 24 |
| Peak memory | 610680 kb |
| Host | smart-6aac910d-86c8-4f6b-98e0-66a00d218d95 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_sleep_sram_ret_contents_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153340899 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sleep _sram_ret_contents_scramble.3153340899 |
| Directory | /workspace/2.chip_sw_sleep_sram_ret_contents_scramble/latest |
| Test location | /workspace/coverage/default/2.chip_sw_spi_device_pass_through.4172117737 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 8047697008 ps |
| CPU time | 905.4 seconds |
| Started | Jul 03 08:07:22 PM PDT 24 |
| Finished | Jul 03 08:22:29 PM PDT 24 |
| Peak memory | 624268 kb |
| Host | smart-c279daf9-1be2-41e8-ba6a-5d173be9af4d |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_passthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4172117737 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_passthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_spi_device_pass_through.4172117737 |
| Directory | /workspace/2.chip_sw_spi_device_pass_through/latest |
| Test location | /workspace/coverage/default/2.chip_sw_spi_device_pass_through_collision.2580180885 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 4686753692 ps |
| CPU time | 702.7 seconds |
| Started | Jul 03 08:05:16 PM PDT 24 |
| Finished | Jul 03 08:17:00 PM PDT 24 |
| Peak memory | 624972 kb |
| Host | smart-3ebc7939-fa71-4bb9-a130-9327028c1166 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_passthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2580180885 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_passthrough_collision_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d efault.vdb -cm_log /dev/null -cm_name 2.chip_sw_spi_device_pass_through_collision.2580180885 |
| Directory | /workspace/2.chip_sw_spi_device_pass_through_collision/latest |
| Test location | /workspace/coverage/default/2.chip_sw_spi_device_tpm.3819960715 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 2897865398 ps |
| CPU time | 353.24 seconds |
| Started | Jul 03 08:06:36 PM PDT 24 |
| Finished | Jul 03 08:12:30 PM PDT 24 |
| Peak memory | 618576 kb |
| Host | smart-431ffed3-56be-4cba-8b60-785033672bc7 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_device_tpm_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3819960715 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_device_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default .vdb -cm_log /dev/null -cm_name 2.chip_sw_spi_device_tpm.3819960715 |
| Directory | /workspace/2.chip_sw_spi_device_tpm/latest |
| Test location | /workspace/coverage/default/2.chip_sw_spi_host_tx_rx.4288540441 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 2650782024 ps |
| CPU time | 271.43 seconds |
| Started | Jul 03 08:05:31 PM PDT 24 |
| Finished | Jul 03 08:10:04 PM PDT 24 |
| Peak memory | 610708 kb |
| Host | smart-304678d1-c7d8-4f74-8aa9-4090a07bb71e |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4288540441 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 2.chip_sw_spi_host_tx_rx.4288540441 |
| Directory | /workspace/2.chip_sw_spi_host_tx_rx/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access.2752127325 |
| Short name | T277 |
| Test name | |
| Test status | |
| Simulation time | 5619759608 ps |
| CPU time | 801.43 seconds |
| Started | Jul 03 08:09:29 PM PDT 24 |
| Finished | Jul 03 08:22:52 PM PDT 24 |
| Peak memory | 610644 kb |
| Host | smart-d1e2c517-3fe7-49c8-84e2-db7daf72d180 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=12_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2752127325 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctr l_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw _sram_ctrl_scrambled_access.2752127325 |
| Directory | /workspace/2.chip_sw_sram_ctrl_scrambled_access/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en.355996888 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 5706167970 ps |
| CPU time | 407.28 seconds |
| Started | Jul 03 08:08:28 PM PDT 24 |
| Finished | Jul 03 08:15:17 PM PDT 24 |
| Peak memory | 608820 kb |
| Host | smart-209da2f3-ff5b-4b91-9dcd-faac7c15892d |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=12_000_000 +bypass_alert_ready_to_end_check=1 +en_jitter=1 +en_scb_tl_err_chk=0 +sw_build_device=sim_dv +s w_images=sram_ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=355996888 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip _sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 2.chip_sw_sram_ctrl_scrambled_access_jitter_en.355996888 |
| Directory | /workspace/2.chip_sw_sram_ctrl_scrambled_access_jitter_en/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.469691521 |
| Short name | T275 |
| Test name | |
| Test status | |
| Simulation time | 5662601654 ps |
| CPU time | 662.92 seconds |
| Started | Jul 03 08:11:45 PM PDT 24 |
| Finished | Jul 03 08:22:49 PM PDT 24 |
| Peak memory | 610176 kb |
| Host | smart-ff4954e8-aa5c-4fbc-8d57-42bbb9c88fe0 |
| User | root |
| Command | /workspace/default/simv +mem_sel=main +sw_test_timeout_ns=12_000_000 +bypass_alert_ready_to_end_check=1 +en_jitter=1 +en_scb_tl_err_chk=0 +cal_sys_clk _70mhz=1 +sw_build_device=sim_dv +sw_images=sram_ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=469691521 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d efault.vdb -cm_log /dev/null -cm_name 2.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.469691521 |
| Directory | /workspace/2.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sram_ctrl_smoketest.1597978290 |
| Short name | T975 |
| Test name | |
| Test status | |
| Simulation time | 2902173008 ps |
| CPU time | 237.46 seconds |
| Started | Jul 03 08:13:10 PM PDT 24 |
| Finished | Jul 03 08:17:08 PM PDT 24 |
| Peak memory | 610672 kb |
| Host | smart-599c2431-6db7-4935-8211-f66f9f974323 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sram_ctrl_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1597978290 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 2.chip_sw_sram_ctrl_smoketest.1597978290 |
| Directory | /workspace/2.chip_sw_sram_ctrl_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sysrst_ctrl_in_irq.3134788614 |
| Short name | T1235 |
| Test name | |
| Test status | |
| Simulation time | 5133475046 ps |
| CPU time | 753.31 seconds |
| Started | Jul 03 08:06:01 PM PDT 24 |
| Finished | Jul 03 08:18:37 PM PDT 24 |
| Peak memory | 612768 kb |
| Host | smart-9203fb87-c43c-4e56-8fdb-6eff2867fd07 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_in_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134788614 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_in_irq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 2.chip_sw_sysrst_ctrl_in_irq.3134788614 |
| Directory | /workspace/2.chip_sw_sysrst_ctrl_in_irq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sysrst_ctrl_inputs.2342731908 |
| Short name | T1268 |
| Test name | |
| Test status | |
| Simulation time | 2853982550 ps |
| CPU time | 284.97 seconds |
| Started | Jul 03 08:06:31 PM PDT 24 |
| Finished | Jul 03 08:11:18 PM PDT 24 |
| Peak memory | 612348 kb |
| Host | smart-96c997e1-bfca-477f-8e15-1fed11a8dc55 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_inputs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2342731908 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_inputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 2.chip_sw_sysrst_ctrl_inputs.2342731908 |
| Directory | /workspace/2.chip_sw_sysrst_ctrl_inputs/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sysrst_ctrl_outputs.54436534 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 3607799076 ps |
| CPU time | 412.54 seconds |
| Started | Jul 03 08:08:00 PM PDT 24 |
| Finished | Jul 03 08:14:54 PM PDT 24 |
| Peak memory | 610600 kb |
| Host | smart-1ffae9f2-6b6a-4254-949d-21328097dc47 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_outputs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54436534 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_outputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 2.chip_sw_sysrst_ctrl_outputs.54436534 |
| Directory | /workspace/2.chip_sw_sysrst_ctrl_outputs/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sysrst_ctrl_reset.211983497 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 24796860408 ps |
| CPU time | 1739.49 seconds |
| Started | Jul 03 08:07:30 PM PDT 24 |
| Finished | Jul 03 08:36:31 PM PDT 24 |
| Peak memory | 614088 kb |
| Host | smart-839f34c9-9935-4fea-8a34-1f98d7f99708 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=36_000_000 +sw_build_device=sim_dv +sw_images=sysrst_ctrl_reset_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21198349 7 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sysrst_ctrl_reset.211983497 |
| Directory | /workspace/2.chip_sw_sysrst_ctrl_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sysrst_ctrl_ulp_z3_wakeup.2842893327 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 6519326640 ps |
| CPU time | 601.44 seconds |
| Started | Jul 03 08:07:42 PM PDT 24 |
| Finished | Jul 03 08:17:45 PM PDT 24 |
| Peak memory | 610752 kb |
| Host | smart-7309a585-5fd2-4dd3-b2e0-1378bf35d8a1 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_ulp_z3_wakeup_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2842893327 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_ulp_z3_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/ coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sysrst_ctrl_ulp_z3_wakeup.2842893327 |
| Directory | /workspace/2.chip_sw_sysrst_ctrl_ulp_z3_wakeup/latest |
| Test location | /workspace/coverage/default/2.chip_sw_uart_rand_baudrate.2218437787 |
| Short name | T846 |
| Test name | |
| Test status | |
| Simulation time | 3974353992 ps |
| CPU time | 559.43 seconds |
| Started | Jul 03 08:04:26 PM PDT 24 |
| Finished | Jul 03 08:13:47 PM PDT 24 |
| Peak memory | 620052 kb |
| Host | smart-191f07a7-9d20-49d1-8e1f-6ee96e578f67 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=2218437787 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_rand_baudrate.2218437787 |
| Directory | /workspace/2.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/2.chip_sw_uart_smoketest.3981084070 |
| Short name | T1149 |
| Test name | |
| Test status | |
| Simulation time | 2635737592 ps |
| CPU time | 292.92 seconds |
| Started | Jul 03 08:12:52 PM PDT 24 |
| Finished | Jul 03 08:17:46 PM PDT 24 |
| Peak memory | 612340 kb |
| Host | smart-224472a7-18aa-4766-af45-d6011e732484 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=uart_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3981084070 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 2.chip_sw_uart_smoketest.3981084070 |
| Directory | /workspace/2.chip_sw_uart_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_uart_tx_rx.2446509479 |
| Short name | T877 |
| Test name | |
| Test status | |
| Simulation time | 3869731496 ps |
| CPU time | 677.72 seconds |
| Started | Jul 03 08:04:24 PM PDT 24 |
| Finished | Jul 03 08:15:43 PM PDT 24 |
| Peak memory | 621920 kb |
| Host | smart-62210e91-6eff-413e-b1c5-dc6a34912250 |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2446509479 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx.2446509479 |
| Directory | /workspace/2.chip_sw_uart_tx_rx/latest |
| Test location | /workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq.3338929943 |
| Short name | T1046 |
| Test name | |
| Test status | |
| Simulation time | 3858541735 ps |
| CPU time | 631.61 seconds |
| Started | Jul 03 08:06:31 PM PDT 24 |
| Finished | Jul 03 08:17:04 PM PDT 24 |
| Peak memory | 620912 kb |
| Host | smart-118fec72-506e-47d9-add9-8bc976e2b72b |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338929943 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_b audrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx _alt_clk_freq.3338929943 |
| Directory | /workspace/2.chip_sw_uart_tx_rx_alt_clk_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.3896921457 |
| Short name | T1012 |
| Test name | |
| Test status | |
| Simulation time | 8442645237 ps |
| CPU time | 1065.49 seconds |
| Started | Jul 03 08:05:01 PM PDT 24 |
| Finished | Jul 03 08:22:48 PM PDT 24 |
| Peak memory | 621076 kb |
| Host | smart-a3c4c434-3d2e-45a7-917a-0563fdd1a1ff |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3896921457 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_b audrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx _alt_clk_freq_low_speed.3896921457 |
| Directory | /workspace/2.chip_sw_uart_tx_rx_alt_clk_freq_low_speed/latest |
| Test location | /workspace/coverage/default/2.chip_sw_uart_tx_rx_bootstrap.3893218688 |
| Short name | T1075 |
| Test name | |
| Test status | |
| Simulation time | 78418541584 ps |
| CPU time | 14393.7 seconds |
| Started | Jul 03 08:06:31 PM PDT 24 |
| Finished | Jul 04 12:06:27 AM PDT 24 |
| Peak memory | 633160 kb |
| Host | smart-dd6cf785-25d3-4b73-8c8e-ed73f616bf5f |
| User | root |
| Command | /workspace/default/simv +use_spi_load_bootstrap=1 +calibrate_usb_clk=1 +test_timeout_ns=160_000_000 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3893218688 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx_bootstrap.3893218688 |
| Directory | /workspace/2.chip_sw_uart_tx_rx_bootstrap/latest |
| Test location | /workspace/coverage/default/2.chip_sw_uart_tx_rx_idx1.3322920181 |
| Short name | T1175 |
| Test name | |
| Test status | |
| Simulation time | 4296374418 ps |
| CPU time | 670.75 seconds |
| Started | Jul 03 08:06:22 PM PDT 24 |
| Finished | Jul 03 08:17:34 PM PDT 24 |
| Peak memory | 621984 kb |
| Host | smart-c14ba37d-e6ad-4afd-9281-c54c4ee6370e |
| User | root |
| Command | /workspace/default/simv +uart_idx=1 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322920181 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx_idx1.3322920181 |
| Directory | /workspace/2.chip_sw_uart_tx_rx_idx1/latest |
| Test location | /workspace/coverage/default/2.chip_sw_uart_tx_rx_idx2.2661975374 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 4396197306 ps |
| CPU time | 702.82 seconds |
| Started | Jul 03 08:04:44 PM PDT 24 |
| Finished | Jul 03 08:16:28 PM PDT 24 |
| Peak memory | 621876 kb |
| Host | smart-e4e1fc4d-b659-4737-8f7f-1d7a423f0621 |
| User | root |
| Command | /workspace/default/simv +uart_idx=2 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2661975374 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx_idx2.2661975374 |
| Directory | /workspace/2.chip_sw_uart_tx_rx_idx2/latest |
| Test location | /workspace/coverage/default/2.chip_sw_uart_tx_rx_idx3.1031946420 |
| Short name | T985 |
| Test name | |
| Test status | |
| Simulation time | 4387160048 ps |
| CPU time | 714.56 seconds |
| Started | Jul 03 08:05:29 PM PDT 24 |
| Finished | Jul 03 08:17:25 PM PDT 24 |
| Peak memory | 621976 kb |
| Host | smart-8aaba498-7fa4-423f-acbb-1da7c907eb98 |
| User | root |
| Command | /workspace/default/simv +uart_idx=3 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031946420 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx_idx3.1031946420 |
| Directory | /workspace/2.chip_sw_uart_tx_rx_idx3/latest |
| Test location | /workspace/coverage/default/2.chip_tap_straps_dev.2325619659 |
| Short name | T411 |
| Test name | |
| Test status | |
| Simulation time | 2940901603 ps |
| CPU time | 144.17 seconds |
| Started | Jul 03 08:09:15 PM PDT 24 |
| Finished | Jul 03 08:11:40 PM PDT 24 |
| Peak memory | 621484 kb |
| Host | smart-0f5c17ff-20aa-4397-9bb8-1128d3226c2e |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStDev +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom: new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2325619659 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_tap_straps_dev.2325619659 |
| Directory | /workspace/2.chip_tap_straps_dev/latest |
| Test location | /workspace/coverage/default/2.chip_tap_straps_prod.787086113 |
| Short name | T1004 |
| Test name | |
| Test status | |
| Simulation time | 2702217667 ps |
| CPU time | 155.58 seconds |
| Started | Jul 03 08:10:18 PM PDT 24 |
| Finished | Jul 03 08:12:55 PM PDT 24 |
| Peak memory | 622608 kb |
| Host | smart-e3bbace7-1cf7-4c9b-b4f3-602a10e5b868 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom :new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787086113 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_tap_straps_prod.787086113 |
| Directory | /workspace/2.chip_tap_straps_prod/latest |
| Test location | /workspace/coverage/default/2.chip_tap_straps_testunlock0.3939592952 |
| Short name | T1123 |
| Test name | |
| Test status | |
| Simulation time | 3498365339 ps |
| CPU time | 342.14 seconds |
| Started | Jul 03 08:11:29 PM PDT 24 |
| Finished | Jul 03 08:17:12 PM PDT 24 |
| Peak memory | 624168 kb |
| Host | smart-b389ff4b-4790-4449-b6bd-ab43e171b41e |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:te st_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3939592952 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_tap_straps_testunlock0.3939592952 |
| Directory | /workspace/2.chip_tap_straps_testunlock0/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_asm_init_dev.4042816787 |
| Short name | T843 |
| Test name | |
| Test status | |
| Simulation time | 15689623916 ps |
| CPU time | 3315.7 seconds |
| Started | Jul 03 08:18:56 PM PDT 24 |
| Finished | Jul 03 09:14:13 PM PDT 24 |
| Peak memory | 608196 kb |
| Host | smart-ad83a6ee-feec-4f0a-9c58-34f20b3741c0 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_dev:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4042816787 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S EQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_asm_init_dev.4042816787 |
| Directory | /workspace/2.rom_e2e_asm_init_dev/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_asm_init_prod.2200084305 |
| Short name | T1078 |
| Test name | |
| Test status | |
| Simulation time | 15303460496 ps |
| CPU time | 4430.07 seconds |
| Started | Jul 03 08:24:43 PM PDT 24 |
| Finished | Jul 03 09:38:35 PM PDT 24 |
| Peak memory | 610804 kb |
| Host | smart-a1ed1010-0c04-4436-bdd7-c3af2cc29374 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2200084305 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_ SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_asm_init_prod.2200084305 |
| Directory | /workspace/2.rom_e2e_asm_init_prod/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_asm_init_prod_end.2748242952 |
| Short name | T1121 |
| Test name | |
| Test status | |
| Simulation time | 15631885690 ps |
| CPU time | 3243.8 seconds |
| Started | Jul 03 08:17:33 PM PDT 24 |
| Finished | Jul 03 09:11:38 PM PDT 24 |
| Peak memory | 610812 kb |
| Host | smart-2b760616-b484-4c56-9390-8f2e14b6d685 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_prod_end:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748242952 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_T EST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 2.rom_e2e_asm_init_prod_end.2748242952 |
| Directory | /workspace/2.rom_e2e_asm_init_prod_end/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_asm_init_rma.701617403 |
| Short name | T1021 |
| Test name | |
| Test status | |
| Simulation time | 14201270019 ps |
| CPU time | 3261.62 seconds |
| Started | Jul 03 08:15:45 PM PDT 24 |
| Finished | Jul 03 09:10:08 PM PDT 24 |
| Peak memory | 608492 kb |
| Host | smart-ce88aa87-ab25-400d-bd86-eac25a5fbd64 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=701617403 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SE Q=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 .rom_e2e_asm_init_rma.701617403 |
| Directory | /workspace/2.rom_e2e_asm_init_rma/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_asm_init_test_unlocked0.4132043831 |
| Short name | T1003 |
| Test name | |
| Test status | |
| Simulation time | 11323589038 ps |
| CPU time | 3271.23 seconds |
| Started | Jul 03 08:24:20 PM PDT 24 |
| Finished | Jul 03 09:18:53 PM PDT 24 |
| Peak memory | 610788 kb |
| Host | smart-2299dd5a-b140-42a1-99d6-e82be4fa6e25 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=410_000_000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4132043831 -assert nopostproc +UVM_TESTNAME=chip_base_te st +UVM_TEST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 2.rom_e2e_asm_init_test_unlocked0.4132043831 |
| Directory | /workspace/2.rom_e2e_asm_init_test_unlocked0/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_invalid_meas.1307424021 |
| Short name | T997 |
| Test name | |
| Test status | |
| Simulation time | 14328796704 ps |
| CPU time | 4327.65 seconds |
| Started | Jul 03 08:24:57 PM PDT 24 |
| Finished | Jul 03 09:37:05 PM PDT 24 |
| Peak memory | 608400 kb |
| Host | smart-19595a3c-7b74-4f7a-9a45-b55af6e1b30c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_invalid _meas:1:new_rules,otp_img_keymgr_otp_invalid_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1307424021 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip _sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_keymgr_in it_rom_ext_invalid_meas.1307424021 |
| Directory | /workspace/2.rom_e2e_keymgr_init_rom_ext_invalid_meas/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_meas.722921080 |
| Short name | T968 |
| Test name | |
| Test status | |
| Simulation time | 15480552832 ps |
| CPU time | 3171.58 seconds |
| Started | Jul 03 08:16:28 PM PDT 24 |
| Finished | Jul 03 09:09:21 PM PDT 24 |
| Peak memory | 610752 kb |
| Host | smart-111c188b-4950-4c15-a3b1-1a2bb59b7485 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_meas:1: new_rules,otp_img_keymgr_otp_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=722921080 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_keymgr_init_rom_ext_meas.722921080 |
| Directory | /workspace/2.rom_e2e_keymgr_init_rom_ext_meas/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_no_meas.281878958 |
| Short name | T905 |
| Test name | |
| Test status | |
| Simulation time | 14452333560 ps |
| CPU time | 3605.18 seconds |
| Started | Jul 03 08:17:02 PM PDT 24 |
| Finished | Jul 03 09:17:07 PM PDT 24 |
| Peak memory | 610760 kb |
| Host | smart-26789085-d2c7-4a29-a163-90dde6429d4d |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_no_meas :1:new_rules,otp_img_keymgr_otp_no_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=281878958 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_keymgr_init_rom_ext_ no_meas.281878958 |
| Directory | /workspace/2.rom_e2e_keymgr_init_rom_ext_no_meas/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_shutdown_exception_c.1866165418 |
| Short name | T1011 |
| Test name | |
| Test status | |
| Simulation time | 14371176970 ps |
| CPU time | 3306.32 seconds |
| Started | Jul 03 08:16:33 PM PDT 24 |
| Finished | Jul 03 09:11:40 PM PDT 24 |
| Peak memory | 610944 kb |
| Host | smart-3453bd06-97e3-4f55-9e6f-23c0a6c52e65 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_shutdown_exception_c:1:ne w_rules,otp_img_secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1866165418 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_shu tdown_exception_c_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_ shutdown_exception_c.1866165418 |
| Directory | /workspace/2.rom_e2e_shutdown_exception_c/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_shutdown_output.2854374312 |
| Short name | T1286 |
| Test name | |
| Test status | |
| Simulation time | 24891830517 ps |
| CPU time | 3032.52 seconds |
| Started | Jul 03 08:15:54 PM PDT 24 |
| Finished | Jul 03 09:06:28 PM PDT 24 |
| Peak memory | 611404 kb |
| Host | smart-11bb4282-beed-41a8-b689-dc4aceaabef0 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_unsigned:1:ot_f lash_binary,otp_img_shutdown_output_test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2854374312 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chi p_sw_rom_e2e_shutdown_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_shutdown_output.2854374312 |
| Directory | /workspace/2.rom_e2e_shutdown_output/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_smoke.3223326977 |
| Short name | T884 |
| Test name | |
| Test status | |
| Simulation time | 14853929740 ps |
| CPU time | 3327.81 seconds |
| Started | Jul 03 08:17:33 PM PDT 24 |
| Finished | Jul 03 09:13:02 PM PDT 24 |
| Peak memory | 610748 kb |
| Host | smart-47ab539f-7670-4ea2-a287-f53572fca290 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_smoke:1:new_rules,otp_img _secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_to p/hw/dv/tools/sim.tcl +ntb_random_seed=3223326977 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_smoke.3223326977 |
| Directory | /workspace/2.rom_e2e_smoke/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_static_critical.1843695214 |
| Short name | T1125 |
| Test name | |
| Test status | |
| Simulation time | 17788620134 ps |
| CPU time | 3990.5 seconds |
| Started | Jul 03 08:17:29 PM PDT 24 |
| Finished | Jul 03 09:24:00 PM PDT 24 |
| Peak memory | 610796 kb |
| Host | smart-705d6c9b-6432-463a-a1fe-6d20e7f6d66f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_static_critical:1:new_rul es,otp_img_secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1843695214 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_static_critical.1843695214 |
| Directory | /workspace/2.rom_e2e_static_critical/latest |
| Test location | /workspace/coverage/default/2.rom_keymgr_functest.1806621653 |
| Short name | T834 |
| Test name | |
| Test status | |
| Simulation time | 3913475604 ps |
| CPU time | 389.87 seconds |
| Started | Jul 03 08:12:36 PM PDT 24 |
| Finished | Jul 03 08:19:07 PM PDT 24 |
| Peak memory | 610644 kb |
| Host | smart-40a20783-0b7b-4499-9629-05d0d7764aa3 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=10_000_000 +sw_build_device=sim_dv +sw_images=keymgr_functest:1:new_rules,test_rom:0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1806621653 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 2.rom_keymgr_functest.1806621653 |
| Directory | /workspace/2.rom_keymgr_functest/latest |
| Test location | /workspace/coverage/default/2.rom_volatile_raw_unlock.4041167170 |
| Short name | T1248 |
| Test name | |
| Test status | |
| Simulation time | 2732446729 ps |
| CPU time | 105.37 seconds |
| Started | Jul 03 08:11:29 PM PDT 24 |
| Finished | Jul 03 08:13:15 PM PDT 24 |
| Peak memory | 616848 kb |
| Host | smart-5294971f-617b-468e-b315-97f54a482eb4 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceExternal48Mhz +rom_prod_mode=1 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_test_key_0:1:ot_flash_binary,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4041167170 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 2.rom_volatile_raw_unlock.4041167170 |
| Directory | /workspace/2.rom_volatile_raw_unlock/latest |
| Test location | /workspace/coverage/default/21.chip_sw_alert_handler_lpg_sleep_mode_alerts.256142126 |
| Short name | T732 |
| Test name | |
| Test status | |
| Simulation time | 4004879894 ps |
| CPU time | 535.71 seconds |
| Started | Jul 03 08:20:17 PM PDT 24 |
| Finished | Jul 03 08:29:13 PM PDT 24 |
| Peak memory | 648368 kb |
| Host | smart-0d68fec7-9f38-4cdb-aa54-ebd620180d66 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=256142126 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.chip_s w_alert_handler_lpg_sleep_mode_alerts.256142126 |
| Directory | /workspace/21.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/22.chip_sw_alert_handler_lpg_sleep_mode_alerts.2618736310 |
| Short name | T301 |
| Test name | |
| Test status | |
| Simulation time | 3456016800 ps |
| CPU time | 412.29 seconds |
| Started | Jul 03 08:17:25 PM PDT 24 |
| Finished | Jul 03 08:24:19 PM PDT 24 |
| Peak memory | 648424 kb |
| Host | smart-2ad32a38-d378-4a97-bda1-f02e319f0387 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2618736310 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2618736310 |
| Directory | /workspace/22.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/23.chip_sw_all_escalation_resets.3766579903 |
| Short name | T1134 |
| Test name | |
| Test status | |
| Simulation time | 4680860672 ps |
| CPU time | 753.2 seconds |
| Started | Jul 03 08:17:28 PM PDT 24 |
| Finished | Jul 03 08:30:01 PM PDT 24 |
| Peak memory | 649720 kb |
| Host | smart-a7bac165-9c7e-4bfa-a51b-cd5450378914 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3766579903 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.chip_sw_all_escalation_resets.3766579903 |
| Directory | /workspace/23.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/24.chip_sw_alert_handler_lpg_sleep_mode_alerts.3416966360 |
| Short name | T741 |
| Test name | |
| Test status | |
| Simulation time | 3552234288 ps |
| CPU time | 362.5 seconds |
| Started | Jul 03 08:17:34 PM PDT 24 |
| Finished | Jul 03 08:23:37 PM PDT 24 |
| Peak memory | 648396 kb |
| Host | smart-ad8dff45-0f05-44c5-8e6d-94eaa9a67649 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3416966360 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3416966360 |
| Directory | /workspace/24.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/24.chip_sw_all_escalation_resets.1113099024 |
| Short name | T1136 |
| Test name | |
| Test status | |
| Simulation time | 5553108488 ps |
| CPU time | 559.41 seconds |
| Started | Jul 03 08:17:10 PM PDT 24 |
| Finished | Jul 03 08:26:30 PM PDT 24 |
| Peak memory | 641356 kb |
| Host | smart-bc545596-fa0d-4a3b-b887-55b4b2e43c65 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1113099024 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.chip_sw_all_escalation_resets.1113099024 |
| Directory | /workspace/24.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/27.chip_sw_all_escalation_resets.3542774949 |
| Short name | T399 |
| Test name | |
| Test status | |
| Simulation time | 5723635000 ps |
| CPU time | 761.21 seconds |
| Started | Jul 03 08:18:37 PM PDT 24 |
| Finished | Jul 03 08:31:19 PM PDT 24 |
| Peak memory | 649652 kb |
| Host | smart-56d5f807-582a-4484-820c-369720956b19 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3542774949 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.chip_sw_all_escalation_resets.3542774949 |
| Directory | /workspace/27.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/28.chip_sw_alert_handler_lpg_sleep_mode_alerts.2704286855 |
| Short name | T247 |
| Test name | |
| Test status | |
| Simulation time | 4003831540 ps |
| CPU time | 338.6 seconds |
| Started | Jul 03 08:18:11 PM PDT 24 |
| Finished | Jul 03 08:23:50 PM PDT 24 |
| Peak memory | 648384 kb |
| Host | smart-4ea97bc5-2d3e-46de-be3a-19832a7bd687 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704286855 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2704286855 |
| Directory | /workspace/28.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/3.chip_sw_all_escalation_resets.4287690871 |
| Short name | T727 |
| Test name | |
| Test status | |
| Simulation time | 5327592280 ps |
| CPU time | 823.22 seconds |
| Started | Jul 03 08:13:59 PM PDT 24 |
| Finished | Jul 03 08:27:43 PM PDT 24 |
| Peak memory | 649528 kb |
| Host | smart-eade5807-8b9b-4aad-b94f-85b333cfa97f |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 4287690871 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_all_escalation_resets.4287690871 |
| Directory | /workspace/3.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/3.chip_sw_aon_timer_sleep_wdog_sleep_pause.985824041 |
| Short name | T1237 |
| Test name | |
| Test status | |
| Simulation time | 6847664632 ps |
| CPU time | 383.85 seconds |
| Started | Jul 03 08:12:41 PM PDT 24 |
| Finished | Jul 03 08:19:06 PM PDT 24 |
| Peak memory | 610652 kb |
| Host | smart-1181c67b-3e92-4387-b675-c5ffdad9dbe5 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_sleep_wdog_sleep_pause_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=985824041 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_aon_timer_sleep_wdog_sleep_pause.985824041 |
| Directory | /workspace/3.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest |
| Test location | /workspace/coverage/default/3.chip_sw_csrng_edn_concurrency.620173267 |
| Short name | T1018 |
| Test name | |
| Test status | |
| Simulation time | 26846831048 ps |
| CPU time | 6059.56 seconds |
| Started | Jul 03 08:14:17 PM PDT 24 |
| Finished | Jul 03 09:55:18 PM PDT 24 |
| Peak memory | 608464 kb |
| Host | smart-0c2c843b-fca4-4d6e-974d-804fc315c962 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +accelerate_cold_power_up_time=3 +accelerate_r egulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620173267 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_csrng_edn_concurrency.620173267 |
| Directory | /workspace/3.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspace/coverage/default/3.chip_sw_data_integrity_escalation.58740911 |
| Short name | T242 |
| Test name | |
| Test status | |
| Simulation time | 5499553416 ps |
| CPU time | 855.5 seconds |
| Started | Jul 03 08:14:07 PM PDT 24 |
| Finished | Jul 03 08:28:23 PM PDT 24 |
| Peak memory | 610728 kb |
| Host | smart-33c1584e-d145-404b-a030-18e83040df20 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=data_integrity_escalation_reset_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=58740911 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_data_integrity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_data_integrity_escalation.58740911 |
| Directory | /workspace/3.chip_sw_data_integrity_escalation/latest |
| Test location | /workspace/coverage/default/3.chip_sw_lc_ctrl_transition.3544304337 |
| Short name | T1058 |
| Test name | |
| Test status | |
| Simulation time | 12499750054 ps |
| CPU time | 750.79 seconds |
| Started | Jul 03 08:13:28 PM PDT 24 |
| Finished | Jul 03 08:26:00 PM PDT 24 |
| Peak memory | 622152 kb |
| Host | smart-7aeeb0a4-a946-443a-b0af-3a799b5e6766 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3544304337 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 3.chip_sw_lc_ctrl_transition.3544304337 |
| Directory | /workspace/3.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/3.chip_sw_sensor_ctrl_alert.4136534374 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 5816797392 ps |
| CPU time | 787.91 seconds |
| Started | Jul 03 08:14:14 PM PDT 24 |
| Finished | Jul 03 08:27:22 PM PDT 24 |
| Peak memory | 609620 kb |
| Host | smart-4c7e9a84-4f75-43ee-8837-d3e835238c00 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_alert_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41365343 74 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_sensor_ctrl_alert.4136534374 |
| Directory | /workspace/3.chip_sw_sensor_ctrl_alert/latest |
| Test location | /workspace/coverage/default/3.chip_sw_uart_rand_baudrate.1246301274 |
| Short name | T281 |
| Test name | |
| Test status | |
| Simulation time | 9032653284 ps |
| CPU time | 1917.74 seconds |
| Started | Jul 03 08:13:00 PM PDT 24 |
| Finished | Jul 03 08:44:59 PM PDT 24 |
| Peak memory | 623176 kb |
| Host | smart-e03bf6a7-0920-49f7-9bd4-4dee3709160b |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=1246301274 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_rand_baudrate.1246301274 |
| Directory | /workspace/3.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/3.chip_sw_uart_tx_rx.518768859 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 4414505272 ps |
| CPU time | 622.1 seconds |
| Started | Jul 03 08:14:59 PM PDT 24 |
| Finished | Jul 03 08:25:22 PM PDT 24 |
| Peak memory | 621708 kb |
| Host | smart-9ed4c630-5b98-459d-ac2d-e1fc54bb2843 |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=518768859 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_tx_rx.518768859 |
| Directory | /workspace/3.chip_sw_uart_tx_rx/latest |
| Test location | /workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq.4112611788 |
| Short name | T937 |
| Test name | |
| Test status | |
| Simulation time | 9163728741 ps |
| CPU time | 1795.5 seconds |
| Started | Jul 03 08:14:39 PM PDT 24 |
| Finished | Jul 03 08:44:35 PM PDT 24 |
| Peak memory | 617952 kb |
| Host | smart-6558740c-b92b-4f5c-8816-9310ffce19f1 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4112611788 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_b audrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_tx_rx _alt_clk_freq.4112611788 |
| Directory | /workspace/3.chip_sw_uart_tx_rx_alt_clk_freq/latest |
| Test location | /workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.3003821549 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 8077116336 ps |
| CPU time | 1144.96 seconds |
| Started | Jul 03 08:12:54 PM PDT 24 |
| Finished | Jul 03 08:32:00 PM PDT 24 |
| Peak memory | 617836 kb |
| Host | smart-e96ce95b-932f-46fc-9a9c-8905d4934743 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3003821549 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_b audrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_tx_rx _alt_clk_freq_low_speed.3003821549 |
| Directory | /workspace/3.chip_sw_uart_tx_rx_alt_clk_freq_low_speed/latest |
| Test location | /workspace/coverage/default/3.chip_sw_uart_tx_rx_idx1.597387786 |
| Short name | T1039 |
| Test name | |
| Test status | |
| Simulation time | 4604434776 ps |
| CPU time | 640.69 seconds |
| Started | Jul 03 08:14:05 PM PDT 24 |
| Finished | Jul 03 08:24:46 PM PDT 24 |
| Peak memory | 622004 kb |
| Host | smart-0cde1de2-d4f6-4d1c-92de-e7ef05a4a2b8 |
| User | root |
| Command | /workspace/default/simv +uart_idx=1 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=597387786 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_tx_rx_idx1.597387786 |
| Directory | /workspace/3.chip_sw_uart_tx_rx_idx1/latest |
| Test location | /workspace/coverage/default/3.chip_sw_uart_tx_rx_idx2.768461290 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 4061422736 ps |
| CPU time | 627.69 seconds |
| Started | Jul 03 08:13:17 PM PDT 24 |
| Finished | Jul 03 08:23:46 PM PDT 24 |
| Peak memory | 621980 kb |
| Host | smart-e35b453f-f54f-4944-be30-28590d1e3fba |
| User | root |
| Command | /workspace/default/simv +uart_idx=2 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768461290 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_tx_rx_idx2.768461290 |
| Directory | /workspace/3.chip_sw_uart_tx_rx_idx2/latest |
| Test location | /workspace/coverage/default/3.chip_sw_uart_tx_rx_idx3.2460708089 |
| Short name | T1119 |
| Test name | |
| Test status | |
| Simulation time | 4596741488 ps |
| CPU time | 745.29 seconds |
| Started | Jul 03 08:12:39 PM PDT 24 |
| Finished | Jul 03 08:25:05 PM PDT 24 |
| Peak memory | 621948 kb |
| Host | smart-edf3451c-4f06-483f-8c60-29c731e7cc97 |
| User | root |
| Command | /workspace/default/simv +uart_idx=3 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2460708089 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_tx_rx_idx3.2460708089 |
| Directory | /workspace/3.chip_sw_uart_tx_rx_idx3/latest |
| Test location | /workspace/coverage/default/3.chip_tap_straps_prod.3898513860 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 11367349507 ps |
| CPU time | 1043.8 seconds |
| Started | Jul 03 08:13:35 PM PDT 24 |
| Finished | Jul 03 08:31:00 PM PDT 24 |
| Peak memory | 623944 kb |
| Host | smart-490be18b-aeac-45cd-9339-9c405a56ac3f |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom :new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3898513860 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_tap_straps_prod.3898513860 |
| Directory | /workspace/3.chip_tap_straps_prod/latest |
| Test location | /workspace/coverage/default/3.chip_tap_straps_rma.1184774817 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 4700739728 ps |
| CPU time | 304.68 seconds |
| Started | Jul 03 08:13:21 PM PDT 24 |
| Finished | Jul 03 08:18:27 PM PDT 24 |
| Peak memory | 622932 kb |
| Host | smart-7daf96dc-777b-40d2-ba5e-bca7695e495f |
| User | root |
| Command | /workspace/default/simv +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1184774817 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 3.chip_tap_straps_rma.1184774817 |
| Directory | /workspace/3.chip_tap_straps_rma/latest |
| Test location | /workspace/coverage/default/30.chip_sw_alert_handler_lpg_sleep_mode_alerts.714417238 |
| Short name | T1020 |
| Test name | |
| Test status | |
| Simulation time | 3701665250 ps |
| CPU time | 283.34 seconds |
| Started | Jul 03 08:17:03 PM PDT 24 |
| Finished | Jul 03 08:21:47 PM PDT 24 |
| Peak memory | 648228 kb |
| Host | smart-9652ce9c-4125-427b-8a40-ffc58a30d934 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=714417238 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.chip_s w_alert_handler_lpg_sleep_mode_alerts.714417238 |
| Directory | /workspace/30.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/32.chip_sw_all_escalation_resets.2979484979 |
| Short name | T693 |
| Test name | |
| Test status | |
| Simulation time | 6092345300 ps |
| CPU time | 550.99 seconds |
| Started | Jul 03 08:18:52 PM PDT 24 |
| Finished | Jul 03 08:28:03 PM PDT 24 |
| Peak memory | 649652 kb |
| Host | smart-ab7ae101-6b29-4b79-a074-e57fdda3e5d4 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2979484979 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.chip_sw_all_escalation_resets.2979484979 |
| Directory | /workspace/32.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/33.chip_sw_alert_handler_lpg_sleep_mode_alerts.1022019124 |
| Short name | T750 |
| Test name | |
| Test status | |
| Simulation time | 3345939560 ps |
| CPU time | 413.83 seconds |
| Started | Jul 03 08:19:51 PM PDT 24 |
| Finished | Jul 03 08:26:46 PM PDT 24 |
| Peak memory | 648308 kb |
| Host | smart-7af5fdb5-071d-4343-b361-58149031fd0c |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1022019124 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1022019124 |
| Directory | /workspace/33.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/36.chip_sw_alert_handler_lpg_sleep_mode_alerts.1188728025 |
| Short name | T680 |
| Test name | |
| Test status | |
| Simulation time | 3344938914 ps |
| CPU time | 413.6 seconds |
| Started | Jul 03 08:18:14 PM PDT 24 |
| Finished | Jul 03 08:25:08 PM PDT 24 |
| Peak memory | 640024 kb |
| Host | smart-c0f05891-86db-4354-9847-c12933d7c53b |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1188728025 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1188728025 |
| Directory | /workspace/36.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/37.chip_sw_all_escalation_resets.4152294353 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 4861208280 ps |
| CPU time | 668.35 seconds |
| Started | Jul 03 08:18:18 PM PDT 24 |
| Finished | Jul 03 08:29:28 PM PDT 24 |
| Peak memory | 623452 kb |
| Host | smart-05ba2156-602a-4291-b0a2-9349c9b99f25 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 4152294353 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.chip_sw_all_escalation_resets.4152294353 |
| Directory | /workspace/37.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/39.chip_sw_alert_handler_lpg_sleep_mode_alerts.3675580430 |
| Short name | T696 |
| Test name | |
| Test status | |
| Simulation time | 4017836216 ps |
| CPU time | 422.74 seconds |
| Started | Jul 03 08:20:23 PM PDT 24 |
| Finished | Jul 03 08:27:26 PM PDT 24 |
| Peak memory | 648472 kb |
| Host | smart-9e9c1cb9-6cbe-4265-9afe-cfe448a8f4db |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3675580430 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3675580430 |
| Directory | /workspace/39.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/39.chip_sw_all_escalation_resets.3670624706 |
| Short name | T336 |
| Test name | |
| Test status | |
| Simulation time | 5212283522 ps |
| CPU time | 508.47 seconds |
| Started | Jul 03 08:18:22 PM PDT 24 |
| Finished | Jul 03 08:26:51 PM PDT 24 |
| Peak memory | 641192 kb |
| Host | smart-ec0247d5-d0e0-488c-b63c-db20b50c70e9 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3670624706 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.chip_sw_all_escalation_resets.3670624706 |
| Directory | /workspace/39.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/4.chip_sw_alert_handler_lpg_sleep_mode_alerts.2067720168 |
| Short name | T751 |
| Test name | |
| Test status | |
| Simulation time | 3507439288 ps |
| CPU time | 343.35 seconds |
| Started | Jul 03 08:13:40 PM PDT 24 |
| Finished | Jul 03 08:19:24 PM PDT 24 |
| Peak memory | 648264 kb |
| Host | smart-5cb0fe0d-0f16-4263-9e00-bbd7c160b785 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2067720168 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_s w_alert_handler_lpg_sleep_mode_alerts.2067720168 |
| Directory | /workspace/4.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/4.chip_sw_aon_timer_sleep_wdog_sleep_pause.3369704110 |
| Short name | T1023 |
| Test name | |
| Test status | |
| Simulation time | 8463086360 ps |
| CPU time | 641.03 seconds |
| Started | Jul 03 08:14:46 PM PDT 24 |
| Finished | Jul 03 08:25:29 PM PDT 24 |
| Peak memory | 608608 kb |
| Host | smart-10b3a35c-ad16-492b-a65f-c83643ec4800 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_sleep_wdog_sleep_pause_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3369704110 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_aon_timer_sleep_wdog_sleep_pause.3369704110 |
| Directory | /workspace/4.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest |
| Test location | /workspace/coverage/default/4.chip_sw_csrng_edn_concurrency.3454098932 |
| Short name | T258 |
| Test name | |
| Test status | |
| Simulation time | 18138551240 ps |
| CPU time | 3784.18 seconds |
| Started | Jul 03 08:14:37 PM PDT 24 |
| Finished | Jul 03 09:17:42 PM PDT 24 |
| Peak memory | 608440 kb |
| Host | smart-e278101c-d7dd-4136-a90a-6fd3be50c85a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +accelerate_cold_power_up_time=3 +accelerate_r egulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3454098932 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 4.chip_sw_csrng_edn_concurrency.3454098932 |
| Directory | /workspace/4.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspace/coverage/default/4.chip_sw_data_integrity_escalation.1580038365 |
| Short name | T1073 |
| Test name | |
| Test status | |
| Simulation time | 5508733868 ps |
| CPU time | 636.8 seconds |
| Started | Jul 03 08:13:40 PM PDT 24 |
| Finished | Jul 03 08:24:18 PM PDT 24 |
| Peak memory | 610704 kb |
| Host | smart-8aa82a87-afe5-4da8-b24c-103490da52f2 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=data_integrity_escalation_reset_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1580038365 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_data_integrity_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_data_integrity_escalation.1580038365 |
| Directory | /workspace/4.chip_sw_data_integrity_escalation/latest |
| Test location | /workspace/coverage/default/4.chip_sw_lc_ctrl_transition.2572865885 |
| Short name | T1246 |
| Test name | |
| Test status | |
| Simulation time | 9765266184 ps |
| CPU time | 1119.14 seconds |
| Started | Jul 03 08:14:09 PM PDT 24 |
| Finished | Jul 03 08:32:49 PM PDT 24 |
| Peak memory | 621768 kb |
| Host | smart-97663c86-e28e-497f-9f68-bd3d4d64fba6 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2572865885 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 4.chip_sw_lc_ctrl_transition.2572865885 |
| Directory | /workspace/4.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/4.chip_sw_sensor_ctrl_alert.4122339376 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 9425860504 ps |
| CPU time | 925.48 seconds |
| Started | Jul 03 08:14:05 PM PDT 24 |
| Finished | Jul 03 08:29:31 PM PDT 24 |
| Peak memory | 610648 kb |
| Host | smart-04a99480-2d75-48df-b9f2-d7ec2277776d |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_alert_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41223393 76 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_sensor_ctrl_alert.4122339376 |
| Directory | /workspace/4.chip_sw_sensor_ctrl_alert/latest |
| Test location | /workspace/coverage/default/4.chip_sw_uart_rand_baudrate.2474495192 |
| Short name | T211 |
| Test name | |
| Test status | |
| Simulation time | 13411274392 ps |
| CPU time | 2031.59 seconds |
| Started | Jul 03 08:13:23 PM PDT 24 |
| Finished | Jul 03 08:47:16 PM PDT 24 |
| Peak memory | 620204 kb |
| Host | smart-c9d53b38-b01d-499f-bf0e-4e6351e3edf5 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=2474495192 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_rand_baudrate.2474495192 |
| Directory | /workspace/4.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq.3899082200 |
| Short name | T967 |
| Test name | |
| Test status | |
| Simulation time | 4044645298 ps |
| CPU time | 599.45 seconds |
| Started | Jul 03 08:15:52 PM PDT 24 |
| Finished | Jul 03 08:25:53 PM PDT 24 |
| Peak memory | 621240 kb |
| Host | smart-736bd7f2-b1e9-489d-95f7-88aaf71430f8 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3899082200 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_b audrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_tx_rx _alt_clk_freq.3899082200 |
| Directory | /workspace/4.chip_sw_uart_tx_rx_alt_clk_freq/latest |
| Test location | /workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.2031280512 |
| Short name | T915 |
| Test name | |
| Test status | |
| Simulation time | 13403399346 ps |
| CPU time | 1433.69 seconds |
| Started | Jul 03 08:14:14 PM PDT 24 |
| Finished | Jul 03 08:38:08 PM PDT 24 |
| Peak memory | 621032 kb |
| Host | smart-72e6592c-7e26-4dd1-990f-734ede7403df |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2031280512 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_b audrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_tx_rx _alt_clk_freq_low_speed.2031280512 |
| Directory | /workspace/4.chip_sw_uart_tx_rx_alt_clk_freq_low_speed/latest |
| Test location | /workspace/coverage/default/4.chip_sw_uart_tx_rx_idx1.3605081596 |
| Short name | T1282 |
| Test name | |
| Test status | |
| Simulation time | 4252858144 ps |
| CPU time | 538.5 seconds |
| Started | Jul 03 08:13:39 PM PDT 24 |
| Finished | Jul 03 08:22:38 PM PDT 24 |
| Peak memory | 621724 kb |
| Host | smart-d47abd1a-e83c-4059-9bde-053971a1bbe6 |
| User | root |
| Command | /workspace/default/simv +uart_idx=1 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3605081596 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_tx_rx_idx1.3605081596 |
| Directory | /workspace/4.chip_sw_uart_tx_rx_idx1/latest |
| Test location | /workspace/coverage/default/4.chip_sw_uart_tx_rx_idx2.2019595380 |
| Short name | T990 |
| Test name | |
| Test status | |
| Simulation time | 4630763530 ps |
| CPU time | 656.22 seconds |
| Started | Jul 03 08:13:18 PM PDT 24 |
| Finished | Jul 03 08:24:15 PM PDT 24 |
| Peak memory | 621968 kb |
| Host | smart-23278362-a6fa-4337-97bd-077b653c9986 |
| User | root |
| Command | /workspace/default/simv +uart_idx=2 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2019595380 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_tx_rx_idx2.2019595380 |
| Directory | /workspace/4.chip_sw_uart_tx_rx_idx2/latest |
| Test location | /workspace/coverage/default/4.chip_sw_uart_tx_rx_idx3.3552010279 |
| Short name | T1212 |
| Test name | |
| Test status | |
| Simulation time | 4029245050 ps |
| CPU time | 669.38 seconds |
| Started | Jul 03 08:14:17 PM PDT 24 |
| Finished | Jul 03 08:25:27 PM PDT 24 |
| Peak memory | 621652 kb |
| Host | smart-ac4c779e-bf23-42ff-9cea-137e42b8f189 |
| User | root |
| Command | /workspace/default/simv +uart_idx=3 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3552010279 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_tx_rx_idx3.3552010279 |
| Directory | /workspace/4.chip_sw_uart_tx_rx_idx3/latest |
| Test location | /workspace/coverage/default/4.chip_tap_straps_dev.3307618063 |
| Short name | T1148 |
| Test name | |
| Test status | |
| Simulation time | 9511700061 ps |
| CPU time | 814.65 seconds |
| Started | Jul 03 08:12:56 PM PDT 24 |
| Finished | Jul 03 08:26:31 PM PDT 24 |
| Peak memory | 623972 kb |
| Host | smart-ef18cb8e-3b69-4531-a7a3-aa6384895896 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStDev +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom: new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3307618063 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_tap_straps_dev.3307618063 |
| Directory | /workspace/4.chip_tap_straps_dev/latest |
| Test location | /workspace/coverage/default/4.chip_tap_straps_prod.3390532978 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 7455352278 ps |
| CPU time | 665.66 seconds |
| Started | Jul 03 08:14:00 PM PDT 24 |
| Finished | Jul 03 08:25:07 PM PDT 24 |
| Peak memory | 623964 kb |
| Host | smart-ad03e758-fe4d-4b47-86ff-6ee76539b67c |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom :new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3390532978 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_tap_straps_prod.3390532978 |
| Directory | /workspace/4.chip_tap_straps_prod/latest |
| Test location | /workspace/coverage/default/41.chip_sw_all_escalation_resets.1982697387 |
| Short name | T364 |
| Test name | |
| Test status | |
| Simulation time | 5036186392 ps |
| CPU time | 700.12 seconds |
| Started | Jul 03 08:19:02 PM PDT 24 |
| Finished | Jul 03 08:30:42 PM PDT 24 |
| Peak memory | 649904 kb |
| Host | smart-b7df2435-f66c-4041-9670-6f924d039b58 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1982697387 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.chip_sw_all_escalation_resets.1982697387 |
| Directory | /workspace/41.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/43.chip_sw_alert_handler_lpg_sleep_mode_alerts.2317403051 |
| Short name | T656 |
| Test name | |
| Test status | |
| Simulation time | 3467721846 ps |
| CPU time | 369.66 seconds |
| Started | Jul 03 08:19:59 PM PDT 24 |
| Finished | Jul 03 08:26:09 PM PDT 24 |
| Peak memory | 648344 kb |
| Host | smart-63e81bf3-62b0-470a-b9b1-b91794d326f5 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2317403051 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2317403051 |
| Directory | /workspace/43.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/43.chip_sw_all_escalation_resets.1000423900 |
| Short name | T692 |
| Test name | |
| Test status | |
| Simulation time | 5759893524 ps |
| CPU time | 516.87 seconds |
| Started | Jul 03 08:20:06 PM PDT 24 |
| Finished | Jul 03 08:28:43 PM PDT 24 |
| Peak memory | 649696 kb |
| Host | smart-d4625f27-f0e5-4601-b193-d0053de7a7a9 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1000423900 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.chip_sw_all_escalation_resets.1000423900 |
| Directory | /workspace/43.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/44.chip_sw_alert_handler_lpg_sleep_mode_alerts.1851770020 |
| Short name | T1239 |
| Test name | |
| Test status | |
| Simulation time | 3312981598 ps |
| CPU time | 386.03 seconds |
| Started | Jul 03 08:20:10 PM PDT 24 |
| Finished | Jul 03 08:26:37 PM PDT 24 |
| Peak memory | 641252 kb |
| Host | smart-45f4db7c-c13c-4f6b-a661-36dd000a2687 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1851770020 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1851770020 |
| Directory | /workspace/44.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/44.chip_sw_all_escalation_resets.2232218037 |
| Short name | T677 |
| Test name | |
| Test status | |
| Simulation time | 4685741712 ps |
| CPU time | 701.76 seconds |
| Started | Jul 03 08:20:11 PM PDT 24 |
| Finished | Jul 03 08:31:53 PM PDT 24 |
| Peak memory | 641144 kb |
| Host | smart-4db5ee26-cbed-487f-874b-84b6bedafe3a |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2232218037 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.chip_sw_all_escalation_resets.2232218037 |
| Directory | /workspace/44.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/45.chip_sw_alert_handler_lpg_sleep_mode_alerts.3164282832 |
| Short name | T1215 |
| Test name | |
| Test status | |
| Simulation time | 3433868032 ps |
| CPU time | 519.58 seconds |
| Started | Jul 03 08:19:58 PM PDT 24 |
| Finished | Jul 03 08:28:38 PM PDT 24 |
| Peak memory | 641264 kb |
| Host | smart-d5b4d958-297c-4e8d-be32-17d762888ef1 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3164282832 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3164282832 |
| Directory | /workspace/45.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/46.chip_sw_alert_handler_lpg_sleep_mode_alerts.3908854523 |
| Short name | T694 |
| Test name | |
| Test status | |
| Simulation time | 4071867710 ps |
| CPU time | 460.61 seconds |
| Started | Jul 03 08:19:36 PM PDT 24 |
| Finished | Jul 03 08:27:17 PM PDT 24 |
| Peak memory | 640000 kb |
| Host | smart-2e02ffbe-68b5-4052-9744-ab97bfce6195 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3908854523 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3908854523 |
| Directory | /workspace/46.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/46.chip_sw_all_escalation_resets.325638321 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 5223597524 ps |
| CPU time | 705.26 seconds |
| Started | Jul 03 08:18:36 PM PDT 24 |
| Finished | Jul 03 08:30:22 PM PDT 24 |
| Peak memory | 615764 kb |
| Host | smart-6dbc4e21-de82-4b25-b33a-fdb64926b244 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 325638321 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.chip_sw_all_escalation_resets.325638321 |
| Directory | /workspace/46.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/47.chip_sw_alert_handler_lpg_sleep_mode_alerts.3200337031 |
| Short name | T728 |
| Test name | |
| Test status | |
| Simulation time | 3248873248 ps |
| CPU time | 451.73 seconds |
| Started | Jul 03 08:18:58 PM PDT 24 |
| Finished | Jul 03 08:26:30 PM PDT 24 |
| Peak memory | 648632 kb |
| Host | smart-c9de49b0-4399-4ff1-85a3-fbaa204ac0db |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3200337031 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3200337031 |
| Directory | /workspace/47.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/48.chip_sw_alert_handler_lpg_sleep_mode_alerts.2458737867 |
| Short name | T725 |
| Test name | |
| Test status | |
| Simulation time | 3852917580 ps |
| CPU time | 306.31 seconds |
| Started | Jul 03 08:19:55 PM PDT 24 |
| Finished | Jul 03 08:25:02 PM PDT 24 |
| Peak memory | 648344 kb |
| Host | smart-10dd64c4-b4a7-4b4f-b645-6158f0bae7e8 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2458737867 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2458737867 |
| Directory | /workspace/48.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/48.chip_sw_all_escalation_resets.3224409316 |
| Short name | T245 |
| Test name | |
| Test status | |
| Simulation time | 4836353660 ps |
| CPU time | 485.54 seconds |
| Started | Jul 03 08:18:21 PM PDT 24 |
| Finished | Jul 03 08:26:28 PM PDT 24 |
| Peak memory | 641660 kb |
| Host | smart-9c6762b3-cd26-42b2-8947-c2db9c02e057 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3224409316 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.chip_sw_all_escalation_resets.3224409316 |
| Directory | /workspace/48.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/49.chip_sw_alert_handler_lpg_sleep_mode_alerts.3494417431 |
| Short name | T746 |
| Test name | |
| Test status | |
| Simulation time | 4119116728 ps |
| CPU time | 453.34 seconds |
| Started | Jul 03 08:18:09 PM PDT 24 |
| Finished | Jul 03 08:25:43 PM PDT 24 |
| Peak memory | 640144 kb |
| Host | smart-8117fce2-24cb-47b5-a214-a7d2db4f9794 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3494417431 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3494417431 |
| Directory | /workspace/49.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/5.chip_sw_alert_handler_lpg_sleep_mode_alerts.1209123210 |
| Short name | T1001 |
| Test name | |
| Test status | |
| Simulation time | 3290741948 ps |
| CPU time | 382.32 seconds |
| Started | Jul 03 08:14:28 PM PDT 24 |
| Finished | Jul 03 08:20:51 PM PDT 24 |
| Peak memory | 648480 kb |
| Host | smart-97117bb1-7271-45d4-bf74-75da6eb5b448 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1209123210 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.chip_s w_alert_handler_lpg_sleep_mode_alerts.1209123210 |
| Directory | /workspace/5.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/5.chip_sw_all_escalation_resets.3959290692 |
| Short name | T735 |
| Test name | |
| Test status | |
| Simulation time | 5321410756 ps |
| CPU time | 587.86 seconds |
| Started | Jul 03 08:14:11 PM PDT 24 |
| Finished | Jul 03 08:24:00 PM PDT 24 |
| Peak memory | 649508 kb |
| Host | smart-cb181223-86c7-4922-bc9e-c69da3c71e91 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3959290692 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.chip_sw_all_escalation_resets.3959290692 |
| Directory | /workspace/5.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/5.chip_sw_csrng_edn_concurrency.3486479843 |
| Short name | T1116 |
| Test name | |
| Test status | |
| Simulation time | 18249384112 ps |
| CPU time | 3849.6 seconds |
| Started | Jul 03 08:15:14 PM PDT 24 |
| Finished | Jul 03 09:19:25 PM PDT 24 |
| Peak memory | 608588 kb |
| Host | smart-400262c8-9c83-4289-94e5-350aa7e4a737 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +accelerate_cold_power_up_time=3 +accelerate_r egulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3486479843 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 5.chip_sw_csrng_edn_concurrency.3486479843 |
| Directory | /workspace/5.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspace/coverage/default/5.chip_sw_lc_ctrl_transition.3498105689 |
| Short name | T981 |
| Test name | |
| Test status | |
| Simulation time | 5013598854 ps |
| CPU time | 430.11 seconds |
| Started | Jul 03 08:13:52 PM PDT 24 |
| Finished | Jul 03 08:21:04 PM PDT 24 |
| Peak memory | 619468 kb |
| Host | smart-0587450c-f6f7-48b3-8236-8b7144b21d25 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3498105689 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 5.chip_sw_lc_ctrl_transition.3498105689 |
| Directory | /workspace/5.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/5.chip_sw_uart_rand_baudrate.3744193688 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 9344621432 ps |
| CPU time | 1719.18 seconds |
| Started | Jul 03 08:14:34 PM PDT 24 |
| Finished | Jul 03 08:43:14 PM PDT 24 |
| Peak memory | 620188 kb |
| Host | smart-5a083cb5-ae15-4e8e-bfb0-d2e0c5df6ce3 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=3744193688 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.chip_sw_uart_rand_baudrate.3744193688 |
| Directory | /workspace/5.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/50.chip_sw_all_escalation_resets.840158267 |
| Short name | T753 |
| Test name | |
| Test status | |
| Simulation time | 5120531372 ps |
| CPU time | 735.29 seconds |
| Started | Jul 03 08:20:34 PM PDT 24 |
| Finished | Jul 03 08:32:50 PM PDT 24 |
| Peak memory | 649516 kb |
| Host | smart-e848600f-53d2-4c7d-a027-a0b7f6362d48 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 840158267 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.chip_sw_all_escalation_resets.840158267 |
| Directory | /workspace/50.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/51.chip_sw_alert_handler_lpg_sleep_mode_alerts.147589972 |
| Short name | T414 |
| Test name | |
| Test status | |
| Simulation time | 3431117434 ps |
| CPU time | 383.76 seconds |
| Started | Jul 03 08:20:30 PM PDT 24 |
| Finished | Jul 03 08:26:55 PM PDT 24 |
| Peak memory | 648652 kb |
| Host | smart-afce19a7-91d2-452b-9169-7dfe675167f1 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=147589972 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.chip_s w_alert_handler_lpg_sleep_mode_alerts.147589972 |
| Directory | /workspace/51.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/51.chip_sw_all_escalation_resets.3066293657 |
| Short name | T207 |
| Test name | |
| Test status | |
| Simulation time | 5488790152 ps |
| CPU time | 681.87 seconds |
| Started | Jul 03 08:20:50 PM PDT 24 |
| Finished | Jul 03 08:32:14 PM PDT 24 |
| Peak memory | 649600 kb |
| Host | smart-f7eee008-4f2c-48eb-9f69-95680847e0e8 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3066293657 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.chip_sw_all_escalation_resets.3066293657 |
| Directory | /workspace/51.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/52.chip_sw_alert_handler_lpg_sleep_mode_alerts.3671468685 |
| Short name | T1162 |
| Test name | |
| Test status | |
| Simulation time | 3554028862 ps |
| CPU time | 425.68 seconds |
| Started | Jul 03 08:21:09 PM PDT 24 |
| Finished | Jul 03 08:28:15 PM PDT 24 |
| Peak memory | 648336 kb |
| Host | smart-5e67156d-8d1e-4d43-9602-016e183f7659 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3671468685 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3671468685 |
| Directory | /workspace/52.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/52.chip_sw_all_escalation_resets.3550966481 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 5960506552 ps |
| CPU time | 571.12 seconds |
| Started | Jul 03 08:20:08 PM PDT 24 |
| Finished | Jul 03 08:29:40 PM PDT 24 |
| Peak memory | 641180 kb |
| Host | smart-caac42ae-9396-4e2f-9838-218ebce0d8d1 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3550966481 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.chip_sw_all_escalation_resets.3550966481 |
| Directory | /workspace/52.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/53.chip_sw_alert_handler_lpg_sleep_mode_alerts.3823627738 |
| Short name | T747 |
| Test name | |
| Test status | |
| Simulation time | 3701579330 ps |
| CPU time | 364.88 seconds |
| Started | Jul 03 08:20:15 PM PDT 24 |
| Finished | Jul 03 08:26:21 PM PDT 24 |
| Peak memory | 648300 kb |
| Host | smart-4cf6208c-56a6-41a0-9550-63480da28603 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3823627738 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3823627738 |
| Directory | /workspace/53.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/54.chip_sw_alert_handler_lpg_sleep_mode_alerts.1362192107 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 4302132382 ps |
| CPU time | 468.02 seconds |
| Started | Jul 03 08:19:22 PM PDT 24 |
| Finished | Jul 03 08:27:10 PM PDT 24 |
| Peak memory | 641232 kb |
| Host | smart-0ce5f4be-3961-414c-a9dc-821fea4fe473 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1362192107 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1362192107 |
| Directory | /workspace/54.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/54.chip_sw_all_escalation_resets.2508083923 |
| Short name | T713 |
| Test name | |
| Test status | |
| Simulation time | 4420878600 ps |
| CPU time | 555.62 seconds |
| Started | Jul 03 08:18:39 PM PDT 24 |
| Finished | Jul 03 08:27:55 PM PDT 24 |
| Peak memory | 649604 kb |
| Host | smart-097bffae-bccd-47a8-b596-70f31285e9d7 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2508083923 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.chip_sw_all_escalation_resets.2508083923 |
| Directory | /workspace/54.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/55.chip_sw_alert_handler_lpg_sleep_mode_alerts.3757268866 |
| Short name | T614 |
| Test name | |
| Test status | |
| Simulation time | 3233041630 ps |
| CPU time | 307.26 seconds |
| Started | Jul 03 08:18:55 PM PDT 24 |
| Finished | Jul 03 08:24:03 PM PDT 24 |
| Peak memory | 648612 kb |
| Host | smart-15252170-b5fd-4fd8-a6ff-e8dedffbaaec |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3757268866 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3757268866 |
| Directory | /workspace/55.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/55.chip_sw_all_escalation_resets.3697175906 |
| Short name | T679 |
| Test name | |
| Test status | |
| Simulation time | 4392968088 ps |
| CPU time | 585.69 seconds |
| Started | Jul 03 08:18:59 PM PDT 24 |
| Finished | Jul 03 08:28:45 PM PDT 24 |
| Peak memory | 649680 kb |
| Host | smart-cd7401c4-cc94-4360-8549-18202b532b1d |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3697175906 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.chip_sw_all_escalation_resets.3697175906 |
| Directory | /workspace/55.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/57.chip_sw_all_escalation_resets.2940576233 |
| Short name | T722 |
| Test name | |
| Test status | |
| Simulation time | 5424546608 ps |
| CPU time | 695.02 seconds |
| Started | Jul 03 08:19:19 PM PDT 24 |
| Finished | Jul 03 08:30:55 PM PDT 24 |
| Peak memory | 649584 kb |
| Host | smart-4b4d6359-e9dc-4902-ad38-e38c36394b97 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2940576233 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.chip_sw_all_escalation_resets.2940576233 |
| Directory | /workspace/57.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/58.chip_sw_alert_handler_lpg_sleep_mode_alerts.2785956161 |
| Short name | T686 |
| Test name | |
| Test status | |
| Simulation time | 3659929708 ps |
| CPU time | 307.35 seconds |
| Started | Jul 03 08:19:45 PM PDT 24 |
| Finished | Jul 03 08:24:53 PM PDT 24 |
| Peak memory | 639932 kb |
| Host | smart-2184c876-41cb-4d61-bdbc-ae8a2b518e0f |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2785956161 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2785956161 |
| Directory | /workspace/58.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/59.chip_sw_all_escalation_resets.2324309610 |
| Short name | T1242 |
| Test name | |
| Test status | |
| Simulation time | 4769925600 ps |
| CPU time | 632.08 seconds |
| Started | Jul 03 08:20:37 PM PDT 24 |
| Finished | Jul 03 08:31:10 PM PDT 24 |
| Peak memory | 615736 kb |
| Host | smart-34235c41-adcd-4b04-a589-44ee5ab3196b |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2324309610 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.chip_sw_all_escalation_resets.2324309610 |
| Directory | /workspace/59.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/6.chip_sw_alert_handler_lpg_sleep_mode_alerts.3592118999 |
| Short name | T737 |
| Test name | |
| Test status | |
| Simulation time | 3869159036 ps |
| CPU time | 411 seconds |
| Started | Jul 03 08:14:00 PM PDT 24 |
| Finished | Jul 03 08:20:51 PM PDT 24 |
| Peak memory | 648456 kb |
| Host | smart-66f47a40-4d4e-427e-a679-c244929fbf55 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3592118999 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.chip_s w_alert_handler_lpg_sleep_mode_alerts.3592118999 |
| Directory | /workspace/6.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/6.chip_sw_csrng_edn_concurrency.1788323101 |
| Short name | T1226 |
| Test name | |
| Test status | |
| Simulation time | 22149082276 ps |
| CPU time | 4430.55 seconds |
| Started | Jul 03 08:16:36 PM PDT 24 |
| Finished | Jul 03 09:30:28 PM PDT 24 |
| Peak memory | 608788 kb |
| Host | smart-8225d44b-db23-457c-b49b-67d1e1396d29 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +accelerate_cold_power_up_time=3 +accelerate_r egulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1788323101 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 6.chip_sw_csrng_edn_concurrency.1788323101 |
| Directory | /workspace/6.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspace/coverage/default/6.chip_sw_lc_ctrl_transition.2817015112 |
| Short name | T938 |
| Test name | |
| Test status | |
| Simulation time | 12222908514 ps |
| CPU time | 1455.34 seconds |
| Started | Jul 03 08:14:45 PM PDT 24 |
| Finished | Jul 03 08:39:01 PM PDT 24 |
| Peak memory | 622704 kb |
| Host | smart-2e8699da-774b-415b-8a93-3b9cb8e5604e |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2817015112 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 6.chip_sw_lc_ctrl_transition.2817015112 |
| Directory | /workspace/6.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/6.chip_sw_uart_rand_baudrate.3122636164 |
| Short name | T1082 |
| Test name | |
| Test status | |
| Simulation time | 8836798780 ps |
| CPU time | 1496.09 seconds |
| Started | Jul 03 08:14:27 PM PDT 24 |
| Finished | Jul 03 08:39:24 PM PDT 24 |
| Peak memory | 620164 kb |
| Host | smart-902f14ee-736c-4763-91d2-861409d35c7b |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=3122636164 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.chip_sw_uart_rand_baudrate.3122636164 |
| Directory | /workspace/6.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/60.chip_sw_alert_handler_lpg_sleep_mode_alerts.3903668988 |
| Short name | T705 |
| Test name | |
| Test status | |
| Simulation time | 4068940004 ps |
| CPU time | 383.34 seconds |
| Started | Jul 03 08:22:24 PM PDT 24 |
| Finished | Jul 03 08:28:48 PM PDT 24 |
| Peak memory | 648464 kb |
| Host | smart-183b3c2a-5895-4f9a-9e7e-4c44b67fafe8 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3903668988 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3903668988 |
| Directory | /workspace/60.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/60.chip_sw_all_escalation_resets.2920371570 |
| Short name | T721 |
| Test name | |
| Test status | |
| Simulation time | 5365843760 ps |
| CPU time | 622.64 seconds |
| Started | Jul 03 08:19:46 PM PDT 24 |
| Finished | Jul 03 08:30:09 PM PDT 24 |
| Peak memory | 649616 kb |
| Host | smart-0bbaf5cd-9249-474d-816a-6f3ee7f9ca21 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2920371570 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.chip_sw_all_escalation_resets.2920371570 |
| Directory | /workspace/60.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/61.chip_sw_alert_handler_lpg_sleep_mode_alerts.1488933641 |
| Short name | T711 |
| Test name | |
| Test status | |
| Simulation time | 3798794788 ps |
| CPU time | 533.66 seconds |
| Started | Jul 03 08:19:56 PM PDT 24 |
| Finished | Jul 03 08:28:50 PM PDT 24 |
| Peak memory | 648424 kb |
| Host | smart-9f28405a-056d-49a5-9417-2bdf2693e592 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1488933641 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1488933641 |
| Directory | /workspace/61.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/61.chip_sw_all_escalation_resets.3228690790 |
| Short name | T707 |
| Test name | |
| Test status | |
| Simulation time | 4649225702 ps |
| CPU time | 527.1 seconds |
| Started | Jul 03 08:22:14 PM PDT 24 |
| Finished | Jul 03 08:31:02 PM PDT 24 |
| Peak memory | 649624 kb |
| Host | smart-a4f08495-d0e0-449e-97f4-2a9c370da163 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3228690790 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.chip_sw_all_escalation_resets.3228690790 |
| Directory | /workspace/61.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/62.chip_sw_all_escalation_resets.3466127555 |
| Short name | T716 |
| Test name | |
| Test status | |
| Simulation time | 6172855120 ps |
| CPU time | 808.14 seconds |
| Started | Jul 03 08:19:46 PM PDT 24 |
| Finished | Jul 03 08:33:15 PM PDT 24 |
| Peak memory | 649840 kb |
| Host | smart-8fc894be-b2a6-46d7-8473-60e7e6111026 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3466127555 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.chip_sw_all_escalation_resets.3466127555 |
| Directory | /workspace/62.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/63.chip_sw_alert_handler_lpg_sleep_mode_alerts.1146455917 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 3724425454 ps |
| CPU time | 360.32 seconds |
| Started | Jul 03 08:20:05 PM PDT 24 |
| Finished | Jul 03 08:26:06 PM PDT 24 |
| Peak memory | 648936 kb |
| Host | smart-7f5256e1-d933-45dc-b141-1ef058de937f |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1146455917 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1146455917 |
| Directory | /workspace/63.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/63.chip_sw_all_escalation_resets.2952200167 |
| Short name | T667 |
| Test name | |
| Test status | |
| Simulation time | 4443547280 ps |
| CPU time | 666.83 seconds |
| Started | Jul 03 08:20:13 PM PDT 24 |
| Finished | Jul 03 08:31:21 PM PDT 24 |
| Peak memory | 649576 kb |
| Host | smart-72452df5-d904-4959-9cbf-d9cd5a296c6f |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2952200167 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.chip_sw_all_escalation_resets.2952200167 |
| Directory | /workspace/63.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/64.chip_sw_alert_handler_lpg_sleep_mode_alerts.480626602 |
| Short name | T685 |
| Test name | |
| Test status | |
| Simulation time | 3904380034 ps |
| CPU time | 311.74 seconds |
| Started | Jul 03 08:22:26 PM PDT 24 |
| Finished | Jul 03 08:27:39 PM PDT 24 |
| Peak memory | 648396 kb |
| Host | smart-f71717c0-f011-447e-b203-c1ebc848eb3c |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=480626602 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.chip_s w_alert_handler_lpg_sleep_mode_alerts.480626602 |
| Directory | /workspace/64.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/64.chip_sw_all_escalation_resets.3430948841 |
| Short name | T1171 |
| Test name | |
| Test status | |
| Simulation time | 4090760208 ps |
| CPU time | 573.1 seconds |
| Started | Jul 03 08:21:20 PM PDT 24 |
| Finished | Jul 03 08:30:54 PM PDT 24 |
| Peak memory | 622928 kb |
| Host | smart-6357b6ee-1204-4e60-af01-16e14615c27e |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3430948841 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.chip_sw_all_escalation_resets.3430948841 |
| Directory | /workspace/64.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/65.chip_sw_alert_handler_lpg_sleep_mode_alerts.4061073933 |
| Short name | T726 |
| Test name | |
| Test status | |
| Simulation time | 3178613864 ps |
| CPU time | 380.38 seconds |
| Started | Jul 03 08:19:45 PM PDT 24 |
| Finished | Jul 03 08:26:06 PM PDT 24 |
| Peak memory | 640020 kb |
| Host | smart-605be9df-6c81-4355-9bd3-3dd0e24071ea |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4061073933 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.chip_ sw_alert_handler_lpg_sleep_mode_alerts.4061073933 |
| Directory | /workspace/65.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/65.chip_sw_all_escalation_resets.3294417626 |
| Short name | T733 |
| Test name | |
| Test status | |
| Simulation time | 5449080892 ps |
| CPU time | 596.84 seconds |
| Started | Jul 03 08:23:01 PM PDT 24 |
| Finished | Jul 03 08:32:59 PM PDT 24 |
| Peak memory | 649504 kb |
| Host | smart-3d8f7219-5d01-4187-84c2-384a88f7c2cd |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3294417626 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.chip_sw_all_escalation_resets.3294417626 |
| Directory | /workspace/65.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/66.chip_sw_alert_handler_lpg_sleep_mode_alerts.1942067749 |
| Short name | T670 |
| Test name | |
| Test status | |
| Simulation time | 3892576368 ps |
| CPU time | 448.3 seconds |
| Started | Jul 03 08:20:14 PM PDT 24 |
| Finished | Jul 03 08:27:43 PM PDT 24 |
| Peak memory | 648360 kb |
| Host | smart-bb7997ba-583e-4882-b96d-7b00f598bfe2 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942067749 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1942067749 |
| Directory | /workspace/66.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/66.chip_sw_all_escalation_resets.3801064046 |
| Short name | T719 |
| Test name | |
| Test status | |
| Simulation time | 4892033792 ps |
| CPU time | 537.81 seconds |
| Started | Jul 03 08:21:20 PM PDT 24 |
| Finished | Jul 03 08:30:18 PM PDT 24 |
| Peak memory | 641144 kb |
| Host | smart-8bf4d93a-f391-4f3c-bc0e-74e7b5327118 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3801064046 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.chip_sw_all_escalation_resets.3801064046 |
| Directory | /workspace/66.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/67.chip_sw_alert_handler_lpg_sleep_mode_alerts.3797600432 |
| Short name | T724 |
| Test name | |
| Test status | |
| Simulation time | 4497325616 ps |
| CPU time | 493.62 seconds |
| Started | Jul 03 08:20:32 PM PDT 24 |
| Finished | Jul 03 08:28:46 PM PDT 24 |
| Peak memory | 648596 kb |
| Host | smart-778baa46-c3c5-4560-b764-db9a776806b4 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3797600432 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3797600432 |
| Directory | /workspace/67.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/67.chip_sw_all_escalation_resets.2002974718 |
| Short name | T683 |
| Test name | |
| Test status | |
| Simulation time | 4819090552 ps |
| CPU time | 631.58 seconds |
| Started | Jul 03 08:20:12 PM PDT 24 |
| Finished | Jul 03 08:30:44 PM PDT 24 |
| Peak memory | 641176 kb |
| Host | smart-2fdab190-8cdf-441f-a7bf-80df7592f53b |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2002974718 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.chip_sw_all_escalation_resets.2002974718 |
| Directory | /workspace/67.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/68.chip_sw_all_escalation_resets.3271400225 |
| Short name | T715 |
| Test name | |
| Test status | |
| Simulation time | 5113045058 ps |
| CPU time | 503.26 seconds |
| Started | Jul 03 08:22:47 PM PDT 24 |
| Finished | Jul 03 08:31:11 PM PDT 24 |
| Peak memory | 641452 kb |
| Host | smart-db6a45c9-b2b8-44f4-84ec-b9dbf8c269cd |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3271400225 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.chip_sw_all_escalation_resets.3271400225 |
| Directory | /workspace/68.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/69.chip_sw_alert_handler_lpg_sleep_mode_alerts.2577820798 |
| Short name | T1270 |
| Test name | |
| Test status | |
| Simulation time | 3184245484 ps |
| CPU time | 380.74 seconds |
| Started | Jul 03 08:24:58 PM PDT 24 |
| Finished | Jul 03 08:31:19 PM PDT 24 |
| Peak memory | 640040 kb |
| Host | smart-1baa30c7-aaf5-49a4-a955-d36190257185 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577820798 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2577820798 |
| Directory | /workspace/69.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/7.chip_sw_alert_handler_lpg_sleep_mode_alerts.3215632454 |
| Short name | T273 |
| Test name | |
| Test status | |
| Simulation time | 3938813222 ps |
| CPU time | 396.47 seconds |
| Started | Jul 03 08:16:39 PM PDT 24 |
| Finished | Jul 03 08:23:17 PM PDT 24 |
| Peak memory | 641228 kb |
| Host | smart-d453f5cc-44a0-4aa5-a763-e0b2cddf2129 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215632454 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.chip_s w_alert_handler_lpg_sleep_mode_alerts.3215632454 |
| Directory | /workspace/7.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/7.chip_sw_all_escalation_resets.2145884050 |
| Short name | T717 |
| Test name | |
| Test status | |
| Simulation time | 5728689562 ps |
| CPU time | 534.93 seconds |
| Started | Jul 03 08:16:45 PM PDT 24 |
| Finished | Jul 03 08:25:41 PM PDT 24 |
| Peak memory | 649828 kb |
| Host | smart-cf80337a-2cd1-4dbb-ae67-c1430cd4bcd2 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2145884050 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.chip_sw_all_escalation_resets.2145884050 |
| Directory | /workspace/7.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/7.chip_sw_lc_ctrl_transition.2419171607 |
| Short name | T995 |
| Test name | |
| Test status | |
| Simulation time | 13330119876 ps |
| CPU time | 1146.39 seconds |
| Started | Jul 03 08:16:15 PM PDT 24 |
| Finished | Jul 03 08:35:23 PM PDT 24 |
| Peak memory | 622776 kb |
| Host | smart-5e3d94cc-d615-487f-ba9c-d1d7c169c9c7 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2419171607 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 7.chip_sw_lc_ctrl_transition.2419171607 |
| Directory | /workspace/7.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/7.chip_sw_uart_rand_baudrate.2867424357 |
| Short name | T979 |
| Test name | |
| Test status | |
| Simulation time | 8639188500 ps |
| CPU time | 1709.94 seconds |
| Started | Jul 03 08:15:05 PM PDT 24 |
| Finished | Jul 03 08:43:35 PM PDT 24 |
| Peak memory | 620248 kb |
| Host | smart-81397531-4c01-49ff-bd84-147b56cbdb19 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=2867424357 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.chip_sw_uart_rand_baudrate.2867424357 |
| Directory | /workspace/7.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/70.chip_sw_alert_handler_lpg_sleep_mode_alerts.3736532589 |
| Short name | T698 |
| Test name | |
| Test status | |
| Simulation time | 3506001768 ps |
| CPU time | 401.83 seconds |
| Started | Jul 03 08:19:48 PM PDT 24 |
| Finished | Jul 03 08:26:31 PM PDT 24 |
| Peak memory | 648680 kb |
| Host | smart-d16bed96-8670-4c08-8a71-c78cbb547f7d |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3736532589 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3736532589 |
| Directory | /workspace/70.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/72.chip_sw_alert_handler_lpg_sleep_mode_alerts.4026315613 |
| Short name | T358 |
| Test name | |
| Test status | |
| Simulation time | 4020332648 ps |
| CPU time | 329.3 seconds |
| Started | Jul 03 08:21:32 PM PDT 24 |
| Finished | Jul 03 08:27:02 PM PDT 24 |
| Peak memory | 648336 kb |
| Host | smart-6aabca27-01be-46e7-8cd3-66985e45ff40 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4026315613 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.chip_ sw_alert_handler_lpg_sleep_mode_alerts.4026315613 |
| Directory | /workspace/72.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/72.chip_sw_all_escalation_resets.1858334640 |
| Short name | T749 |
| Test name | |
| Test status | |
| Simulation time | 5808816942 ps |
| CPU time | 618.6 seconds |
| Started | Jul 03 08:20:57 PM PDT 24 |
| Finished | Jul 03 08:31:16 PM PDT 24 |
| Peak memory | 649476 kb |
| Host | smart-eb191d4e-1903-4290-be19-3bad65dd4c47 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1858334640 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.chip_sw_all_escalation_resets.1858334640 |
| Directory | /workspace/72.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/74.chip_sw_alert_handler_lpg_sleep_mode_alerts.3428136760 |
| Short name | T248 |
| Test name | |
| Test status | |
| Simulation time | 3614002584 ps |
| CPU time | 425.39 seconds |
| Started | Jul 03 08:21:44 PM PDT 24 |
| Finished | Jul 03 08:28:50 PM PDT 24 |
| Peak memory | 648324 kb |
| Host | smart-2d27ddb0-559e-4ade-b39d-149a819515a8 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428136760 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3428136760 |
| Directory | /workspace/74.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/74.chip_sw_all_escalation_resets.1249740636 |
| Short name | T730 |
| Test name | |
| Test status | |
| Simulation time | 4351163880 ps |
| CPU time | 505.35 seconds |
| Started | Jul 03 08:23:24 PM PDT 24 |
| Finished | Jul 03 08:31:50 PM PDT 24 |
| Peak memory | 641256 kb |
| Host | smart-7cd3ec72-deaa-496b-bccd-ad1b584cd37e |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1249740636 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.chip_sw_all_escalation_resets.1249740636 |
| Directory | /workspace/74.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/75.chip_sw_alert_handler_lpg_sleep_mode_alerts.3017556665 |
| Short name | T1010 |
| Test name | |
| Test status | |
| Simulation time | 3644800256 ps |
| CPU time | 413.58 seconds |
| Started | Jul 03 08:21:41 PM PDT 24 |
| Finished | Jul 03 08:28:35 PM PDT 24 |
| Peak memory | 648440 kb |
| Host | smart-1fb2fab8-434e-4dbb-92e4-a43025d62ca8 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3017556665 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3017556665 |
| Directory | /workspace/75.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/76.chip_sw_alert_handler_lpg_sleep_mode_alerts.3647730093 |
| Short name | T673 |
| Test name | |
| Test status | |
| Simulation time | 4497210698 ps |
| CPU time | 448.23 seconds |
| Started | Jul 03 08:22:21 PM PDT 24 |
| Finished | Jul 03 08:29:50 PM PDT 24 |
| Peak memory | 640156 kb |
| Host | smart-6aa7eaf1-bb5b-44d6-b6d2-9cfefee5108b |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3647730093 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3647730093 |
| Directory | /workspace/76.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/76.chip_sw_all_escalation_resets.1246777414 |
| Short name | T340 |
| Test name | |
| Test status | |
| Simulation time | 5670639888 ps |
| CPU time | 626.29 seconds |
| Started | Jul 03 08:21:00 PM PDT 24 |
| Finished | Jul 03 08:31:27 PM PDT 24 |
| Peak memory | 641080 kb |
| Host | smart-cbb6223a-c39b-45bf-9c38-f0a0b21c7bb2 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1246777414 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.chip_sw_all_escalation_resets.1246777414 |
| Directory | /workspace/76.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/77.chip_sw_alert_handler_lpg_sleep_mode_alerts.3694167897 |
| Short name | T356 |
| Test name | |
| Test status | |
| Simulation time | 4149497698 ps |
| CPU time | 401.96 seconds |
| Started | Jul 03 08:21:07 PM PDT 24 |
| Finished | Jul 03 08:27:49 PM PDT 24 |
| Peak memory | 641212 kb |
| Host | smart-991a2b83-7558-4690-81ef-2fc4462bd26f |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3694167897 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3694167897 |
| Directory | /workspace/77.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/77.chip_sw_all_escalation_resets.667735068 |
| Short name | T387 |
| Test name | |
| Test status | |
| Simulation time | 5926610990 ps |
| CPU time | 633.64 seconds |
| Started | Jul 03 08:22:06 PM PDT 24 |
| Finished | Jul 03 08:32:40 PM PDT 24 |
| Peak memory | 649784 kb |
| Host | smart-4b8dfb45-f1c9-443d-ae09-ca036d9febf9 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 667735068 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.chip_sw_all_escalation_resets.667735068 |
| Directory | /workspace/77.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/78.chip_sw_alert_handler_lpg_sleep_mode_alerts.379380604 |
| Short name | T729 |
| Test name | |
| Test status | |
| Simulation time | 3473083446 ps |
| CPU time | 359.97 seconds |
| Started | Jul 03 08:21:06 PM PDT 24 |
| Finished | Jul 03 08:27:07 PM PDT 24 |
| Peak memory | 648620 kb |
| Host | smart-badf2e0f-d003-4360-b3cd-1561dcea4029 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379380604 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.chip_s w_alert_handler_lpg_sleep_mode_alerts.379380604 |
| Directory | /workspace/78.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/78.chip_sw_all_escalation_resets.2578640198 |
| Short name | T664 |
| Test name | |
| Test status | |
| Simulation time | 4669506450 ps |
| CPU time | 548.61 seconds |
| Started | Jul 03 08:21:00 PM PDT 24 |
| Finished | Jul 03 08:30:10 PM PDT 24 |
| Peak memory | 649504 kb |
| Host | smart-62e81bf7-7102-477c-805c-ebb726e22651 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2578640198 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.chip_sw_all_escalation_resets.2578640198 |
| Directory | /workspace/78.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/79.chip_sw_alert_handler_lpg_sleep_mode_alerts.3037800856 |
| Short name | T1201 |
| Test name | |
| Test status | |
| Simulation time | 3540736440 ps |
| CPU time | 392.75 seconds |
| Started | Jul 03 08:25:02 PM PDT 24 |
| Finished | Jul 03 08:31:35 PM PDT 24 |
| Peak memory | 648344 kb |
| Host | smart-362dce7b-8d40-4c7c-b159-e5c39c4b2b68 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3037800856 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3037800856 |
| Directory | /workspace/79.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/79.chip_sw_all_escalation_resets.1419869990 |
| Short name | T659 |
| Test name | |
| Test status | |
| Simulation time | 4893217772 ps |
| CPU time | 554.92 seconds |
| Started | Jul 03 08:22:40 PM PDT 24 |
| Finished | Jul 03 08:31:55 PM PDT 24 |
| Peak memory | 641144 kb |
| Host | smart-b6fc432f-d2b0-477e-b2c7-65b6facff1e6 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1419869990 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.chip_sw_all_escalation_resets.1419869990 |
| Directory | /workspace/79.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/8.chip_sw_alert_handler_lpg_sleep_mode_alerts.2495886770 |
| Short name | T743 |
| Test name | |
| Test status | |
| Simulation time | 3879079144 ps |
| CPU time | 436.46 seconds |
| Started | Jul 03 08:16:03 PM PDT 24 |
| Finished | Jul 03 08:23:20 PM PDT 24 |
| Peak memory | 641220 kb |
| Host | smart-49d82b78-6888-4ae5-8f56-5cfcc21c8e93 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2495886770 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.chip_s w_alert_handler_lpg_sleep_mode_alerts.2495886770 |
| Directory | /workspace/8.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/8.chip_sw_all_escalation_resets.4118007791 |
| Short name | T217 |
| Test name | |
| Test status | |
| Simulation time | 4472139988 ps |
| CPU time | 542.87 seconds |
| Started | Jul 03 08:15:45 PM PDT 24 |
| Finished | Jul 03 08:24:49 PM PDT 24 |
| Peak memory | 649760 kb |
| Host | smart-33f217da-bab7-4ad2-b92b-b5ca0602f7c0 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 4118007791 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.chip_sw_all_escalation_resets.4118007791 |
| Directory | /workspace/8.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/8.chip_sw_csrng_edn_concurrency.4238093103 |
| Short name | T903 |
| Test name | |
| Test status | |
| Simulation time | 19565945376 ps |
| CPU time | 3636.45 seconds |
| Started | Jul 03 08:16:07 PM PDT 24 |
| Finished | Jul 03 09:16:44 PM PDT 24 |
| Peak memory | 608828 kb |
| Host | smart-5f58a2be-711c-4968-96c5-ff743de2ca09 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +accelerate_cold_power_up_time=3 +accelerate_r egulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4238093103 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 8.chip_sw_csrng_edn_concurrency.4238093103 |
| Directory | /workspace/8.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspace/coverage/default/8.chip_sw_lc_ctrl_transition.1518676308 |
| Short name | T922 |
| Test name | |
| Test status | |
| Simulation time | 10530177019 ps |
| CPU time | 1044.89 seconds |
| Started | Jul 03 08:16:43 PM PDT 24 |
| Finished | Jul 03 08:34:09 PM PDT 24 |
| Peak memory | 622648 kb |
| Host | smart-fc777c89-ab1d-4f62-aa0d-3d4849cc1891 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1518676308 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 8.chip_sw_lc_ctrl_transition.1518676308 |
| Directory | /workspace/8.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/8.chip_sw_uart_rand_baudrate.2563686242 |
| Short name | T1225 |
| Test name | |
| Test status | |
| Simulation time | 7993535056 ps |
| CPU time | 1423.1 seconds |
| Started | Jul 03 08:15:31 PM PDT 24 |
| Finished | Jul 03 08:39:16 PM PDT 24 |
| Peak memory | 620056 kb |
| Host | smart-863e648e-7d26-462a-a01d-031ae7ed0d56 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=2563686242 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.chip_sw_uart_rand_baudrate.2563686242 |
| Directory | /workspace/8.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/80.chip_sw_alert_handler_lpg_sleep_mode_alerts.1786304767 |
| Short name | T240 |
| Test name | |
| Test status | |
| Simulation time | 3750350536 ps |
| CPU time | 259.49 seconds |
| Started | Jul 03 08:19:59 PM PDT 24 |
| Finished | Jul 03 08:24:19 PM PDT 24 |
| Peak memory | 648388 kb |
| Host | smart-74afaa4b-f251-4a25-b685-1717e2748903 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1786304767 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1786304767 |
| Directory | /workspace/80.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/80.chip_sw_all_escalation_resets.3937762476 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 5454901620 ps |
| CPU time | 560.93 seconds |
| Started | Jul 03 08:20:44 PM PDT 24 |
| Finished | Jul 03 08:30:05 PM PDT 24 |
| Peak memory | 650144 kb |
| Host | smart-5b0c3af6-96d3-4f53-9df8-0e03e5794722 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3937762476 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.chip_sw_all_escalation_resets.3937762476 |
| Directory | /workspace/80.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/81.chip_sw_alert_handler_lpg_sleep_mode_alerts.3323194598 |
| Short name | T283 |
| Test name | |
| Test status | |
| Simulation time | 4388451336 ps |
| CPU time | 415.02 seconds |
| Started | Jul 03 08:20:32 PM PDT 24 |
| Finished | Jul 03 08:27:28 PM PDT 24 |
| Peak memory | 648732 kb |
| Host | smart-ed529b2b-8ec4-4405-aa25-720edd6de214 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3323194598 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3323194598 |
| Directory | /workspace/81.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/81.chip_sw_all_escalation_resets.4246134771 |
| Short name | T756 |
| Test name | |
| Test status | |
| Simulation time | 6209631800 ps |
| CPU time | 527.21 seconds |
| Started | Jul 03 08:20:31 PM PDT 24 |
| Finished | Jul 03 08:29:19 PM PDT 24 |
| Peak memory | 649452 kb |
| Host | smart-b930b008-b3f9-4e70-9e88-39994b259ee8 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 4246134771 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.chip_sw_all_escalation_resets.4246134771 |
| Directory | /workspace/81.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/82.chip_sw_alert_handler_lpg_sleep_mode_alerts.3611044173 |
| Short name | T658 |
| Test name | |
| Test status | |
| Simulation time | 3722778172 ps |
| CPU time | 383.98 seconds |
| Started | Jul 03 08:21:41 PM PDT 24 |
| Finished | Jul 03 08:28:06 PM PDT 24 |
| Peak memory | 639892 kb |
| Host | smart-b5805230-b4c2-466f-b4df-05fd3f109f1e |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3611044173 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3611044173 |
| Directory | /workspace/82.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/82.chip_sw_all_escalation_resets.4189500396 |
| Short name | T758 |
| Test name | |
| Test status | |
| Simulation time | 5088988812 ps |
| CPU time | 649.03 seconds |
| Started | Jul 03 08:21:51 PM PDT 24 |
| Finished | Jul 03 08:32:41 PM PDT 24 |
| Peak memory | 649624 kb |
| Host | smart-a709d5f9-de3f-4600-b710-176a5235e048 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 4189500396 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.chip_sw_all_escalation_resets.4189500396 |
| Directory | /workspace/82.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/83.chip_sw_alert_handler_lpg_sleep_mode_alerts.3894629444 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 3974725970 ps |
| CPU time | 355.8 seconds |
| Started | Jul 03 08:20:29 PM PDT 24 |
| Finished | Jul 03 08:26:26 PM PDT 24 |
| Peak memory | 641240 kb |
| Host | smart-7c2e39b2-0289-476e-9b9b-1f50d15945f3 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3894629444 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3894629444 |
| Directory | /workspace/83.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/83.chip_sw_all_escalation_resets.4013238842 |
| Short name | T669 |
| Test name | |
| Test status | |
| Simulation time | 6043321672 ps |
| CPU time | 596.49 seconds |
| Started | Jul 03 08:21:06 PM PDT 24 |
| Finished | Jul 03 08:31:03 PM PDT 24 |
| Peak memory | 649500 kb |
| Host | smart-092125c9-4650-4384-9a70-665a965544f1 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 4013238842 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.chip_sw_all_escalation_resets.4013238842 |
| Directory | /workspace/83.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/84.chip_sw_alert_handler_lpg_sleep_mode_alerts.2282719994 |
| Short name | T718 |
| Test name | |
| Test status | |
| Simulation time | 3501731848 ps |
| CPU time | 341.19 seconds |
| Started | Jul 03 08:21:26 PM PDT 24 |
| Finished | Jul 03 08:27:08 PM PDT 24 |
| Peak memory | 648428 kb |
| Host | smart-6a31111b-7f00-40fe-836b-3f310eda4bf6 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282719994 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2282719994 |
| Directory | /workspace/84.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/84.chip_sw_all_escalation_resets.3359069263 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 5166292306 ps |
| CPU time | 633.91 seconds |
| Started | Jul 03 08:20:59 PM PDT 24 |
| Finished | Jul 03 08:31:34 PM PDT 24 |
| Peak memory | 623456 kb |
| Host | smart-76b42934-6258-4854-b623-99d12da0a6de |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3359069263 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.chip_sw_all_escalation_resets.3359069263 |
| Directory | /workspace/84.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/85.chip_sw_alert_handler_lpg_sleep_mode_alerts.1011257239 |
| Short name | T363 |
| Test name | |
| Test status | |
| Simulation time | 3585960376 ps |
| CPU time | 334.08 seconds |
| Started | Jul 03 08:21:38 PM PDT 24 |
| Finished | Jul 03 08:27:13 PM PDT 24 |
| Peak memory | 648276 kb |
| Host | smart-24f8f64b-a4b9-4a1b-9793-0513399149cd |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1011257239 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1011257239 |
| Directory | /workspace/85.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/85.chip_sw_all_escalation_resets.3089512249 |
| Short name | T757 |
| Test name | |
| Test status | |
| Simulation time | 5940145700 ps |
| CPU time | 663.57 seconds |
| Started | Jul 03 08:22:18 PM PDT 24 |
| Finished | Jul 03 08:33:23 PM PDT 24 |
| Peak memory | 649500 kb |
| Host | smart-852c67d1-b3df-49ac-94db-6e287ebebc2b |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3089512249 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.chip_sw_all_escalation_resets.3089512249 |
| Directory | /workspace/85.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/86.chip_sw_alert_handler_lpg_sleep_mode_alerts.3963182751 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 3019469752 ps |
| CPU time | 338.28 seconds |
| Started | Jul 03 08:22:15 PM PDT 24 |
| Finished | Jul 03 08:27:54 PM PDT 24 |
| Peak memory | 649012 kb |
| Host | smart-74325c8c-1150-4108-a288-42a48ceebf8d |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3963182751 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3963182751 |
| Directory | /workspace/86.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/86.chip_sw_all_escalation_resets.1604247412 |
| Short name | T377 |
| Test name | |
| Test status | |
| Simulation time | 5084634684 ps |
| CPU time | 599.99 seconds |
| Started | Jul 03 08:20:58 PM PDT 24 |
| Finished | Jul 03 08:30:59 PM PDT 24 |
| Peak memory | 649592 kb |
| Host | smart-17ff2d57-ef3d-4ed9-8eb9-741b7db18ed1 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1604247412 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.chip_sw_all_escalation_resets.1604247412 |
| Directory | /workspace/86.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/87.chip_sw_alert_handler_lpg_sleep_mode_alerts.294715272 |
| Short name | T1177 |
| Test name | |
| Test status | |
| Simulation time | 3314857504 ps |
| CPU time | 399.26 seconds |
| Started | Jul 03 08:22:52 PM PDT 24 |
| Finished | Jul 03 08:29:33 PM PDT 24 |
| Peak memory | 641176 kb |
| Host | smart-8ac12829-b8f4-4556-88b4-9c1143c02a38 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=294715272 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.chip_s w_alert_handler_lpg_sleep_mode_alerts.294715272 |
| Directory | /workspace/87.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/87.chip_sw_all_escalation_resets.4015758621 |
| Short name | T681 |
| Test name | |
| Test status | |
| Simulation time | 5369096200 ps |
| CPU time | 529.3 seconds |
| Started | Jul 03 08:22:47 PM PDT 24 |
| Finished | Jul 03 08:31:37 PM PDT 24 |
| Peak memory | 641088 kb |
| Host | smart-25789a4d-2df9-4172-ac37-23e0aa97da7f |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 4015758621 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.chip_sw_all_escalation_resets.4015758621 |
| Directory | /workspace/87.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/88.chip_sw_alert_handler_lpg_sleep_mode_alerts.2494532570 |
| Short name | T708 |
| Test name | |
| Test status | |
| Simulation time | 3790683936 ps |
| CPU time | 447.98 seconds |
| Started | Jul 03 08:21:37 PM PDT 24 |
| Finished | Jul 03 08:29:05 PM PDT 24 |
| Peak memory | 648448 kb |
| Host | smart-960418f7-aabe-4244-9b02-0b0ca1f964dc |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494532570 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2494532570 |
| Directory | /workspace/88.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/88.chip_sw_all_escalation_resets.2164273714 |
| Short name | T704 |
| Test name | |
| Test status | |
| Simulation time | 5216459240 ps |
| CPU time | 603.16 seconds |
| Started | Jul 03 08:21:00 PM PDT 24 |
| Finished | Jul 03 08:31:04 PM PDT 24 |
| Peak memory | 649700 kb |
| Host | smart-bf70318f-c3df-42f3-b47b-47239525727b |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2164273714 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.chip_sw_all_escalation_resets.2164273714 |
| Directory | /workspace/88.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/9.chip_sw_alert_handler_lpg_sleep_mode_alerts.2973192991 |
| Short name | T613 |
| Test name | |
| Test status | |
| Simulation time | 3505141128 ps |
| CPU time | 434.59 seconds |
| Started | Jul 03 08:17:04 PM PDT 24 |
| Finished | Jul 03 08:24:20 PM PDT 24 |
| Peak memory | 648648 kb |
| Host | smart-2f978043-71fe-4891-a122-b33557ebd0c6 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2973192991 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.chip_s w_alert_handler_lpg_sleep_mode_alerts.2973192991 |
| Directory | /workspace/9.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/9.chip_sw_all_escalation_resets.4041524372 |
| Short name | T665 |
| Test name | |
| Test status | |
| Simulation time | 6156197700 ps |
| CPU time | 534.46 seconds |
| Started | Jul 03 08:16:29 PM PDT 24 |
| Finished | Jul 03 08:25:25 PM PDT 24 |
| Peak memory | 641136 kb |
| Host | smart-3584d251-290b-430a-a6b5-b647f75335a6 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 4041524372 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.chip_sw_all_escalation_resets.4041524372 |
| Directory | /workspace/9.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/9.chip_sw_csrng_edn_concurrency.7209040 |
| Short name | T1118 |
| Test name | |
| Test status | |
| Simulation time | 18068511760 ps |
| CPU time | 3619.49 seconds |
| Started | Jul 03 08:17:07 PM PDT 24 |
| Finished | Jul 03 09:17:28 PM PDT 24 |
| Peak memory | 608496 kb |
| Host | smart-6613ec9d-b8d6-45e0-9b06-d980b4a075bd |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +accelerate_cold_power_up_time=3 +accelerate_r egulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7209040 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 9.chip_sw_csrng_edn_concurrency.7209040 |
| Directory | /workspace/9.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspace/coverage/default/9.chip_sw_lc_ctrl_transition.582877454 |
| Short name | T942 |
| Test name | |
| Test status | |
| Simulation time | 9937550445 ps |
| CPU time | 932.33 seconds |
| Started | Jul 03 08:16:19 PM PDT 24 |
| Finished | Jul 03 08:31:53 PM PDT 24 |
| Peak memory | 622248 kb |
| Host | smart-dfc359df-a9ad-470c-8111-287f7d4c6f2b |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582877454 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul t.vdb -cm_log /dev/null -cm_name 9.chip_sw_lc_ctrl_transition.582877454 |
| Directory | /workspace/9.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/9.chip_sw_uart_rand_baudrate.2848001297 |
| Short name | T833 |
| Test name | |
| Test status | |
| Simulation time | 3747674314 ps |
| CPU time | 452.16 seconds |
| Started | Jul 03 08:14:56 PM PDT 24 |
| Finished | Jul 03 08:22:29 PM PDT 24 |
| Peak memory | 620064 kb |
| Host | smart-eb88eb4c-a82d-4ac3-b2a8-5669331dc9b9 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=2848001297 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.chip_sw_uart_rand_baudrate.2848001297 |
| Directory | /workspace/9.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/90.chip_sw_all_escalation_resets.2239504033 |
| Short name | T759 |
| Test name | |
| Test status | |
| Simulation time | 5482003468 ps |
| CPU time | 415.29 seconds |
| Started | Jul 03 08:21:24 PM PDT 24 |
| Finished | Jul 03 08:28:20 PM PDT 24 |
| Peak memory | 641472 kb |
| Host | smart-afd29778-acc1-4066-bb95-cd4cab469547 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2239504033 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.chip_sw_all_escalation_resets.2239504033 |
| Directory | /workspace/90.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/92.chip_sw_all_escalation_resets.1561064898 |
| Short name | T339 |
| Test name | |
| Test status | |
| Simulation time | 6398217660 ps |
| CPU time | 641.34 seconds |
| Started | Jul 03 08:22:20 PM PDT 24 |
| Finished | Jul 03 08:33:02 PM PDT 24 |
| Peak memory | 641108 kb |
| Host | smart-9f62a5e1-8268-4eae-a76e-57e34d16a29f |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1561064898 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.chip_sw_all_escalation_resets.1561064898 |
| Directory | /workspace/92.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/93.chip_sw_all_escalation_resets.744150566 |
| Short name | T342 |
| Test name | |
| Test status | |
| Simulation time | 6423615276 ps |
| CPU time | 500.34 seconds |
| Started | Jul 03 08:21:35 PM PDT 24 |
| Finished | Jul 03 08:29:56 PM PDT 24 |
| Peak memory | 641472 kb |
| Host | smart-39ec99e0-495a-4151-8e7b-574a4319c128 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 744150566 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.chip_sw_all_escalation_resets.744150566 |
| Directory | /workspace/93.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/94.chip_sw_all_escalation_resets.2270059844 |
| Short name | T297 |
| Test name | |
| Test status | |
| Simulation time | 4944220404 ps |
| CPU time | 621.65 seconds |
| Started | Jul 03 08:23:06 PM PDT 24 |
| Finished | Jul 03 08:33:28 PM PDT 24 |
| Peak memory | 649772 kb |
| Host | smart-e8598f80-fe12-428f-a0c4-752e6fea6c27 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2270059844 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.chip_sw_all_escalation_resets.2270059844 |
| Directory | /workspace/94.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/95.chip_sw_all_escalation_resets.840540658 |
| Short name | T740 |
| Test name | |
| Test status | |
| Simulation time | 5335810154 ps |
| CPU time | 462.14 seconds |
| Started | Jul 03 08:23:39 PM PDT 24 |
| Finished | Jul 03 08:31:21 PM PDT 24 |
| Peak memory | 649560 kb |
| Host | smart-b2aeb0a7-0729-4686-8dc1-4fed2486d59b |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 840540658 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.chip_sw_all_escalation_resets.840540658 |
| Directory | /workspace/95.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/96.chip_sw_all_escalation_resets.253494026 |
| Short name | T688 |
| Test name | |
| Test status | |
| Simulation time | 5530884920 ps |
| CPU time | 516.75 seconds |
| Started | Jul 03 08:23:52 PM PDT 24 |
| Finished | Jul 03 08:32:30 PM PDT 24 |
| Peak memory | 649536 kb |
| Host | smart-68634cd4-31b0-4e9a-84d5-5c897e0a2c11 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 253494026 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.chip_sw_all_escalation_resets.253494026 |
| Directory | /workspace/96.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/97.chip_sw_all_escalation_resets.4257410130 |
| Short name | T292 |
| Test name | |
| Test status | |
| Simulation time | 4410312888 ps |
| CPU time | 644.8 seconds |
| Started | Jul 03 08:22:38 PM PDT 24 |
| Finished | Jul 03 08:33:23 PM PDT 24 |
| Peak memory | 644236 kb |
| Host | smart-edfc9af8-0ef6-42d3-a7d5-631ee3887f3c |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 4257410130 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.chip_sw_all_escalation_resets.4257410130 |
| Directory | /workspace/97.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/98.chip_sw_all_escalation_resets.427468637 |
| Short name | T964 |
| Test name | |
| Test status | |
| Simulation time | 6084701940 ps |
| CPU time | 582.51 seconds |
| Started | Jul 03 08:22:06 PM PDT 24 |
| Finished | Jul 03 08:31:49 PM PDT 24 |
| Peak memory | 623368 kb |
| Host | smart-6d69cb9a-98ce-4bcd-a7d3-7a91b2fa44bd |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 427468637 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.chip_sw_all_escalation_resets.427468637 |
| Directory | /workspace/98.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/99.chip_sw_all_escalation_resets.3604928844 |
| Short name | T745 |
| Test name | |
| Test status | |
| Simulation time | 5743745784 ps |
| CPU time | 660 seconds |
| Started | Jul 03 08:22:26 PM PDT 24 |
| Finished | Jul 03 08:33:27 PM PDT 24 |
| Peak memory | 649672 kb |
| Host | smart-d5935683-2bda-414b-8be0-a55f84551345 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3604928844 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.chip_sw_all_escalation_resets.3604928844 |
| Directory | /workspace/99.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/2.chip_padctrl_attributes.960370577 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 5121814232 ps |
| CPU time | 241.27 seconds |
| Started | Jul 03 08:15:21 PM PDT 24 |
| Finished | Jul 03 08:19:23 PM PDT 24 |
| Peak memory | 640964 kb |
| Host | smart-d9ba0033-edbf-49a2-b289-f4a7dbd081aa |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=960370577 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TES T_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/n ull -cm_name 2.chip_padctrl_attributes.960370577 |
| Directory | /workspace/2.chip_padctrl_attributes/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/4.chip_padctrl_attributes.3047392244 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 4160849810 ps |
| CPU time | 198.17 seconds |
| Started | Jul 03 08:15:05 PM PDT 24 |
| Finished | Jul 03 08:18:24 PM PDT 24 |
| Peak memory | 642736 kb |
| Host | smart-7805cbf7-519c-4dd5-b96e-2b96e82538ef |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3047392244 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/ null -cm_name 4.chip_padctrl_attributes.3047392244 |
| Directory | /workspace/4.chip_padctrl_attributes/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/5.chip_padctrl_attributes.4159115290 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 4855770448 ps |
| CPU time | 235.68 seconds |
| Started | Jul 03 08:15:05 PM PDT 24 |
| Finished | Jul 03 08:19:01 PM PDT 24 |
| Peak memory | 641096 kb |
| Host | smart-042c7855-96ca-4b06-a1a8-c212ac9d555a |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4159115290 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/ null -cm_name 5.chip_padctrl_attributes.4159115290 |
| Directory | /workspace/5.chip_padctrl_attributes/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/6.chip_padctrl_attributes.4081546994 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 5820225464 ps |
| CPU time | 300.05 seconds |
| Started | Jul 03 08:15:11 PM PDT 24 |
| Finished | Jul 03 08:20:12 PM PDT 24 |
| Peak memory | 649156 kb |
| Host | smart-41b7b500-82a1-4a8d-94e7-96805358a115 |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4081546994 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/ null -cm_name 6.chip_padctrl_attributes.4081546994 |
| Directory | /workspace/6.chip_padctrl_attributes/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/7.chip_padctrl_attributes.2456845028 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 5257495710 ps |
| CPU time | 216.7 seconds |
| Started | Jul 03 08:15:06 PM PDT 24 |
| Finished | Jul 03 08:18:43 PM PDT 24 |
| Peak memory | 657556 kb |
| Host | smart-1ca937f3-9e95-4b78-b7fa-1e9d1187ad88 |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2456845028 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/ null -cm_name 7.chip_padctrl_attributes.2456845028 |
| Directory | /workspace/7.chip_padctrl_attributes/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/8.chip_padctrl_attributes.622221941 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 5277469376 ps |
| CPU time | 221.95 seconds |
| Started | Jul 03 08:15:18 PM PDT 24 |
| Finished | Jul 03 08:19:01 PM PDT 24 |
| Peak memory | 641000 kb |
| Host | smart-ec4ae632-a8e4-43dc-a80a-b2ca0d1c9a74 |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=622221941 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TES T_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/n ull -cm_name 8.chip_padctrl_attributes.622221941 |
| Directory | /workspace/8.chip_padctrl_attributes/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/9.chip_padctrl_attributes.1566138032 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 4142155695 ps |
| CPU time | 287.12 seconds |
| Started | Jul 03 08:15:21 PM PDT 24 |
| Finished | Jul 03 08:20:10 PM PDT 24 |
| Peak memory | 640952 kb |
| Host | smart-6bae6a95-5419-4bf8-9f09-4d3cfec317a1 |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566138032 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/ null -cm_name 9.chip_padctrl_attributes.1566138032 |
| Directory | /workspace/9.chip_padctrl_attributes/latest |
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