| T734 |
/workspace/coverage/default/10.chip_sw_all_escalation_resets.3299355694 |
|
|
Jul 03 08:15:11 PM PDT 24 |
Jul 03 08:27:42 PM PDT 24 |
6561649642 ps |
| T750 |
/workspace/coverage/default/33.chip_sw_alert_handler_lpg_sleep_mode_alerts.1022019124 |
|
|
Jul 03 08:19:51 PM PDT 24 |
Jul 03 08:26:46 PM PDT 24 |
3345939560 ps |
| T1133 |
/workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_meas.1474017937 |
|
|
Jul 03 07:56:35 PM PDT 24 |
Jul 03 09:00:01 PM PDT 24 |
14968480000 ps |
| T316 |
/workspace/coverage/default/2.chip_sw_i2c_host_tx_rx_idx1.797466986 |
|
|
Jul 03 08:05:28 PM PDT 24 |
Jul 03 08:19:04 PM PDT 24 |
5337739720 ps |
| T1134 |
/workspace/coverage/default/23.chip_sw_all_escalation_resets.3766579903 |
|
|
Jul 03 08:17:28 PM PDT 24 |
Jul 03 08:30:01 PM PDT 24 |
4680860672 ps |
| T1135 |
/workspace/coverage/default/2.chip_sw_pwrmgr_sysrst_ctrl_reset.3729080824 |
|
|
Jul 03 08:06:21 PM PDT 24 |
Jul 03 08:32:21 PM PDT 24 |
9110846160 ps |
| T1136 |
/workspace/coverage/default/24.chip_sw_all_escalation_resets.1113099024 |
|
|
Jul 03 08:17:10 PM PDT 24 |
Jul 03 08:26:30 PM PDT 24 |
5553108488 ps |
| T1137 |
/workspace/coverage/default/17.chip_sw_uart_rand_baudrate.1115962199 |
|
|
Jul 03 08:19:15 PM PDT 24 |
Jul 03 08:59:42 PM PDT 24 |
12765881736 ps |
| T1138 |
/workspace/coverage/default/0.chip_sw_pwrmgr_sysrst_ctrl_reset.57916548 |
|
|
Jul 03 07:49:46 PM PDT 24 |
Jul 03 08:14:02 PM PDT 24 |
7814345805 ps |
| T714 |
/workspace/coverage/default/40.chip_sw_all_escalation_resets.1041883900 |
|
|
Jul 03 08:18:45 PM PDT 24 |
Jul 03 08:29:52 PM PDT 24 |
5006804900 ps |
| T1139 |
/workspace/coverage/default/2.chip_sw_pwrmgr_sleep_power_glitch_reset.3504468767 |
|
|
Jul 03 08:06:29 PM PDT 24 |
Jul 03 08:16:10 PM PDT 24 |
5816519352 ps |
| T1140 |
/workspace/coverage/default/0.chip_sw_alert_handler_escalation.2472410980 |
|
|
Jul 03 07:49:46 PM PDT 24 |
Jul 03 07:58:28 PM PDT 24 |
4865427886 ps |
| T1141 |
/workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_prod.552170286 |
|
|
Jul 03 07:48:05 PM PDT 24 |
Jul 03 08:10:54 PM PDT 24 |
7096395070 ps |
| T622 |
/workspace/coverage/default/0.chip_sw_rv_dm_access_after_escalation_reset.2482599419 |
|
|
Jul 03 07:50:13 PM PDT 24 |
Jul 03 08:00:22 PM PDT 24 |
4610701976 ps |
| T692 |
/workspace/coverage/default/43.chip_sw_all_escalation_resets.1000423900 |
|
|
Jul 03 08:20:06 PM PDT 24 |
Jul 03 08:28:43 PM PDT 24 |
5759893524 ps |
| T1142 |
/workspace/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en.2398250445 |
|
|
Jul 03 07:49:55 PM PDT 24 |
Jul 03 07:55:17 PM PDT 24 |
2756617168 ps |
| T1143 |
/workspace/coverage/default/2.chip_sw_rv_core_ibex_rnd.606853497 |
|
|
Jul 03 08:08:17 PM PDT 24 |
Jul 03 08:26:21 PM PDT 24 |
5299438712 ps |
| T1144 |
/workspace/coverage/default/1.chip_sw_pwrmgr_usb_clk_disabled_when_active.2415888001 |
|
|
Jul 03 08:02:42 PM PDT 24 |
Jul 03 08:10:19 PM PDT 24 |
4807607082 ps |
| T1145 |
/workspace/coverage/default/2.chip_sw_entropy_src_smoketest.628653044 |
|
|
Jul 03 08:13:26 PM PDT 24 |
Jul 03 08:23:41 PM PDT 24 |
3414508380 ps |
| T261 |
/workspace/coverage/default/2.chip_sw_rstmgr_cpu_info.2305336270 |
|
|
Jul 03 08:07:03 PM PDT 24 |
Jul 03 08:15:44 PM PDT 24 |
5880060200 ps |
| T1146 |
/workspace/coverage/default/0.chip_sw_alert_handler_ping_ok.3058772659 |
|
|
Jul 03 07:51:27 PM PDT 24 |
Jul 03 08:15:33 PM PDT 24 |
8247163024 ps |
| T1147 |
/workspace/coverage/default/1.chip_sw_hmac_smoketest.4282590294 |
|
|
Jul 03 08:04:00 PM PDT 24 |
Jul 03 08:08:42 PM PDT 24 |
2762637808 ps |
| T1148 |
/workspace/coverage/default/4.chip_tap_straps_dev.3307618063 |
|
|
Jul 03 08:12:56 PM PDT 24 |
Jul 03 08:26:31 PM PDT 24 |
9511700061 ps |
| T1149 |
/workspace/coverage/default/2.chip_sw_uart_smoketest.3981084070 |
|
|
Jul 03 08:12:52 PM PDT 24 |
Jul 03 08:17:46 PM PDT 24 |
2635737592 ps |
| T1150 |
/workspace/coverage/default/0.chip_sw_sysrst_ctrl_outputs.804993117 |
|
|
Jul 03 07:51:13 PM PDT 24 |
Jul 03 07:58:59 PM PDT 24 |
4055003752 ps |
| T1151 |
/workspace/coverage/default/0.chip_sw_uart_tx_rx_idx2.4107496202 |
|
|
Jul 03 07:48:03 PM PDT 24 |
Jul 03 07:59:32 PM PDT 24 |
4298719312 ps |
| T1152 |
/workspace/coverage/default/0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.2824249596 |
|
|
Jul 03 07:52:12 PM PDT 24 |
Jul 03 07:59:52 PM PDT 24 |
3594027018 ps |
| T1153 |
/workspace/coverage/default/0.chip_sw_power_idle_load.977118545 |
|
|
Jul 03 07:57:44 PM PDT 24 |
Jul 03 08:12:38 PM PDT 24 |
4240606806 ps |
| T1154 |
/workspace/coverage/default/2.chip_sw_rstmgr_rst_cnsty_escalation.4007100583 |
|
|
Jul 03 08:05:43 PM PDT 24 |
Jul 03 08:18:51 PM PDT 24 |
4972639814 ps |
| T100 |
/workspace/coverage/default/63.chip_sw_alert_handler_lpg_sleep_mode_alerts.1146455917 |
|
|
Jul 03 08:20:05 PM PDT 24 |
Jul 03 08:26:06 PM PDT 24 |
3724425454 ps |
| T1155 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.201212407 |
|
|
Jul 03 07:55:17 PM PDT 24 |
Jul 03 08:53:40 PM PDT 24 |
14866830486 ps |
| T1156 |
/workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_dev.975580973 |
|
|
Jul 03 07:54:32 PM PDT 24 |
Jul 03 08:17:48 PM PDT 24 |
8435511916 ps |
| T1157 |
/workspace/coverage/default/0.chip_sw_edn_entropy_reqs_jitter.472075 |
|
|
Jul 03 07:51:10 PM PDT 24 |
Jul 03 08:05:17 PM PDT 24 |
4897488256 ps |
| T1158 |
/workspace/coverage/default/1.chip_sw_sram_ctrl_smoketest.2861893840 |
|
|
Jul 03 08:04:47 PM PDT 24 |
Jul 03 08:08:18 PM PDT 24 |
2884436618 ps |
| T16 |
/workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_wake_ups.315057283 |
|
|
Jul 03 07:52:25 PM PDT 24 |
Jul 03 08:30:09 PM PDT 24 |
22724126220 ps |
| T1159 |
/workspace/coverage/default/20.chip_sw_alert_handler_lpg_sleep_mode_alerts.3707089887 |
|
|
Jul 03 08:19:21 PM PDT 24 |
Jul 03 08:26:37 PM PDT 24 |
4017295482 ps |
| T1160 |
/workspace/coverage/default/1.chip_sw_aes_idle.35159254 |
|
|
Jul 03 07:58:13 PM PDT 24 |
Jul 03 08:02:18 PM PDT 24 |
3262348508 ps |
| T1161 |
/workspace/coverage/default/2.chip_sw_hmac_smoketest.2199868914 |
|
|
Jul 03 08:12:36 PM PDT 24 |
Jul 03 08:17:54 PM PDT 24 |
3505792712 ps |
| T741 |
/workspace/coverage/default/24.chip_sw_alert_handler_lpg_sleep_mode_alerts.3416966360 |
|
|
Jul 03 08:17:34 PM PDT 24 |
Jul 03 08:23:37 PM PDT 24 |
3552234288 ps |
| T1162 |
/workspace/coverage/default/52.chip_sw_alert_handler_lpg_sleep_mode_alerts.3671468685 |
|
|
Jul 03 08:21:09 PM PDT 24 |
Jul 03 08:28:15 PM PDT 24 |
3554028862 ps |
| T1163 |
/workspace/coverage/default/0.chip_sw_edn_auto_mode.3587803513 |
|
|
Jul 03 07:48:42 PM PDT 24 |
Jul 03 08:15:29 PM PDT 24 |
5891093370 ps |
| T1164 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.1223610677 |
|
|
Jul 03 08:00:52 PM PDT 24 |
Jul 03 09:40:15 PM PDT 24 |
24457671318 ps |
| T715 |
/workspace/coverage/default/68.chip_sw_all_escalation_resets.3271400225 |
|
|
Jul 03 08:22:47 PM PDT 24 |
Jul 03 08:31:11 PM PDT 24 |
5113045058 ps |
| T1165 |
/workspace/coverage/default/2.chip_sw_clkmgr_off_hmac_trans.2758948551 |
|
|
Jul 03 08:09:59 PM PDT 24 |
Jul 03 08:18:55 PM PDT 24 |
3780121360 ps |
| T368 |
/workspace/coverage/default/1.chip_sw_i2c_host_tx_rx.3273038908 |
|
|
Jul 03 07:53:30 PM PDT 24 |
Jul 03 08:06:03 PM PDT 24 |
5321620096 ps |
| T1166 |
/workspace/coverage/default/2.chip_sw_otbn_randomness.327738011 |
|
|
Jul 03 08:06:59 PM PDT 24 |
Jul 03 08:25:24 PM PDT 24 |
5844886492 ps |
| T1167 |
/workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.1722538954 |
|
|
Jul 03 07:58:38 PM PDT 24 |
Jul 03 08:04:32 PM PDT 24 |
7949592624 ps |
| T1168 |
/workspace/coverage/default/1.chip_sw_lc_ctrl_transition.3091464478 |
|
|
Jul 03 07:58:21 PM PDT 24 |
Jul 03 08:04:50 PM PDT 24 |
4769508535 ps |
| T1169 |
/workspace/coverage/default/1.chip_tap_straps_prod.4252612691 |
|
|
Jul 03 08:00:32 PM PDT 24 |
Jul 03 08:18:19 PM PDT 24 |
8703245018 ps |
| T1170 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.2127155510 |
|
|
Jul 03 07:57:13 PM PDT 24 |
Jul 03 08:45:52 PM PDT 24 |
11084953706 ps |
| T1171 |
/workspace/coverage/default/64.chip_sw_all_escalation_resets.3430948841 |
|
|
Jul 03 08:21:20 PM PDT 24 |
Jul 03 08:30:54 PM PDT 24 |
4090760208 ps |
| T1172 |
/workspace/coverage/default/1.chip_sw_pwrmgr_sleep_wake_5_bug.3855509487 |
|
|
Jul 03 08:01:22 PM PDT 24 |
Jul 03 08:12:32 PM PDT 24 |
6586375976 ps |
| T239 |
/workspace/coverage/default/2.chip_sw_lc_walkthrough_dev.2640808229 |
|
|
Jul 03 08:06:12 PM PDT 24 |
Jul 03 09:30:11 PM PDT 24 |
47572120770 ps |
| T1173 |
/workspace/coverage/default/1.chip_sw_pwrmgr_sysrst_ctrl_reset.4005336073 |
|
|
Jul 03 07:55:03 PM PDT 24 |
Jul 03 08:15:02 PM PDT 24 |
6768525804 ps |
| T688 |
/workspace/coverage/default/96.chip_sw_all_escalation_resets.253494026 |
|
|
Jul 03 08:23:52 PM PDT 24 |
Jul 03 08:32:30 PM PDT 24 |
5530884920 ps |
| T1174 |
/workspace/coverage/default/1.chip_sw_lc_walkthrough_prod.1253049091 |
|
|
Jul 03 07:55:37 PM PDT 24 |
Jul 03 09:26:34 PM PDT 24 |
50313755797 ps |
| T1175 |
/workspace/coverage/default/2.chip_sw_uart_tx_rx_idx1.3322920181 |
|
|
Jul 03 08:06:22 PM PDT 24 |
Jul 03 08:17:34 PM PDT 24 |
4296374418 ps |
| T86 |
/workspace/coverage/default/0.chip_sw_usbdev_pullup.3523587976 |
|
|
Jul 03 07:47:01 PM PDT 24 |
Jul 03 07:52:03 PM PDT 24 |
3199095594 ps |
| T1176 |
/workspace/coverage/default/0.chip_sw_otbn_smoketest.2663959166 |
|
|
Jul 03 07:54:39 PM PDT 24 |
Jul 03 08:23:14 PM PDT 24 |
6482536810 ps |
| T1177 |
/workspace/coverage/default/87.chip_sw_alert_handler_lpg_sleep_mode_alerts.294715272 |
|
|
Jul 03 08:22:52 PM PDT 24 |
Jul 03 08:29:33 PM PDT 24 |
3314857504 ps |
| T1178 |
/workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_meas.1657535336 |
|
|
Jul 03 08:07:58 PM PDT 24 |
Jul 03 09:02:36 PM PDT 24 |
15073708134 ps |
| T1179 |
/workspace/coverage/default/2.chip_sw_kmac_smoketest.4212956707 |
|
|
Jul 03 08:11:53 PM PDT 24 |
Jul 03 08:17:18 PM PDT 24 |
2871300120 ps |
| T751 |
/workspace/coverage/default/4.chip_sw_alert_handler_lpg_sleep_mode_alerts.2067720168 |
|
|
Jul 03 08:13:40 PM PDT 24 |
Jul 03 08:19:24 PM PDT 24 |
3507439288 ps |
| T1180 |
/workspace/coverage/default/2.chip_sw_ast_clk_outputs.1047272938 |
|
|
Jul 03 08:09:53 PM PDT 24 |
Jul 03 08:29:09 PM PDT 24 |
8214323928 ps |
| T1181 |
/workspace/coverage/default/1.chip_sw_otbn_mem_scramble.1387272494 |
|
|
Jul 03 07:55:42 PM PDT 24 |
Jul 03 08:03:53 PM PDT 24 |
3743015382 ps |
| T1182 |
/workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_rma.2467391190 |
|
|
Jul 03 08:05:37 PM PDT 24 |
Jul 03 08:27:13 PM PDT 24 |
8465608052 ps |
| T1183 |
/workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_por_reset.1385821789 |
|
|
Jul 03 07:55:02 PM PDT 24 |
Jul 03 08:08:28 PM PDT 24 |
8309551186 ps |
| T1184 |
/workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_no_scramble.41442902 |
|
|
Jul 03 07:50:04 PM PDT 24 |
Jul 03 08:03:10 PM PDT 24 |
6468421780 ps |
| T1185 |
/workspace/coverage/default/1.chip_sw_flash_init_reduced_freq.1362364568 |
|
|
Jul 03 08:02:14 PM PDT 24 |
Jul 03 08:35:06 PM PDT 24 |
21484510362 ps |
| T1186 |
/workspace/coverage/default/0.chip_sw_rstmgr_smoketest.967268543 |
|
|
Jul 03 07:51:34 PM PDT 24 |
Jul 03 07:55:50 PM PDT 24 |
2445399688 ps |
| T1187 |
/workspace/coverage/default/0.chip_sw_sram_ctrl_smoketest.3507689769 |
|
|
Jul 03 07:52:18 PM PDT 24 |
Jul 03 07:55:03 PM PDT 24 |
2947433520 ps |
| T1188 |
/workspace/coverage/default/2.chip_sw_rv_plic_smoketest.726280024 |
|
|
Jul 03 08:12:29 PM PDT 24 |
Jul 03 08:18:07 PM PDT 24 |
2810079246 ps |
| T1189 |
/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx2.2143240600 |
|
|
Jul 03 07:51:03 PM PDT 24 |
Jul 03 08:06:35 PM PDT 24 |
5076152128 ps |
| T1190 |
/workspace/coverage/default/1.rom_e2e_asm_init_test_unlocked0.2738206444 |
|
|
Jul 03 08:06:35 PM PDT 24 |
Jul 03 08:53:32 PM PDT 24 |
11954066280 ps |
| T1191 |
/workspace/coverage/default/13.chip_sw_uart_rand_baudrate.526238089 |
|
|
Jul 03 08:15:20 PM PDT 24 |
Jul 03 08:26:17 PM PDT 24 |
4303693920 ps |
| T1192 |
/workspace/coverage/default/2.chip_sw_alert_handler_ping_timeout.3407048748 |
|
|
Jul 03 08:10:58 PM PDT 24 |
Jul 03 08:19:55 PM PDT 24 |
4012794400 ps |
| T1193 |
/workspace/coverage/default/1.chip_sw_clkmgr_jitter_frequency.1949196580 |
|
|
Jul 03 07:59:55 PM PDT 24 |
Jul 03 08:07:35 PM PDT 24 |
3901792020 ps |
| T1194 |
/workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_no_scramble.3210668493 |
|
|
Jul 03 08:08:51 PM PDT 24 |
Jul 03 08:16:35 PM PDT 24 |
8326405520 ps |
| T170 |
/workspace/coverage/default/2.chip_sw_spi_device_pass_through_collision.2580180885 |
|
|
Jul 03 08:05:16 PM PDT 24 |
Jul 03 08:17:00 PM PDT 24 |
4686753692 ps |
| T262 |
/workspace/coverage/default/42.chip_sw_all_escalation_resets.2853374731 |
|
|
Jul 03 08:20:00 PM PDT 24 |
Jul 03 08:30:26 PM PDT 24 |
5971811630 ps |
| T662 |
/workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_alerts.1016473370 |
|
|
Jul 03 07:52:45 PM PDT 24 |
Jul 03 08:01:22 PM PDT 24 |
4192867872 ps |
| T1195 |
/workspace/coverage/default/1.chip_sw_aes_enc_jitter_en_reduced_freq.565591702 |
|
|
Jul 03 08:03:06 PM PDT 24 |
Jul 03 08:08:20 PM PDT 24 |
3507529205 ps |
| T1196 |
/workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en.2611568399 |
|
|
Jul 03 07:59:25 PM PDT 24 |
Jul 03 09:08:57 PM PDT 24 |
18328237685 ps |
| T1197 |
/workspace/coverage/default/2.chip_sw_edn_entropy_reqs.1314538758 |
|
|
Jul 03 08:09:22 PM PDT 24 |
Jul 03 08:24:54 PM PDT 24 |
4971289186 ps |
| T205 |
/workspace/coverage/default/0.chip_sw_flash_rma_unlocked.1959080907 |
|
|
Jul 03 07:47:58 PM PDT 24 |
Jul 03 09:08:43 PM PDT 24 |
43890738843 ps |
| T1198 |
/workspace/coverage/default/0.chip_sw_kmac_mode_kmac.2067397997 |
|
|
Jul 03 07:49:21 PM PDT 24 |
Jul 03 07:55:25 PM PDT 24 |
2695484288 ps |
| T1199 |
/workspace/coverage/default/0.chip_sw_usbdev_vbus.243271946 |
|
|
Jul 03 07:48:23 PM PDT 24 |
Jul 03 07:53:26 PM PDT 24 |
2771290396 ps |
| T13 |
/workspace/coverage/default/0.chip_sw_sleep_pin_wake.1809988152 |
|
|
Jul 03 07:48:09 PM PDT 24 |
Jul 03 07:52:17 PM PDT 24 |
3063429600 ps |
| T395 |
/workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_alerts.2667670090 |
|
|
Jul 03 08:07:17 PM PDT 24 |
Jul 03 08:13:50 PM PDT 24 |
3660190380 ps |
| T101 |
/workspace/coverage/default/80.chip_sw_all_escalation_resets.3937762476 |
|
|
Jul 03 08:20:44 PM PDT 24 |
Jul 03 08:30:05 PM PDT 24 |
5454901620 ps |
| T396 |
/workspace/coverage/default/1.chip_sw_sysrst_ctrl_inputs.175623442 |
|
|
Jul 03 07:55:29 PM PDT 24 |
Jul 03 08:01:03 PM PDT 24 |
3735633560 ps |
| T397 |
/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.4147330728 |
|
|
Jul 03 07:47:55 PM PDT 24 |
Jul 03 08:12:56 PM PDT 24 |
13577709553 ps |
| T398 |
/workspace/coverage/default/0.chip_sw_rom_ctrl_integrity_check.2438519255 |
|
|
Jul 03 07:50:55 PM PDT 24 |
Jul 03 07:58:30 PM PDT 24 |
9526464482 ps |
| T399 |
/workspace/coverage/default/27.chip_sw_all_escalation_resets.3542774949 |
|
|
Jul 03 08:18:37 PM PDT 24 |
Jul 03 08:31:19 PM PDT 24 |
5723635000 ps |
| T122 |
/workspace/coverage/default/1.chip_sw_csrng_edn_concurrency_reduced_freq.2819221867 |
|
|
Jul 03 08:02:32 PM PDT 24 |
Jul 04 02:18:30 AM PDT 24 |
166779566366 ps |
| T400 |
/workspace/coverage/default/2.chip_sw_rv_dm_access_after_escalation_reset.3661866557 |
|
|
Jul 03 08:11:01 PM PDT 24 |
Jul 03 08:21:10 PM PDT 24 |
4783963205 ps |
| T401 |
/workspace/coverage/default/1.chip_sw_clkmgr_off_peri.2094036381 |
|
|
Jul 03 08:00:58 PM PDT 24 |
Jul 03 08:28:22 PM PDT 24 |
10436408908 ps |
| T1200 |
/workspace/coverage/default/0.chip_sw_aon_timer_smoketest.136594383 |
|
|
Jul 03 07:57:16 PM PDT 24 |
Jul 03 08:02:21 PM PDT 24 |
3032304628 ps |
| T1201 |
/workspace/coverage/default/79.chip_sw_alert_handler_lpg_sleep_mode_alerts.3037800856 |
|
|
Jul 03 08:25:02 PM PDT 24 |
Jul 03 08:31:35 PM PDT 24 |
3540736440 ps |
| T1202 |
/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.2198864438 |
|
|
Jul 03 08:00:13 PM PDT 24 |
Jul 03 08:14:37 PM PDT 24 |
4373652718 ps |
| T1203 |
/workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en.2213789980 |
|
|
Jul 03 08:00:08 PM PDT 24 |
Jul 03 08:11:14 PM PDT 24 |
5284624621 ps |
| T1204 |
/workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_pings.2049657684 |
|
|
Jul 03 07:58:10 PM PDT 24 |
Jul 03 08:26:03 PM PDT 24 |
11820016036 ps |
| T1205 |
/workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_test_unlocked0.3825225888 |
|
|
Jul 03 07:55:45 PM PDT 24 |
Jul 03 08:08:10 PM PDT 24 |
3762437390 ps |
| T1206 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_prod_end.2226454335 |
|
|
Jul 03 07:56:24 PM PDT 24 |
Jul 03 09:02:23 PM PDT 24 |
15804490600 ps |
| T1207 |
/workspace/coverage/default/0.chip_sw_edn_sw_mode.2347926787 |
|
|
Jul 03 07:54:00 PM PDT 24 |
Jul 03 08:15:04 PM PDT 24 |
5455204088 ps |
| T1208 |
/workspace/coverage/default/1.chip_sw_csrng_kat_test.4017993069 |
|
|
Jul 03 07:58:54 PM PDT 24 |
Jul 03 08:03:47 PM PDT 24 |
3170248462 ps |
| T670 |
/workspace/coverage/default/66.chip_sw_alert_handler_lpg_sleep_mode_alerts.1942067749 |
|
|
Jul 03 08:20:14 PM PDT 24 |
Jul 03 08:27:43 PM PDT 24 |
3892576368 ps |
| T320 |
/workspace/coverage/default/0.chip_sw_i2c_device_tx_rx.1587420542 |
|
|
Jul 03 07:48:12 PM PDT 24 |
Jul 03 07:58:56 PM PDT 24 |
3966737806 ps |
| T1209 |
/workspace/coverage/default/0.chip_sw_clkmgr_off_aes_trans.3666946385 |
|
|
Jul 03 07:50:58 PM PDT 24 |
Jul 03 07:58:21 PM PDT 24 |
4787795112 ps |
| T1210 |
/workspace/coverage/default/2.chip_sw_clkmgr_reset_frequency.3069978820 |
|
|
Jul 03 08:10:43 PM PDT 24 |
Jul 03 08:19:14 PM PDT 24 |
4015596616 ps |
| T1211 |
/workspace/coverage/default/0.chip_sw_csrng_lc_hw_debug_en_test.260536184 |
|
|
Jul 03 07:48:14 PM PDT 24 |
Jul 03 07:59:16 PM PDT 24 |
4770940668 ps |
| T1212 |
/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx3.3552010279 |
|
|
Jul 03 08:14:17 PM PDT 24 |
Jul 03 08:25:27 PM PDT 24 |
4029245050 ps |
| T1213 |
/workspace/coverage/default/0.chip_sw_entropy_src_ast_rng_req.1122372426 |
|
|
Jul 03 07:53:55 PM PDT 24 |
Jul 03 07:57:15 PM PDT 24 |
2404756772 ps |
| T369 |
/workspace/coverage/default/1.chip_sw_i2c_host_tx_rx_idx1.3445319916 |
|
|
Jul 03 07:53:20 PM PDT 24 |
Jul 03 08:10:42 PM PDT 24 |
5691294868 ps |
| T92 |
/workspace/coverage/default/0.chip_jtag_csr_rw.2085058159 |
|
|
Jul 03 07:42:05 PM PDT 24 |
Jul 03 08:15:15 PM PDT 24 |
15917412891 ps |
| T1214 |
/workspace/coverage/default/0.chip_sw_clkmgr_reset_frequency.1148814913 |
|
|
Jul 03 07:50:41 PM PDT 24 |
Jul 03 07:58:37 PM PDT 24 |
3304843818 ps |
| T1215 |
/workspace/coverage/default/45.chip_sw_alert_handler_lpg_sleep_mode_alerts.3164282832 |
|
|
Jul 03 08:19:58 PM PDT 24 |
Jul 03 08:28:38 PM PDT 24 |
3433868032 ps |
| T1216 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_write_clear.4223651843 |
|
|
Jul 03 08:11:52 PM PDT 24 |
Jul 03 08:18:01 PM PDT 24 |
2570488832 ps |
| T1217 |
/workspace/coverage/default/11.chip_sw_lc_ctrl_transition.1116545125 |
|
|
Jul 03 08:16:35 PM PDT 24 |
Jul 03 08:26:45 PM PDT 24 |
6245110466 ps |
| T1218 |
/workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq.1441307198 |
|
|
Jul 03 08:03:40 PM PDT 24 |
Jul 03 09:01:51 PM PDT 24 |
17097130384 ps |
| T1219 |
/workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en.394316889 |
|
|
Jul 03 08:07:13 PM PDT 24 |
Jul 03 09:01:54 PM PDT 24 |
18896310598 ps |
| T672 |
/workspace/coverage/default/68.chip_sw_alert_handler_lpg_sleep_mode_alerts.1105842218 |
|
|
Jul 03 08:20:36 PM PDT 24 |
Jul 03 08:25:38 PM PDT 24 |
3472823156 ps |
| T1220 |
/workspace/coverage/default/1.chip_sw_alert_handler_ping_ok.3007948105 |
|
|
Jul 03 07:57:08 PM PDT 24 |
Jul 03 08:22:14 PM PDT 24 |
7453856560 ps |
| T691 |
/workspace/coverage/default/0.chip_sw_all_escalation_resets.2119367887 |
|
|
Jul 03 07:46:36 PM PDT 24 |
Jul 03 07:57:11 PM PDT 24 |
5417557430 ps |
| T731 |
/workspace/coverage/default/28.chip_sw_all_escalation_resets.3416739577 |
|
|
Jul 03 08:19:43 PM PDT 24 |
Jul 03 08:28:42 PM PDT 24 |
4531996000 ps |
| T1221 |
/workspace/coverage/default/1.chip_sw_clkmgr_off_otbn_trans.4173027005 |
|
|
Jul 03 07:59:41 PM PDT 24 |
Jul 03 08:08:32 PM PDT 24 |
4889409616 ps |
| T742 |
/workspace/coverage/default/18.chip_sw_all_escalation_resets.2318647450 |
|
|
Jul 03 08:16:13 PM PDT 24 |
Jul 03 08:30:00 PM PDT 24 |
6036651480 ps |
| T1222 |
/workspace/coverage/default/2.chip_sw_kmac_entropy.1264828678 |
|
|
Jul 03 08:05:46 PM PDT 24 |
Jul 03 08:09:27 PM PDT 24 |
2845164052 ps |
| T713 |
/workspace/coverage/default/54.chip_sw_all_escalation_resets.2508083923 |
|
|
Jul 03 08:18:39 PM PDT 24 |
Jul 03 08:27:55 PM PDT 24 |
4420878600 ps |
| T1223 |
/workspace/coverage/default/1.chip_sw_otbn_smoketest.1750145163 |
|
|
Jul 03 08:04:10 PM PDT 24 |
Jul 03 08:33:43 PM PDT 24 |
8400829892 ps |
| T1224 |
/workspace/coverage/default/1.chip_sw_uart_smoketest.846730952 |
|
|
Jul 03 08:03:13 PM PDT 24 |
Jul 03 08:07:55 PM PDT 24 |
2772524872 ps |
| T285 |
/workspace/coverage/default/1.chip_sw_rv_core_ibex_address_translation.1851838557 |
|
|
Jul 03 08:01:46 PM PDT 24 |
Jul 03 08:06:34 PM PDT 24 |
2935411608 ps |
| T1225 |
/workspace/coverage/default/8.chip_sw_uart_rand_baudrate.2563686242 |
|
|
Jul 03 08:15:31 PM PDT 24 |
Jul 03 08:39:16 PM PDT 24 |
7993535056 ps |
| T1226 |
/workspace/coverage/default/6.chip_sw_csrng_edn_concurrency.1788323101 |
|
|
Jul 03 08:16:36 PM PDT 24 |
Jul 03 09:30:28 PM PDT 24 |
22149082276 ps |
| T1227 |
/workspace/coverage/default/0.chip_sw_rv_timer_smoketest.3935390715 |
|
|
Jul 03 07:51:39 PM PDT 24 |
Jul 03 07:55:49 PM PDT 24 |
3113516024 ps |
| T1228 |
/workspace/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.2383449646 |
|
|
Jul 03 08:01:41 PM PDT 24 |
Jul 03 08:06:57 PM PDT 24 |
3151782581 ps |
| T663 |
/workspace/coverage/default/91.chip_sw_all_escalation_resets.3401135564 |
|
|
Jul 03 08:23:01 PM PDT 24 |
Jul 03 08:34:31 PM PDT 24 |
5116799750 ps |
| T1229 |
/workspace/coverage/default/0.chip_sw_uart_smoketest.2451858747 |
|
|
Jul 03 07:55:17 PM PDT 24 |
Jul 03 08:00:01 PM PDT 24 |
2952770348 ps |
| T1230 |
/workspace/coverage/default/0.chip_sw_kmac_entropy.82644711 |
|
|
Jul 03 07:47:59 PM PDT 24 |
Jul 03 07:51:50 PM PDT 24 |
2493847300 ps |
| T144 |
/workspace/coverage/default/1.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.2796756998 |
|
|
Jul 03 07:59:11 PM PDT 24 |
Jul 03 08:07:40 PM PDT 24 |
5098013856 ps |
| T1231 |
/workspace/coverage/default/0.chip_sw_rstmgr_sw_req.520943970 |
|
|
Jul 03 07:49:04 PM PDT 24 |
Jul 03 07:56:23 PM PDT 24 |
5318239150 ps |
| T655 |
/workspace/coverage/default/2.chip_sw_rv_core_ibex_nmi_irq.1933071091 |
|
|
Jul 03 08:09:36 PM PDT 24 |
Jul 03 08:23:57 PM PDT 24 |
5608123310 ps |
| T344 |
/workspace/coverage/default/0.chip_sival_flash_info_access.4133641921 |
|
|
Jul 03 07:51:53 PM PDT 24 |
Jul 03 07:57:25 PM PDT 24 |
2801834248 ps |
| T696 |
/workspace/coverage/default/39.chip_sw_alert_handler_lpg_sleep_mode_alerts.3675580430 |
|
|
Jul 03 08:20:23 PM PDT 24 |
Jul 03 08:27:26 PM PDT 24 |
4017836216 ps |
| T1232 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0.1184198206 |
|
|
Jul 03 08:02:29 PM PDT 24 |
Jul 03 09:25:47 PM PDT 24 |
17311901059 ps |
| T693 |
/workspace/coverage/default/32.chip_sw_all_escalation_resets.2979484979 |
|
|
Jul 03 08:18:52 PM PDT 24 |
Jul 03 08:28:03 PM PDT 24 |
6092345300 ps |
| T744 |
/workspace/coverage/default/31.chip_sw_alert_handler_lpg_sleep_mode_alerts.3361924354 |
|
|
Jul 03 08:17:38 PM PDT 24 |
Jul 03 08:24:59 PM PDT 24 |
3886055216 ps |
| T294 |
/workspace/coverage/default/0.chip_sw_sram_ctrl_execution_main.119248114 |
|
|
Jul 03 07:51:41 PM PDT 24 |
Jul 03 08:06:48 PM PDT 24 |
8008535634 ps |
| T1233 |
/workspace/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.3256525761 |
|
|
Jul 03 07:50:23 PM PDT 24 |
Jul 03 07:56:10 PM PDT 24 |
3102877214 ps |
| T1234 |
/workspace/coverage/default/1.chip_sw_entropy_src_kat_test.2274546712 |
|
|
Jul 03 07:56:45 PM PDT 24 |
Jul 03 08:00:25 PM PDT 24 |
2737986662 ps |
| T1235 |
/workspace/coverage/default/2.chip_sw_sysrst_ctrl_in_irq.3134788614 |
|
|
Jul 03 08:06:01 PM PDT 24 |
Jul 03 08:18:37 PM PDT 24 |
5133475046 ps |
| T345 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en.1398736130 |
|
|
Jul 03 08:05:12 PM PDT 24 |
Jul 03 08:14:11 PM PDT 24 |
3406282272 ps |
| T1236 |
/workspace/coverage/default/1.chip_sw_ast_clk_outputs.2304430423 |
|
|
Jul 03 08:02:12 PM PDT 24 |
Jul 03 08:20:35 PM PDT 24 |
8007133996 ps |
| T623 |
/workspace/coverage/default/3.chip_tap_straps_dev.1069644224 |
|
|
Jul 03 08:12:39 PM PDT 24 |
Jul 03 08:27:15 PM PDT 24 |
10314436513 ps |
| T719 |
/workspace/coverage/default/66.chip_sw_all_escalation_resets.3801064046 |
|
|
Jul 03 08:21:20 PM PDT 24 |
Jul 03 08:30:18 PM PDT 24 |
4892033792 ps |
| T1237 |
/workspace/coverage/default/3.chip_sw_aon_timer_sleep_wdog_sleep_pause.985824041 |
|
|
Jul 03 08:12:41 PM PDT 24 |
Jul 03 08:19:06 PM PDT 24 |
6847664632 ps |
| T1238 |
/workspace/coverage/default/1.chip_sw_example_manufacturer.4092429112 |
|
|
Jul 03 07:54:00 PM PDT 24 |
Jul 03 07:57:10 PM PDT 24 |
2687006952 ps |
| T1239 |
/workspace/coverage/default/44.chip_sw_alert_handler_lpg_sleep_mode_alerts.1851770020 |
|
|
Jul 03 08:20:10 PM PDT 24 |
Jul 03 08:26:37 PM PDT 24 |
3312981598 ps |
| T1240 |
/workspace/coverage/default/1.chip_sw_rstmgr_sw_rst.3722471384 |
|
|
Jul 03 07:54:37 PM PDT 24 |
Jul 03 07:59:46 PM PDT 24 |
2952982784 ps |
| T1241 |
/workspace/coverage/default/1.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.3399889038 |
|
|
Jul 03 07:56:46 PM PDT 24 |
Jul 03 08:06:16 PM PDT 24 |
19022938320 ps |
| T1242 |
/workspace/coverage/default/59.chip_sw_all_escalation_resets.2324309610 |
|
|
Jul 03 08:20:37 PM PDT 24 |
Jul 03 08:31:10 PM PDT 24 |
4769925600 ps |
| T728 |
/workspace/coverage/default/47.chip_sw_alert_handler_lpg_sleep_mode_alerts.3200337031 |
|
|
Jul 03 08:18:58 PM PDT 24 |
Jul 03 08:26:30 PM PDT 24 |
3248873248 ps |
| T1243 |
/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.3678923472 |
|
|
Jul 03 07:50:41 PM PDT 24 |
Jul 03 08:02:44 PM PDT 24 |
4157220840 ps |
| T1244 |
/workspace/coverage/default/0.chip_sw_pwrmgr_full_aon_reset.282288729 |
|
|
Jul 03 07:50:25 PM PDT 24 |
Jul 03 07:56:11 PM PDT 24 |
7003453586 ps |
| T1245 |
/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_power_glitch_reset.2704167717 |
|
|
Jul 03 07:51:23 PM PDT 24 |
Jul 03 07:59:59 PM PDT 24 |
4467761248 ps |
| T1246 |
/workspace/coverage/default/4.chip_sw_lc_ctrl_transition.2572865885 |
|
|
Jul 03 08:14:09 PM PDT 24 |
Jul 03 08:32:49 PM PDT 24 |
9765266184 ps |
| T123 |
/workspace/coverage/default/0.chip_sw_csrng_edn_concurrency_reduced_freq.3658973081 |
|
|
Jul 03 07:50:20 PM PDT 24 |
Jul 03 10:58:43 PM PDT 24 |
79745242388 ps |
| T1247 |
/workspace/coverage/default/0.chip_sw_lc_walkthrough_rma.519287829 |
|
|
Jul 03 07:51:35 PM PDT 24 |
Jul 03 09:28:48 PM PDT 24 |
45713589372 ps |
| T1248 |
/workspace/coverage/default/2.rom_volatile_raw_unlock.4041167170 |
|
|
Jul 03 08:11:29 PM PDT 24 |
Jul 03 08:13:15 PM PDT 24 |
2732446729 ps |
| T313 |
/workspace/coverage/default/0.chip_sw_rstmgr_alert_info.2540178782 |
|
|
Jul 03 07:48:12 PM PDT 24 |
Jul 03 08:22:52 PM PDT 24 |
13846547152 ps |
| T611 |
/workspace/coverage/default/1.chip_sw_edn_boot_mode.1526018650 |
|
|
Jul 03 07:57:16 PM PDT 24 |
Jul 03 08:06:06 PM PDT 24 |
3233186172 ps |
| T1249 |
/workspace/coverage/default/2.chip_sw_inject_scramble_seed.211373479 |
|
|
Jul 03 08:04:28 PM PDT 24 |
Jul 03 11:14:34 PM PDT 24 |
64728646732 ps |
| T1250 |
/workspace/coverage/default/0.chip_sw_clkmgr_sleep_frequency.2392790287 |
|
|
Jul 03 07:48:49 PM PDT 24 |
Jul 03 07:58:16 PM PDT 24 |
4366477832 ps |
| T1251 |
/workspace/coverage/default/0.chip_sw_aon_timer_wdog_bite_reset.3845650305 |
|
|
Jul 03 07:49:18 PM PDT 24 |
Jul 03 08:03:14 PM PDT 24 |
9170609144 ps |
| T1252 |
/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.1638404962 |
|
|
Jul 03 07:49:24 PM PDT 24 |
Jul 03 08:02:30 PM PDT 24 |
4262054576 ps |
| T705 |
/workspace/coverage/default/60.chip_sw_alert_handler_lpg_sleep_mode_alerts.3903668988 |
|
|
Jul 03 08:22:24 PM PDT 24 |
Jul 03 08:28:48 PM PDT 24 |
4068940004 ps |
| T1253 |
/workspace/coverage/default/0.chip_sw_clkmgr_jitter_frequency.2584696019 |
|
|
Jul 03 07:50:59 PM PDT 24 |
Jul 03 07:57:38 PM PDT 24 |
3332510408 ps |
| T1254 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_dev.2242770039 |
|
|
Jul 03 07:58:54 PM PDT 24 |
Jul 03 09:00:36 PM PDT 24 |
15425309680 ps |
| T1255 |
/workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_rma.955891932 |
|
|
Jul 03 07:55:14 PM PDT 24 |
Jul 03 08:21:28 PM PDT 24 |
8637823198 ps |
| T355 |
/workspace/coverage/default/1.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.3962428589 |
|
|
Jul 03 08:01:02 PM PDT 24 |
Jul 03 08:07:13 PM PDT 24 |
5602497320 ps |
| T312 |
/workspace/coverage/default/1.chip_sw_rstmgr_alert_info.2738077695 |
|
|
Jul 03 07:53:57 PM PDT 24 |
Jul 03 08:21:50 PM PDT 24 |
13519082104 ps |
| T1256 |
/workspace/coverage/default/0.chip_sw_alert_handler_lpg_reset_toggle.3078834189 |
|
|
Jul 03 07:47:22 PM PDT 24 |
Jul 03 08:18:59 PM PDT 24 |
8580007250 ps |
| T1257 |
/workspace/coverage/default/1.chip_sw_alert_handler_lpg_clkoff.2121906305 |
|
|
Jul 03 07:57:14 PM PDT 24 |
Jul 03 08:23:50 PM PDT 24 |
5902185240 ps |
| T1258 |
/workspace/coverage/default/1.chip_sw_rv_plic_smoketest.178181325 |
|
|
Jul 03 08:02:33 PM PDT 24 |
Jul 03 08:06:33 PM PDT 24 |
3236786140 ps |
| T1259 |
/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.2101018723 |
|
|
Jul 03 08:02:02 PM PDT 24 |
Jul 03 08:12:25 PM PDT 24 |
5072538408 ps |
| T224 |
/workspace/coverage/default/1.chip_sw_keymgr_sideload_aes.1809471163 |
|
|
Jul 03 08:06:41 PM PDT 24 |
Jul 03 08:44:15 PM PDT 24 |
11201020420 ps |
| T1260 |
/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_lc.1196859303 |
|
|
Jul 03 07:49:03 PM PDT 24 |
Jul 03 08:00:02 PM PDT 24 |
12515305559 ps |
| T745 |
/workspace/coverage/default/99.chip_sw_all_escalation_resets.3604928844 |
|
|
Jul 03 08:22:26 PM PDT 24 |
Jul 03 08:33:27 PM PDT 24 |
5743745784 ps |
| T1261 |
/workspace/coverage/default/26.chip_sw_all_escalation_resets.222829087 |
|
|
Jul 03 08:18:48 PM PDT 24 |
Jul 03 08:29:48 PM PDT 24 |
5357760784 ps |
| T1262 |
/workspace/coverage/default/0.rom_volatile_raw_unlock.578144967 |
|
|
Jul 03 07:55:43 PM PDT 24 |
Jul 03 07:57:50 PM PDT 24 |
2442905324 ps |
| T1263 |
/workspace/coverage/default/2.chip_sw_pwrmgr_sleep_wake_5_bug.1863672624 |
|
|
Jul 03 08:10:28 PM PDT 24 |
Jul 03 08:21:55 PM PDT 24 |
7306923356 ps |
| T1264 |
/workspace/coverage/default/1.chip_sw_edn_auto_mode.3941098646 |
|
|
Jul 03 07:59:03 PM PDT 24 |
Jul 03 08:15:43 PM PDT 24 |
4184385712 ps |
| T1265 |
/workspace/coverage/default/13.chip_sw_lc_ctrl_transition.2781770744 |
|
|
Jul 03 08:16:42 PM PDT 24 |
Jul 03 08:35:41 PM PDT 24 |
11738297553 ps |
| T172 |
/workspace/coverage/default/1.chip_jtag_mem_access.1029055885 |
|
|
Jul 03 07:53:37 PM PDT 24 |
Jul 03 08:21:51 PM PDT 24 |
13720609040 ps |
| T328 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.136263484 |
|
|
Jul 03 07:49:45 PM PDT 24 |
Jul 03 08:00:19 PM PDT 24 |
4987920225 ps |
| T338 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.3725627261 |
|
|
Jul 03 08:02:19 PM PDT 24 |
Jul 03 08:17:16 PM PDT 24 |
4966149270 ps |
| T1266 |
/workspace/coverage/default/1.chip_sw_aes_entropy.2047702358 |
|
|
Jul 03 08:00:15 PM PDT 24 |
Jul 03 08:06:21 PM PDT 24 |
3054759460 ps |
| T1267 |
/workspace/coverage/default/1.chip_sw_gpio_smoketest.1459328304 |
|
|
Jul 03 08:04:05 PM PDT 24 |
Jul 03 08:08:20 PM PDT 24 |
2418695730 ps |
| T1268 |
/workspace/coverage/default/2.chip_sw_sysrst_ctrl_inputs.2342731908 |
|
|
Jul 03 08:06:31 PM PDT 24 |
Jul 03 08:11:18 PM PDT 24 |
2853982550 ps |
| T1269 |
/workspace/coverage/default/2.chip_sw_pwrmgr_b2b_sleep_reset_req.2182613920 |
|
|
Jul 03 08:07:53 PM PDT 24 |
Jul 03 08:41:01 PM PDT 24 |
25110437461 ps |
| T1270 |
/workspace/coverage/default/69.chip_sw_alert_handler_lpg_sleep_mode_alerts.2577820798 |
|
|
Jul 03 08:24:58 PM PDT 24 |
Jul 03 08:31:19 PM PDT 24 |
3184245484 ps |
| T1271 |
/workspace/coverage/default/0.rom_e2e_asm_init_dev.3944229536 |
|
|
Jul 03 07:57:39 PM PDT 24 |
Jul 03 08:56:08 PM PDT 24 |
15061916320 ps |
| T286 |
/workspace/coverage/default/2.chip_sw_rv_core_ibex_icache_invalidate.3074090878 |
|
|
Jul 03 08:11:59 PM PDT 24 |
Jul 03 08:15:39 PM PDT 24 |
2830031833 ps |
| T1272 |
/workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.3014931082 |
|
|
Jul 03 08:02:04 PM PDT 24 |
Jul 03 08:13:13 PM PDT 24 |
5009397007 ps |
| T1273 |
/workspace/coverage/default/1.chip_sw_sensor_ctrl_status.4143165402 |
|
|
Jul 03 07:58:45 PM PDT 24 |
Jul 03 08:02:14 PM PDT 24 |
3285635067 ps |
| T314 |
/workspace/coverage/default/0.chip_sw_entropy_src_csrng.2989224809 |
|
|
Jul 03 07:49:01 PM PDT 24 |
Jul 03 08:10:40 PM PDT 24 |
5462248240 ps |
| T1274 |
/workspace/coverage/default/2.chip_sw_flash_scrambling_smoketest.2353329472 |
|
|
Jul 03 08:18:17 PM PDT 24 |
Jul 03 08:21:57 PM PDT 24 |
2858972056 ps |
| T1275 |
/workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_power_glitch_reset.1806453517 |
|
|
Jul 03 07:56:24 PM PDT 24 |
Jul 03 08:43:57 PM PDT 24 |
33212756286 ps |
| T182 |
/workspace/coverage/default/0.chip_plic_all_irqs_10.2701994111 |
|
|
Jul 03 07:50:39 PM PDT 24 |
Jul 03 07:58:07 PM PDT 24 |
4302404404 ps |
| T1276 |
/workspace/coverage/default/0.chip_sw_pattgen_ios.1120864049 |
|
|
Jul 03 07:49:09 PM PDT 24 |
Jul 03 07:54:31 PM PDT 24 |
2718704128 ps |
| T1277 |
/workspace/coverage/default/0.chip_sw_pwrmgr_usbdev_smoketest.3849666030 |
|
|
Jul 03 07:52:11 PM PDT 24 |
Jul 03 07:57:25 PM PDT 24 |
6396262944 ps |
| T1278 |
/workspace/coverage/default/2.chip_sw_example_flash.2822746567 |
|
|
Jul 03 08:04:23 PM PDT 24 |
Jul 03 08:07:07 PM PDT 24 |
2120348240 ps |
| T1279 |
/workspace/coverage/default/1.chip_sw_lc_ctrl_otp_hw_cfg0.40723399 |
|
|
Jul 03 07:53:55 PM PDT 24 |
Jul 03 07:57:50 PM PDT 24 |
3150963690 ps |
| T287 |
/workspace/coverage/default/2.chip_sw_rv_core_ibex_address_translation.3523063299 |
|
|
Jul 03 08:11:01 PM PDT 24 |
Jul 03 08:15:31 PM PDT 24 |
3154297720 ps |
| T315 |
/workspace/coverage/default/2.chip_sw_entropy_src_csrng.2257967850 |
|
|
Jul 03 08:10:04 PM PDT 24 |
Jul 03 08:47:13 PM PDT 24 |
7031440664 ps |
| T1280 |
/workspace/coverage/default/11.chip_sw_all_escalation_resets.4025551458 |
|
|
Jul 03 08:16:56 PM PDT 24 |
Jul 03 08:27:05 PM PDT 24 |
5265588498 ps |
| T1281 |
/workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_por_reset.2162126959 |
|
|
Jul 03 07:48:15 PM PDT 24 |
Jul 03 07:59:30 PM PDT 24 |
6592929559 ps |
| T1282 |
/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx1.3605081596 |
|
|
Jul 03 08:13:39 PM PDT 24 |
Jul 03 08:22:38 PM PDT 24 |
4252858144 ps |
| T1283 |
/workspace/coverage/default/15.chip_sw_uart_rand_baudrate.1812337070 |
|
|
Jul 03 08:15:50 PM PDT 24 |
Jul 03 08:25:59 PM PDT 24 |
4053819976 ps |
| T673 |
/workspace/coverage/default/76.chip_sw_alert_handler_lpg_sleep_mode_alerts.3647730093 |
|
|
Jul 03 08:22:21 PM PDT 24 |
Jul 03 08:29:50 PM PDT 24 |
4497210698 ps |
| T702 |
/workspace/coverage/default/27.chip_sw_alert_handler_lpg_sleep_mode_alerts.489703474 |
|
|
Jul 03 08:17:36 PM PDT 24 |
Jul 03 08:24:50 PM PDT 24 |
3846785470 ps |
| T1284 |
/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.2535863568 |
|
|
Jul 03 07:48:00 PM PDT 24 |
Jul 03 07:56:42 PM PDT 24 |
8299932020 ps |
| T752 |
/workspace/coverage/default/1.chip_sw_all_escalation_resets.1391719034 |
|
|
Jul 03 07:54:00 PM PDT 24 |
Jul 03 08:04:37 PM PDT 24 |
5284711696 ps |
| T1285 |
/workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_scramble.3153340899 |
|
|
Jul 03 08:08:32 PM PDT 24 |
Jul 03 08:25:08 PM PDT 24 |
8359262504 ps |
| T1286 |
/workspace/coverage/default/2.rom_e2e_shutdown_output.2854374312 |
|
|
Jul 03 08:15:54 PM PDT 24 |
Jul 03 09:06:28 PM PDT 24 |
24891830517 ps |
| T1287 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_mem_protection.1239486638 |
|
|
Jul 03 07:53:44 PM PDT 24 |
Jul 03 08:14:29 PM PDT 24 |
6129313672 ps |
| T1288 |
/workspace/coverage/default/2.chip_sw_alert_handler_reverse_ping_in_deep_sleep.3948964304 |
|
|
Jul 03 08:09:18 PM PDT 24 |
Jul 03 11:30:00 PM PDT 24 |
255706183824 ps |
| T698 |
/workspace/coverage/default/70.chip_sw_alert_handler_lpg_sleep_mode_alerts.3736532589 |
|
|
Jul 03 08:19:48 PM PDT 24 |
Jul 03 08:26:31 PM PDT 24 |
3506001768 ps |
| T1289 |
/workspace/coverage/default/0.chip_sw_example_rom.1829387382 |
|
|
Jul 03 07:46:20 PM PDT 24 |
Jul 03 07:48:39 PM PDT 24 |
2533755120 ps |
| T102 |
/workspace/coverage/default/10.chip_sw_alert_handler_lpg_sleep_mode_alerts.2040381690 |
|
|
Jul 03 08:16:42 PM PDT 24 |
Jul 03 08:24:31 PM PDT 24 |
4160621036 ps |
| T1290 |
/workspace/coverage/default/1.chip_sw_uart_tx_rx_idx2.1981136247 |
|
|
Jul 03 07:54:50 PM PDT 24 |
Jul 03 08:06:26 PM PDT 24 |
4095990838 ps |
| T711 |
/workspace/coverage/default/61.chip_sw_alert_handler_lpg_sleep_mode_alerts.1488933641 |
|
|
Jul 03 08:19:56 PM PDT 24 |
Jul 03 08:28:50 PM PDT 24 |
3798794788 ps |
| T1291 |
/workspace/coverage/default/18.chip_sw_uart_rand_baudrate.1469945123 |
|
|
Jul 03 08:17:21 PM PDT 24 |
Jul 03 08:48:06 PM PDT 24 |
8413840666 ps |
| T1292 |
/workspace/coverage/default/1.chip_sw_edn_kat.918197119 |
|
|
Jul 03 07:59:05 PM PDT 24 |
Jul 03 08:10:56 PM PDT 24 |
3378493170 ps |
| T1293 |
/workspace/coverage/default/1.chip_sw_clkmgr_jitter.2890732194 |
|
|
Jul 03 08:01:00 PM PDT 24 |
Jul 03 08:03:54 PM PDT 24 |
2385436098 ps |
| T1294 |
/workspace/coverage/default/2.chip_sw_hmac_oneshot.2510331412 |
|
|
Jul 03 08:07:18 PM PDT 24 |
Jul 03 08:12:25 PM PDT 24 |
3276168220 ps |
| T1295 |
/workspace/coverage/default/1.chip_sw_clkmgr_sleep_frequency.1504081056 |
|
|
Jul 03 08:00:19 PM PDT 24 |
Jul 03 08:10:42 PM PDT 24 |
4720887688 ps |
| T1296 |
/workspace/coverage/default/0.chip_sw_lc_walkthrough_prod.1224545468 |
|
|
Jul 03 07:51:01 PM PDT 24 |
Jul 03 09:18:52 PM PDT 24 |
48403854982 ps |
| T1297 |
/workspace/coverage/default/2.chip_sw_aes_enc_jitter_en_reduced_freq.2931675776 |
|
|
Jul 03 08:10:48 PM PDT 24 |
Jul 03 08:15:09 PM PDT 24 |
3505196462 ps |
| T1298 |
/workspace/coverage/default/0.chip_sw_clkmgr_jitter_reduced_freq.2278360463 |
|
|
Jul 03 07:51:52 PM PDT 24 |
Jul 03 07:56:01 PM PDT 24 |
3254225924 ps |
| T1299 |
/workspace/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.3122902513 |
|
|
Jul 03 08:05:30 PM PDT 24 |
Jul 03 08:07:30 PM PDT 24 |
2540491125 ps |
| T87 |
/workspace/coverage/cover_reg_top/15.chip_csr_rw.1205579652 |
|
|
Jul 03 07:24:55 PM PDT 24 |
Jul 03 07:36:34 PM PDT 24 |
6756466950 ps |
| T88 |
/workspace/coverage/cover_reg_top/59.xbar_error_and_unmapped_addr.1962730194 |
|
|
Jul 03 07:33:14 PM PDT 24 |
Jul 03 07:33:57 PM PDT 24 |
1084130144 ps |
| T135 |
/workspace/coverage/cover_reg_top/8.chip_same_csr_outstanding.3850582998 |
|
|
Jul 03 07:23:21 PM PDT 24 |
Jul 03 07:55:50 PM PDT 24 |
16362991022 ps |
| T89 |
/workspace/coverage/cover_reg_top/42.xbar_same_source.4064939549 |
|
|
Jul 03 07:30:25 PM PDT 24 |
Jul 03 07:30:55 PM PDT 24 |
379115449 ps |
| T91 |
/workspace/coverage/cover_reg_top/32.xbar_random_large_delays.3127703844 |
|
|
Jul 03 07:28:18 PM PDT 24 |
Jul 03 07:40:28 PM PDT 24 |
66043523370 ps |
| T249 |
/workspace/coverage/cover_reg_top/50.xbar_smoke_slow_rsp.4147740767 |
|
|
Jul 03 07:31:39 PM PDT 24 |
Jul 03 07:33:10 PM PDT 24 |
5540213316 ps |
| T250 |
/workspace/coverage/cover_reg_top/74.xbar_error_random.3360597543 |
|
|
Jul 03 07:35:47 PM PDT 24 |
Jul 03 07:36:58 PM PDT 24 |
1890268345 ps |
| T427 |
/workspace/coverage/cover_reg_top/61.xbar_same_source.2673134015 |
|
|
Jul 03 07:33:38 PM PDT 24 |
Jul 03 07:33:53 PM PDT 24 |
331808485 ps |
| T500 |
/workspace/coverage/cover_reg_top/36.xbar_access_same_device.581281851 |
|
|
Jul 03 07:28:57 PM PDT 24 |
Jul 03 07:30:34 PM PDT 24 |
1269549083 ps |