Unified Coverage Report :: Group :: tl_agent_pkg::max_outstanding_cg::SHAPE{max_outstanding=64}

Group : tl_agent_pkg::max_outstanding_cg::SHAPE{max_outstanding=64}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

3 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	3741448	1			T76	6080		T77	1423		T78	1212
values[2]	766989	1			T76	881		T77	463		T78	385
values[3]	110471	1			T76	1		T77	29		T78	18
values[4]	58243	1			T77	2		T78	1		T422	16
values[5]	38517	1			T422	16		T437	137		T438	71
values[6]	28846	1			T422	17		T437	111		T438	70
values[7]	23131	1			T422	16		T437	73		T438	62
values[8]	19317	1			T422	16		T437	40		T438	62
values[9]	17217	1			T422	16		T437	61		T438	60
values[10]	16103	1			T422	17		T437	46		T438	61
values[11]	14582	1			T422	16		T437	34		T438	66
values[12]	13735	1			T422	16		T437	28		T438	69
values[13]	12946	1			T422	16		T437	21		T438	77
values[14]	12401	1			T422	16		T437	25		T438	79
values[15]	11988	1			T422	16		T437	13		T438	49
values[16]	11819	1			T422	16		T437	28		T438	51
values[17]	11342	1			T422	16		T437	19		T438	52
values[18]	10702	1			T422	16		T437	14		T438	42
values[19]	10497	1			T422	17		T437	21		T438	45
values[20]	10513	1			T422	16		T437	51		T438	85
values[21]	10017	1			T422	17		T437	28		T438	47
values[22]	9603	1			T422	16		T437	20		T438	72
values[23]	9268	1			T422	16		T437	26		T438	74
values[24]	8914	1			T422	16		T437	18		T438	65
values[25]	8518	1			T422	16		T437	31		T438	43
values[26]	8090	1			T422	17		T437	29		T438	46
values[27]	7862	1			T422	16		T437	16		T438	55
values[28]	7588	1			T422	16		T437	10		T438	35
values[29]	7030	1			T422	17		T437	6		T438	30
values[30]	6676	1			T422	16		T437	19		T438	21
values[31]	6194	1			T422	16		T437	29		T438	35
values[32]	5935	1			T422	16		T437	16		T438	34
values[33]	5399	1			T422	16		T437	10		T438	20
values[34]	4880	1			T422	17		T437	10		T438	20
values[35]	4661	1			T422	16		T437	8		T438	11
values[36]	4418	1			T422	17		T437	4		T438	35
values[37]	4122	1			T422	17		T437	9		T438	31
values[38]	3995	1			T422	16		T437	8		T438	20
values[39]	3855	1			T422	17		T437	6		T438	14
values[40]	3815	1			T422	16		T437	11		T438	12
values[41]	3698	1			T422	16		T437	10		T438	18
values[42]	3568	1			T422	16		T437	12		T438	11
values[43]	3408	1			T422	16		T437	10		T438	4
values[44]	3410	1			T422	16		T437	6		T438	10
values[45]	3305	1			T422	16		T437	3		T438	11
values[46]	3228	1			T422	16		T437	14		T438	4
values[47]	3244	1			T422	16		T437	7		T438	8
values[48]	3126	1			T422	16		T437	5		T438	5
values[49]	3109	1			T422	16		T437	10		T438	6
values[50]	3062	1			T422	16		T437	16		T438	6
values[51]	2977	1			T422	16		T437	11		T438	3
values[52]	2936	1			T422	17		T437	8		T438	7
values[53]	2846	1			T422	16		T437	7		T438	7
values[54]	2863	1			T422	16		T437	8		T438	8
values[55]	2671	1			T422	16		T437	7		T438	2
values[56]	2703	1			T422	16		T437	5		T520	6
values[57]	2656	1			T422	16		T437	5		T520	5
values[58]	2623	1			T422	16		T437	3		T520	5
values[59]	2718	1			T422	16		T437	5		T520	5
values[60]	2605	1			T422	16		T437	8		T520	5
values[61]	2854	1			T422	16		T437	12		T520	5
values[62]	4199	1			T422	16		T437	20		T520	5
values[63]	11293	1			T422	17		T437	58		T520	5
values[64]	241071	1			T422	3012		T437	132		T520	940

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	4810602	1			T76	6499		T77	1543		T78	1149
values[2]	831383	1			T76	847		T77	466		T78	347
values[3]	85980	1			T76	7		T77	135		T78	115
values[4]	14892	1			T76	1		T77	32		T78	30
values[5]	5370	1			T77	9		T78	9		T422	19
values[6]	3325	1			T77	2		T78	1		T422	5
values[7]	2683	1			T422	3		T437	16		T520	2
values[8]	2218	1			T422	2		T437	17		T520	2
values[9]	1929	1			T422	2		T437	16		T520	2
values[10]	1701	1			T422	2		T437	15		T520	1
values[11]	1480	1			T422	2		T437	13		T520	1
values[12]	1375	1			T422	2		T437	18		T520	1
values[13]	1234	1			T422	2		T437	12		T520	1
values[14]	1210	1			T422	2		T437	9		T520	1
values[15]	1096	1			T422	2		T437	8		T520	1
values[16]	1057	1			T422	2		T437	3		T520	2
values[17]	1008	1			T422	2		T437	4		T520	1
values[18]	1005	1			T422	2		T437	10		T520	1
values[19]	927	1			T422	2		T437	9		T520	1
values[20]	883	1			T422	3		T437	5		T520	1
values[21]	937	1			T422	2		T437	9		T520	1
values[22]	882	1			T422	2		T437	6		T520	1
values[23]	800	1			T422	2		T437	6		T520	1
values[24]	810	1			T422	2		T437	8		T520	1
values[25]	749	1			T422	2		T437	6		T520	1
values[26]	728	1			T422	2		T437	4		T520	1
values[27]	699	1			T422	2		T437	3		T520	1
values[28]	654	1			T422	2		T437	2		T520	1
values[29]	682	1			T422	2		T437	3		T520	1
values[30]	749	1			T422	2		T437	7		T520	1
values[31]	726	1			T422	2		T437	3		T520	1
values[32]	624	1			T422	2		T437	4		T520	1
values[33]	596	1			T422	2		T437	3		T520	1
values[34]	568	1			T422	2		T437	6		T520	1
values[35]	574	1			T422	2		T437	4		T520	1
values[36]	525	1			T422	2		T437	10		T520	1
values[37]	543	1			T422	2		T437	6		T520	1
values[38]	532	1			T422	2		T437	4		T520	1
values[39]	545	1			T422	2		T437	7		T520	1
values[40]	528	1			T422	2		T437	13		T520	1
values[41]	535	1			T422	2		T437	7		T520	1
values[42]	534	1			T422	2		T437	2		T520	1
values[43]	499	1			T422	2		T437	4		T520	1
values[44]	480	1			T422	2		T437	7		T520	1
values[45]	458	1			T422	2		T437	4		T520	1
values[46]	482	1			T422	3		T437	3		T520	1
values[47]	453	1			T422	2		T437	4		T520	1
values[48]	470	1			T422	2		T437	8		T520	1
values[49]	479	1			T422	2		T437	8		T520	1
values[50]	460	1			T422	2		T437	7		T520	1
values[51]	448	1			T422	2		T437	14		T520	1
values[52]	455	1			T422	2		T437	4		T520	1
values[53]	434	1			T422	2		T437	9		T520	1
values[54]	435	1			T422	2		T437	6		T520	1
values[55]	411	1			T422	2		T437	4		T520	1
values[56]	408	1			T422	2		T437	3		T520	1
values[57]	422	1			T422	2		T437	3		T520	1
values[58]	410	1			T422	2		T437	7		T520	1
values[59]	414	1			T422	2		T437	8		T520	1
values[60]	396	1			T422	2		T437	3		T520	1
values[61]	437	1			T422	2		T437	9		T520	1
values[62]	726	1			T422	2		T437	5		T520	1
values[63]	2924	1			T422	3		T437	55		T520	2
values[64]	31047	1			T422	422		T437	115		T520	228

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	545847	1			T76	120		T77	14		T78	12
values[2]	2726518	1			T76	6172		T77	1312		T78	168
values[3]	1170344	1			T76	993		T77	471		T78	1203
values[4]	147541	1			T76	1		T77	29		T78	257
values[5]	75588	1			T78	19		T422	16		T437	362
values[6]	49659	1			T78	1		T422	16		T437	208
values[7]	36090	1			T422	16		T437	138		T438	76
values[8]	28553	1			T422	16		T437	58		T438	64
values[9]	24009	1			T422	17		T437	34		T438	70
values[10]	20775	1			T422	16		T437	43		T438	75
values[11]	18391	1			T422	16		T437	47		T438	68
values[12]	17490	1			T422	16		T437	57		T438	81
values[13]	16413	1			T422	17		T437	64		T438	72
values[14]	15372	1			T422	16		T437	42		T438	73
values[15]	14649	1			T422	16		T437	22		T438	67
values[16]	14127	1			T422	17		T437	29		T438	64
values[17]	13450	1			T422	16		T437	25		T438	99
values[18]	12649	1			T422	16		T437	25		T438	70
values[19]	12071	1			T422	16		T437	28		T438	45
values[20]	11754	1			T422	17		T437	36		T438	48
values[21]	11463	1			T422	16		T437	35		T438	49
values[22]	11214	1			T422	16		T437	37		T438	47
values[23]	10873	1			T422	17		T437	13		T438	52
values[24]	10272	1			T422	16		T437	22		T438	58
values[25]	9904	1			T422	17		T437	26		T438	69
values[26]	9282	1			T422	16		T437	26		T438	62
values[27]	8782	1			T422	17		T437	24		T438	46
values[28]	8686	1			T422	16		T437	23		T438	36
values[29]	7898	1			T422	16		T437	15		T438	30
values[30]	7315	1			T422	16		T437	7		T438	29
values[31]	6956	1			T422	16		T437	14		T438	46
values[32]	6507	1			T422	16		T437	13		T438	54
values[33]	5885	1			T422	17		T437	12		T438	45
values[34]	5605	1			T422	16		T437	7		T438	42
values[35]	5245	1			T422	16		T437	13		T438	30
values[36]	4760	1			T422	16		T437	12		T438	27
values[37]	4415	1			T422	16		T437	4		T438	19
values[38]	4327	1			T422	16		T437	4		T438	20
values[39]	4113	1			T422	16		T437	7		T438	22
values[40]	3927	1			T422	16		T437	13		T438	7
values[41]	3759	1			T422	16		T437	12		T438	8
values[42]	3563	1			T422	16		T437	6		T438	5
values[43]	3645	1			T422	17		T437	7		T438	4
values[44]	3647	1			T422	16		T437	8		T520	5
values[45]	3583	1			T422	16		T437	7		T520	6
values[46]	3581	1			T422	16		T437	11		T520	5
values[47]	3490	1			T422	16		T437	9		T520	5
values[48]	3394	1			T422	16		T437	8		T520	5
values[49]	3318	1			T422	16		T437	3		T520	5
values[50]	3241	1			T422	17		T437	5		T520	5
values[51]	3287	1			T422	16		T437	10		T520	5
values[52]	3217	1			T422	17		T437	7		T520	5
values[53]	3157	1			T422	16		T437	10		T520	6
values[54]	3108	1			T422	16		T437	8		T520	5
values[55]	3019	1			T422	16		T437	10		T520	5
values[56]	3033	1			T422	17		T437	13		T520	5
values[57]	2896	1			T422	16		T437	8		T520	5
values[58]	2890	1			T422	16		T437	6		T520	5
values[59]	2807	1			T422	16		T437	12		T520	5
values[60]	2801	1			T422	17		T437	9		T520	5
values[61]	2900	1			T422	16		T437	11		T520	5
values[62]	3913	1			T422	16		T437	11		T520	5
values[63]	9856	1			T422	17		T437	28		T520	6
values[64]	237012	1			T422	3100		T437	91		T520	967