Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

4 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2008119	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

34789774

1

T4

19790

T5

86431

T6

6393

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	25836468	1			T4	7526		T5	74357		T6	2612
values[0x0]	9557176	1			T4	12264		T5	12074		T6	3781
values[0x1]	1404249	1			T4	1310		T5	7		T6	209

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	703643	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

36094250

1

T4

21100

T5

86438

T6

6602

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	17149421	1			T4	10552		T5	43219		T6	3301
valid_sources[0x01]	17148417	1			T4	10548		T5	43219		T6	3301
valid_sources[0x02]	40515	1			T70	1		T196	7		T195	1
valid_sources[0x03]	39901	1			T143	67		T535	3		T391	142
valid_sources[0x04]	40109	1			T70	1		T195	1		T143	82
valid_sources[0x05]	40677	1			T196	1		T143	101		T391	183
valid_sources[0x06]	40118	1			T196	1		T143	84		T535	1
valid_sources[0x07]	40267	1			T70	2		T143	85		T535	490
valid_sources[0x08]	43755	1			T70	1		T64	2		T195	2
valid_sources[0x09]	39923	1			T64	4		T143	76		T391	193
valid_sources[0x0a]	39947	1			T70	1		T196	1		T143	94
valid_sources[0x0b]	39537	1			T70	1		T64	3		T196	1
valid_sources[0x0c]	40458	1			T143	102		T391	152		T392	83
valid_sources[0x0d]	40336	1			T70	1		T143	85		T535	2
valid_sources[0x0e]	40006	1			T143	95		T391	163		T392	77
valid_sources[0x0f]	40072	1			T70	2		T143	81		T535	10
valid_sources[0x10]	39752	1			T70	1		T195	3		T143	110
valid_sources[0x11]	39683	1			T70	1		T143	84		T535	2
valid_sources[0x12]	40018	1			T64	1		T143	93		T535	15
valid_sources[0x13]	39996	1			T196	4		T143	94		T535	12
valid_sources[0x14]	40183	1			T70	1		T195	1		T143	60
valid_sources[0x15]	39134	1			T143	80		T535	2		T391	194
valid_sources[0x16]	39993	1			T70	1		T143	88		T535	9
valid_sources[0x17]	40956	1			T196	2		T143	80		T391	161
valid_sources[0x18]	39960	1			T70	2		T143	63		T535	3
valid_sources[0x19]	40023	1			T70	1		T195	1		T143	83
valid_sources[0x1a]	41302	1			T195	1		T143	77		T535	8
valid_sources[0x1b]	40326	1			T143	87		T535	9		T391	164
valid_sources[0x1c]	40554	1			T64	1		T143	72		T391	166
valid_sources[0x1d]	40076	1			T70	1		T64	1		T143	76
valid_sources[0x1e]	39756	1			T71	39		T143	71		T391	160
valid_sources[0x1f]	40253	1			T70	1		T64	2		T196	1
valid_sources[0x20]	39867	1			T143	92		T535	5		T391	175

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

25034735

1

T4

7526

T5

74357

T6

2612

values[0x0]

all_enables

biggest_size

9513620

1

T4

12264

T5

12074

T6

3781

values[0x1]

all_enables

biggest_size

241419

1

T70

19

T71

20

T64

20

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2978327	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

471547

1

T76

36

T77

269

T78

234

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1166482	1			T76	129		T77	637		T78	505
values[0x0]	1115835	1			T76	32		T77	647		T78	533
values[0x1]	1167557	1			T76	132		T77	633		T78	578

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2307788	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1142086

1

T76

112

T77

643

T78

527

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	52833	1			T76	4		T77	68		T78	36
valid_sources[0x01]	52782	1			T76	7		T77	31		T78	57
valid_sources[0x02]	53064	1			T76	2		T77	5		T78	36
valid_sources[0x03]	54682	1			T76	2		T77	4		T78	2
valid_sources[0x04]	53565	1			T76	6		T77	23		T78	34
valid_sources[0x05]	54170	1			T76	5		T77	21		T78	19
valid_sources[0x06]	53492	1			T76	5		T77	27		T78	3
valid_sources[0x07]	54245	1			T76	5		T77	16		T78	21
valid_sources[0x08]	54076	1			T76	4		T77	15		T78	16
valid_sources[0x09]	54641	1			T76	3		T77	18		T78	14
valid_sources[0x0a]	54389	1			T76	5		T77	29		T78	26
valid_sources[0x0b]	52478	1			T76	5		T77	31		T78	20
valid_sources[0x0c]	53685	1			T76	4		T77	20		T78	19
valid_sources[0x0d]	53700	1			T76	11		T77	25		T78	20
valid_sources[0x0e]	54248	1			T76	3		T77	34		T78	20
valid_sources[0x0f]	54890	1			T76	3		T77	20		T78	45
valid_sources[0x10]	53104	1			T76	7		T77	45		T78	47
valid_sources[0x11]	54339	1			T76	3		T77	39		T78	32
valid_sources[0x12]	54979	1			T76	3		T78	28		T521	1
valid_sources[0x13]	54638	1			T76	6		T77	50		T78	54
valid_sources[0x14]	52243	1			T76	7		T77	24		T78	10
valid_sources[0x15]	54087	1			T76	5		T77	36		T78	12
valid_sources[0x16]	54808	1			T76	6		T77	19		T78	62
valid_sources[0x17]	52892	1			T76	5		T77	12		T78	33
valid_sources[0x18]	53119	1			T76	1		T77	17		T78	9
valid_sources[0x19]	53262	1			T76	3		T77	7		T78	36
valid_sources[0x1a]	55443	1			T76	5		T77	13		T78	28
valid_sources[0x1b]	54287	1			T76	6		T77	37		T78	19
valid_sources[0x1c]	54836	1			T76	2		T77	49		T78	17
valid_sources[0x1d]	54086	1			T76	9		T77	26		T78	23
valid_sources[0x1e]	52474	1			T76	6		T77	45		T78	26
valid_sources[0x1f]	54050	1			T76	2		T77	37		T78	13
valid_sources[0x20]	54123	1			T76	8		T77	42		T78	26

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

49447

1

T76

13

T77

30

T78

19

values[0x0]

all_enables

biggest_size

372525

1

T76

14

T77

220

T78

188

values[0x1]

all_enables

biggest_size

49575

1

T76

9

T77

19

T78

27

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3190533	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

519910

1

T76

26

T77

311

T78

252

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1270111	1			T76	141		T77	771		T78	541
values[0x0]	1171611	1			T76	27		T77	707		T78	528
values[0x1]	1268721	1			T76	132		T77	709		T78	582

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2449355	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1261088

1

T76

121

T77

745

T78

571

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	56610	1			T76	3		T77	32		T78	35
valid_sources[0x01]	58682	1			T76	7		T77	39		T78	34
valid_sources[0x02]	58370	1			T76	9		T77	38		T78	41
valid_sources[0x03]	58321	1			T76	6		T77	28		T78	23
valid_sources[0x04]	58445	1			T76	7		T77	39		T78	30
valid_sources[0x05]	58110	1			T76	7		T77	30		T78	26
valid_sources[0x06]	58226	1			T76	2		T77	18		T78	21
valid_sources[0x07]	57812	1			T76	7		T77	32		T78	23
valid_sources[0x08]	58696	1			T76	4		T77	36		T78	23
valid_sources[0x09]	58684	1			T76	2		T77	39		T78	27
valid_sources[0x0a]	57810	1			T76	1		T77	34		T78	31
valid_sources[0x0b]	56800	1			T76	3		T77	35		T78	19
valid_sources[0x0c]	58883	1			T76	5		T77	37		T78	31
valid_sources[0x0d]	57945	1			T76	9		T77	42		T78	23
valid_sources[0x0e]	58776	1			T76	5		T77	31		T78	27
valid_sources[0x0f]	57932	1			T76	4		T77	28		T78	16
valid_sources[0x10]	56758	1			T76	4		T77	32		T78	28
valid_sources[0x11]	57690	1			T76	1		T77	38		T78	39
valid_sources[0x12]	58239	1			T76	3		T77	34		T78	19
valid_sources[0x13]	58119	1			T76	4		T77	29		T78	26
valid_sources[0x14]	58004	1			T76	10		T77	39		T78	25
valid_sources[0x15]	58170	1			T76	4		T77	33		T78	20
valid_sources[0x16]	57991	1			T76	3		T77	38		T78	28
valid_sources[0x17]	58040	1			T76	7		T77	32		T78	33
valid_sources[0x18]	57792	1			T76	7		T77	38		T78	24
valid_sources[0x19]	57490	1			T76	4		T77	25		T78	14
valid_sources[0x1a]	59896	1			T76	10		T77	42		T78	22
valid_sources[0x1b]	58069	1			T76	4		T77	28		T78	28
valid_sources[0x1c]	58223	1			T76	11		T77	32		T78	25
valid_sources[0x1d]	58271	1			T76	7		T77	29		T78	31
valid_sources[0x1e]	57948	1			T76	5		T77	30		T78	25
valid_sources[0x1f]	57507	1			T76	7		T77	22		T78	21
valid_sources[0x20]	57490	1			T76	9		T77	38		T78	27

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

54658

1

T76

6

T77

45

T78

23

values[0x0]

all_enables

biggest_size

411125

1

T76

10

T77

234

T78

207

values[0x1]

all_enables

biggest_size

54127

1

T76

10

T77

32

T78

22

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2997673	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

474593

1

T76

29

T77

236

T78

226

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1175035	1			T76	131		T77	613		T78	566
values[0x0]	1123656	1			T76	27		T77	590		T78	559
values[0x1]	1173575	1			T76	154		T77	623		T78	535

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2322537	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1149729

1

T76

122

T77

572

T78

546

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	53548	1			T76	5		T77	22		T78	26
valid_sources[0x01]	54332	1			T76	7		T77	28		T78	20
valid_sources[0x02]	54885	1			T76	4		T77	30		T78	37
valid_sources[0x03]	55062	1			T76	2		T77	34		T78	27
valid_sources[0x04]	54847	1			T76	2		T77	16		T78	37
valid_sources[0x05]	54899	1			T76	3		T77	28		T78	30
valid_sources[0x06]	53569	1			T76	5		T77	18		T78	35
valid_sources[0x07]	54535	1			T76	5		T77	45		T78	29
valid_sources[0x08]	53923	1			T76	4		T77	38		T78	34
valid_sources[0x09]	54801	1			T76	5		T77	37		T78	29
valid_sources[0x0a]	54604	1			T76	3		T77	29		T78	52
valid_sources[0x0b]	53430	1			T76	6		T77	14		T78	18
valid_sources[0x0c]	53915	1			T76	6		T77	38		T78	12
valid_sources[0x0d]	54154	1			T76	8		T77	32		T78	32
valid_sources[0x0e]	54862	1			T76	5		T77	32		T78	21
valid_sources[0x0f]	54366	1			T76	10		T77	32		T78	20
valid_sources[0x10]	53623	1			T76	2		T77	38		T78	34
valid_sources[0x11]	54207	1			T76	6		T77	28		T78	21
valid_sources[0x12]	54818	1			T76	8		T77	25		T78	30
valid_sources[0x13]	55406	1			T76	7		T77	32		T78	24
valid_sources[0x14]	52495	1			T76	6		T77	19		T78	26
valid_sources[0x15]	54944	1			T76	7		T77	16		T78	23
valid_sources[0x16]	55843	1			T76	2		T77	28		T78	22
valid_sources[0x17]	53543	1			T76	3		T77	31		T78	34
valid_sources[0x18]	52850	1			T76	3		T77	21		T78	33
valid_sources[0x19]	54201	1			T76	1		T77	25		T78	15
valid_sources[0x1a]	55242	1			T77	19		T78	8		T521	2
valid_sources[0x1b]	55157	1			T76	10		T77	35		T78	25
valid_sources[0x1c]	54391	1			T76	1		T77	38		T78	23
valid_sources[0x1d]	54223	1			T76	4		T77	26		T78	25
valid_sources[0x1e]	53883	1			T76	2		T77	25		T78	39
valid_sources[0x1f]	54365	1			T76	5		T77	26		T78	29
valid_sources[0x20]	53545	1			T76	4		T77	33		T78	17

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

49749

1

T76

7

T77

14

T78

24

values[0x0]

all_enables

biggest_size

375352

1

T76

8

T77

197

T78

181

values[0x1]

all_enables

biggest_size

49492

1

T76

14

T77

25

T78

21