Unified Coverage Report :: Module Instance :: tb.dut.top_earlgrey.u_uart0.uart_core.u_uart_txfifo

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	514187433	57911819	0	0
DepthKnown_A	514187433	514080758	0	0
RvalidKnown_A	514187433	514080758	0	0
WreadyKnown_A	514187433	514080758	0	0
gen_passthru_fifo.paramCheckPass	1010	1010	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	514187433	57911819	0	0
T4	421177	35606	0	0
T5	938470	114552	0	0
T6	129527	17411	0	0
T18	87616	9463	0	0
T19	513980	64820	0	0
T22	95704	10146	0	0
T44	551953	50259	0	0
T52	124773	12515	0	0
T60	877981	3461	0	0
T86	151811	210993	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	514187433	514080758	0	0
T4	421177	420831	0	0
T5	938470	938419	0	0
T6	129527	129472	0	0
T18	87616	87558	0	0
T19	513980	513868	0	0
T22	95704	95646	0	0
T44	551953	551672	0	0
T52	124773	124711	0	0
T60	877981	877926	0	0
T86	151811	151806	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	514187433	514080758	0	0
T4	421177	420831	0	0
T5	938470	938419	0	0
T6	129527	129472	0	0
T18	87616	87558	0	0
T19	513980	513868	0	0
T22	95704	95646	0	0
T44	551953	551672	0	0
T52	124773	124711	0	0
T60	877981	877926	0	0
T86	151811	151806	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	514187433	514080758	0	0
T4	421177	420831	0	0
T5	938470	938419	0	0
T6	129527	129472	0	0
T18	87616	87558	0	0
T19	513980	513868	0	0
T22	95704	95646	0	0
T44	551953	551672	0	0
T52	124773	124711	0	0
T60	877981	877926	0	0
T86	151811	151806	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1010	1010	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T22	1	1	0	0
T44	1	1	0	0
T52	1	1	0	0
T60	1	1	0	0
T86	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	2	50.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	0	0.00
CONT_ASSIGN	49	1	0	0.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	0	1
49	0	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	514187433	45569027	0	0
DepthKnown_A	514187433	514080758	0	0
RvalidKnown_A	514187433	514080758	0	0
WreadyKnown_A	514187433	514080758	0	0
gen_passthru_fifo.paramCheckPass	1010	1010	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	514187433	45569027	0	0
T4	421177	28084	0	0
T5	938470	95737	0	0
T6	129527	12335	0	0
T18	87616	7289	0	0
T19	513980	60360	0	0
T22	95704	7643	0	0
T44	551953	36970	0	0
T52	124773	8627	0	0
T60	877981	1868	0	0
T86	151811	191634	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	514187433	514080758	0	0
T4	421177	420831	0	0
T5	938470	938419	0	0
T6	129527	129472	0	0
T18	87616	87558	0	0
T19	513980	513868	0	0
T22	95704	95646	0	0
T44	551953	551672	0	0
T52	124773	124711	0	0
T60	877981	877926	0	0
T86	151811	151806	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	514187433	514080758	0	0
T4	421177	420831	0	0
T5	938470	938419	0	0
T6	129527	129472	0	0
T18	87616	87558	0	0
T19	513980	513868	0	0
T22	95704	95646	0	0
T44	551953	551672	0	0
T52	124773	124711	0	0
T60	877981	877926	0	0
T86	151811	151806	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	514187433	514080758	0	0
T4	421177	420831	0	0
T5	938470	938419	0	0
T6	129527	129472	0	0
T18	87616	87558	0	0
T19	513980	513868	0	0
T22	95704	95646	0	0
T44	551953	551672	0	0
T52	124773	124711	0	0
T60	877981	877926	0	0
T86	151811	151806	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1010	1010	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T22	1	1	0	0
T44	1	1	0	0
T52	1	1	0	0
T60	1	1	0	0
T86	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	514187433	40633341	0	0
DepthKnown_A	514187433	514080758	0	0
RvalidKnown_A	514187433	514080758	0	0
WreadyKnown_A	514187433	514080758	0	0
gen_passthru_fifo.paramCheckPass	1010	1010	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	514187433	40633341	0	0
T4	421177	21608	0	0
T5	938470	150390	0	0
T6	129527	6870	0	0
T18	87616	3309	0	0
T19	513980	13095	0	0
T22	95704	8030	0	0
T44	551953	22577	0	0
T52	124773	9782	0	0
T60	877981	459	0	0
T86	151811	386703	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	514187433	514080758	0	0
T4	421177	420831	0	0
T5	938470	938419	0	0
T6	129527	129472	0	0
T18	87616	87558	0	0
T19	513980	513868	0	0
T22	95704	95646	0	0
T44	551953	551672	0	0
T52	124773	124711	0	0
T60	877981	877926	0	0
T86	151811	151806	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	514187433	514080758	0	0
T4	421177	420831	0	0
T5	938470	938419	0	0
T6	129527	129472	0	0
T18	87616	87558	0	0
T19	513980	513868	0	0
T22	95704	95646	0	0
T44	551953	551672	0	0
T52	124773	124711	0	0
T60	877981	877926	0	0
T86	151811	151806	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	514187433	514080758	0	0
T4	421177	420831	0	0
T5	938470	938419	0	0
T6	129527	129472	0	0
T18	87616	87558	0	0
T19	513980	513868	0	0
T22	95704	95646	0	0
T44	551953	551672	0	0
T52	124773	124711	0	0
T60	877981	877926	0	0
T86	151811	151806	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1010	1010	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T22	1	1	0	0
T44	1	1	0	0
T52	1	1	0	0
T60	1	1	0	0
T86	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	514187433	34299498	0	0
DepthKnown_A	514187433	514080758	0	0
RvalidKnown_A	514187433	514080758	0	0
WreadyKnown_A	514187433	514080758	0	0
gen_passthru_fifo.paramCheckPass	1010	1010	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	514187433	34299498	0	0
T4	421177	21100	0	0
T5	938470	86438	0	0
T6	129527	6602	0	0
T18	87616	3183	0	0
T19	513980	12816	0	0
T22	95704	7574	0	0
T44	551953	21809	0	0
T52	124773	9512	0	0
T60	877981	351	0	0
T86	151811	386026	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	514187433	514080758	0	0
T4	421177	420831	0	0
T5	938470	938419	0	0
T6	129527	129472	0	0
T18	87616	87558	0	0
T19	513980	513868	0	0
T22	95704	95646	0	0
T44	551953	551672	0	0
T52	124773	124711	0	0
T60	877981	877926	0	0
T86	151811	151806	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	514187433	514080758	0	0
T4	421177	420831	0	0
T5	938470	938419	0	0
T6	129527	129472	0	0
T18	87616	87558	0	0
T19	513980	513868	0	0
T22	95704	95646	0	0
T44	551953	551672	0	0
T52	124773	124711	0	0
T60	877981	877926	0	0
T86	151811	151806	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	514187433	514080758	0	0
T4	421177	420831	0	0
T5	938470	938419	0	0
T6	129527	129472	0	0
T18	87616	87558	0	0
T19	513980	513868	0	0
T22	95704	95646	0	0
T44	551953	551672	0	0
T52	124773	124711	0	0
T60	877981	877926	0	0
T86	151811	151806	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1010	1010	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T22	1	1	0	0
T44	1	1	0	0
T52	1	1	0	0
T60	1	1	0	0
T86	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	597954551	97048	0	0
DepthKnown_A	597954551	597835643	0	0
RvalidKnown_A	597954551	597835643	0	0
WreadyKnown_A	597954551	597835643	0	0
gen_passthru_fifo.paramCheckPass	2901	2901	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	597954551	97048	0	0
T4	421177	68	0	0
T5	938470	34	0	0
T6	129527	26	0	0
T18	87616	16	0	0
T19	513980	30	0	0
T22	95704	208	0	0
T44	551953	181	0	0
T52	124773	94	0	0
T60	877981	8	0	0
T86	151811	89	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	597954551	597835643	0	0
T4	421177	420831	0	0
T5	938470	938419	0	0
T6	129527	129472	0	0
T18	87616	87558	0	0
T19	513980	513868	0	0
T22	95704	95646	0	0
T44	551953	551672	0	0
T52	124773	124711	0	0
T60	877981	877926	0	0
T86	151811	151806	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	597954551	597835643	0	0
T4	421177	420831	0	0
T5	938470	938419	0	0
T6	129527	129472	0	0
T18	87616	87558	0	0
T19	513980	513868	0	0
T22	95704	95646	0	0
T44	551953	551672	0	0
T52	124773	124711	0	0
T60	877981	877926	0	0
T86	151811	151806	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	597954551	597835643	0	0
T4	421177	420831	0	0
T5	938470	938419	0	0
T6	129527	129472	0	0
T18	87616	87558	0	0
T19	513980	513868	0	0
T22	95704	95646	0	0
T44	551953	551672	0	0
T52	124773	124711	0	0
T60	877981	877926	0	0
T86	151811	151806	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2901	2901	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T22	1	1	0	0
T44	1	1	0	0
T52	1	1	0	0
T60	1	1	0	0
T86	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	597954551	100964	0	0
DepthKnown_A	597954551	597835643	0	0
RvalidKnown_A	597954551	597835643	0	0
WreadyKnown_A	597954551	597835643	0	0
gen_passthru_fifo.paramCheckPass	2901	2901	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	597954551	100964	0	0
T4	421177	68	0	0
T5	938470	34	0	0
T6	129527	26	0	0
T18	87616	16	0	0
T19	513980	30	0	0
T22	95704	208	0	0
T44	551953	181	0	0
T52	124773	94	0	0
T60	877981	8	0	0
T86	151811	89	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	597954551	597835643	0	0
T4	421177	420831	0	0
T5	938470	938419	0	0
T6	129527	129472	0	0
T18	87616	87558	0	0
T19	513980	513868	0	0
T22	95704	95646	0	0
T44	551953	551672	0	0
T52	124773	124711	0	0
T60	877981	877926	0	0
T86	151811	151806	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	597954551	597835643	0	0
T4	421177	420831	0	0
T5	938470	938419	0	0
T6	129527	129472	0	0
T18	87616	87558	0	0
T19	513980	513868	0	0
T22	95704	95646	0	0
T44	551953	551672	0	0
T52	124773	124711	0	0
T60	877981	877926	0	0
T86	151811	151806	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	597954551	597835643	0	0
T4	421177	420831	0	0
T5	938470	938419	0	0
T6	129527	129472	0	0
T18	87616	87558	0	0
T19	513980	513868	0	0
T22	95704	95646	0	0
T44	551953	551672	0	0
T52	124773	124711	0	0
T60	877981	877926	0	0
T86	151811	151806	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2901	2901	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T22	1	1	0	0
T44	1	1	0	0
T52	1	1	0	0
T60	1	1	0	0
T86	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	597954551	52884	0	0
DepthKnown_A	597954551	597835643	0	0
RvalidKnown_A	597954551	597835643	0	0
WreadyKnown_A	597954551	597835643	0	0
gen_passthru_fifo.paramCheckPass	2901	2901	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	597954551	52884	0	0
T4	421177	64	0	0
T5	938470	5	0	0
T6	129527	23	0	0
T18	87616	13	0	0
T19	513980	28	0	0
T22	95704	205	0	0
T44	551953	176	0	0
T52	124773	93	0	0
T60	877981	8	0	0
T86	151811	40	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	597954551	597835643	0	0
T4	421177	420831	0	0
T5	938470	938419	0	0
T6	129527	129472	0	0
T18	87616	87558	0	0
T19	513980	513868	0	0
T22	95704	95646	0	0
T44	551953	551672	0	0
T52	124773	124711	0	0
T60	877981	877926	0	0
T86	151811	151806	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	597954551	597835643	0	0
T4	421177	420831	0	0
T5	938470	938419	0	0
T6	129527	129472	0	0
T18	87616	87558	0	0
T19	513980	513868	0	0
T22	95704	95646	0	0
T44	551953	551672	0	0
T52	124773	124711	0	0
T60	877981	877926	0	0
T86	151811	151806	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	597954551	597835643	0	0
T4	421177	420831	0	0
T5	938470	938419	0	0
T6	129527	129472	0	0
T18	87616	87558	0	0
T19	513980	513868	0	0
T22	95704	95646	0	0
T44	551953	551672	0	0
T52	124773	124711	0	0
T60	877981	877926	0	0
T86	151811	151806	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2901	2901	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T22	1	1	0	0
T44	1	1	0	0
T52	1	1	0	0
T60	1	1	0	0
T86	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	597954551	52884	0	0
DepthKnown_A	597954551	597835643	0	0
RvalidKnown_A	597954551	597835643	0	0
WreadyKnown_A	597954551	597835643	0	0
gen_passthru_fifo.paramCheckPass	2901	2901	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	597954551	52884	0	0
T4	421177	64	0	0
T5	938470	5	0	0
T6	129527	23	0	0
T18	87616	13	0	0
T19	513980	28	0	0
T22	95704	205	0	0
T44	551953	176	0	0
T52	124773	93	0	0
T60	877981	8	0	0
T86	151811	40	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	597954551	597835643	0	0
T4	421177	420831	0	0
T5	938470	938419	0	0
T6	129527	129472	0	0
T18	87616	87558	0	0
T19	513980	513868	0	0
T22	95704	95646	0	0
T44	551953	551672	0	0
T52	124773	124711	0	0
T60	877981	877926	0	0
T86	151811	151806	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	597954551	597835643	0	0
T4	421177	420831	0	0
T5	938470	938419	0	0
T6	129527	129472	0	0
T18	87616	87558	0	0
T19	513980	513868	0	0
T22	95704	95646	0	0
T44	551953	551672	0	0
T52	124773	124711	0	0
T60	877981	877926	0	0
T86	151811	151806	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	597954551	597835643	0	0
T4	421177	420831	0	0
T5	938470	938419	0	0
T6	129527	129472	0	0
T18	87616	87558	0	0
T19	513980	513868	0	0
T22	95704	95646	0	0
T44	551953	551672	0	0
T52	124773	124711	0	0
T60	877981	877926	0	0
T86	151811	151806	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2901	2901	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T22	1	1	0	0
T44	1	1	0	0
T52	1	1	0	0
T60	1	1	0	0
T86	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	597954551	44164	0	0
DepthKnown_A	597954551	597835643	0	0
RvalidKnown_A	597954551	597835643	0	0
WreadyKnown_A	597954551	597835643	0	0
gen_passthru_fifo.paramCheckPass	2901	2901	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	597954551	44164	0	0
T4	421177	4	0	0
T5	938470	29	0	0
T6	129527	3	0	0
T18	87616	3	0	0
T19	513980	2	0	0
T22	95704	3	0	0
T44	551953	5	0	0
T52	124773	1	0	0
T60	877981	0	0	0
T62	0	1	0	0
T86	151811	49	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	597954551	597835643	0	0
T4	421177	420831	0	0
T5	938470	938419	0	0
T6	129527	129472	0	0
T18	87616	87558	0	0
T19	513980	513868	0	0
T22	95704	95646	0	0
T44	551953	551672	0	0
T52	124773	124711	0	0
T60	877981	877926	0	0
T86	151811	151806	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	597954551	597835643	0	0
T4	421177	420831	0	0
T5	938470	938419	0	0
T6	129527	129472	0	0
T18	87616	87558	0	0
T19	513980	513868	0	0
T22	95704	95646	0	0
T44	551953	551672	0	0
T52	124773	124711	0	0
T60	877981	877926	0	0
T86	151811	151806	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	597954551	597835643	0	0
T4	421177	420831	0	0
T5	938470	938419	0	0
T6	129527	129472	0	0
T18	87616	87558	0	0
T19	513980	513868	0	0
T22	95704	95646	0	0
T44	551953	551672	0	0
T52	124773	124711	0	0
T60	877981	877926	0	0
T86	151811	151806	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2901	2901	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T22	1	1	0	0
T44	1	1	0	0
T52	1	1	0	0
T60	1	1	0	0
T86	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	597954551	48080	0	0
DepthKnown_A	597954551	597835643	0	0
RvalidKnown_A	597954551	597835643	0	0
WreadyKnown_A	597954551	597835643	0	0
gen_passthru_fifo.paramCheckPass	2901	2901	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	597954551	48080	0	0
T4	421177	4	0	0
T5	938470	29	0	0
T6	129527	3	0	0
T18	87616	3	0	0
T19	513980	2	0	0
T22	95704	3	0	0
T44	551953	5	0	0
T52	124773	1	0	0
T60	877981	0	0	0
T62	0	1	0	0
T86	151811	49	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	597954551	597835643	0	0
T4	421177	420831	0	0
T5	938470	938419	0	0
T6	129527	129472	0	0
T18	87616	87558	0	0
T19	513980	513868	0	0
T22	95704	95646	0	0
T44	551953	551672	0	0
T52	124773	124711	0	0
T60	877981	877926	0	0
T86	151811	151806	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	597954551	597835643	0	0
T4	421177	420831	0	0
T5	938470	938419	0	0
T6	129527	129472	0	0
T18	87616	87558	0	0
T19	513980	513868	0	0
T22	95704	95646	0	0
T44	551953	551672	0	0
T52	124773	124711	0	0
T60	877981	877926	0	0
T86	151811	151806	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	597954551	597835643	0	0
T4	421177	420831	0	0
T5	938470	938419	0	0
T6	129527	129472	0	0
T18	87616	87558	0	0
T19	513980	513868	0	0
T22	95704	95646	0	0
T44	551953	551672	0	0
T52	124773	124711	0	0
T60	877981	877926	0	0
T86	151811	151806	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2901	2901	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T22	1	1	0	0
T44	1	1	0	0
T52	1	1	0	0
T60	1	1	0	0
T86	1	1	0	0