Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[21].u_mio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 8 | 8 | 100.00 |
| CONT_ASSIGN | 39 | 0 | 0 | |
| CONT_ASSIGN | 51 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 78 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 80 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 84 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 92 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 95 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 39 |
|
unreachable |
| 51 |
1 |
1 |
| 78 |
1 |
1 |
| 80 |
1 |
1 |
| 84 |
1 |
1 |
| 85 |
1 |
1 |
| 92 |
1 |
1 |
| 93 |
1 |
1 |
| 95 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[21].u_mio_pad.gen_generic.u_impl_generic
| Total | Covered | Percent |
|---|
| Conditions | 33 | 33 | 100.00 |
| Logical | 33 | 33 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 51
EXPRESSION (ie_i & ((~attr_i.input_disable)))
--1- ------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Unreachable | |
| 1 | 0 | Covered | T41,T42,T43 |
| 1 | 1 | Covered | T4,T5,T6 |
LINE 78
EXPRESSION (ie ? inout_io : 1'bz)
-1
| -1- | Status | Tests |
|---|
| 0 | Covered | T41,T42,T43 |
| 1 | Covered | T4,T5,T6 |
LINE 80
EXPRESSION (attr_i.invert ^ in_raw_o)
------1------ ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T22,T19,T70 |
| 0 | 1 | Covered | T22,T19,T108 |
| 1 | 0 | Covered | T41,T42,T43 |
| 1 | 1 | Covered | T41,T42,T43 |
LINE 84
EXPRESSION (out_i ^ attr_i.invert)
--1-- ------2------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T4,T5,T6 |
| 0 | 1 | Covered | T41,T42,T43 |
| 1 | 0 | Covered | T19,T108,T212 |
| 1 | 1 | Covered | T41,T42,T43 |
LINE 85
EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
--1- ---------------------------------2---------------------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | Covered | T41,T42,T43 |
| 1 | 1 | Covered | T19,T108,T212 |
LINE 85
SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
--------------------1------------------- -----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T41,T42,T43 |
| 0 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | Covered | T41,T42,T43 |
LINE 85
SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
--------1-------- ---------2--------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | Covered | T41,T42,T43 |
| 1 | 1 | Covered | T41,T42,T43 |
LINE 92
EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
---------------------1--------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T41,T42,T43 |
LINE 92
SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
------1----- ------------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T41,T42,T43 |
| 1 | 0 | Covered | T19,T108,T212 |
| 1 | 1 | Covered | T41,T42,T43 |
LINE 93
EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
-----------------------1-----------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T19,T108,T212 |
LINE 93
SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
------1----- --------------2--------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | Covered | T41,T42,T43 |
| 1 | 1 | Covered | T19,T108,T212 |
LINE 95
EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
-------1------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T41,T42,T43 |
Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[21].u_mio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
8 |
8 |
100.00 |
| TERNARY |
78 |
2 |
2 |
100.00 |
| TERNARY |
92 |
2 |
2 |
100.00 |
| TERNARY |
93 |
2 |
2 |
100.00 |
| TERNARY |
95 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 78 (ie) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T4,T5,T6 |
| 0 |
Covered |
T41,T42,T43 |
LineNo. Expression
-1-: 92 ((gen_bidir.oe && attr_i.drive_strength[0])) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T41,T42,T43 |
| 0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 93 ((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T19,T108,T212 |
| 0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 95 (attr_i.pull_en) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T41,T42,T43 |
| 0 |
Covered |
T4,T5,T6 |
Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[21].u_mio_pad.gen_generic.u_impl_generic
Assertion Details
| Name | Attempts | Real Successes | Failures | Incomplete |
|
AnalogNoScan_A |
1010 |
1010 |
0 |
0 |
AnalogNoScan_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
1010 |
1010 |
0 |
0 |
| T4 |
1 |
1 |
0 |
0 |
| T5 |
1 |
1 |
0 |
0 |
| T6 |
1 |
1 |
0 |
0 |
| T18 |
1 |
1 |
0 |
0 |
| T19 |
1 |
1 |
0 |
0 |
| T22 |
1 |
1 |
0 |
0 |
| T44 |
1 |
1 |
0 |
0 |
| T52 |
1 |
1 |
0 |
0 |
| T60 |
1 |
1 |
0 |
0 |
| T86 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[22].u_mio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 8 | 8 | 100.00 |
| CONT_ASSIGN | 39 | 0 | 0 | |
| CONT_ASSIGN | 51 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 78 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 80 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 84 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 92 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 95 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 39 |
|
unreachable |
| 51 |
1 |
1 |
| 78 |
1 |
1 |
| 80 |
1 |
1 |
| 84 |
1 |
1 |
| 85 |
1 |
1 |
| 92 |
1 |
1 |
| 93 |
1 |
1 |
| 95 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[22].u_mio_pad.gen_generic.u_impl_generic
| Total | Covered | Percent |
|---|
| Conditions | 33 | 33 | 100.00 |
| Logical | 33 | 33 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 51
EXPRESSION (ie_i & ((~attr_i.input_disable)))
--1- ------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Unreachable | |
| 1 | 0 | Covered | T41,T42,T43 |
| 1 | 1 | Covered | T4,T5,T6 |
LINE 78
EXPRESSION (ie ? inout_io : 1'bz)
-1
| -1- | Status | Tests |
|---|
| 0 | Covered | T41,T42,T43 |
| 1 | Covered | T4,T5,T6 |
LINE 80
EXPRESSION (attr_i.invert ^ in_raw_o)
------1------ ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T4,T5,T6 |
| 0 | 1 | Covered | T5,T58,T59 |
| 1 | 0 | Covered | T41,T42,T43 |
| 1 | 1 | Covered | T41,T42,T43 |
LINE 84
EXPRESSION (out_i ^ attr_i.invert)
--1-- ------2------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T4,T5,T6 |
| 0 | 1 | Covered | T41,T42,T43 |
| 1 | 0 | Covered | T23,T41,T42 |
| 1 | 1 | Covered | T41,T42,T43 |
LINE 85
EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
--1- ---------------------------------2---------------------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | Covered | T41,T42,T43 |
| 1 | 1 | Covered | T22,T23,T41 |
LINE 85
SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
--------------------1------------------- -----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T41,T42,T43 |
| 0 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | Covered | T41,T42,T43 |
LINE 85
SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
--------1-------- ---------2--------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | Covered | T41,T42,T43 |
| 1 | 1 | Covered | T41,T42,T43 |
LINE 92
EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
---------------------1--------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T41,T42,T43 |
LINE 92
SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
------1----- ------------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T41,T42,T43 |
| 1 | 0 | Covered | T22,T23,T41 |
| 1 | 1 | Covered | T41,T42,T43 |
LINE 93
EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
-----------------------1-----------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T22,T23,T41 |
LINE 93
SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
------1----- --------------2--------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | Covered | T41,T42,T43 |
| 1 | 1 | Covered | T22,T23,T41 |
LINE 95
EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
-------1------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T5,T58,T59 |
Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[22].u_mio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
8 |
8 |
100.00 |
| TERNARY |
78 |
2 |
2 |
100.00 |
| TERNARY |
92 |
2 |
2 |
100.00 |
| TERNARY |
93 |
2 |
2 |
100.00 |
| TERNARY |
95 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 78 (ie) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T4,T5,T6 |
| 0 |
Covered |
T41,T42,T43 |
LineNo. Expression
-1-: 92 ((gen_bidir.oe && attr_i.drive_strength[0])) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T41,T42,T43 |
| 0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 93 ((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T22,T23,T41 |
| 0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 95 (attr_i.pull_en) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T5,T58,T59 |
| 0 |
Covered |
T4,T5,T6 |
Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[22].u_mio_pad.gen_generic.u_impl_generic
Assertion Details
| Name | Attempts | Real Successes | Failures | Incomplete |
|
AnalogNoScan_A |
1010 |
1010 |
0 |
0 |
AnalogNoScan_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
1010 |
1010 |
0 |
0 |
| T4 |
1 |
1 |
0 |
0 |
| T5 |
1 |
1 |
0 |
0 |
| T6 |
1 |
1 |
0 |
0 |
| T18 |
1 |
1 |
0 |
0 |
| T19 |
1 |
1 |
0 |
0 |
| T22 |
1 |
1 |
0 |
0 |
| T44 |
1 |
1 |
0 |
0 |
| T52 |
1 |
1 |
0 |
0 |
| T60 |
1 |
1 |
0 |
0 |
| T86 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[23].u_mio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 8 | 8 | 100.00 |
| CONT_ASSIGN | 39 | 0 | 0 | |
| CONT_ASSIGN | 51 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 78 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 80 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 84 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 92 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 95 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 39 |
|
unreachable |
| 51 |
1 |
1 |
| 78 |
1 |
1 |
| 80 |
1 |
1 |
| 84 |
1 |
1 |
| 85 |
1 |
1 |
| 92 |
1 |
1 |
| 93 |
1 |
1 |
| 95 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[23].u_mio_pad.gen_generic.u_impl_generic
| Total | Covered | Percent |
|---|
| Conditions | 33 | 33 | 100.00 |
| Logical | 33 | 33 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 51
EXPRESSION (ie_i & ((~attr_i.input_disable)))
--1- ------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Unreachable | |
| 1 | 0 | Covered | T41,T42,T43 |
| 1 | 1 | Covered | T4,T5,T6 |
LINE 78
EXPRESSION (ie ? inout_io : 1'bz)
-1
| -1- | Status | Tests |
|---|
| 0 | Covered | T41,T42,T43 |
| 1 | Covered | T4,T5,T6 |
LINE 80
EXPRESSION (attr_i.invert ^ in_raw_o)
------1------ ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T4,T5,T6 |
| 0 | 1 | Covered | T85,T142,T23 |
| 1 | 0 | Covered | T41,T42,T43 |
| 1 | 1 | Covered | T41,T42,T43 |
LINE 84
EXPRESSION (out_i ^ attr_i.invert)
--1-- ------2------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T4,T5,T6 |
| 0 | 1 | Covered | T41,T42,T43 |
| 1 | 0 | Covered | T41,T42,T43 |
| 1 | 1 | Covered | T41,T42,T43 |
LINE 85
EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
--1- ---------------------------------2---------------------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | Covered | T41,T42,T43 |
| 1 | 1 | Covered | T22,T41,T42 |
LINE 85
SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
--------------------1------------------- -----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T41,T42,T43 |
| 0 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | Covered | T41,T42,T43 |
LINE 85
SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
--------1-------- ---------2--------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | Covered | T41,T42,T43 |
| 1 | 1 | Covered | T41,T42,T43 |
LINE 92
EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
---------------------1--------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T41,T42,T43 |
LINE 92
SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
------1----- ------------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T41,T42,T43 |
| 1 | 0 | Covered | T22,T41,T42 |
| 1 | 1 | Covered | T41,T42,T43 |
LINE 93
EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
-----------------------1-----------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T22,T41,T42 |
LINE 93
SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
------1----- --------------2--------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | Covered | T41,T42,T43 |
| 1 | 1 | Covered | T22,T41,T42 |
LINE 95
EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
-------1------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T5,T58,T59 |
Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[23].u_mio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
8 |
8 |
100.00 |
| TERNARY |
78 |
2 |
2 |
100.00 |
| TERNARY |
92 |
2 |
2 |
100.00 |
| TERNARY |
93 |
2 |
2 |
100.00 |
| TERNARY |
95 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 78 (ie) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T4,T5,T6 |
| 0 |
Covered |
T41,T42,T43 |
LineNo. Expression
-1-: 92 ((gen_bidir.oe && attr_i.drive_strength[0])) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T41,T42,T43 |
| 0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 93 ((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T22,T41,T42 |
| 0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 95 (attr_i.pull_en) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T5,T58,T59 |
| 0 |
Covered |
T4,T5,T6 |
Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[23].u_mio_pad.gen_generic.u_impl_generic
Assertion Details
| Name | Attempts | Real Successes | Failures | Incomplete |
|
AnalogNoScan_A |
1010 |
1010 |
0 |
0 |
AnalogNoScan_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
1010 |
1010 |
0 |
0 |
| T4 |
1 |
1 |
0 |
0 |
| T5 |
1 |
1 |
0 |
0 |
| T6 |
1 |
1 |
0 |
0 |
| T18 |
1 |
1 |
0 |
0 |
| T19 |
1 |
1 |
0 |
0 |
| T22 |
1 |
1 |
0 |
0 |
| T44 |
1 |
1 |
0 |
0 |
| T52 |
1 |
1 |
0 |
0 |
| T60 |
1 |
1 |
0 |
0 |
| T86 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[24].u_mio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 8 | 8 | 100.00 |
| CONT_ASSIGN | 39 | 0 | 0 | |
| CONT_ASSIGN | 51 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 78 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 80 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 84 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 92 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 95 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 39 |
|
unreachable |
| 51 |
1 |
1 |
| 78 |
1 |
1 |
| 80 |
1 |
1 |
| 84 |
1 |
1 |
| 85 |
1 |
1 |
| 92 |
1 |
1 |
| 93 |
1 |
1 |
| 95 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[24].u_mio_pad.gen_generic.u_impl_generic
| Total | Covered | Percent |
|---|
| Conditions | 33 | 33 | 100.00 |
| Logical | 33 | 33 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 51
EXPRESSION (ie_i & ((~attr_i.input_disable)))
--1- ------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Unreachable | |
| 1 | 0 | Covered | T41,T42,T43 |
| 1 | 1 | Covered | T4,T5,T6 |
LINE 78
EXPRESSION (ie ? inout_io : 1'bz)
-1
| -1- | Status | Tests |
|---|
| 0 | Covered | T41,T42,T43 |
| 1 | Covered | T4,T5,T6 |
LINE 80
EXPRESSION (attr_i.invert ^ in_raw_o)
------1------ ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T4,T5,T6 |
| 0 | 1 | Covered | T22,T85,T142 |
| 1 | 0 | Covered | T41,T42,T43 |
| 1 | 1 | Covered | T41,T42,T43 |
LINE 84
EXPRESSION (out_i ^ attr_i.invert)
--1-- ------2------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T4,T5,T6 |
| 0 | 1 | Covered | T41,T42,T43 |
| 1 | 0 | Covered | T22,T41,T42 |
| 1 | 1 | Covered | T41,T42,T43 |
LINE 85
EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
--1- ---------------------------------2---------------------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | Covered | T41,T42,T43 |
| 1 | 1 | Covered | T22,T23,T41 |
LINE 85
SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
--------------------1------------------- -----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T41,T42,T43 |
| 0 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | Covered | T41,T42,T43 |
LINE 85
SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
--------1-------- ---------2--------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | Covered | T41,T42,T43 |
| 1 | 1 | Covered | T41,T42,T43 |
LINE 92
EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
---------------------1--------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T41,T42,T43 |
LINE 92
SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
------1----- ------------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T41,T42,T43 |
| 1 | 0 | Covered | T22,T23,T41 |
| 1 | 1 | Covered | T41,T42,T43 |
LINE 93
EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
-----------------------1-----------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T22,T23,T41 |
LINE 93
SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
------1----- --------------2--------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | Covered | T41,T42,T43 |
| 1 | 1 | Covered | T22,T23,T41 |
LINE 95
EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
-------1------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T5,T58,T59 |
Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[24].u_mio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
8 |
8 |
100.00 |
| TERNARY |
78 |
2 |
2 |
100.00 |
| TERNARY |
92 |
2 |
2 |
100.00 |
| TERNARY |
93 |
2 |
2 |
100.00 |
| TERNARY |
95 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 78 (ie) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T4,T5,T6 |
| 0 |
Covered |
T41,T42,T43 |
LineNo. Expression
-1-: 92 ((gen_bidir.oe && attr_i.drive_strength[0])) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T41,T42,T43 |
| 0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 93 ((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T22,T23,T41 |
| 0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 95 (attr_i.pull_en) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T5,T58,T59 |
| 0 |
Covered |
T4,T5,T6 |
Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[24].u_mio_pad.gen_generic.u_impl_generic
Assertion Details
| Name | Attempts | Real Successes | Failures | Incomplete |
|
AnalogNoScan_A |
1010 |
1010 |
0 |
0 |
AnalogNoScan_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
1010 |
1010 |
0 |
0 |
| T4 |
1 |
1 |
0 |
0 |
| T5 |
1 |
1 |
0 |
0 |
| T6 |
1 |
1 |
0 |
0 |
| T18 |
1 |
1 |
0 |
0 |
| T19 |
1 |
1 |
0 |
0 |
| T22 |
1 |
1 |
0 |
0 |
| T44 |
1 |
1 |
0 |
0 |
| T52 |
1 |
1 |
0 |
0 |
| T60 |
1 |
1 |
0 |
0 |
| T86 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[25].u_mio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 8 | 8 | 100.00 |
| CONT_ASSIGN | 39 | 0 | 0 | |
| CONT_ASSIGN | 51 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 78 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 80 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 84 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 92 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 95 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 39 |
|
unreachable |
| 51 |
1 |
1 |
| 78 |
1 |
1 |
| 80 |
1 |
1 |
| 84 |
1 |
1 |
| 85 |
1 |
1 |
| 92 |
1 |
1 |
| 93 |
1 |
1 |
| 95 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[25].u_mio_pad.gen_generic.u_impl_generic
| Total | Covered | Percent |
|---|
| Conditions | 33 | 33 | 100.00 |
| Logical | 33 | 33 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 51
EXPRESSION (ie_i & ((~attr_i.input_disable)))
--1- ------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Unreachable | |
| 1 | 0 | Covered | T41,T42,T43 |
| 1 | 1 | Covered | T4,T5,T6 |
LINE 78
EXPRESSION (ie ? inout_io : 1'bz)
-1
| -1- | Status | Tests |
|---|
| 0 | Covered | T41,T42,T43 |
| 1 | Covered | T4,T5,T6 |
LINE 80
EXPRESSION (attr_i.invert ^ in_raw_o)
------1------ ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T22,T70,T71 |
| 0 | 1 | Covered | T4,T6,T22 |
| 1 | 0 | Covered | T41,T42,T43 |
| 1 | 1 | Covered | T41,T42,T43 |
LINE 84
EXPRESSION (out_i ^ attr_i.invert)
--1-- ------2------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T4,T5,T6 |
| 0 | 1 | Covered | T41,T42,T43 |
| 1 | 0 | Covered | T24,T41,T42 |
| 1 | 1 | Covered | T41,T42,T43 |
LINE 85
EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
--1- ---------------------------------2---------------------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | Covered | T41,T42,T43 |
| 1 | 1 | Covered | T24,T41,T42 |
LINE 85
SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
--------------------1------------------- -----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T41,T42,T43 |
| 0 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | Covered | T41,T42,T43 |
LINE 85
SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
--------1-------- ---------2--------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | Covered | T41,T42,T43 |
| 1 | 1 | Covered | T41,T42,T43 |
LINE 92
EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
---------------------1--------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T41,T42,T43 |
LINE 92
SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
------1----- ------------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T41,T42,T43 |
| 1 | 0 | Covered | T24,T41,T42 |
| 1 | 1 | Covered | T41,T42,T43 |
LINE 93
EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
-----------------------1-----------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T24,T41,T42 |
LINE 93
SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
------1----- --------------2--------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | Covered | T41,T42,T43 |
| 1 | 1 | Covered | T24,T41,T42 |
LINE 95
EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
-------1------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T4,T6,T22 |
Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[25].u_mio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
8 |
8 |
100.00 |
| TERNARY |
78 |
2 |
2 |
100.00 |
| TERNARY |
92 |
2 |
2 |
100.00 |
| TERNARY |
93 |
2 |
2 |
100.00 |
| TERNARY |
95 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 78 (ie) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T4,T5,T6 |
| 0 |
Covered |
T41,T42,T43 |
LineNo. Expression
-1-: 92 ((gen_bidir.oe && attr_i.drive_strength[0])) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T41,T42,T43 |
| 0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 93 ((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T24,T41,T42 |
| 0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 95 (attr_i.pull_en) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T4,T6,T22 |
| 0 |
Covered |
T4,T5,T6 |
Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[25].u_mio_pad.gen_generic.u_impl_generic
Assertion Details
| Name | Attempts | Real Successes | Failures | Incomplete |
|
AnalogNoScan_A |
1010 |
1010 |
0 |
0 |
AnalogNoScan_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
1010 |
1010 |
0 |
0 |
| T4 |
1 |
1 |
0 |
0 |
| T5 |
1 |
1 |
0 |
0 |
| T6 |
1 |
1 |
0 |
0 |
| T18 |
1 |
1 |
0 |
0 |
| T19 |
1 |
1 |
0 |
0 |
| T22 |
1 |
1 |
0 |
0 |
| T44 |
1 |
1 |
0 |
0 |
| T52 |
1 |
1 |
0 |
0 |
| T60 |
1 |
1 |
0 |
0 |
| T86 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[26].u_mio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 8 | 8 | 100.00 |
| CONT_ASSIGN | 39 | 0 | 0 | |
| CONT_ASSIGN | 51 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 78 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 80 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 84 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 92 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 95 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 39 |
|
unreachable |
| 51 |
1 |
1 |
| 78 |
1 |
1 |
| 80 |
1 |
1 |
| 84 |
1 |
1 |
| 85 |
1 |
1 |
| 92 |
1 |
1 |
| 93 |
1 |
1 |
| 95 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[26].u_mio_pad.gen_generic.u_impl_generic
| Total | Covered | Percent |
|---|
| Conditions | 33 | 33 | 100.00 |
| Logical | 33 | 33 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 51
EXPRESSION (ie_i & ((~attr_i.input_disable)))
--1- ------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Unreachable | |
| 1 | 0 | Covered | T41,T42,T43 |
| 1 | 1 | Covered | T4,T5,T6 |
LINE 78
EXPRESSION (ie ? inout_io : 1'bz)
-1
| -1- | Status | Tests |
|---|
| 0 | Covered | T41,T42,T43 |
| 1 | Covered | T4,T5,T6 |
LINE 80
EXPRESSION (attr_i.invert ^ in_raw_o)
------1------ ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T5,T22,T58 |
| 0 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | Covered | T41,T42,T43 |
| 1 | 1 | Covered | T41,T42,T183 |
LINE 84
EXPRESSION (out_i ^ attr_i.invert)
--1-- ------2------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T4,T5,T6 |
| 0 | 1 | Covered | T41,T42,T43 |
| 1 | 0 | Covered | T4,T5,T6 |
| 1 | 1 | Covered | T41,T42,T43 |
LINE 85
EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
--1- ---------------------------------2---------------------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | Covered | T41,T42,T43 |
| 1 | 1 | Covered | T4,T5,T6 |
LINE 85
SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
--------------------1------------------- -----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T41,T42,T43 |
| 0 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | Covered | T41,T42,T43 |
LINE 85
SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
--------1-------- ---------2--------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | Covered | T41,T42,T43 |
| 1 | 1 | Covered | T41,T42,T43 |
LINE 92
EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
---------------------1--------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T41,T42,T43 |
LINE 92
SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
------1----- ------------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T41,T42,T43 |
| 1 | 0 | Covered | T4,T5,T6 |
| 1 | 1 | Covered | T41,T42,T43 |
LINE 93
EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
-----------------------1-----------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T4,T5,T6 |
LINE 93
SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
------1----- --------------2--------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | Covered | T41,T42,T43 |
| 1 | 1 | Covered | T4,T5,T6 |
LINE 95
EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
-------1------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T41,T42,T43 |
Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[26].u_mio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
8 |
8 |
100.00 |
| TERNARY |
78 |
2 |
2 |
100.00 |
| TERNARY |
92 |
2 |
2 |
100.00 |
| TERNARY |
93 |
2 |
2 |
100.00 |
| TERNARY |
95 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 78 (ie) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T4,T5,T6 |
| 0 |
Covered |
T41,T42,T43 |
LineNo. Expression
-1-: 92 ((gen_bidir.oe && attr_i.drive_strength[0])) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T41,T42,T43 |
| 0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 93 ((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T4,T5,T6 |
| 0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 95 (attr_i.pull_en) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T41,T42,T43 |
| 0 |
Covered |
T4,T5,T6 |
Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[26].u_mio_pad.gen_generic.u_impl_generic
Assertion Details
| Name | Attempts | Real Successes | Failures | Incomplete |
|
AnalogNoScan_A |
1010 |
1010 |
0 |
0 |
AnalogNoScan_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
1010 |
1010 |
0 |
0 |
| T4 |
1 |
1 |
0 |
0 |
| T5 |
1 |
1 |
0 |
0 |
| T6 |
1 |
1 |
0 |
0 |
| T18 |
1 |
1 |
0 |
0 |
| T19 |
1 |
1 |
0 |
0 |
| T22 |
1 |
1 |
0 |
0 |
| T44 |
1 |
1 |
0 |
0 |
| T52 |
1 |
1 |
0 |
0 |
| T60 |
1 |
1 |
0 |
0 |
| T86 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[27].u_mio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 8 | 8 | 100.00 |
| CONT_ASSIGN | 39 | 0 | 0 | |
| CONT_ASSIGN | 51 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 78 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 80 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 84 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 92 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 95 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 39 |
|
unreachable |
| 51 |
1 |
1 |
| 78 |
1 |
1 |
| 80 |
1 |
1 |
| 84 |
1 |
1 |
| 85 |
1 |
1 |
| 92 |
1 |
1 |
| 93 |
1 |
1 |
| 95 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[27].u_mio_pad.gen_generic.u_impl_generic
| Total | Covered | Percent |
|---|
| Conditions | 33 | 33 | 100.00 |
| Logical | 33 | 33 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 51
EXPRESSION (ie_i & ((~attr_i.input_disable)))
--1- ------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Unreachable | |
| 1 | 0 | Covered | T41,T42,T43 |
| 1 | 1 | Covered | T4,T5,T6 |
LINE 78
EXPRESSION (ie ? inout_io : 1'bz)
-1
| -1- | Status | Tests |
|---|
| 0 | Covered | T41,T42,T43 |
| 1 | Covered | T4,T5,T6 |
LINE 80
EXPRESSION (attr_i.invert ^ in_raw_o)
------1------ ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T4,T5,T6 |
| 0 | 1 | Covered | T22,T60,T190 |
| 1 | 0 | Covered | T41,T42,T43 |
| 1 | 1 | Covered | T41,T42,T43 |
LINE 84
EXPRESSION (out_i ^ attr_i.invert)
--1-- ------2------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T4,T5,T6 |
| 0 | 1 | Covered | T41,T42,T43 |
| 1 | 0 | Covered | T22,T23,T24 |
| 1 | 1 | Covered | T41,T42,T43 |
LINE 85
EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
--1- ---------------------------------2---------------------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | Covered | T41,T42,T43 |
| 1 | 1 | Covered | T22,T23,T24 |
LINE 85
SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
--------------------1------------------- -----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T41,T42,T43 |
| 0 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | Covered | T41,T42,T43 |
LINE 85
SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
--------1-------- ---------2--------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | Covered | T41,T42,T43 |
| 1 | 1 | Covered | T41,T42,T43 |
LINE 92
EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
---------------------1--------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T41,T42,T43 |
LINE 92
SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
------1----- ------------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T41,T42,T43 |
| 1 | 0 | Covered | T22,T23,T24 |
| 1 | 1 | Covered | T41,T42,T43 |
LINE 93
EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
-----------------------1-----------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T22,T23,T24 |
LINE 93
SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
------1----- --------------2--------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | Covered | T41,T42,T43 |
| 1 | 1 | Covered | T22,T23,T24 |
LINE 95
EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
-------1------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T41,T42,T43 |
Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[27].u_mio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
8 |
8 |
100.00 |
| TERNARY |
78 |
2 |
2 |
100.00 |
| TERNARY |
92 |
2 |
2 |
100.00 |
| TERNARY |
93 |
2 |
2 |
100.00 |
| TERNARY |
95 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 78 (ie) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T4,T5,T6 |
| 0 |
Covered |
T41,T42,T43 |
LineNo. Expression
-1-: 92 ((gen_bidir.oe && attr_i.drive_strength[0])) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T41,T42,T43 |
| 0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 93 ((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T22,T23,T24 |
| 0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 95 (attr_i.pull_en) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T41,T42,T43 |
| 0 |
Covered |
T4,T5,T6 |
Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[27].u_mio_pad.gen_generic.u_impl_generic
Assertion Details
| Name | Attempts | Real Successes | Failures | Incomplete |
|
AnalogNoScan_A |
1010 |
1010 |
0 |
0 |
AnalogNoScan_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
1010 |
1010 |
0 |
0 |
| T4 |
1 |
1 |
0 |
0 |
| T5 |
1 |
1 |
0 |
0 |
| T6 |
1 |
1 |
0 |
0 |
| T18 |
1 |
1 |
0 |
0 |
| T19 |
1 |
1 |
0 |
0 |
| T22 |
1 |
1 |
0 |
0 |
| T44 |
1 |
1 |
0 |
0 |
| T52 |
1 |
1 |
0 |
0 |
| T60 |
1 |
1 |
0 |
0 |
| T86 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[28].u_mio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 8 | 8 | 100.00 |
| CONT_ASSIGN | 39 | 0 | 0 | |
| CONT_ASSIGN | 51 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 78 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 80 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 84 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 92 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 95 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 39 |
|
unreachable |
| 51 |
1 |
1 |
| 78 |
1 |
1 |
| 80 |
1 |
1 |
| 84 |
1 |
1 |
| 85 |
1 |
1 |
| 92 |
1 |
1 |
| 93 |
1 |
1 |
| 95 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[28].u_mio_pad.gen_generic.u_impl_generic
| Total | Covered | Percent |
|---|
| Conditions | 33 | 33 | 100.00 |
| Logical | 33 | 33 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 51
EXPRESSION (ie_i & ((~attr_i.input_disable)))
--1- ------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Unreachable | |
| 1 | 0 | Covered | T41,T42,T43 |
| 1 | 1 | Covered | T4,T5,T6 |
LINE 78
EXPRESSION (ie ? inout_io : 1'bz)
-1
| -1- | Status | Tests |
|---|
| 0 | Covered | T41,T42,T43 |
| 1 | Covered | T4,T5,T6 |
LINE 80
EXPRESSION (attr_i.invert ^ in_raw_o)
------1------ ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T4,T21,T118 |
| 0 | 1 | Covered | T4,T22,T21 |
| 1 | 0 | Covered | T41,T42,T43 |
| 1 | 1 | Covered | T41,T42,T43 |
LINE 84
EXPRESSION (out_i ^ attr_i.invert)
--1-- ------2------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T4,T5,T6 |
| 0 | 1 | Covered | T41,T42,T43 |
| 1 | 0 | Covered | T22,T24,T41 |
| 1 | 1 | Covered | T41,T42,T43 |
LINE 85
EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
--1- ---------------------------------2---------------------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | Covered | T41,T42,T43 |
| 1 | 1 | Covered | T22,T23,T24 |
LINE 85
SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
--------------------1------------------- -----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T41,T42,T43 |
| 0 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | Covered | T41,T42,T43 |
LINE 85
SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
--------1-------- ---------2--------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | Covered | T41,T42,T43 |
| 1 | 1 | Covered | T41,T42,T43 |
LINE 92
EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
---------------------1--------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T41,T42,T43 |
LINE 92
SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
------1----- ------------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T41,T42,T43 |
| 1 | 0 | Covered | T22,T23,T24 |
| 1 | 1 | Covered | T41,T42,T43 |
LINE 93
EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
-----------------------1-----------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T22,T23,T24 |
LINE 93
SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
------1----- --------------2--------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | Covered | T41,T42,T43 |
| 1 | 1 | Covered | T22,T23,T24 |
LINE 95
EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
-------1------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T41,T42,T43 |
Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[28].u_mio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
8 |
8 |
100.00 |
| TERNARY |
78 |
2 |
2 |
100.00 |
| TERNARY |
92 |
2 |
2 |
100.00 |
| TERNARY |
93 |
2 |
2 |
100.00 |
| TERNARY |
95 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 78 (ie) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T4,T5,T6 |
| 0 |
Covered |
T41,T42,T43 |
LineNo. Expression
-1-: 92 ((gen_bidir.oe && attr_i.drive_strength[0])) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T41,T42,T43 |
| 0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 93 ((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T22,T23,T24 |
| 0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 95 (attr_i.pull_en) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T41,T42,T43 |
| 0 |
Covered |
T4,T5,T6 |
Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[28].u_mio_pad.gen_generic.u_impl_generic
Assertion Details
| Name | Attempts | Real Successes | Failures | Incomplete |
|
AnalogNoScan_A |
1010 |
1010 |
0 |
0 |
AnalogNoScan_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
1010 |
1010 |
0 |
0 |
| T4 |
1 |
1 |
0 |
0 |
| T5 |
1 |
1 |
0 |
0 |
| T6 |
1 |
1 |
0 |
0 |
| T18 |
1 |
1 |
0 |
0 |
| T19 |
1 |
1 |
0 |
0 |
| T22 |
1 |
1 |
0 |
0 |
| T44 |
1 |
1 |
0 |
0 |
| T52 |
1 |
1 |
0 |
0 |
| T60 |
1 |
1 |
0 |
0 |
| T86 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[29].u_mio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 8 | 8 | 100.00 |
| CONT_ASSIGN | 39 | 0 | 0 | |
| CONT_ASSIGN | 51 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 78 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 80 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 84 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 92 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 95 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 39 |
|
unreachable |
| 51 |
1 |
1 |
| 78 |
1 |
1 |
| 80 |
1 |
1 |
| 84 |
1 |
1 |
| 85 |
1 |
1 |
| 92 |
1 |
1 |
| 93 |
1 |
1 |
| 95 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[29].u_mio_pad.gen_generic.u_impl_generic
| Total | Covered | Percent |
|---|
| Conditions | 33 | 33 | 100.00 |
| Logical | 33 | 33 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 51
EXPRESSION (ie_i & ((~attr_i.input_disable)))
--1- ------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Unreachable | |
| 1 | 0 | Covered | T41,T42,T43 |
| 1 | 1 | Covered | T4,T5,T6 |
LINE 78
EXPRESSION (ie ? inout_io : 1'bz)
-1
| -1- | Status | Tests |
|---|
| 0 | Covered | T41,T42,T43 |
| 1 | Covered | T4,T5,T6 |
LINE 80
EXPRESSION (attr_i.invert ^ in_raw_o)
------1------ ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T22,T70,T31 |
| 0 | 1 | Covered | T22,T31,T199 |
| 1 | 0 | Covered | T41,T42,T43 |
| 1 | 1 | Covered | T41,T42,T43 |
LINE 84
EXPRESSION (out_i ^ attr_i.invert)
--1-- ------2------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T4,T5,T6 |
| 0 | 1 | Covered | T41,T42,T43 |
| 1 | 0 | Covered | T34,T35,T204 |
| 1 | 1 | Covered | T41,T42,T43 |
LINE 85
EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
--1- ---------------------------------2---------------------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | Covered | T41,T42,T43 |
| 1 | 1 | Covered | T23,T34,T35 |
LINE 85
SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
--------------------1------------------- -----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T41,T42,T43 |
| 0 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | Covered | T41,T42,T43 |
LINE 85
SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
--------1-------- ---------2--------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | Covered | T41,T42,T43 |
| 1 | 1 | Covered | T41,T42,T43 |
LINE 92
EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
---------------------1--------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T41,T42,T43 |
LINE 92
SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
------1----- ------------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T41,T42,T43 |
| 1 | 0 | Covered | T23,T34,T35 |
| 1 | 1 | Covered | T41,T42,T43 |
LINE 93
EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
-----------------------1-----------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T23,T34,T35 |
LINE 93
SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
------1----- --------------2--------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | Covered | T41,T42,T43 |
| 1 | 1 | Covered | T23,T34,T35 |
LINE 95
EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
-------1------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T41,T42,T43 |
Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[29].u_mio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
8 |
8 |
100.00 |
| TERNARY |
78 |
2 |
2 |
100.00 |
| TERNARY |
92 |
2 |
2 |
100.00 |
| TERNARY |
93 |
2 |
2 |
100.00 |
| TERNARY |
95 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 78 (ie) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T4,T5,T6 |
| 0 |
Covered |
T41,T42,T43 |
LineNo. Expression
-1-: 92 ((gen_bidir.oe && attr_i.drive_strength[0])) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T41,T42,T43 |
| 0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 93 ((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T23,T34,T35 |
| 0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 95 (attr_i.pull_en) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T41,T42,T43 |
| 0 |
Covered |
T4,T5,T6 |
Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[29].u_mio_pad.gen_generic.u_impl_generic
Assertion Details
| Name | Attempts | Real Successes | Failures | Incomplete |
|
AnalogNoScan_A |
1010 |
1010 |
0 |
0 |
AnalogNoScan_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
1010 |
1010 |
0 |
0 |
| T4 |
1 |
1 |
0 |
0 |
| T5 |
1 |
1 |
0 |
0 |
| T6 |
1 |
1 |
0 |
0 |
| T18 |
1 |
1 |
0 |
0 |
| T19 |
1 |
1 |
0 |
0 |
| T22 |
1 |
1 |
0 |
0 |
| T44 |
1 |
1 |
0 |
0 |
| T52 |
1 |
1 |
0 |
0 |
| T60 |
1 |
1 |
0 |
0 |
| T86 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[30].u_mio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 8 | 8 | 100.00 |
| CONT_ASSIGN | 39 | 0 | 0 | |
| CONT_ASSIGN | 51 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 78 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 80 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 84 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 92 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 95 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 39 |
|
unreachable |
| 51 |
1 |
1 |
| 78 |
1 |
1 |
| 80 |
1 |
1 |
| 84 |
1 |
1 |
| 85 |
1 |
1 |
| 92 |
1 |
1 |
| 93 |
1 |
1 |
| 95 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[30].u_mio_pad.gen_generic.u_impl_generic
| Total | Covered | Percent |
|---|
| Conditions | 33 | 33 | 100.00 |
| Logical | 33 | 33 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 51
EXPRESSION (ie_i & ((~attr_i.input_disable)))
--1- ------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Unreachable | |
| 1 | 0 | Covered | T41,T42,T43 |
| 1 | 1 | Covered | T4,T5,T6 |
LINE 78
EXPRESSION (ie ? inout_io : 1'bz)
-1
| -1- | Status | Tests |
|---|
| 0 | Covered | T41,T42,T43 |
| 1 | Covered | T4,T5,T6 |
LINE 80
EXPRESSION (attr_i.invert ^ in_raw_o)
------1------ ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T5,T6,T22 |
| 0 | 1 | Covered | T4,T60,T62 |
| 1 | 0 | Covered | T41,T42,T43 |
| 1 | 1 | Covered | T41,T42,T43 |
LINE 84
EXPRESSION (out_i ^ attr_i.invert)
--1-- ------2------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T4,T5,T6 |
| 0 | 1 | Covered | T41,T42,T43 |
| 1 | 0 | Covered | T41,T42,T43 |
| 1 | 1 | Covered | T41,T42,T43 |
LINE 85
EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
--1- ---------------------------------2---------------------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | Covered | T41,T42,T43 |
| 1 | 1 | Covered | T22,T24,T41 |
LINE 85
SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
--------------------1------------------- -----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T41,T42,T43 |
| 0 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | Covered | T41,T42,T43 |
LINE 85
SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
--------1-------- ---------2--------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | Covered | T41,T42,T43 |
| 1 | 1 | Covered | T41,T42,T43 |
LINE 92
EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
---------------------1--------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T41,T42,T43 |
LINE 92
SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
------1----- ------------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T41,T42,T43 |
| 1 | 0 | Covered | T22,T24,T41 |
| 1 | 1 | Covered | T41,T42,T43 |
LINE 93
EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
-----------------------1-----------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T22,T24,T41 |
LINE 93
SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
------1----- --------------2--------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | Covered | T41,T42,T43 |
| 1 | 1 | Covered | T22,T24,T41 |
LINE 95
EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
-------1------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T41,T42,T43 |
Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[30].u_mio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
8 |
8 |
100.00 |
| TERNARY |
78 |
2 |
2 |
100.00 |
| TERNARY |
92 |
2 |
2 |
100.00 |
| TERNARY |
93 |
2 |
2 |
100.00 |
| TERNARY |
95 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 78 (ie) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T4,T5,T6 |
| 0 |
Covered |
T41,T42,T43 |
LineNo. Expression
-1-: 92 ((gen_bidir.oe && attr_i.drive_strength[0])) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T41,T42,T43 |
| 0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 93 ((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T22,T24,T41 |
| 0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 95 (attr_i.pull_en) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T41,T42,T43 |
| 0 |
Covered |
T4,T5,T6 |
Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[30].u_mio_pad.gen_generic.u_impl_generic
Assertion Details
| Name | Attempts | Real Successes | Failures | Incomplete |
|
AnalogNoScan_A |
1010 |
1010 |
0 |
0 |
AnalogNoScan_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
1010 |
1010 |
0 |
0 |
| T4 |
1 |
1 |
0 |
0 |
| T5 |
1 |
1 |
0 |
0 |
| T6 |
1 |
1 |
0 |
0 |
| T18 |
1 |
1 |
0 |
0 |
| T19 |
1 |
1 |
0 |
0 |
| T22 |
1 |
1 |
0 |
0 |
| T44 |
1 |
1 |
0 |
0 |
| T52 |
1 |
1 |
0 |
0 |
| T60 |
1 |
1 |
0 |
0 |
| T86 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[31].u_mio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 8 | 8 | 100.00 |
| CONT_ASSIGN | 39 | 0 | 0 | |
| CONT_ASSIGN | 51 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 78 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 80 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 84 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 92 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 95 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 39 |
|
unreachable |
| 51 |
1 |
1 |
| 78 |
1 |
1 |
| 80 |
1 |
1 |
| 84 |
1 |
1 |
| 85 |
1 |
1 |
| 92 |
1 |
1 |
| 93 |
1 |
1 |
| 95 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[31].u_mio_pad.gen_generic.u_impl_generic
| Total | Covered | Percent |
|---|
| Conditions | 33 | 33 | 100.00 |
| Logical | 33 | 33 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 51
EXPRESSION (ie_i & ((~attr_i.input_disable)))
--1- ------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Unreachable | |
| 1 | 0 | Covered | T41,T42,T43 |
| 1 | 1 | Covered | T4,T5,T6 |
LINE 78
EXPRESSION (ie ? inout_io : 1'bz)
-1
| -1- | Status | Tests |
|---|
| 0 | Covered | T41,T42,T43 |
| 1 | Covered | T4,T5,T6 |
LINE 80
EXPRESSION (attr_i.invert ^ in_raw_o)
------1------ ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T22,T70,T71 |
| 0 | 1 | Covered | T22,T49,T199 |
| 1 | 0 | Covered | T41,T42,T43 |
| 1 | 1 | Covered | T41,T42,T43 |
LINE 84
EXPRESSION (out_i ^ attr_i.invert)
--1-- ------2------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T4,T5,T6 |
| 0 | 1 | Covered | T41,T42,T43 |
| 1 | 0 | Covered | T28,T38,T83 |
| 1 | 1 | Covered | T41,T42,T43 |
LINE 85
EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
--1- ---------------------------------2---------------------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | Covered | T41,T42,T43 |
| 1 | 1 | Covered | T28,T38,T83 |
LINE 85
SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
--------------------1------------------- -----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T41,T42,T43 |
| 0 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | Covered | T41,T42,T43 |
LINE 85
SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
--------1-------- ---------2--------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | Covered | T41,T42,T43 |
| 1 | 1 | Covered | T41,T42,T43 |
LINE 92
EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
---------------------1--------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T41,T42,T43 |
LINE 92
SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
------1----- ------------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T41,T42,T43 |
| 1 | 0 | Covered | T28,T38,T83 |
| 1 | 1 | Covered | T41,T42,T43 |
LINE 93
EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
-----------------------1-----------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T28,T38,T83 |
LINE 93
SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
------1----- --------------2--------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | Covered | T41,T42,T43 |
| 1 | 1 | Covered | T28,T38,T83 |
LINE 95
EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
-------1------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T41,T42,T43 |
Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[31].u_mio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
8 |
8 |
100.00 |
| TERNARY |
78 |
2 |
2 |
100.00 |
| TERNARY |
92 |
2 |
2 |
100.00 |
| TERNARY |
93 |
2 |
2 |
100.00 |
| TERNARY |
95 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 78 (ie) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T4,T5,T6 |
| 0 |
Covered |
T41,T42,T43 |
LineNo. Expression
-1-: 92 ((gen_bidir.oe && attr_i.drive_strength[0])) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T41,T42,T43 |
| 0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 93 ((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T28,T38,T83 |
| 0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 95 (attr_i.pull_en) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T41,T42,T43 |
| 0 |
Covered |
T4,T5,T6 |
Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[31].u_mio_pad.gen_generic.u_impl_generic
Assertion Details
| Name | Attempts | Real Successes | Failures | Incomplete |
|
AnalogNoScan_A |
1010 |
1010 |
0 |
0 |
AnalogNoScan_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
1010 |
1010 |
0 |
0 |
| T4 |
1 |
1 |
0 |
0 |
| T5 |
1 |
1 |
0 |
0 |
| T6 |
1 |
1 |
0 |
0 |
| T18 |
1 |
1 |
0 |
0 |
| T19 |
1 |
1 |
0 |
0 |
| T22 |
1 |
1 |
0 |
0 |
| T44 |
1 |
1 |
0 |
0 |
| T52 |
1 |
1 |
0 |
0 |
| T60 |
1 |
1 |
0 |
0 |
| T86 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[32].u_mio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 8 | 8 | 100.00 |
| CONT_ASSIGN | 39 | 0 | 0 | |
| CONT_ASSIGN | 51 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 78 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 80 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 84 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 92 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 95 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 39 |
|
unreachable |
| 51 |
1 |
1 |
| 78 |
1 |
1 |
| 80 |
1 |
1 |
| 84 |
1 |
1 |
| 85 |
1 |
1 |
| 92 |
1 |
1 |
| 93 |
1 |
1 |
| 95 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[32].u_mio_pad.gen_generic.u_impl_generic
| Total | Covered | Percent |
|---|
| Conditions | 33 | 33 | 100.00 |
| Logical | 33 | 33 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 51
EXPRESSION (ie_i & ((~attr_i.input_disable)))
--1- ------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Unreachable | |
| 1 | 0 | Covered | T41,T42,T43 |
| 1 | 1 | Covered | T4,T5,T6 |
LINE 78
EXPRESSION (ie ? inout_io : 1'bz)
-1
| -1- | Status | Tests |
|---|
| 0 | Covered | T41,T42,T43 |
| 1 | Covered | T4,T5,T6 |
LINE 80
EXPRESSION (attr_i.invert ^ in_raw_o)
------1------ ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T19,T70,T108 |
| 0 | 1 | Covered | T22,T19,T108 |
| 1 | 0 | Covered | T41,T42,T43 |
| 1 | 1 | Covered | T41,T42,T43 |
LINE 84
EXPRESSION (out_i ^ attr_i.invert)
--1-- ------2------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T4,T5,T6 |
| 0 | 1 | Covered | T41,T42,T43 |
| 1 | 0 | Covered | T22,T19,T108 |
| 1 | 1 | Covered | T41,T42,T43 |
LINE 85
EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
--1- ---------------------------------2---------------------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | Covered | T41,T42,T43 |
| 1 | 1 | Covered | T22,T19,T108 |
LINE 85
SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
--------------------1------------------- -----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T41,T42,T43 |
| 0 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | Covered | T41,T42,T43 |
LINE 85
SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
--------1-------- ---------2--------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | Covered | T41,T42,T43 |
| 1 | 1 | Covered | T41,T42,T43 |
LINE 92
EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
---------------------1--------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T41,T42,T43 |
LINE 92
SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
------1----- ------------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T41,T42,T43 |
| 1 | 0 | Covered | T22,T19,T108 |
| 1 | 1 | Covered | T41,T42,T43 |
LINE 93
EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
-----------------------1-----------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T22,T19,T108 |
LINE 93
SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
------1----- --------------2--------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | Covered | T41,T42,T43 |
| 1 | 1 | Covered | T22,T19,T108 |
LINE 95
EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
-------1------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T41,T42,T43 |
Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[32].u_mio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
8 |
8 |
100.00 |
| TERNARY |
78 |
2 |
2 |
100.00 |
| TERNARY |
92 |
2 |
2 |
100.00 |
| TERNARY |
93 |
2 |
2 |
100.00 |
| TERNARY |
95 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 78 (ie) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T4,T5,T6 |
| 0 |
Covered |
T41,T42,T43 |
LineNo. Expression
-1-: 92 ((gen_bidir.oe && attr_i.drive_strength[0])) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T41,T42,T43 |
| 0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 93 ((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T22,T19,T108 |
| 0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 95 (attr_i.pull_en) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T41,T42,T43 |
| 0 |
Covered |
T4,T5,T6 |
Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[32].u_mio_pad.gen_generic.u_impl_generic
Assertion Details
| Name | Attempts | Real Successes | Failures | Incomplete |
|
AnalogNoScan_A |
1010 |
1010 |
0 |
0 |
AnalogNoScan_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
1010 |
1010 |
0 |
0 |
| T4 |
1 |
1 |
0 |
0 |
| T5 |
1 |
1 |
0 |
0 |
| T6 |
1 |
1 |
0 |
0 |
| T18 |
1 |
1 |
0 |
0 |
| T19 |
1 |
1 |
0 |
0 |
| T22 |
1 |
1 |
0 |
0 |
| T44 |
1 |
1 |
0 |
0 |
| T52 |
1 |
1 |
0 |
0 |
| T60 |
1 |
1 |
0 |
0 |
| T86 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[33].u_mio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 8 | 8 | 100.00 |
| CONT_ASSIGN | 39 | 0 | 0 | |
| CONT_ASSIGN | 51 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 78 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 80 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 84 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 92 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 95 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 39 |
|
unreachable |
| 51 |
1 |
1 |
| 78 |
1 |
1 |
| 80 |
1 |
1 |
| 84 |
1 |
1 |
| 85 |
1 |
1 |
| 92 |
1 |
1 |
| 93 |
1 |
1 |
| 95 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[33].u_mio_pad.gen_generic.u_impl_generic
| Total | Covered | Percent |
|---|
| Conditions | 33 | 33 | 100.00 |
| Logical | 33 | 33 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 51
EXPRESSION (ie_i & ((~attr_i.input_disable)))
--1- ------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Unreachable | |
| 1 | 0 | Covered | T41,T42,T43 |
| 1 | 1 | Covered | T4,T5,T6 |
LINE 78
EXPRESSION (ie ? inout_io : 1'bz)
-1
| -1- | Status | Tests |
|---|
| 0 | Covered | T41,T42,T43 |
| 1 | Covered | T4,T5,T6 |
LINE 80
EXPRESSION (attr_i.invert ^ in_raw_o)
------1------ ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T19,T70,T108 |
| 0 | 1 | Covered | T22,T19,T108 |
| 1 | 0 | Covered | T41,T42,T43 |
| 1 | 1 | Covered | T41,T42,T43 |
LINE 84
EXPRESSION (out_i ^ attr_i.invert)
--1-- ------2------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T4,T5,T6 |
| 0 | 1 | Covered | T41,T42,T43 |
| 1 | 0 | Covered | T22,T19,T108 |
| 1 | 1 | Covered | T41,T42,T43 |
LINE 85
EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
--1- ---------------------------------2---------------------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | Covered | T41,T42,T43 |
| 1 | 1 | Covered | T22,T19,T108 |
LINE 85
SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
--------------------1------------------- -----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T41,T42,T43 |
| 0 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | Covered | T41,T42,T43 |
LINE 85
SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
--------1-------- ---------2--------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | Covered | T41,T42,T43 |
| 1 | 1 | Covered | T41,T42,T43 |
LINE 92
EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
---------------------1--------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T41,T42,T43 |
LINE 92
SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
------1----- ------------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T41,T42,T43 |
| 1 | 0 | Covered | T22,T19,T108 |
| 1 | 1 | Covered | T41,T42,T43 |
LINE 93
EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
-----------------------1-----------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T22,T19,T108 |
LINE 93
SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
------1----- --------------2--------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | Covered | T41,T42,T43 |
| 1 | 1 | Covered | T22,T19,T108 |
LINE 95
EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
-------1------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T41,T42,T43 |
Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[33].u_mio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
8 |
8 |
100.00 |
| TERNARY |
78 |
2 |
2 |
100.00 |
| TERNARY |
92 |
2 |
2 |
100.00 |
| TERNARY |
93 |
2 |
2 |
100.00 |
| TERNARY |
95 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 78 (ie) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T4,T5,T6 |
| 0 |
Covered |
T41,T42,T43 |
LineNo. Expression
-1-: 92 ((gen_bidir.oe && attr_i.drive_strength[0])) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T41,T42,T43 |
| 0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 93 ((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T22,T19,T108 |
| 0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 95 (attr_i.pull_en) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T41,T42,T43 |
| 0 |
Covered |
T4,T5,T6 |
Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[33].u_mio_pad.gen_generic.u_impl_generic
Assertion Details
| Name | Attempts | Real Successes | Failures | Incomplete |
|
AnalogNoScan_A |
1010 |
1010 |
0 |
0 |
AnalogNoScan_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
1010 |
1010 |
0 |
0 |
| T4 |
1 |
1 |
0 |
0 |
| T5 |
1 |
1 |
0 |
0 |
| T6 |
1 |
1 |
0 |
0 |
| T18 |
1 |
1 |
0 |
0 |
| T19 |
1 |
1 |
0 |
0 |
| T22 |
1 |
1 |
0 |
0 |
| T44 |
1 |
1 |
0 |
0 |
| T52 |
1 |
1 |
0 |
0 |
| T60 |
1 |
1 |
0 |
0 |
| T86 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[34].u_mio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 8 | 8 | 100.00 |
| CONT_ASSIGN | 39 | 0 | 0 | |
| CONT_ASSIGN | 51 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 78 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 80 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 84 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 92 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 95 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 39 |
|
unreachable |
| 51 |
1 |
1 |
| 78 |
1 |
1 |
| 80 |
1 |
1 |
| 84 |
1 |
1 |
| 85 |
1 |
1 |
| 92 |
1 |
1 |
| 93 |
1 |
1 |
| 95 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[34].u_mio_pad.gen_generic.u_impl_generic
| Total | Covered | Percent |
|---|
| Conditions | 33 | 33 | 100.00 |
| Logical | 33 | 33 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 51
EXPRESSION (ie_i & ((~attr_i.input_disable)))
--1- ------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Unreachable | |
| 1 | 0 | Covered | T41,T42,T43 |
| 1 | 1 | Covered | T4,T5,T6 |
LINE 78
EXPRESSION (ie ? inout_io : 1'bz)
-1
| -1- | Status | Tests |
|---|
| 0 | Covered | T41,T42,T43 |
| 1 | Covered | T4,T5,T6 |
LINE 80
EXPRESSION (attr_i.invert ^ in_raw_o)
------1------ ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T22,T19,T70 |
| 0 | 1 | Covered | T22,T19,T108 |
| 1 | 0 | Covered | T41,T42,T43 |
| 1 | 1 | Covered | T41,T42,T43 |
LINE 84
EXPRESSION (out_i ^ attr_i.invert)
--1-- ------2------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T4,T5,T6 |
| 0 | 1 | Covered | T41,T42,T43 |
| 1 | 0 | Covered | T19,T108,T212 |
| 1 | 1 | Covered | T41,T42,T43 |
LINE 85
EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
--1- ---------------------------------2---------------------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | Covered | T41,T42,T43 |
| 1 | 1 | Covered | T19,T108,T212 |
LINE 85
SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
--------------------1------------------- -----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T41,T42,T43 |
| 0 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | Covered | T41,T42,T43 |
LINE 85
SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
--------1-------- ---------2--------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | Covered | T41,T42,T43 |
| 1 | 1 | Covered | T41,T42,T43 |
LINE 92
EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
---------------------1--------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T41,T42,T43 |
LINE 92
SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
------1----- ------------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T41,T42,T43 |
| 1 | 0 | Covered | T19,T108,T212 |
| 1 | 1 | Covered | T41,T42,T43 |
LINE 93
EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
-----------------------1-----------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T19,T108,T212 |
LINE 93
SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
------1----- --------------2--------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | Covered | T41,T42,T43 |
| 1 | 1 | Covered | T19,T108,T212 |
LINE 95
EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
-------1------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T41,T42,T43 |
Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[34].u_mio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
8 |
8 |
100.00 |
| TERNARY |
78 |
2 |
2 |
100.00 |
| TERNARY |
92 |
2 |
2 |
100.00 |
| TERNARY |
93 |
2 |
2 |
100.00 |
| TERNARY |
95 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 78 (ie) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T4,T5,T6 |
| 0 |
Covered |
T41,T42,T43 |
LineNo. Expression
-1-: 92 ((gen_bidir.oe && attr_i.drive_strength[0])) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T41,T42,T43 |
| 0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 93 ((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T19,T108,T212 |
| 0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 95 (attr_i.pull_en) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T41,T42,T43 |
| 0 |
Covered |
T4,T5,T6 |
Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[34].u_mio_pad.gen_generic.u_impl_generic
Assertion Details
| Name | Attempts | Real Successes | Failures | Incomplete |
|
AnalogNoScan_A |
1010 |
1010 |
0 |
0 |
AnalogNoScan_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
1010 |
1010 |
0 |
0 |
| T4 |
1 |
1 |
0 |
0 |
| T5 |
1 |
1 |
0 |
0 |
| T6 |
1 |
1 |
0 |
0 |
| T18 |
1 |
1 |
0 |
0 |
| T19 |
1 |
1 |
0 |
0 |
| T22 |
1 |
1 |
0 |
0 |
| T44 |
1 |
1 |
0 |
0 |
| T52 |
1 |
1 |
0 |
0 |
| T60 |
1 |
1 |
0 |
0 |
| T86 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[35].u_mio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 8 | 8 | 100.00 |
| CONT_ASSIGN | 39 | 0 | 0 | |
| CONT_ASSIGN | 51 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 78 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 80 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 84 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 92 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 95 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 39 |
|
unreachable |
| 51 |
1 |
1 |
| 78 |
1 |
1 |
| 80 |
1 |
1 |
| 84 |
1 |
1 |
| 85 |
1 |
1 |
| 92 |
1 |
1 |
| 93 |
1 |
1 |
| 95 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[35].u_mio_pad.gen_generic.u_impl_generic
| Total | Covered | Percent |
|---|
| Conditions | 33 | 33 | 100.00 |
| Logical | 33 | 33 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 51
EXPRESSION (ie_i & ((~attr_i.input_disable)))
--1- ------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Unreachable | |
| 1 | 0 | Covered | T41,T42,T43 |
| 1 | 1 | Covered | T4,T5,T6 |
LINE 78
EXPRESSION (ie ? inout_io : 1'bz)
-1
| -1- | Status | Tests |
|---|
| 0 | Covered | T41,T42,T43 |
| 1 | Covered | T4,T5,T6 |
LINE 80
EXPRESSION (attr_i.invert ^ in_raw_o)
------1------ ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T4,T60,T62 |
| 0 | 1 | Covered | T4,T22,T60 |
| 1 | 0 | Covered | T41,T42,T43 |
| 1 | 1 | Covered | T41,T42,T43 |
LINE 84
EXPRESSION (out_i ^ attr_i.invert)
--1-- ------2------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T4,T5,T6 |
| 0 | 1 | Covered | T41,T42,T43 |
| 1 | 0 | Covered | T22,T28,T38 |
| 1 | 1 | Covered | T41,T42,T43 |
LINE 85
EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
--1- ---------------------------------2---------------------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | Covered | T41,T42,T43 |
| 1 | 1 | Covered | T22,T28,T23 |
LINE 85
SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
--------------------1------------------- -----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T41,T42,T43 |
| 0 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | Covered | T41,T42,T43 |
LINE 85
SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
--------1-------- ---------2--------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | Covered | T41,T42,T43 |
| 1 | 1 | Covered | T41,T42,T43 |
LINE 92
EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
---------------------1--------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T41,T42,T43 |
LINE 92
SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
------1----- ------------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T41,T42,T43 |
| 1 | 0 | Covered | T22,T28,T23 |
| 1 | 1 | Covered | T41,T42,T43 |
LINE 93
EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
-----------------------1-----------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T22,T28,T23 |
LINE 93
SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
------1----- --------------2--------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | Covered | T41,T42,T43 |
| 1 | 1 | Covered | T22,T28,T23 |
LINE 95
EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
-------1------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T41,T42,T43 |
Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[35].u_mio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
8 |
8 |
100.00 |
| TERNARY |
78 |
2 |
2 |
100.00 |
| TERNARY |
92 |
2 |
2 |
100.00 |
| TERNARY |
93 |
2 |
2 |
100.00 |
| TERNARY |
95 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 78 (ie) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T4,T5,T6 |
| 0 |
Covered |
T41,T42,T43 |
LineNo. Expression
-1-: 92 ((gen_bidir.oe && attr_i.drive_strength[0])) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T41,T42,T43 |
| 0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 93 ((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T22,T28,T23 |
| 0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 95 (attr_i.pull_en) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T41,T42,T43 |
| 0 |
Covered |
T4,T5,T6 |
Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[35].u_mio_pad.gen_generic.u_impl_generic
Assertion Details
| Name | Attempts | Real Successes | Failures | Incomplete |
|
AnalogNoScan_A |
1010 |
1010 |
0 |
0 |
AnalogNoScan_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
1010 |
1010 |
0 |
0 |
| T4 |
1 |
1 |
0 |
0 |
| T5 |
1 |
1 |
0 |
0 |
| T6 |
1 |
1 |
0 |
0 |
| T18 |
1 |
1 |
0 |
0 |
| T19 |
1 |
1 |
0 |
0 |
| T22 |
1 |
1 |
0 |
0 |
| T44 |
1 |
1 |
0 |
0 |
| T52 |
1 |
1 |
0 |
0 |
| T60 |
1 |
1 |
0 |
0 |
| T86 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[36].u_mio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 8 | 8 | 100.00 |
| CONT_ASSIGN | 39 | 0 | 0 | |
| CONT_ASSIGN | 51 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 78 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 80 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 84 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 92 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 95 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 39 |
|
unreachable |
| 51 |
1 |
1 |
| 78 |
1 |
1 |
| 80 |
1 |
1 |
| 84 |
1 |
1 |
| 85 |
1 |
1 |
| 92 |
1 |
1 |
| 93 |
1 |
1 |
| 95 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[36].u_mio_pad.gen_generic.u_impl_generic
| Total | Covered | Percent |
|---|
| Conditions | 33 | 33 | 100.00 |
| Logical | 33 | 33 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 51
EXPRESSION (ie_i & ((~attr_i.input_disable)))
--1- ------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Unreachable | |
| 1 | 0 | Covered | T41,T42,T43 |
| 1 | 1 | Covered | T4,T5,T6 |
LINE 78
EXPRESSION (ie ? inout_io : 1'bz)
-1
| -1- | Status | Tests |
|---|
| 0 | Covered | T41,T42,T43 |
| 1 | Covered | T4,T5,T6 |
LINE 80
EXPRESSION (attr_i.invert ^ in_raw_o)
------1------ ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T4,T22,T60 |
| 0 | 1 | Covered | T4,T60,T62 |
| 1 | 0 | Covered | T41,T42,T43 |
| 1 | 1 | Covered | T41,T42,T43 |
LINE 84
EXPRESSION (out_i ^ attr_i.invert)
--1-- ------2------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T4,T5,T6 |
| 0 | 1 | Covered | T41,T42,T43 |
| 1 | 0 | Covered | T4,T60,T62 |
| 1 | 1 | Covered | T41,T42,T43 |
LINE 85
EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
--1- ---------------------------------2---------------------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | Covered | T41,T42,T43 |
| 1 | 1 | Covered | T4,T22,T60 |
LINE 85
SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
--------------------1------------------- -----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T41,T42,T43 |
| 0 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | Covered | T41,T42,T43 |
LINE 85
SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
--------1-------- ---------2--------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | Covered | T41,T42,T43 |
| 1 | 1 | Covered | T41,T42,T43 |
LINE 92
EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
---------------------1--------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T41,T42,T43 |
LINE 92
SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
------1----- ------------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T41,T42,T43 |
| 1 | 0 | Covered | T4,T22,T60 |
| 1 | 1 | Covered | T41,T42,T43 |
LINE 93
EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
-----------------------1-----------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T4,T22,T60 |
LINE 93
SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
------1----- --------------2--------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | Covered | T41,T42,T43 |
| 1 | 1 | Covered | T4,T22,T60 |
LINE 95
EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
-------1------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T41,T42,T43 |
Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[36].u_mio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
8 |
8 |
100.00 |
| TERNARY |
78 |
2 |
2 |
100.00 |
| TERNARY |
92 |
2 |
2 |
100.00 |
| TERNARY |
93 |
2 |
2 |
100.00 |
| TERNARY |
95 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 78 (ie) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T4,T5,T6 |
| 0 |
Covered |
T41,T42,T43 |
LineNo. Expression
-1-: 92 ((gen_bidir.oe && attr_i.drive_strength[0])) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T41,T42,T43 |
| 0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 93 ((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T4,T22,T60 |
| 0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 95 (attr_i.pull_en) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T41,T42,T43 |
| 0 |
Covered |
T4,T5,T6 |
Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[36].u_mio_pad.gen_generic.u_impl_generic
Assertion Details
| Name | Attempts | Real Successes | Failures | Incomplete |
|
AnalogNoScan_A |
1010 |
1010 |
0 |
0 |
AnalogNoScan_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
1010 |
1010 |
0 |
0 |
| T4 |
1 |
1 |
0 |
0 |
| T5 |
1 |
1 |
0 |
0 |
| T6 |
1 |
1 |
0 |
0 |
| T18 |
1 |
1 |
0 |
0 |
| T19 |
1 |
1 |
0 |
0 |
| T22 |
1 |
1 |
0 |
0 |
| T44 |
1 |
1 |
0 |
0 |
| T52 |
1 |
1 |
0 |
0 |
| T60 |
1 |
1 |
0 |
0 |
| T86 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[37].u_mio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 8 | 8 | 100.00 |
| CONT_ASSIGN | 39 | 0 | 0 | |
| CONT_ASSIGN | 51 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 78 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 80 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 84 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 92 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 95 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 39 |
|
unreachable |
| 51 |
1 |
1 |
| 78 |
1 |
1 |
| 80 |
1 |
1 |
| 84 |
1 |
1 |
| 85 |
1 |
1 |
| 92 |
1 |
1 |
| 93 |
1 |
1 |
| 95 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[37].u_mio_pad.gen_generic.u_impl_generic
| Total | Covered | Percent |
|---|
| Conditions | 33 | 33 | 100.00 |
| Logical | 33 | 33 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 51
EXPRESSION (ie_i & ((~attr_i.input_disable)))
--1- ------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Unreachable | |
| 1 | 0 | Covered | T41,T42,T43 |
| 1 | 1 | Covered | T4,T5,T6 |
LINE 78
EXPRESSION (ie ? inout_io : 1'bz)
-1
| -1- | Status | Tests |
|---|
| 0 | Covered | T41,T42,T43 |
| 1 | Covered | T4,T5,T6 |
LINE 80
EXPRESSION (attr_i.invert ^ in_raw_o)
------1------ ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T4,T22,T60 |
| 0 | 1 | Covered | T4,T22,T60 |
| 1 | 0 | Covered | T41,T42,T43 |
| 1 | 1 | Covered | T41,T42,T43 |
LINE 84
EXPRESSION (out_i ^ attr_i.invert)
--1-- ------2------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T4,T5,T6 |
| 0 | 1 | Covered | T41,T42,T43 |
| 1 | 0 | Covered | T28,T38,T83 |
| 1 | 1 | Covered | T41,T42,T43 |
LINE 85
EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
--1- ---------------------------------2---------------------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | Covered | T41,T42,T43 |
| 1 | 1 | Covered | T28,T23,T38 |
LINE 85
SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
--------------------1------------------- -----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T41,T42,T43 |
| 0 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | Covered | T41,T42,T43 |
LINE 85
SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
--------1-------- ---------2--------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | Covered | T41,T42,T43 |
| 1 | 1 | Covered | T41,T42,T43 |
LINE 92
EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
---------------------1--------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T41,T42,T43 |
LINE 92
SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
------1----- ------------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T41,T42,T43 |
| 1 | 0 | Covered | T28,T23,T38 |
| 1 | 1 | Covered | T41,T42,T43 |
LINE 93
EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
-----------------------1-----------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T28,T23,T38 |
LINE 93
SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
------1----- --------------2--------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | Covered | T41,T42,T43 |
| 1 | 1 | Covered | T28,T23,T38 |
LINE 95
EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
-------1------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T41,T42,T43 |
Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[37].u_mio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
8 |
8 |
100.00 |
| TERNARY |
78 |
2 |
2 |
100.00 |
| TERNARY |
92 |
2 |
2 |
100.00 |
| TERNARY |
93 |
2 |
2 |
100.00 |
| TERNARY |
95 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 78 (ie) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T4,T5,T6 |
| 0 |
Covered |
T41,T42,T43 |
LineNo. Expression
-1-: 92 ((gen_bidir.oe && attr_i.drive_strength[0])) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T41,T42,T43 |
| 0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 93 ((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T28,T23,T38 |
| 0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 95 (attr_i.pull_en) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T41,T42,T43 |
| 0 |
Covered |
T4,T5,T6 |
Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[37].u_mio_pad.gen_generic.u_impl_generic
Assertion Details
| Name | Attempts | Real Successes | Failures | Incomplete |
|
AnalogNoScan_A |
1010 |
1010 |
0 |
0 |
AnalogNoScan_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
1010 |
1010 |
0 |
0 |
| T4 |
1 |
1 |
0 |
0 |
| T5 |
1 |
1 |
0 |
0 |
| T6 |
1 |
1 |
0 |
0 |
| T18 |
1 |
1 |
0 |
0 |
| T19 |
1 |
1 |
0 |
0 |
| T22 |
1 |
1 |
0 |
0 |
| T44 |
1 |
1 |
0 |
0 |
| T52 |
1 |
1 |
0 |
0 |
| T60 |
1 |
1 |
0 |
0 |
| T86 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[38].u_mio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 8 | 8 | 100.00 |
| CONT_ASSIGN | 39 | 0 | 0 | |
| CONT_ASSIGN | 51 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 78 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 80 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 84 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 92 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 95 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 39 |
|
unreachable |
| 51 |
1 |
1 |
| 78 |
1 |
1 |
| 80 |
1 |
1 |
| 84 |
1 |
1 |
| 85 |
1 |
1 |
| 92 |
1 |
1 |
| 93 |
1 |
1 |
| 95 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[38].u_mio_pad.gen_generic.u_impl_generic
| Total | Covered | Percent |
|---|
| Conditions | 33 | 33 | 100.00 |
| Logical | 33 | 33 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 51
EXPRESSION (ie_i & ((~attr_i.input_disable)))
--1- ------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Unreachable | |
| 1 | 0 | Covered | T41,T42,T43 |
| 1 | 1 | Covered | T4,T5,T6 |
LINE 78
EXPRESSION (ie ? inout_io : 1'bz)
-1
| -1- | Status | Tests |
|---|
| 0 | Covered | T41,T42,T43 |
| 1 | Covered | T4,T5,T6 |
LINE 80
EXPRESSION (attr_i.invert ^ in_raw_o)
------1------ ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T4,T60,T62 |
| 0 | 1 | Covered | T4,T22,T60 |
| 1 | 0 | Covered | T41,T42,T43 |
| 1 | 1 | Covered | T41,T42,T43 |
LINE 84
EXPRESSION (out_i ^ attr_i.invert)
--1-- ------2------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T4,T5,T6 |
| 0 | 1 | Covered | T41,T42,T43 |
| 1 | 0 | Covered | T22,T28,T23 |
| 1 | 1 | Covered | T41,T42,T43 |
LINE 85
EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
--1- ---------------------------------2---------------------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | Covered | T41,T42,T43 |
| 1 | 1 | Covered | T22,T28,T23 |
LINE 85
SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
--------------------1------------------- -----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T41,T42,T43 |
| 0 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | Covered | T41,T42,T43 |
LINE 85
SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
--------1-------- ---------2--------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | Covered | T41,T42,T43 |
| 1 | 1 | Covered | T41,T42,T43 |
LINE 92
EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
---------------------1--------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T41,T42,T43 |
LINE 92
SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
------1----- ------------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T41,T42,T43 |
| 1 | 0 | Covered | T22,T28,T23 |
| 1 | 1 | Covered | T41,T42,T43 |
LINE 93
EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
-----------------------1-----------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T22,T28,T23 |
LINE 93
SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
------1----- --------------2--------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | Covered | T41,T42,T43 |
| 1 | 1 | Covered | T22,T28,T23 |
LINE 95
EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
-------1------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T41,T42,T43 |
Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[38].u_mio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
8 |
8 |
100.00 |
| TERNARY |
78 |
2 |
2 |
100.00 |
| TERNARY |
92 |
2 |
2 |
100.00 |
| TERNARY |
93 |
2 |
2 |
100.00 |
| TERNARY |
95 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 78 (ie) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T4,T5,T6 |
| 0 |
Covered |
T41,T42,T43 |
LineNo. Expression
-1-: 92 ((gen_bidir.oe && attr_i.drive_strength[0])) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T41,T42,T43 |
| 0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 93 ((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T22,T28,T23 |
| 0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 95 (attr_i.pull_en) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T41,T42,T43 |
| 0 |
Covered |
T4,T5,T6 |
Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[38].u_mio_pad.gen_generic.u_impl_generic
Assertion Details
| Name | Attempts | Real Successes | Failures | Incomplete |
|
AnalogNoScan_A |
1010 |
1010 |
0 |
0 |
AnalogNoScan_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
1010 |
1010 |
0 |
0 |
| T4 |
1 |
1 |
0 |
0 |
| T5 |
1 |
1 |
0 |
0 |
| T6 |
1 |
1 |
0 |
0 |
| T18 |
1 |
1 |
0 |
0 |
| T19 |
1 |
1 |
0 |
0 |
| T22 |
1 |
1 |
0 |
0 |
| T44 |
1 |
1 |
0 |
0 |
| T52 |
1 |
1 |
0 |
0 |
| T60 |
1 |
1 |
0 |
0 |
| T86 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[39].u_mio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 8 | 8 | 100.00 |
| CONT_ASSIGN | 39 | 0 | 0 | |
| CONT_ASSIGN | 51 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 78 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 80 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 84 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 92 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 95 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 39 |
|
unreachable |
| 51 |
1 |
1 |
| 78 |
1 |
1 |
| 80 |
1 |
1 |
| 84 |
1 |
1 |
| 85 |
1 |
1 |
| 92 |
1 |
1 |
| 93 |
1 |
1 |
| 95 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[39].u_mio_pad.gen_generic.u_impl_generic
| Total | Covered | Percent |
|---|
| Conditions | 33 | 33 | 100.00 |
| Logical | 33 | 33 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 51
EXPRESSION (ie_i & ((~attr_i.input_disable)))
--1- ------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Unreachable | |
| 1 | 0 | Covered | T41,T42,T43 |
| 1 | 1 | Covered | T4,T5,T6 |
LINE 78
EXPRESSION (ie ? inout_io : 1'bz)
-1
| -1- | Status | Tests |
|---|
| 0 | Covered | T41,T42,T43 |
| 1 | Covered | T4,T5,T6 |
LINE 80
EXPRESSION (attr_i.invert ^ in_raw_o)
------1------ ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T4,T60,T62 |
| 0 | 1 | Covered | T4,T22,T60 |
| 1 | 0 | Covered | T41,T42,T43 |
| 1 | 1 | Covered | T41,T42,T43 |
LINE 84
EXPRESSION (out_i ^ attr_i.invert)
--1-- ------2------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T4,T5,T6 |
| 0 | 1 | Covered | T41,T42,T43 |
| 1 | 0 | Covered | T22,T28,T38 |
| 1 | 1 | Covered | T41,T42,T43 |
LINE 85
EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
--1- ---------------------------------2---------------------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | Covered | T41,T42,T43 |
| 1 | 1 | Covered | T22,T28,T23 |
LINE 85
SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
--------------------1------------------- -----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T41,T42,T43 |
| 0 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | Covered | T41,T42,T43 |
LINE 85
SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
--------1-------- ---------2--------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | Covered | T41,T42,T43 |
| 1 | 1 | Covered | T41,T42,T43 |
LINE 92
EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
---------------------1--------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T41,T42,T43 |
LINE 92
SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
------1----- ------------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T41,T42,T43 |
| 1 | 0 | Covered | T22,T28,T23 |
| 1 | 1 | Covered | T41,T42,T43 |
LINE 93
EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
-----------------------1-----------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T22,T28,T23 |
LINE 93
SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
------1----- --------------2--------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | Covered | T41,T42,T43 |
| 1 | 1 | Covered | T22,T28,T23 |
LINE 95
EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
-------1------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T41,T42,T43 |
Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[39].u_mio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
8 |
8 |
100.00 |
| TERNARY |
78 |
2 |
2 |
100.00 |
| TERNARY |
92 |
2 |
2 |
100.00 |
| TERNARY |
93 |
2 |
2 |
100.00 |
| TERNARY |
95 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 78 (ie) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T4,T5,T6 |
| 0 |
Covered |
T41,T42,T43 |
LineNo. Expression
-1-: 92 ((gen_bidir.oe && attr_i.drive_strength[0])) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T41,T42,T43 |
| 0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 93 ((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T22,T28,T23 |
| 0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 95 (attr_i.pull_en) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T41,T42,T43 |
| 0 |
Covered |
T4,T5,T6 |
Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[39].u_mio_pad.gen_generic.u_impl_generic
Assertion Details
| Name | Attempts | Real Successes | Failures | Incomplete |
|
AnalogNoScan_A |
1010 |
1010 |
0 |
0 |
AnalogNoScan_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
1010 |
1010 |
0 |
0 |
| T4 |
1 |
1 |
0 |
0 |
| T5 |
1 |
1 |
0 |
0 |
| T6 |
1 |
1 |
0 |
0 |
| T18 |
1 |
1 |
0 |
0 |
| T19 |
1 |
1 |
0 |
0 |
| T22 |
1 |
1 |
0 |
0 |
| T44 |
1 |
1 |
0 |
0 |
| T52 |
1 |
1 |
0 |
0 |
| T60 |
1 |
1 |
0 |
0 |
| T86 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[40].u_mio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 8 | 8 | 100.00 |
| CONT_ASSIGN | 39 | 0 | 0 | |
| CONT_ASSIGN | 51 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 78 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 80 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 84 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 92 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 95 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 39 |
|
unreachable |
| 51 |
1 |
1 |
| 78 |
1 |
1 |
| 80 |
1 |
1 |
| 84 |
1 |
1 |
| 85 |
1 |
1 |
| 92 |
1 |
1 |
| 93 |
1 |
1 |
| 95 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[40].u_mio_pad.gen_generic.u_impl_generic
| Total | Covered | Percent |
|---|
| Conditions | 33 | 33 | 100.00 |
| Logical | 33 | 33 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 51
EXPRESSION (ie_i & ((~attr_i.input_disable)))
--1- ------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Unreachable | |
| 1 | 0 | Covered | T41,T42,T43 |
| 1 | 1 | Covered | T4,T5,T6 |
LINE 78
EXPRESSION (ie ? inout_io : 1'bz)
-1
| -1- | Status | Tests |
|---|
| 0 | Covered | T41,T42,T43 |
| 1 | Covered | T4,T5,T6 |
LINE 80
EXPRESSION (attr_i.invert ^ in_raw_o)
------1------ ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T4,T5,T6 |
| 0 | 1 | Covered | T22,T60,T190 |
| 1 | 0 | Covered | T41,T42,T43 |
| 1 | 1 | Covered | T42,T43,T183 |
LINE 84
EXPRESSION (out_i ^ attr_i.invert)
--1-- ------2------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T4,T5,T6 |
| 0 | 1 | Covered | T41,T42,T43 |
| 1 | 0 | Covered | T28,T23,T38 |
| 1 | 1 | Covered | T41,T42,T43 |
LINE 85
EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
--1- ---------------------------------2---------------------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | Covered | T41,T42,T43 |
| 1 | 1 | Covered | T28,T23,T38 |
LINE 85
SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
--------------------1------------------- -----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T41,T42,T43 |
| 0 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | Covered | T41,T42,T43 |
LINE 85
SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
--------1-------- ---------2--------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | Covered | T41,T42,T43 |
| 1 | 1 | Covered | T41,T42,T43 |
LINE 92
EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
---------------------1--------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T41,T42,T43 |
LINE 92
SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
------1----- ------------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T41,T42,T43 |
| 1 | 0 | Covered | T28,T23,T38 |
| 1 | 1 | Covered | T41,T42,T43 |
LINE 93
EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
-----------------------1-----------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T28,T23,T38 |
LINE 93
SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
------1----- --------------2--------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | Covered | T41,T42,T43 |
| 1 | 1 | Covered | T28,T23,T38 |
LINE 95
EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
-------1------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T41,T42,T43 |
Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[40].u_mio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
8 |
8 |
100.00 |
| TERNARY |
78 |
2 |
2 |
100.00 |
| TERNARY |
92 |
2 |
2 |
100.00 |
| TERNARY |
93 |
2 |
2 |
100.00 |
| TERNARY |
95 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 78 (ie) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T4,T5,T6 |
| 0 |
Covered |
T41,T42,T43 |
LineNo. Expression
-1-: 92 ((gen_bidir.oe && attr_i.drive_strength[0])) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T41,T42,T43 |
| 0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 93 ((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T28,T23,T38 |
| 0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 95 (attr_i.pull_en) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T41,T42,T43 |
| 0 |
Covered |
T4,T5,T6 |
Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[40].u_mio_pad.gen_generic.u_impl_generic
Assertion Details
| Name | Attempts | Real Successes | Failures | Incomplete |
|
AnalogNoScan_A |
1010 |
1010 |
0 |
0 |
AnalogNoScan_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
1010 |
1010 |
0 |
0 |
| T4 |
1 |
1 |
0 |
0 |
| T5 |
1 |
1 |
0 |
0 |
| T6 |
1 |
1 |
0 |
0 |
| T18 |
1 |
1 |
0 |
0 |
| T19 |
1 |
1 |
0 |
0 |
| T22 |
1 |
1 |
0 |
0 |
| T44 |
1 |
1 |
0 |
0 |
| T52 |
1 |
1 |
0 |
0 |
| T60 |
1 |
1 |
0 |
0 |
| T86 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[41].u_mio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 8 | 8 | 100.00 |
| CONT_ASSIGN | 39 | 0 | 0 | |
| CONT_ASSIGN | 51 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 78 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 80 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 84 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 92 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 95 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 39 |
|
unreachable |
| 51 |
1 |
1 |
| 78 |
1 |
1 |
| 80 |
1 |
1 |
| 84 |
1 |
1 |
| 85 |
1 |
1 |
| 92 |
1 |
1 |
| 93 |
1 |
1 |
| 95 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[41].u_mio_pad.gen_generic.u_impl_generic
| Total | Covered | Percent |
|---|
| Conditions | 33 | 33 | 100.00 |
| Logical | 33 | 33 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 51
EXPRESSION (ie_i & ((~attr_i.input_disable)))
--1- ------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Unreachable | |
| 1 | 0 | Covered | T41,T42,T43 |
| 1 | 1 | Covered | T4,T5,T6 |
LINE 78
EXPRESSION (ie ? inout_io : 1'bz)
-1
| -1- | Status | Tests |
|---|
| 0 | Covered | T41,T42,T43 |
| 1 | Covered | T4,T5,T6 |
LINE 80
EXPRESSION (attr_i.invert ^ in_raw_o)
------1------ ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T22,T70,T71 |
| 0 | 1 | Covered | T22,T28,T23 |
| 1 | 0 | Covered | T41,T42,T43 |
| 1 | 1 | Covered | T41,T42,T43 |
LINE 84
EXPRESSION (out_i ^ attr_i.invert)
--1-- ------2------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T4,T5,T6 |
| 0 | 1 | Covered | T41,T42,T43 |
| 1 | 0 | Covered | T28,T38,T83 |
| 1 | 1 | Covered | T41,T42,T43 |
LINE 85
EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
--1- ---------------------------------2---------------------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | Covered | T41,T42,T43 |
| 1 | 1 | Covered | T28,T38,T83 |
LINE 85
SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
--------------------1------------------- -----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T41,T42,T43 |
| 0 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | Covered | T41,T42,T43 |
LINE 85
SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
--------1-------- ---------2--------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | Covered | T41,T42,T43 |
| 1 | 1 | Covered | T41,T42,T43 |
LINE 92
EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
---------------------1--------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T41,T42,T43 |
LINE 92
SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
------1----- ------------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T41,T42,T43 |
| 1 | 0 | Covered | T28,T38,T83 |
| 1 | 1 | Covered | T41,T42,T43 |
LINE 93
EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
-----------------------1-----------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T28,T38,T83 |
LINE 93
SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
------1----- --------------2--------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | Covered | T41,T42,T43 |
| 1 | 1 | Covered | T28,T38,T83 |
LINE 95
EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
-------1------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T41,T42,T43 |
Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[41].u_mio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
8 |
8 |
100.00 |
| TERNARY |
78 |
2 |
2 |
100.00 |
| TERNARY |
92 |
2 |
2 |
100.00 |
| TERNARY |
93 |
2 |
2 |
100.00 |
| TERNARY |
95 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 78 (ie) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T4,T5,T6 |
| 0 |
Covered |
T41,T42,T43 |
LineNo. Expression
-1-: 92 ((gen_bidir.oe && attr_i.drive_strength[0])) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T41,T42,T43 |
| 0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 93 ((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T28,T38,T83 |
| 0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 95 (attr_i.pull_en) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T41,T42,T43 |
| 0 |
Covered |
T4,T5,T6 |
Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[41].u_mio_pad.gen_generic.u_impl_generic
Assertion Details
| Name | Attempts | Real Successes | Failures | Incomplete |
|
AnalogNoScan_A |
1010 |
1010 |
0 |
0 |
AnalogNoScan_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
1010 |
1010 |
0 |
0 |
| T4 |
1 |
1 |
0 |
0 |
| T5 |
1 |
1 |
0 |
0 |
| T6 |
1 |
1 |
0 |
0 |
| T18 |
1 |
1 |
0 |
0 |
| T19 |
1 |
1 |
0 |
0 |
| T22 |
1 |
1 |
0 |
0 |
| T44 |
1 |
1 |
0 |
0 |
| T52 |
1 |
1 |
0 |
0 |
| T60 |
1 |
1 |
0 |
0 |
| T86 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[42].u_mio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 8 | 8 | 100.00 |
| CONT_ASSIGN | 39 | 0 | 0 | |
| CONT_ASSIGN | 51 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 78 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 80 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 84 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 92 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 95 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 39 |
|
unreachable |
| 51 |
1 |
1 |
| 78 |
1 |
1 |
| 80 |
1 |
1 |
| 84 |
1 |
1 |
| 85 |
1 |
1 |
| 92 |
1 |
1 |
| 93 |
1 |
1 |
| 95 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[42].u_mio_pad.gen_generic.u_impl_generic
| Total | Covered | Percent |
|---|
| Conditions | 33 | 33 | 100.00 |
| Logical | 33 | 33 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 51
EXPRESSION (ie_i & ((~attr_i.input_disable)))
--1- ------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Unreachable | |
| 1 | 0 | Covered | T41,T42,T43 |
| 1 | 1 | Covered | T4,T5,T6 |
LINE 78
EXPRESSION (ie ? inout_io : 1'bz)
-1
| -1- | Status | Tests |
|---|
| 0 | Covered | T41,T42,T43 |
| 1 | Covered | T4,T5,T6 |
LINE 80
EXPRESSION (attr_i.invert ^ in_raw_o)
------1------ ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T4,T5,T6 |
| 0 | 1 | Covered | T22,T190,T28 |
| 1 | 0 | Covered | T41,T42,T43 |
| 1 | 1 | Covered | T41,T42,T43 |
LINE 84
EXPRESSION (out_i ^ attr_i.invert)
--1-- ------2------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T4,T5,T6 |
| 0 | 1 | Covered | T41,T42,T43 |
| 1 | 0 | Covered | T22,T28,T38 |
| 1 | 1 | Covered | T41,T42,T43 |
LINE 85
EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
--1- ---------------------------------2---------------------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | Covered | T41,T42,T43 |
| 1 | 1 | Covered | T22,T28,T23 |
LINE 85
SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
--------------------1------------------- -----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T41,T42,T43 |
| 0 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | Covered | T41,T42,T43 |
LINE 85
SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
--------1-------- ---------2--------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | Covered | T41,T42,T43 |
| 1 | 1 | Covered | T41,T42,T43 |
LINE 92
EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
---------------------1--------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T41,T42,T43 |
LINE 92
SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
------1----- ------------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T41,T42,T43 |
| 1 | 0 | Covered | T22,T28,T23 |
| 1 | 1 | Covered | T41,T42,T43 |
LINE 93
EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
-----------------------1-----------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T22,T28,T23 |
LINE 93
SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
------1----- --------------2--------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | Covered | T41,T42,T43 |
| 1 | 1 | Covered | T22,T28,T23 |
LINE 95
EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
-------1------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T41,T42,T43 |
Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[42].u_mio_pad.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
8 |
8 |
100.00 |
| TERNARY |
78 |
2 |
2 |
100.00 |
| TERNARY |
92 |
2 |
2 |
100.00 |
| TERNARY |
93 |
2 |
2 |
100.00 |
| TERNARY |
95 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 78 (ie) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T4,T5,T6 |
| 0 |
Covered |
T41,T42,T43 |
LineNo. Expression
-1-: 92 ((gen_bidir.oe && attr_i.drive_strength[0])) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T41,T42,T43 |
| 0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 93 ((gen_bidir.oe && (!attr_i.drive_strength[0]))) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T22,T28,T23 |
| 0 |
Covered |
T4,T5,T6 |
LineNo. Expression
-1-: 95 (attr_i.pull_en) ?
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T41,T42,T43 |
| 0 |
Covered |
T4,T5,T6 |
Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[42].u_mio_pad.gen_generic.u_impl_generic
Assertion Details
| Name | Attempts | Real Successes | Failures | Incomplete |
|
AnalogNoScan_A |
1010 |
1010 |
0 |
0 |
AnalogNoScan_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
1010 |
1010 |
0 |
0 |
| T4 |
1 |
1 |
0 |
0 |
| T5 |
1 |
1 |
0 |
0 |
| T6 |
1 |
1 |
0 |
0 |
| T18 |
1 |
1 |
0 |
0 |
| T19 |
1 |
1 |
0 |
0 |
| T22 |
1 |
1 |
0 |
0 |
| T44 |
1 |
1 |
0 |
0 |
| T52 |
1 |
1 |
0 |
0 |
| T60 |
1 |
1 |
0 |
0 |
| T86 |
1 |
1 |
0 |
0 |