| T356 |
/workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_pings.4140513196 |
|
|
Jul 05 07:17:17 PM PDT 24 |
Jul 05 07:50:49 PM PDT 24 |
13186396720 ps |
| T702 |
/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_por_reset.4207688697 |
|
|
Jul 05 07:00:34 PM PDT 24 |
Jul 05 07:13:52 PM PDT 24 |
7656347700 ps |
| T703 |
/workspace/coverage/default/2.chip_sw_edn_sw_mode.4252587055 |
|
|
Jul 05 07:28:46 PM PDT 24 |
Jul 05 08:10:18 PM PDT 24 |
11118939380 ps |
| T184 |
/workspace/coverage/default/0.chip_sw_rstmgr_sw_rst.3075964308 |
|
|
Jul 05 06:58:49 PM PDT 24 |
Jul 05 07:02:53 PM PDT 24 |
3021199432 ps |
| T704 |
/workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.409204828 |
|
|
Jul 05 07:25:55 PM PDT 24 |
Jul 05 07:31:46 PM PDT 24 |
5672144190 ps |
| T705 |
/workspace/coverage/default/0.chip_sw_pwrmgr_sysrst_ctrl_reset.2056631977 |
|
|
Jul 05 06:58:11 PM PDT 24 |
Jul 05 07:17:16 PM PDT 24 |
6440140728 ps |
| T321 |
/workspace/coverage/default/0.chip_sw_keymgr_sideload_otbn.1190450356 |
|
|
Jul 05 07:01:29 PM PDT 24 |
Jul 05 08:16:54 PM PDT 24 |
16190010608 ps |
| T706 |
/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_lc.2064497370 |
|
|
Jul 05 07:03:07 PM PDT 24 |
Jul 05 07:11:49 PM PDT 24 |
6662972024 ps |
| T412 |
/workspace/coverage/default/31.chip_sw_alert_handler_lpg_sleep_mode_alerts.253533360 |
|
|
Jul 05 07:40:31 PM PDT 24 |
Jul 05 07:47:59 PM PDT 24 |
3082221018 ps |
| T707 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_dev.498053282 |
|
|
Jul 05 07:13:00 PM PDT 24 |
Jul 05 08:27:10 PM PDT 24 |
15811002116 ps |
| T119 |
/workspace/coverage/default/0.chip_sw_usbdev_pullup.57560441 |
|
|
Jul 05 06:56:30 PM PDT 24 |
Jul 05 07:00:41 PM PDT 24 |
3089619700 ps |
| T708 |
/workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.2381819900 |
|
|
Jul 05 07:17:45 PM PDT 24 |
Jul 05 07:26:20 PM PDT 24 |
5108352040 ps |
| T544 |
/workspace/coverage/default/13.chip_sw_all_escalation_resets.4155528571 |
|
|
Jul 05 07:37:38 PM PDT 24 |
Jul 05 07:47:13 PM PDT 24 |
4949557048 ps |
| T508 |
/workspace/coverage/default/12.chip_sw_alert_handler_lpg_sleep_mode_alerts.629823238 |
|
|
Jul 05 07:43:26 PM PDT 24 |
Jul 05 07:51:27 PM PDT 24 |
3658003484 ps |
| T467 |
/workspace/coverage/default/44.chip_sw_all_escalation_resets.2588306410 |
|
|
Jul 05 07:41:28 PM PDT 24 |
Jul 05 07:51:58 PM PDT 24 |
4692303000 ps |
| T262 |
/workspace/coverage/default/95.chip_sw_all_escalation_resets.498162189 |
|
|
Jul 05 07:46:06 PM PDT 24 |
Jul 05 07:54:49 PM PDT 24 |
5588037386 ps |
| T709 |
/workspace/coverage/default/1.chip_sw_alert_handler_ping_timeout.705560851 |
|
|
Jul 05 07:17:11 PM PDT 24 |
Jul 05 07:25:22 PM PDT 24 |
4240683980 ps |
| T556 |
/workspace/coverage/default/45.chip_sw_alert_handler_lpg_sleep_mode_alerts.2036895774 |
|
|
Jul 05 07:41:57 PM PDT 24 |
Jul 05 07:48:18 PM PDT 24 |
3077891262 ps |
| T710 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_rma.3732456965 |
|
|
Jul 05 07:11:56 PM PDT 24 |
Jul 05 08:50:52 PM PDT 24 |
22875461628 ps |
| T711 |
/workspace/coverage/default/2.chip_sw_aes_smoketest.409313420 |
|
|
Jul 05 07:34:53 PM PDT 24 |
Jul 05 07:39:22 PM PDT 24 |
2848596476 ps |
| T551 |
/workspace/coverage/default/84.chip_sw_alert_handler_lpg_sleep_mode_alerts.565558957 |
|
|
Jul 05 07:44:09 PM PDT 24 |
Jul 05 07:50:31 PM PDT 24 |
4251179300 ps |
| T137 |
/workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_wake_ups.670733118 |
|
|
Jul 05 07:31:04 PM PDT 24 |
Jul 05 08:00:10 PM PDT 24 |
20600194600 ps |
| T468 |
/workspace/coverage/default/13.chip_sw_alert_handler_lpg_sleep_mode_alerts.271795544 |
|
|
Jul 05 07:39:59 PM PDT 24 |
Jul 05 07:45:23 PM PDT 24 |
3211639844 ps |
| T397 |
/workspace/coverage/default/2.chip_sw_hmac_enc_jitter_en.137970739 |
|
|
Jul 05 07:28:38 PM PDT 24 |
Jul 05 07:35:08 PM PDT 24 |
3403450188 ps |
| T288 |
/workspace/coverage/default/1.chip_sw_otbn_mem_scramble.813455002 |
|
|
Jul 05 07:17:16 PM PDT 24 |
Jul 05 07:26:14 PM PDT 24 |
3882825918 ps |
| T712 |
/workspace/coverage/default/2.chip_sw_kmac_entropy.2260035769 |
|
|
Jul 05 07:25:14 PM PDT 24 |
Jul 05 07:29:34 PM PDT 24 |
3412064402 ps |
| T458 |
/workspace/coverage/default/51.chip_sw_alert_handler_lpg_sleep_mode_alerts.2049405619 |
|
|
Jul 05 07:42:33 PM PDT 24 |
Jul 05 07:48:14 PM PDT 24 |
3481871848 ps |
| T713 |
/workspace/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.1100559574 |
|
|
Jul 05 07:33:07 PM PDT 24 |
Jul 05 08:07:54 PM PDT 24 |
12349325690 ps |
| T714 |
/workspace/coverage/default/10.chip_sw_uart_rand_baudrate.2048406741 |
|
|
Jul 05 07:38:37 PM PDT 24 |
Jul 05 07:47:28 PM PDT 24 |
3736545146 ps |
| T546 |
/workspace/coverage/default/20.chip_sw_alert_handler_lpg_sleep_mode_alerts.284163914 |
|
|
Jul 05 07:39:46 PM PDT 24 |
Jul 05 07:49:01 PM PDT 24 |
4195003044 ps |
| T715 |
/workspace/coverage/default/2.chip_sw_csrng_fuse_en_sw_app_read_test.2214610898 |
|
|
Jul 05 07:28:29 PM PDT 24 |
Jul 05 07:36:17 PM PDT 24 |
5065074120 ps |
| T155 |
/workspace/coverage/default/2.chip_sw_otp_ctrl_vendor_test_csr_access.578102965 |
|
|
Jul 05 07:24:13 PM PDT 24 |
Jul 05 07:26:05 PM PDT 24 |
2249248789 ps |
| T244 |
/workspace/coverage/default/0.chip_sw_sysrst_ctrl_outputs.1600493417 |
|
|
Jul 05 07:01:34 PM PDT 24 |
Jul 05 07:06:58 PM PDT 24 |
4048259448 ps |
| T195 |
/workspace/coverage/default/2.chip_sw_i2c_device_tx_rx.3414113789 |
|
|
Jul 05 07:23:38 PM PDT 24 |
Jul 05 07:32:16 PM PDT 24 |
3965161944 ps |
| T251 |
/workspace/coverage/default/61.chip_sw_all_escalation_resets.2336749372 |
|
|
Jul 05 07:42:44 PM PDT 24 |
Jul 05 07:53:02 PM PDT 24 |
6117324600 ps |
| T501 |
/workspace/coverage/default/25.chip_sw_alert_handler_lpg_sleep_mode_alerts.2496370734 |
|
|
Jul 05 07:42:04 PM PDT 24 |
Jul 05 07:48:28 PM PDT 24 |
3818401516 ps |
| T716 |
/workspace/coverage/default/2.chip_sw_aes_enc_jitter_en.3958106589 |
|
|
Jul 05 07:28:56 PM PDT 24 |
Jul 05 07:33:12 PM PDT 24 |
3383867306 ps |
| T717 |
/workspace/coverage/default/1.chip_sw_otp_ctrl_ecc_error_vendor_test.516710380 |
|
|
Jul 05 07:14:15 PM PDT 24 |
Jul 05 07:19:07 PM PDT 24 |
3055742171 ps |
| T718 |
/workspace/coverage/default/1.rom_e2e_asm_init_rma.924800129 |
|
|
Jul 05 07:26:48 PM PDT 24 |
Jul 05 08:26:53 PM PDT 24 |
14722393519 ps |
| T719 |
/workspace/coverage/default/0.chip_sw_lc_walkthrough_testunlocks.110881181 |
|
|
Jul 05 06:58:55 PM PDT 24 |
Jul 05 07:42:55 PM PDT 24 |
28820166074 ps |
| T335 |
/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_disabled.3227800580 |
|
|
Jul 05 06:59:22 PM PDT 24 |
Jul 05 07:03:20 PM PDT 24 |
3046512648 ps |
| T720 |
/workspace/coverage/default/1.chip_sw_alert_handler_escalation.4140526332 |
|
|
Jul 05 07:18:10 PM PDT 24 |
Jul 05 07:27:33 PM PDT 24 |
5006493288 ps |
| T721 |
/workspace/coverage/default/1.chip_sw_clkmgr_jitter_frequency.881136619 |
|
|
Jul 05 07:18:38 PM PDT 24 |
Jul 05 07:27:18 PM PDT 24 |
3553978966 ps |
| T722 |
/workspace/coverage/default/2.rom_e2e_shutdown_exception_c.1146062826 |
|
|
Jul 05 07:37:47 PM PDT 24 |
Jul 05 08:31:21 PM PDT 24 |
14508665135 ps |
| T509 |
/workspace/coverage/default/34.chip_sw_alert_handler_lpg_sleep_mode_alerts.1410219480 |
|
|
Jul 05 07:39:11 PM PDT 24 |
Jul 05 07:45:08 PM PDT 24 |
3871931572 ps |
| T398 |
/workspace/coverage/default/0.chip_sw_rv_core_ibex_nmi_irq.937845547 |
|
|
Jul 05 06:59:42 PM PDT 24 |
Jul 05 07:13:33 PM PDT 24 |
4920465400 ps |
| T723 |
/workspace/coverage/default/0.chip_sw_rstmgr_rst_cnsty_escalation.3009523858 |
|
|
Jul 05 06:56:00 PM PDT 24 |
Jul 05 07:07:58 PM PDT 24 |
5916168230 ps |
| T724 |
/workspace/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.1376328072 |
|
|
Jul 05 07:05:48 PM PDT 24 |
Jul 05 07:10:47 PM PDT 24 |
3006951580 ps |
| T725 |
/workspace/coverage/default/1.chip_sw_rom_ctrl_integrity_check.539083762 |
|
|
Jul 05 07:20:03 PM PDT 24 |
Jul 05 07:31:22 PM PDT 24 |
9498762753 ps |
| T726 |
/workspace/coverage/default/4.chip_sw_uart_rand_baudrate.3115853800 |
|
|
Jul 05 07:35:27 PM PDT 24 |
Jul 05 08:01:36 PM PDT 24 |
8285518962 ps |
| T727 |
/workspace/coverage/default/1.chip_sw_clkmgr_off_aes_trans.2077385513 |
|
|
Jul 05 07:19:06 PM PDT 24 |
Jul 05 07:27:29 PM PDT 24 |
4620792266 ps |
| T324 |
/workspace/coverage/default/0.chip_sw_flash_init.2836076754 |
|
|
Jul 05 06:56:28 PM PDT 24 |
Jul 05 07:40:52 PM PDT 24 |
18085640264 ps |
| T728 |
/workspace/coverage/default/0.chip_sw_clkmgr_smoketest.1428528170 |
|
|
Jul 05 07:10:00 PM PDT 24 |
Jul 05 07:14:32 PM PDT 24 |
2993544860 ps |
| T235 |
/workspace/coverage/default/2.chip_sw_spi_device_pass_through.2900333614 |
|
|
Jul 05 07:24:24 PM PDT 24 |
Jul 05 07:35:26 PM PDT 24 |
6179737286 ps |
| T729 |
/workspace/coverage/default/0.chip_sw_rv_dm_access_after_wakeup.3789664286 |
|
|
Jul 05 07:03:36 PM PDT 24 |
Jul 05 07:14:15 PM PDT 24 |
6278239844 ps |
| T274 |
/workspace/coverage/default/1.chip_sw_data_integrity_escalation.3262157530 |
|
|
Jul 05 07:19:58 PM PDT 24 |
Jul 05 07:33:24 PM PDT 24 |
6312172100 ps |
| T275 |
/workspace/coverage/default/2.chip_sw_keymgr_sideload_otbn.3213373281 |
|
|
Jul 05 07:30:06 PM PDT 24 |
Jul 05 08:27:39 PM PDT 24 |
11928354776 ps |
| T276 |
/workspace/coverage/default/1.chip_sw_rv_plic_smoketest.554326912 |
|
|
Jul 05 07:23:03 PM PDT 24 |
Jul 05 07:27:11 PM PDT 24 |
2284912680 ps |
| T277 |
/workspace/coverage/default/0.chip_sw_edn_auto_mode.934586326 |
|
|
Jul 05 07:01:13 PM PDT 24 |
Jul 05 07:21:46 PM PDT 24 |
4572805048 ps |
| T278 |
/workspace/coverage/default/23.chip_sw_alert_handler_lpg_sleep_mode_alerts.1302134612 |
|
|
Jul 05 07:40:10 PM PDT 24 |
Jul 05 07:47:18 PM PDT 24 |
4353202710 ps |
| T279 |
/workspace/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en.793818713 |
|
|
Jul 05 07:01:41 PM PDT 24 |
Jul 05 07:27:14 PM PDT 24 |
7576825321 ps |
| T280 |
/workspace/coverage/default/2.chip_sw_hmac_smoketest.488497331 |
|
|
Jul 05 07:36:57 PM PDT 24 |
Jul 05 07:41:48 PM PDT 24 |
3115660460 ps |
| T281 |
/workspace/coverage/default/0.chip_sw_ast_clk_outputs.3767989428 |
|
|
Jul 05 07:02:59 PM PDT 24 |
Jul 05 07:23:50 PM PDT 24 |
7337568816 ps |
| T282 |
/workspace/coverage/default/1.chip_sw_aes_smoketest.3399786870 |
|
|
Jul 05 07:21:42 PM PDT 24 |
Jul 05 07:25:47 PM PDT 24 |
2827372880 ps |
| T283 |
/workspace/coverage/default/0.chip_sw_kmac_entropy.950298494 |
|
|
Jul 05 06:58:09 PM PDT 24 |
Jul 05 07:03:30 PM PDT 24 |
2515839560 ps |
| T488 |
/workspace/coverage/default/56.chip_sw_all_escalation_resets.3951927843 |
|
|
Jul 05 07:43:29 PM PDT 24 |
Jul 05 07:52:52 PM PDT 24 |
5782947432 ps |
| T730 |
/workspace/coverage/default/1.chip_sw_rstmgr_sw_req.1911248646 |
|
|
Jul 05 07:15:02 PM PDT 24 |
Jul 05 07:22:45 PM PDT 24 |
5332747176 ps |
| T731 |
/workspace/coverage/default/0.chip_sw_rstmgr_sw_req.2241410491 |
|
|
Jul 05 06:58:03 PM PDT 24 |
Jul 05 07:06:43 PM PDT 24 |
4817102932 ps |
| T327 |
/workspace/coverage/default/2.chip_sw_flash_init_reduced_freq.3747411377 |
|
|
Jul 05 07:32:25 PM PDT 24 |
Jul 05 08:04:34 PM PDT 24 |
20031658016 ps |
| T732 |
/workspace/coverage/default/89.chip_sw_alert_handler_lpg_sleep_mode_alerts.126581796 |
|
|
Jul 05 07:44:45 PM PDT 24 |
Jul 05 07:52:30 PM PDT 24 |
3907464592 ps |
| T733 |
/workspace/coverage/default/18.chip_sw_uart_rand_baudrate.64054469 |
|
|
Jul 05 07:38:28 PM PDT 24 |
Jul 05 08:02:53 PM PDT 24 |
8035750690 ps |
| T734 |
/workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_scramble.507124182 |
|
|
Jul 05 07:02:10 PM PDT 24 |
Jul 05 07:12:02 PM PDT 24 |
7257593718 ps |
| T735 |
/workspace/coverage/default/17.chip_sw_uart_rand_baudrate.299959197 |
|
|
Jul 05 07:39:08 PM PDT 24 |
Jul 05 08:11:04 PM PDT 24 |
8600468880 ps |
| T426 |
/workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_wake_ups.3874028999 |
|
|
Jul 05 07:18:59 PM PDT 24 |
Jul 05 07:28:05 PM PDT 24 |
7086260332 ps |
| T736 |
/workspace/coverage/default/2.chip_sw_hmac_enc_idle.224610317 |
|
|
Jul 05 07:29:42 PM PDT 24 |
Jul 05 07:35:01 PM PDT 24 |
3452975080 ps |
| T737 |
/workspace/coverage/default/13.chip_sw_lc_ctrl_transition.2700178357 |
|
|
Jul 05 07:39:43 PM PDT 24 |
Jul 05 07:46:19 PM PDT 24 |
5910614244 ps |
| T738 |
/workspace/coverage/default/1.chip_sw_entropy_src_ast_rng_req.1365989876 |
|
|
Jul 05 07:17:54 PM PDT 24 |
Jul 05 07:21:53 PM PDT 24 |
3140407732 ps |
| T739 |
/workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_scramble.3792302794 |
|
|
Jul 05 07:29:22 PM PDT 24 |
Jul 05 07:38:02 PM PDT 24 |
8350554470 ps |
| T740 |
/workspace/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.3250302113 |
|
|
Jul 05 07:04:22 PM PDT 24 |
Jul 05 07:16:52 PM PDT 24 |
5971500964 ps |
| T741 |
/workspace/coverage/default/2.chip_sw_lc_walkthrough_testunlocks.3093845851 |
|
|
Jul 05 07:24:38 PM PDT 24 |
Jul 05 07:53:03 PM PDT 24 |
19844205260 ps |
| T93 |
/workspace/coverage/default/4.chip_sw_sensor_ctrl_alert.3887360515 |
|
|
Jul 05 07:34:40 PM PDT 24 |
Jul 05 07:50:35 PM PDT 24 |
6327718810 ps |
| T742 |
/workspace/coverage/default/6.chip_sw_csrng_edn_concurrency.1955489834 |
|
|
Jul 05 07:37:23 PM PDT 24 |
Jul 05 09:10:32 PM PDT 24 |
25018269070 ps |
| T531 |
/workspace/coverage/default/59.chip_sw_all_escalation_resets.3695886301 |
|
|
Jul 05 07:42:47 PM PDT 24 |
Jul 05 07:54:19 PM PDT 24 |
4916389276 ps |
| T743 |
/workspace/coverage/default/1.chip_sw_pwrmgr_b2b_sleep_reset_req.124173833 |
|
|
Jul 05 07:19:29 PM PDT 24 |
Jul 05 07:59:39 PM PDT 24 |
21890682791 ps |
| T40 |
/workspace/coverage/default/1.chip_sw_gpio.892090223 |
|
|
Jul 05 07:13:36 PM PDT 24 |
Jul 05 07:23:01 PM PDT 24 |
4573300283 ps |
| T744 |
/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.2579843994 |
|
|
Jul 05 07:30:19 PM PDT 24 |
Jul 05 07:42:44 PM PDT 24 |
3651877112 ps |
| T745 |
/workspace/coverage/default/27.chip_sw_alert_handler_lpg_sleep_mode_alerts.4077092725 |
|
|
Jul 05 07:39:28 PM PDT 24 |
Jul 05 07:45:03 PM PDT 24 |
2826772500 ps |
| T746 |
/workspace/coverage/default/43.chip_sw_alert_handler_lpg_sleep_mode_alerts.3587728006 |
|
|
Jul 05 07:40:43 PM PDT 24 |
Jul 05 07:47:21 PM PDT 24 |
3793577574 ps |
| T747 |
/workspace/coverage/default/3.chip_sw_lc_ctrl_transition.3432650878 |
|
|
Jul 05 07:34:23 PM PDT 24 |
Jul 05 07:55:13 PM PDT 24 |
9493727644 ps |
| T748 |
/workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.2717407893 |
|
|
Jul 05 07:32:17 PM PDT 24 |
Jul 05 08:24:48 PM PDT 24 |
25104647978 ps |
| T363 |
/workspace/coverage/default/2.chip_sw_entropy_src_csrng.3879043744 |
|
|
Jul 05 07:29:00 PM PDT 24 |
Jul 05 07:49:39 PM PDT 24 |
5481671256 ps |
| T325 |
/workspace/coverage/default/2.chip_sw_lc_walkthrough_rma.1227067479 |
|
|
Jul 05 07:24:29 PM PDT 24 |
Jul 05 08:55:00 PM PDT 24 |
47258836566 ps |
| T749 |
/workspace/coverage/default/1.chip_sw_sleep_sram_ret_contents_scramble.3900764746 |
|
|
Jul 05 07:18:43 PM PDT 24 |
Jul 05 07:31:09 PM PDT 24 |
7643546138 ps |
| T750 |
/workspace/coverage/default/1.chip_sw_uart_tx_rx_idx1.3141665958 |
|
|
Jul 05 07:12:00 PM PDT 24 |
Jul 05 07:23:20 PM PDT 24 |
4809569072 ps |
| T422 |
/workspace/coverage/default/2.chip_sw_edn_boot_mode.3904695013 |
|
|
Jul 05 07:28:32 PM PDT 24 |
Jul 05 07:38:55 PM PDT 24 |
3370825140 ps |
| T751 |
/workspace/coverage/default/40.chip_sw_all_escalation_resets.4101458387 |
|
|
Jul 05 07:44:51 PM PDT 24 |
Jul 05 07:55:39 PM PDT 24 |
4629829684 ps |
| T752 |
/workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.1866399309 |
|
|
Jul 05 07:25:54 PM PDT 24 |
Jul 05 07:48:24 PM PDT 24 |
11141059929 ps |
| T753 |
/workspace/coverage/default/1.chip_sw_pwrmgr_wdog_reset.3486833508 |
|
|
Jul 05 07:16:19 PM PDT 24 |
Jul 05 07:25:20 PM PDT 24 |
4704199730 ps |
| T754 |
/workspace/coverage/default/1.chip_sw_aon_timer_irq.3820890761 |
|
|
Jul 05 07:15:21 PM PDT 24 |
Jul 05 07:21:48 PM PDT 24 |
3311815216 ps |
| T383 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.980682682 |
|
|
Jul 05 07:31:53 PM PDT 24 |
Jul 05 07:42:49 PM PDT 24 |
5148715521 ps |
| T755 |
/workspace/coverage/default/3.chip_sw_uart_tx_rx.2623232030 |
|
|
Jul 05 07:34:34 PM PDT 24 |
Jul 05 07:48:43 PM PDT 24 |
4529437784 ps |
| T86 |
/workspace/coverage/default/1.chip_sw_ast_clk_rst_inputs.120903580 |
|
|
Jul 05 07:22:07 PM PDT 24 |
Jul 05 08:06:04 PM PDT 24 |
20418513239 ps |
| T756 |
/workspace/coverage/default/0.chip_sw_uart_tx_rx_idx2.3571709643 |
|
|
Jul 05 06:56:49 PM PDT 24 |
Jul 05 07:07:23 PM PDT 24 |
4362476736 ps |
| T189 |
/workspace/coverage/default/2.chip_sw_rstmgr_alert_info.3450039108 |
|
|
Jul 05 07:25:13 PM PDT 24 |
Jul 05 07:57:33 PM PDT 24 |
14850040700 ps |
| T757 |
/workspace/coverage/default/2.chip_sw_keymgr_key_derivation.3814132314 |
|
|
Jul 05 07:29:37 PM PDT 24 |
Jul 05 08:01:14 PM PDT 24 |
8975410760 ps |
| T451 |
/workspace/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.4275212148 |
|
|
Jul 05 07:26:01 PM PDT 24 |
Jul 05 07:28:04 PM PDT 24 |
2072294237 ps |
| T471 |
/workspace/coverage/default/15.chip_sw_all_escalation_resets.4110952745 |
|
|
Jul 05 07:39:33 PM PDT 24 |
Jul 05 07:51:40 PM PDT 24 |
5542516030 ps |
| T758 |
/workspace/coverage/default/0.chip_sw_csrng_kat_test.1665537486 |
|
|
Jul 05 07:00:37 PM PDT 24 |
Jul 05 07:04:37 PM PDT 24 |
2606174884 ps |
| T759 |
/workspace/coverage/default/2.chip_sw_aon_timer_wdog_bite_reset.278531105 |
|
|
Jul 05 07:26:27 PM PDT 24 |
Jul 05 07:42:55 PM PDT 24 |
8549452832 ps |
| T760 |
/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.796010530 |
|
|
Jul 05 07:02:12 PM PDT 24 |
Jul 05 07:13:14 PM PDT 24 |
4065233890 ps |
| T761 |
/workspace/coverage/default/2.chip_sw_csrng_kat_test.3615025043 |
|
|
Jul 05 07:30:00 PM PDT 24 |
Jul 05 07:34:46 PM PDT 24 |
2975497320 ps |
| T762 |
/workspace/coverage/default/0.chip_sw_keymgr_sideload_kmac.3203756399 |
|
|
Jul 05 07:02:32 PM PDT 24 |
Jul 05 07:21:14 PM PDT 24 |
6407192630 ps |
| T476 |
/workspace/coverage/default/33.chip_sw_all_escalation_resets.703279035 |
|
|
Jul 05 07:39:52 PM PDT 24 |
Jul 05 07:51:45 PM PDT 24 |
6280943604 ps |
| T763 |
/workspace/coverage/default/3.chip_sw_uart_tx_rx_idx1.764811418 |
|
|
Jul 05 07:34:32 PM PDT 24 |
Jul 05 07:43:41 PM PDT 24 |
4374361544 ps |
| T764 |
/workspace/coverage/default/2.chip_sw_pwrmgr_sysrst_ctrl_reset.149609342 |
|
|
Jul 05 07:26:10 PM PDT 24 |
Jul 05 07:51:32 PM PDT 24 |
8837954362 ps |
| T253 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.1624370021 |
|
|
Jul 05 07:12:50 PM PDT 24 |
Jul 05 09:05:54 PM PDT 24 |
24387458800 ps |
| T765 |
/workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_power_glitch_reset.2699334236 |
|
|
Jul 05 07:26:02 PM PDT 24 |
Jul 05 08:18:08 PM PDT 24 |
38693181698 ps |
| T766 |
/workspace/coverage/default/8.chip_sw_csrng_edn_concurrency.497711100 |
|
|
Jul 05 07:37:25 PM PDT 24 |
Jul 05 08:46:58 PM PDT 24 |
19337048048 ps |
| T54 |
/workspace/coverage/default/1.chip_sw_spi_device_tpm.2199835668 |
|
|
Jul 05 07:12:05 PM PDT 24 |
Jul 05 07:19:00 PM PDT 24 |
3998010665 ps |
| T767 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_write_clear.2439096845 |
|
|
Jul 05 07:06:29 PM PDT 24 |
Jul 05 07:13:28 PM PDT 24 |
3515981694 ps |
| T768 |
/workspace/coverage/default/2.chip_sw_pwrmgr_all_reset_reqs.3343125078 |
|
|
Jul 05 07:26:01 PM PDT 24 |
Jul 05 07:54:53 PM PDT 24 |
12299413838 ps |
| T769 |
/workspace/coverage/default/2.chip_sw_uart_tx_rx_idx2.2777375376 |
|
|
Jul 05 07:22:51 PM PDT 24 |
Jul 05 07:35:39 PM PDT 24 |
4454483976 ps |
| T770 |
/workspace/coverage/default/1.chip_sw_kmac_smoketest.1573808524 |
|
|
Jul 05 07:21:58 PM PDT 24 |
Jul 05 07:27:12 PM PDT 24 |
2791530552 ps |
| T771 |
/workspace/coverage/default/19.chip_sw_uart_rand_baudrate.701265853 |
|
|
Jul 05 07:39:31 PM PDT 24 |
Jul 05 07:49:56 PM PDT 24 |
4565592752 ps |
| T772 |
/workspace/coverage/default/1.rom_e2e_shutdown_output.1147576326 |
|
|
Jul 05 07:26:28 PM PDT 24 |
Jul 05 08:26:39 PM PDT 24 |
34312146426 ps |
| T423 |
/workspace/coverage/default/1.chip_sw_edn_boot_mode.102240276 |
|
|
Jul 05 07:18:17 PM PDT 24 |
Jul 05 07:27:54 PM PDT 24 |
3145557000 ps |
| T497 |
/workspace/coverage/default/85.chip_sw_all_escalation_resets.3841899286 |
|
|
Jul 05 07:43:34 PM PDT 24 |
Jul 05 07:53:16 PM PDT 24 |
5444456936 ps |
| T289 |
/workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access.1436628999 |
|
|
Jul 05 07:01:52 PM PDT 24 |
Jul 05 07:08:48 PM PDT 24 |
4888208120 ps |
| T773 |
/workspace/coverage/default/2.chip_sw_edn_kat.2875528928 |
|
|
Jul 05 07:29:23 PM PDT 24 |
Jul 05 07:41:14 PM PDT 24 |
3775391482 ps |
| T332 |
/workspace/coverage/default/2.chip_sw_lc_walkthrough_dev.3853511157 |
|
|
Jul 05 07:25:08 PM PDT 24 |
Jul 05 08:50:41 PM PDT 24 |
50279036812 ps |
| T774 |
/workspace/coverage/default/48.chip_sw_alert_handler_lpg_sleep_mode_alerts.2524742527 |
|
|
Jul 05 07:43:03 PM PDT 24 |
Jul 05 07:49:51 PM PDT 24 |
3491606240 ps |
| T541 |
/workspace/coverage/default/15.chip_sw_alert_handler_lpg_sleep_mode_alerts.3027680755 |
|
|
Jul 05 07:37:24 PM PDT 24 |
Jul 05 07:43:54 PM PDT 24 |
4316332550 ps |
| T455 |
/workspace/coverage/default/49.chip_sw_all_escalation_resets.2327176669 |
|
|
Jul 05 07:42:42 PM PDT 24 |
Jul 05 07:53:10 PM PDT 24 |
4601418100 ps |
| T333 |
/workspace/coverage/default/2.chip_sw_flash_init.2141574466 |
|
|
Jul 05 07:22:23 PM PDT 24 |
Jul 05 07:53:51 PM PDT 24 |
24338830916 ps |
| T161 |
/workspace/coverage/default/0.chip_sw_lc_ctrl_program_error.3497117934 |
|
|
Jul 05 07:03:33 PM PDT 24 |
Jul 05 07:14:50 PM PDT 24 |
4815590472 ps |
| T452 |
/workspace/coverage/default/1.chip_sw_lc_ctrl_rand_to_scrap.701536244 |
|
|
Jul 05 07:13:29 PM PDT 24 |
Jul 05 07:19:25 PM PDT 24 |
4292255472 ps |
| T120 |
/workspace/coverage/default/0.chip_sw_usbdev_pincfg.1844161054 |
|
|
Jul 05 06:56:26 PM PDT 24 |
Jul 05 09:07:29 PM PDT 24 |
31383577792 ps |
| T300 |
/workspace/coverage/default/1.chip_sw_rv_core_ibex_icache_invalidate.1010179792 |
|
|
Jul 05 07:21:43 PM PDT 24 |
Jul 05 07:25:57 PM PDT 24 |
2566177819 ps |
| T775 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_clock_freqs.4208333532 |
|
|
Jul 05 07:13:35 PM PDT 24 |
Jul 05 07:35:47 PM PDT 24 |
5980608130 ps |
| T553 |
/workspace/coverage/default/83.chip_sw_alert_handler_lpg_sleep_mode_alerts.3141555648 |
|
|
Jul 05 07:43:56 PM PDT 24 |
Jul 05 07:48:59 PM PDT 24 |
4057680904 ps |
| T532 |
/workspace/coverage/default/26.chip_sw_alert_handler_lpg_sleep_mode_alerts.1144159619 |
|
|
Jul 05 07:40:11 PM PDT 24 |
Jul 05 07:47:55 PM PDT 24 |
4064833094 ps |
| T776 |
/workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_por_reset.2518593520 |
|
|
Jul 05 07:14:24 PM PDT 24 |
Jul 05 07:29:19 PM PDT 24 |
8192045320 ps |
| T777 |
/workspace/coverage/default/1.chip_sw_sram_ctrl_smoketest.1111973127 |
|
|
Jul 05 07:23:48 PM PDT 24 |
Jul 05 07:27:37 PM PDT 24 |
2730290840 ps |
| T778 |
/workspace/coverage/default/39.chip_sw_alert_handler_lpg_sleep_mode_alerts.3194991928 |
|
|
Jul 05 07:45:28 PM PDT 24 |
Jul 05 07:52:18 PM PDT 24 |
3722581702 ps |
| T192 |
/workspace/coverage/default/0.chip_plic_all_irqs_0.2355578299 |
|
|
Jul 05 07:01:57 PM PDT 24 |
Jul 05 07:19:30 PM PDT 24 |
6115194590 ps |
| T779 |
/workspace/coverage/default/15.chip_sw_uart_rand_baudrate.2523141420 |
|
|
Jul 05 07:38:33 PM PDT 24 |
Jul 05 07:48:58 PM PDT 24 |
4187825124 ps |
| T407 |
/workspace/coverage/default/0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.4220485648 |
|
|
Jul 05 07:05:04 PM PDT 24 |
Jul 05 07:14:01 PM PDT 24 |
6818994466 ps |
| T780 |
/workspace/coverage/default/0.chip_sw_kmac_idle.1046796552 |
|
|
Jul 05 07:02:40 PM PDT 24 |
Jul 05 07:08:42 PM PDT 24 |
3710582468 ps |
| T781 |
/workspace/coverage/default/7.chip_sw_csrng_edn_concurrency.1875227704 |
|
|
Jul 05 07:37:45 PM PDT 24 |
Jul 05 08:48:59 PM PDT 24 |
20466786004 ps |
| T408 |
/workspace/coverage/default/2.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.3117773632 |
|
|
Jul 05 07:32:09 PM PDT 24 |
Jul 05 07:39:34 PM PDT 24 |
5874640042 ps |
| T530 |
/workspace/coverage/default/77.chip_sw_all_escalation_resets.2118001787 |
|
|
Jul 05 07:43:28 PM PDT 24 |
Jul 05 07:53:25 PM PDT 24 |
5095115384 ps |
| T490 |
/workspace/coverage/default/14.chip_sw_alert_handler_lpg_sleep_mode_alerts.3896941728 |
|
|
Jul 05 07:37:32 PM PDT 24 |
Jul 05 07:45:10 PM PDT 24 |
4252638712 ps |
| T537 |
/workspace/coverage/default/72.chip_sw_all_escalation_resets.2249415783 |
|
|
Jul 05 07:42:37 PM PDT 24 |
Jul 05 07:54:06 PM PDT 24 |
5303078772 ps |
| T495 |
/workspace/coverage/default/88.chip_sw_all_escalation_resets.1535061922 |
|
|
Jul 05 07:44:25 PM PDT 24 |
Jul 05 07:52:57 PM PDT 24 |
5049245966 ps |
| T405 |
/workspace/coverage/default/1.chip_sw_power_sleep_load.612981252 |
|
|
Jul 05 07:25:09 PM PDT 24 |
Jul 05 07:32:25 PM PDT 24 |
4715152836 ps |
| T330 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_lc_rw_en.3265918752 |
|
|
Jul 05 07:13:01 PM PDT 24 |
Jul 05 07:20:15 PM PDT 24 |
5117048391 ps |
| T782 |
/workspace/coverage/default/0.chip_sw_edn_kat.1898211465 |
|
|
Jul 05 07:01:11 PM PDT 24 |
Jul 05 07:14:04 PM PDT 24 |
3396222724 ps |
| T783 |
/workspace/coverage/default/1.chip_sw_clkmgr_sleep_frequency.164854274 |
|
|
Jul 05 07:19:40 PM PDT 24 |
Jul 05 07:29:24 PM PDT 24 |
4800156000 ps |
| T534 |
/workspace/coverage/default/50.chip_sw_alert_handler_lpg_sleep_mode_alerts.1833728036 |
|
|
Jul 05 07:42:57 PM PDT 24 |
Jul 05 07:49:40 PM PDT 24 |
3356401760 ps |
| T529 |
/workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_alerts.3354316075 |
|
|
Jul 05 07:29:25 PM PDT 24 |
Jul 05 07:37:11 PM PDT 24 |
4420871120 ps |
| T784 |
/workspace/coverage/default/0.chip_sw_otp_ctrl_dai_lock.2711788304 |
|
|
Jul 05 06:57:49 PM PDT 24 |
Jul 05 08:31:54 PM PDT 24 |
27959389560 ps |
| T785 |
/workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq.2623317649 |
|
|
Jul 05 07:15:59 PM PDT 24 |
Jul 05 08:18:05 PM PDT 24 |
16837943804 ps |
| T245 |
/workspace/coverage/default/0.chip_sw_sysrst_ctrl_in_irq.3189089233 |
|
|
Jul 05 07:00:42 PM PDT 24 |
Jul 05 07:11:14 PM PDT 24 |
4767477968 ps |
| T786 |
/workspace/coverage/default/0.chip_sw_power_idle_load.1161466926 |
|
|
Jul 05 07:05:13 PM PDT 24 |
Jul 05 07:17:01 PM PDT 24 |
4202589008 ps |
| T787 |
/workspace/coverage/default/0.chip_sw_edn_entropy_reqs.3335553016 |
|
|
Jul 05 07:02:14 PM PDT 24 |
Jul 05 07:24:49 PM PDT 24 |
7001260160 ps |
| T788 |
/workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access.4124465923 |
|
|
Jul 05 07:30:31 PM PDT 24 |
Jul 05 07:43:38 PM PDT 24 |
4344572728 ps |
| T338 |
/workspace/coverage/default/30.chip_sw_alert_handler_lpg_sleep_mode_alerts.1303338319 |
|
|
Jul 05 07:39:33 PM PDT 24 |
Jul 05 07:45:57 PM PDT 24 |
3677333534 ps |
| T349 |
/workspace/coverage/default/0.rom_e2e_jtag_inject_dev.4191836033 |
|
|
Jul 05 07:09:15 PM PDT 24 |
Jul 05 08:03:07 PM PDT 24 |
32050000769 ps |
| T254 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.2812801987 |
|
|
Jul 05 07:13:52 PM PDT 24 |
Jul 05 08:51:23 PM PDT 24 |
23398516288 ps |
| T789 |
/workspace/coverage/default/2.chip_sw_pwrmgr_usbdev_smoketest.743987801 |
|
|
Jul 05 07:35:06 PM PDT 24 |
Jul 05 07:44:06 PM PDT 24 |
5374845556 ps |
| T790 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_dev.1360844579 |
|
|
Jul 05 07:11:47 PM PDT 24 |
Jul 05 08:54:22 PM PDT 24 |
24322599720 ps |
| T791 |
/workspace/coverage/default/2.chip_sw_otp_ctrl_ecc_error_vendor_test.301757766 |
|
|
Jul 05 07:25:48 PM PDT 24 |
Jul 05 07:30:34 PM PDT 24 |
2494043774 ps |
| T157 |
/workspace/coverage/default/0.chip_sw_otp_ctrl_escalation.1793154295 |
|
|
Jul 05 06:57:49 PM PDT 24 |
Jul 05 07:08:30 PM PDT 24 |
5198464600 ps |
| T390 |
/workspace/coverage/default/1.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.3683278062 |
|
|
Jul 05 07:17:06 PM PDT 24 |
Jul 05 07:28:57 PM PDT 24 |
19238799144 ps |
| T792 |
/workspace/coverage/default/1.chip_sw_rv_dm_access_after_wakeup.3369016847 |
|
|
Jul 05 07:20:01 PM PDT 24 |
Jul 05 07:28:09 PM PDT 24 |
6082434904 ps |
| T793 |
/workspace/coverage/default/1.chip_sw_lc_ctrl_otp_hw_cfg0.659604859 |
|
|
Jul 05 07:13:08 PM PDT 24 |
Jul 05 07:18:14 PM PDT 24 |
2412668380 ps |
| T794 |
/workspace/coverage/default/2.chip_sw_sysrst_ctrl_outputs.3728142728 |
|
|
Jul 05 07:25:57 PM PDT 24 |
Jul 05 07:32:16 PM PDT 24 |
3800889830 ps |
| T795 |
/workspace/coverage/default/1.chip_sw_hmac_enc_jitter_en.2834515146 |
|
|
Jul 05 07:17:08 PM PDT 24 |
Jul 05 07:22:28 PM PDT 24 |
3441538074 ps |
| T796 |
/workspace/coverage/default/0.chip_sw_example_rom.3542123025 |
|
|
Jul 05 06:54:54 PM PDT 24 |
Jul 05 06:56:50 PM PDT 24 |
1976793730 ps |
| T797 |
/workspace/coverage/default/0.chip_sw_alert_handler_ping_timeout.1345192471 |
|
|
Jul 05 06:59:39 PM PDT 24 |
Jul 05 07:08:03 PM PDT 24 |
4484400548 ps |
| T196 |
/workspace/coverage/default/2.chip_sw_i2c_host_tx_rx.3134675765 |
|
|
Jul 05 07:24:24 PM PDT 24 |
Jul 05 07:40:24 PM PDT 24 |
5261268360 ps |
| T798 |
/workspace/coverage/default/1.chip_sw_keymgr_sideload_kmac.305110740 |
|
|
Jul 05 07:17:30 PM PDT 24 |
Jul 05 07:42:30 PM PDT 24 |
6718227000 ps |
| T557 |
/workspace/coverage/default/41.chip_sw_alert_handler_lpg_sleep_mode_alerts.638892634 |
|
|
Jul 05 07:41:38 PM PDT 24 |
Jul 05 07:49:36 PM PDT 24 |
4130222344 ps |
| T799 |
/workspace/coverage/default/12.chip_sw_lc_ctrl_transition.1211269387 |
|
|
Jul 05 07:38:34 PM PDT 24 |
Jul 05 07:53:36 PM PDT 24 |
12121827998 ps |
| T800 |
/workspace/coverage/default/2.chip_sw_uart_tx_rx_idx3.4164649254 |
|
|
Jul 05 07:22:32 PM PDT 24 |
Jul 05 07:33:53 PM PDT 24 |
3824932360 ps |
| T801 |
/workspace/coverage/default/2.chip_sw_example_rom.3871975148 |
|
|
Jul 05 07:22:37 PM PDT 24 |
Jul 05 07:24:42 PM PDT 24 |
2568051360 ps |
| T331 |
/workspace/coverage/default/1.chip_sw_lc_walkthrough_prod.1977509387 |
|
|
Jul 05 07:14:37 PM PDT 24 |
Jul 05 08:46:54 PM PDT 24 |
49389880725 ps |
| T190 |
/workspace/coverage/default/2.chip_sw_rstmgr_sw_rst.2462770926 |
|
|
Jul 05 07:25:09 PM PDT 24 |
Jul 05 07:29:43 PM PDT 24 |
2894626480 ps |
| T802 |
/workspace/coverage/default/0.chip_sw_aes_masking_off.2000775943 |
|
|
Jul 05 07:02:15 PM PDT 24 |
Jul 05 07:07:41 PM PDT 24 |
3247962072 ps |
| T803 |
/workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en.3022988596 |
|
|
Jul 05 07:01:25 PM PDT 24 |
Jul 05 07:10:51 PM PDT 24 |
3803546545 ps |
| T804 |
/workspace/coverage/default/0.chip_sw_clkmgr_reset_frequency.3776987587 |
|
|
Jul 05 07:03:22 PM PDT 24 |
Jul 05 07:10:03 PM PDT 24 |
4128658212 ps |
| T427 |
/workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_wake_ups.2719438096 |
|
|
Jul 05 07:19:05 PM PDT 24 |
Jul 05 07:47:48 PM PDT 24 |
23989898230 ps |
| T805 |
/workspace/coverage/default/1.chip_sw_uart_tx_rx.740001252 |
|
|
Jul 05 07:11:32 PM PDT 24 |
Jul 05 07:21:02 PM PDT 24 |
3736769250 ps |
| T806 |
/workspace/coverage/default/2.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.4254242212 |
|
|
Jul 05 07:27:09 PM PDT 24 |
Jul 05 07:34:07 PM PDT 24 |
19078776000 ps |
| T402 |
/workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.2768006578 |
|
|
Jul 05 07:32:56 PM PDT 24 |
Jul 05 07:43:50 PM PDT 24 |
4756220532 ps |
| T107 |
/workspace/coverage/default/0.chip_sw_spi_device_pass_through.1178599224 |
|
|
Jul 05 06:57:33 PM PDT 24 |
Jul 05 07:09:09 PM PDT 24 |
6901087895 ps |
| T807 |
/workspace/coverage/default/26.chip_sw_all_escalation_resets.1068866059 |
|
|
Jul 05 07:42:20 PM PDT 24 |
Jul 05 07:53:07 PM PDT 24 |
5428955300 ps |
| T88 |
/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.3768198612 |
|
|
Jul 05 07:02:29 PM PDT 24 |
Jul 05 07:08:49 PM PDT 24 |
5426402370 ps |
| T808 |
/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.513217115 |
|
|
Jul 05 07:00:56 PM PDT 24 |
Jul 05 07:07:32 PM PDT 24 |
7005989888 ps |
| T809 |
/workspace/coverage/default/2.rom_e2e_asm_init_prod_end.2224917063 |
|
|
Jul 05 07:38:49 PM PDT 24 |
Jul 05 08:33:04 PM PDT 24 |
15891934633 ps |
| T810 |
/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.3573328389 |
|
|
Jul 05 07:22:04 PM PDT 24 |
Jul 05 07:34:14 PM PDT 24 |
4942358640 ps |
| T525 |
/workspace/coverage/default/53.chip_sw_all_escalation_resets.2799403145 |
|
|
Jul 05 07:41:47 PM PDT 24 |
Jul 05 07:51:54 PM PDT 24 |
5253203064 ps |
| T555 |
/workspace/coverage/default/28.chip_sw_all_escalation_resets.3281518570 |
|
|
Jul 05 07:39:00 PM PDT 24 |
Jul 05 07:48:59 PM PDT 24 |
5895832088 ps |
| T811 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.3040385615 |
|
|
Jul 05 07:12:19 PM PDT 24 |
Jul 05 08:23:47 PM PDT 24 |
11344032416 ps |
| T41 |
/workspace/coverage/default/2.chip_sw_gpio.616818358 |
|
|
Jul 05 07:23:12 PM PDT 24 |
Jul 05 07:34:26 PM PDT 24 |
3737992708 ps |
| T538 |
/workspace/coverage/default/11.chip_sw_alert_handler_lpg_sleep_mode_alerts.328260611 |
|
|
Jul 05 07:40:01 PM PDT 24 |
Jul 05 07:46:56 PM PDT 24 |
3760684654 ps |
| T812 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_lc_rw_en.2211300827 |
|
|
Jul 05 07:24:32 PM PDT 24 |
Jul 05 07:36:03 PM PDT 24 |
5358520047 ps |
| T813 |
/workspace/coverage/default/2.chip_sw_sram_ctrl_smoketest.1268836679 |
|
|
Jul 05 07:35:29 PM PDT 24 |
Jul 05 07:40:08 PM PDT 24 |
3014038596 ps |
| T814 |
/workspace/coverage/default/1.chip_sw_csrng_smoketest.1305777063 |
|
|
Jul 05 07:21:39 PM PDT 24 |
Jul 05 07:25:19 PM PDT 24 |
2714987046 ps |
| T815 |
/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.1871588118 |
|
|
Jul 05 07:18:46 PM PDT 24 |
Jul 05 07:31:05 PM PDT 24 |
4434921960 ps |
| T816 |
/workspace/coverage/default/2.chip_sw_sensor_ctrl_alert.3857125243 |
|
|
Jul 05 07:29:40 PM PDT 24 |
Jul 05 07:43:34 PM PDT 24 |
7225128688 ps |
| T148 |
/workspace/coverage/default/1.chip_plic_all_irqs_20.3187786024 |
|
|
Jul 05 07:19:36 PM PDT 24 |
Jul 05 07:33:38 PM PDT 24 |
4722804130 ps |
| T496 |
/workspace/coverage/default/4.chip_sw_alert_handler_lpg_sleep_mode_alerts.483755946 |
|
|
Jul 05 07:37:04 PM PDT 24 |
Jul 05 07:44:43 PM PDT 24 |
4250138640 ps |
| T492 |
/workspace/coverage/default/65.chip_sw_alert_handler_lpg_sleep_mode_alerts.2096120532 |
|
|
Jul 05 07:41:56 PM PDT 24 |
Jul 05 07:49:04 PM PDT 24 |
3946577080 ps |
| T817 |
/workspace/coverage/default/0.chip_sw_flash_crash_alert.1091180211 |
|
|
Jul 05 07:04:37 PM PDT 24 |
Jul 05 07:15:40 PM PDT 24 |
5493014134 ps |
| T818 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.497381776 |
|
|
Jul 05 07:04:10 PM PDT 24 |
Jul 05 07:23:13 PM PDT 24 |
7342493039 ps |
| T819 |
/workspace/coverage/default/4.chip_sw_uart_tx_rx.765475844 |
|
|
Jul 05 07:34:49 PM PDT 24 |
Jul 05 07:47:42 PM PDT 24 |
4382500800 ps |
| T820 |
/workspace/coverage/default/2.chip_sw_alert_handler_entropy.495928075 |
|
|
Jul 05 07:27:57 PM PDT 24 |
Jul 05 07:34:21 PM PDT 24 |
2821874042 ps |
| T821 |
/workspace/coverage/default/1.chip_sw_otbn_smoketest.3845547682 |
|
|
Jul 05 07:23:00 PM PDT 24 |
Jul 05 07:39:53 PM PDT 24 |
4867181672 ps |
| T822 |
/workspace/coverage/default/0.chip_sw_lc_ctrl_raw_to_scrap.1776664536 |
|
|
Jul 05 06:57:12 PM PDT 24 |
Jul 05 06:59:22 PM PDT 24 |
3752692092 ps |
| T823 |
/workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_reset_reqs.3240828378 |
|
|
Jul 05 07:14:30 PM PDT 24 |
Jul 05 07:48:04 PM PDT 24 |
18978539241 ps |
| T51 |
/workspace/coverage/default/2.chip_sw_sysrst_ctrl_ulp_z3_wakeup.3164043189 |
|
|
Jul 05 07:26:27 PM PDT 24 |
Jul 05 07:34:57 PM PDT 24 |
5050973780 ps |
| T558 |
/workspace/coverage/default/39.chip_sw_all_escalation_resets.464773038 |
|
|
Jul 05 07:40:17 PM PDT 24 |
Jul 05 07:51:32 PM PDT 24 |
4132240316 ps |
| T824 |
/workspace/coverage/default/0.chip_sw_entropy_src_kat_test.902961961 |
|
|
Jul 05 07:01:11 PM PDT 24 |
Jul 05 07:03:54 PM PDT 24 |
3161101752 ps |
| T503 |
/workspace/coverage/default/23.chip_sw_all_escalation_resets.566347359 |
|
|
Jul 05 07:40:06 PM PDT 24 |
Jul 05 07:52:08 PM PDT 24 |
5232789734 ps |
| T825 |
/workspace/coverage/default/1.chip_sw_aon_timer_wdog_bite_reset.2963602482 |
|
|
Jul 05 07:15:29 PM PDT 24 |
Jul 05 07:33:36 PM PDT 24 |
10237345110 ps |
| T826 |
/workspace/coverage/default/1.chip_sw_alert_handler_reverse_ping_in_deep_sleep.3457740857 |
|
|
Jul 05 07:16:32 PM PDT 24 |
Jul 05 11:06:25 PM PDT 24 |
255774021752 ps |
| T512 |
/workspace/coverage/default/32.chip_sw_alert_handler_lpg_sleep_mode_alerts.2820745169 |
|
|
Jul 05 07:40:41 PM PDT 24 |
Jul 05 07:47:12 PM PDT 24 |
3813998972 ps |
| T827 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.3053708427 |
|
|
Jul 05 07:12:12 PM PDT 24 |
Jul 05 08:53:13 PM PDT 24 |
24405608728 ps |
| T828 |
/workspace/coverage/default/3.chip_sw_all_escalation_resets.3615466872 |
|
|
Jul 05 07:33:45 PM PDT 24 |
Jul 05 07:45:01 PM PDT 24 |
4930507092 ps |
| T829 |
/workspace/coverage/default/0.chip_sw_clkmgr_off_kmac_trans.3528546028 |
|
|
Jul 05 07:01:56 PM PDT 24 |
Jul 05 07:09:00 PM PDT 24 |
4935562072 ps |
| T830 |
/workspace/coverage/default/0.chip_sw_entropy_src_ast_rng_req.1561550093 |
|
|
Jul 05 07:00:46 PM PDT 24 |
Jul 05 07:04:05 PM PDT 24 |
2656384640 ps |
| T831 |
/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx3.4167028144 |
|
|
Jul 05 07:35:02 PM PDT 24 |
Jul 05 07:46:58 PM PDT 24 |
4311517488 ps |
| T89 |
/workspace/coverage/default/2.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.1367495942 |
|
|
Jul 05 07:31:00 PM PDT 24 |
Jul 05 07:38:47 PM PDT 24 |
5713826074 ps |
| T832 |
/workspace/coverage/default/1.chip_sw_sysrst_ctrl_ec_rst_l.3420331684 |
|
|
Jul 05 07:15:29 PM PDT 24 |
Jul 05 08:07:54 PM PDT 24 |
20605749970 ps |
| T833 |
/workspace/coverage/default/0.chip_sw_aes_idle.498535459 |
|
|
Jul 05 07:00:14 PM PDT 24 |
Jul 05 07:03:24 PM PDT 24 |
3495087384 ps |
| T263 |
/workspace/coverage/default/82.chip_sw_all_escalation_resets.381053137 |
|
|
Jul 05 07:43:46 PM PDT 24 |
Jul 05 07:51:56 PM PDT 24 |
5882153964 ps |
| T378 |
/workspace/coverage/default/79.chip_sw_all_escalation_resets.664573485 |
|
|
Jul 05 07:44:22 PM PDT 24 |
Jul 05 07:54:29 PM PDT 24 |
6037139704 ps |
| T834 |
/workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_por_reset.370663345 |
|
|
Jul 05 07:15:58 PM PDT 24 |
Jul 05 07:32:17 PM PDT 24 |
8141644768 ps |
| T540 |
/workspace/coverage/default/17.chip_sw_alert_handler_lpg_sleep_mode_alerts.2709905806 |
|
|
Jul 05 07:38:32 PM PDT 24 |
Jul 05 07:45:38 PM PDT 24 |
3489311076 ps |
| T835 |
/workspace/coverage/default/1.chip_sw_rv_timer_irq.768004692 |
|
|
Jul 05 07:14:56 PM PDT 24 |
Jul 05 07:18:30 PM PDT 24 |
2737341950 ps |
| T836 |
/workspace/coverage/default/2.chip_sw_uart_tx_rx_idx1.1509087382 |
|
|
Jul 05 07:22:10 PM PDT 24 |
Jul 05 07:30:33 PM PDT 24 |
3868622200 ps |
| T837 |
/workspace/coverage/default/1.chip_sw_lc_walkthrough_testunlocks.1806061109 |
|
|
Jul 05 07:14:37 PM PDT 24 |
Jul 05 07:49:25 PM PDT 24 |
27225249056 ps |
| T838 |
/workspace/coverage/default/0.chip_sw_alert_handler_entropy.2387374199 |
|
|
Jul 05 07:00:35 PM PDT 24 |
Jul 05 07:05:31 PM PDT 24 |
3218278812 ps |
| T839 |
/workspace/coverage/default/0.chip_sw_rstmgr_smoketest.2383916288 |
|
|
Jul 05 07:11:33 PM PDT 24 |
Jul 05 07:15:09 PM PDT 24 |
2627037500 ps |
| T840 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.2773047054 |
|
|
Jul 05 07:32:21 PM PDT 24 |
Jul 05 07:51:05 PM PDT 24 |
7288762654 ps |
| T841 |
/workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en.2265678169 |
|
|
Jul 05 07:15:47 PM PDT 24 |
Jul 05 08:22:22 PM PDT 24 |
18326414575 ps |
| T71 |
/workspace/coverage/default/1.chip_sw_sensor_ctrl_status.3356612698 |
|
|
Jul 05 07:18:23 PM PDT 24 |
Jul 05 07:23:45 PM PDT 24 |
2540828085 ps |
| T842 |
/workspace/coverage/default/0.chip_sw_otbn_smoketest.2742757738 |
|
|
Jul 05 07:11:20 PM PDT 24 |
Jul 05 07:26:09 PM PDT 24 |
4892170728 ps |
| T843 |
/workspace/coverage/default/6.chip_sw_uart_rand_baudrate.228898791 |
|
|
Jul 05 07:36:44 PM PDT 24 |
Jul 05 07:46:29 PM PDT 24 |
3840503608 ps |