| T844 |
/workspace/coverage/default/63.chip_sw_all_escalation_resets.3194111322 |
|
|
Jul 05 07:41:37 PM PDT 24 |
Jul 05 07:50:22 PM PDT 24 |
4839609200 ps |
| T542 |
/workspace/coverage/default/86.chip_sw_all_escalation_resets.2661460299 |
|
|
Jul 05 07:43:34 PM PDT 24 |
Jul 05 07:50:27 PM PDT 24 |
4859612800 ps |
| T845 |
/workspace/coverage/default/2.chip_sw_sysrst_ctrl_in_irq.2303215315 |
|
|
Jul 05 07:25:45 PM PDT 24 |
Jul 05 07:34:47 PM PDT 24 |
4504543463 ps |
| T846 |
/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.1202790059 |
|
|
Jul 05 07:18:27 PM PDT 24 |
Jul 05 07:28:23 PM PDT 24 |
4786746798 ps |
| T847 |
/workspace/coverage/default/2.chip_sw_pwrmgr_b2b_sleep_reset_req.1417605441 |
|
|
Jul 05 07:30:24 PM PDT 24 |
Jul 05 08:10:21 PM PDT 24 |
29899220527 ps |
| T48 |
/workspace/coverage/default/2.chip_sw_spi_host_tx_rx.4039837406 |
|
|
Jul 05 07:23:53 PM PDT 24 |
Jul 05 07:28:40 PM PDT 24 |
3638878726 ps |
| T848 |
/workspace/coverage/default/1.chip_sw_hmac_multistream.3025822700 |
|
|
Jul 05 07:17:35 PM PDT 24 |
Jul 05 07:46:39 PM PDT 24 |
7899446392 ps |
| T849 |
/workspace/coverage/default/2.chip_sw_aes_idle.393957130 |
|
|
Jul 05 07:27:19 PM PDT 24 |
Jul 05 07:32:54 PM PDT 24 |
3335108494 ps |
| T850 |
/workspace/coverage/default/1.chip_sw_pwrmgr_sleep_power_glitch_reset.965689841 |
|
|
Jul 05 07:14:49 PM PDT 24 |
Jul 05 07:23:27 PM PDT 24 |
6388522540 ps |
| T851 |
/workspace/coverage/default/1.chip_sw_hmac_smoketest.3170119545 |
|
|
Jul 05 07:23:59 PM PDT 24 |
Jul 05 07:29:26 PM PDT 24 |
3750697476 ps |
| T227 |
/workspace/coverage/default/0.rom_e2e_jtag_inject_rma.1291903013 |
|
|
Jul 05 07:09:45 PM PDT 24 |
Jul 05 07:58:19 PM PDT 24 |
37362112830 ps |
| T852 |
/workspace/coverage/default/0.chip_sw_kmac_mode_kmac.3935478246 |
|
|
Jul 05 07:01:55 PM PDT 24 |
Jul 05 07:07:11 PM PDT 24 |
2750414084 ps |
| T853 |
/workspace/coverage/default/1.chip_sw_clkmgr_jitter_reduced_freq.1360953801 |
|
|
Jul 05 07:20:53 PM PDT 24 |
Jul 05 07:24:56 PM PDT 24 |
2597953207 ps |
| T547 |
/workspace/coverage/default/87.chip_sw_alert_handler_lpg_sleep_mode_alerts.258499726 |
|
|
Jul 05 07:43:35 PM PDT 24 |
Jul 05 07:48:54 PM PDT 24 |
3049750064 ps |
| T548 |
/workspace/coverage/default/10.chip_sw_all_escalation_resets.3589635027 |
|
|
Jul 05 07:37:56 PM PDT 24 |
Jul 05 07:52:00 PM PDT 24 |
4648191822 ps |
| T854 |
/workspace/coverage/default/1.chip_sw_kmac_mode_kmac.237653522 |
|
|
Jul 05 07:18:11 PM PDT 24 |
Jul 05 07:22:57 PM PDT 24 |
2579572944 ps |
| T855 |
/workspace/coverage/default/2.chip_sw_aes_enc_jitter_en_reduced_freq.281032800 |
|
|
Jul 05 07:32:36 PM PDT 24 |
Jul 05 07:36:31 PM PDT 24 |
2624736677 ps |
| T514 |
/workspace/coverage/default/60.chip_sw_all_escalation_resets.3122327697 |
|
|
Jul 05 07:44:21 PM PDT 24 |
Jul 05 07:53:08 PM PDT 24 |
4529752412 ps |
| T290 |
/workspace/coverage/default/67.chip_sw_alert_handler_lpg_sleep_mode_alerts.712579643 |
|
|
Jul 05 07:45:38 PM PDT 24 |
Jul 05 07:51:25 PM PDT 24 |
3778468656 ps |
| T67 |
/workspace/coverage/default/2.chip_jtag_mem_access.3289938640 |
|
|
Jul 05 07:24:19 PM PDT 24 |
Jul 05 07:48:06 PM PDT 24 |
13922938440 ps |
| T856 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0.1313274096 |
|
|
Jul 05 07:11:13 PM PDT 24 |
Jul 05 08:01:13 PM PDT 24 |
11535057020 ps |
| T504 |
/workspace/coverage/default/54.chip_sw_alert_handler_lpg_sleep_mode_alerts.1154441959 |
|
|
Jul 05 07:42:33 PM PDT 24 |
Jul 05 07:49:48 PM PDT 24 |
4141042440 ps |
| T857 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_access.2548393305 |
|
|
Jul 05 06:57:01 PM PDT 24 |
Jul 05 07:17:40 PM PDT 24 |
5564939204 ps |
| T858 |
/workspace/coverage/default/9.chip_sw_csrng_edn_concurrency.3236767325 |
|
|
Jul 05 07:36:18 PM PDT 24 |
Jul 05 09:12:14 PM PDT 24 |
27022139160 ps |
| T859 |
/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.3024236183 |
|
|
Jul 05 07:03:24 PM PDT 24 |
Jul 05 07:12:41 PM PDT 24 |
4635186274 ps |
| T198 |
/workspace/coverage/default/2.chip_sw_i2c_host_tx_rx_idx1.1186369404 |
|
|
Jul 05 07:23:13 PM PDT 24 |
Jul 05 07:36:15 PM PDT 24 |
4787367902 ps |
| T153 |
/workspace/coverage/default/0.chip_sw_otp_ctrl_vendor_test_csr_access.4038192974 |
|
|
Jul 05 07:00:19 PM PDT 24 |
Jul 05 07:03:12 PM PDT 24 |
2536076196 ps |
| T110 |
/workspace/coverage/default/1.chip_plic_all_irqs_10.3474911229 |
|
|
Jul 05 07:19:59 PM PDT 24 |
Jul 05 07:31:13 PM PDT 24 |
4482154442 ps |
| T860 |
/workspace/coverage/default/1.chip_sw_rstmgr_smoketest.882573582 |
|
|
Jul 05 07:22:50 PM PDT 24 |
Jul 05 07:27:18 PM PDT 24 |
2988233780 ps |
| T72 |
/workspace/coverage/default/0.chip_sw_pwrmgr_full_aon_reset.382668874 |
|
|
Jul 05 07:00:19 PM PDT 24 |
Jul 05 07:09:54 PM PDT 24 |
8400880200 ps |
| T413 |
/workspace/coverage/default/70.chip_sw_all_escalation_resets.3227052591 |
|
|
Jul 05 07:44:37 PM PDT 24 |
Jul 05 07:55:39 PM PDT 24 |
4590790920 ps |
| T861 |
/workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.3216085651 |
|
|
Jul 05 07:36:11 PM PDT 24 |
Jul 05 07:46:30 PM PDT 24 |
4048784862 ps |
| T520 |
/workspace/coverage/default/90.chip_sw_all_escalation_resets.4178522772 |
|
|
Jul 05 07:43:48 PM PDT 24 |
Jul 05 07:55:05 PM PDT 24 |
4123003484 ps |
| T350 |
/workspace/coverage/default/0.rom_e2e_jtag_inject_test_unlocked0.4232546429 |
|
|
Jul 05 07:08:31 PM PDT 24 |
Jul 05 07:44:31 PM PDT 24 |
24478319219 ps |
| T862 |
/workspace/coverage/default/64.chip_sw_alert_handler_lpg_sleep_mode_alerts.1622383388 |
|
|
Jul 05 07:43:02 PM PDT 24 |
Jul 05 07:50:10 PM PDT 24 |
3754186636 ps |
| T863 |
/workspace/coverage/default/0.chip_sw_uart_tx_rx_idx3.2174066044 |
|
|
Jul 05 06:55:57 PM PDT 24 |
Jul 05 07:04:38 PM PDT 24 |
3683087896 ps |
| T864 |
/workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.1636678637 |
|
|
Jul 05 07:04:45 PM PDT 24 |
Jul 05 08:16:57 PM PDT 24 |
24848831019 ps |
| T865 |
/workspace/coverage/default/0.chip_sw_clkmgr_jitter.4264282786 |
|
|
Jul 05 07:02:40 PM PDT 24 |
Jul 05 07:07:05 PM PDT 24 |
2856784172 ps |
| T866 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_write_clear.2882973175 |
|
|
Jul 05 07:31:15 PM PDT 24 |
Jul 05 07:36:49 PM PDT 24 |
3131316798 ps |
| T228 |
/workspace/coverage/default/2.chip_sw_sram_ctrl_execution_main.4063857682 |
|
|
Jul 05 07:30:29 PM PDT 24 |
Jul 05 07:43:24 PM PDT 24 |
6678716235 ps |
| T867 |
/workspace/coverage/default/2.chip_sw_aon_timer_wdog_lc_escalate.1160076130 |
|
|
Jul 05 07:26:30 PM PDT 24 |
Jul 05 07:38:54 PM PDT 24 |
5632364728 ps |
| T404 |
/workspace/coverage/default/1.chip_sw_plic_sw_irq.205387182 |
|
|
Jul 05 07:21:37 PM PDT 24 |
Jul 05 07:26:45 PM PDT 24 |
3191686760 ps |
| T868 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_lc_rw_en.3607450597 |
|
|
Jul 05 06:57:30 PM PDT 24 |
Jul 05 07:08:58 PM PDT 24 |
5314164374 ps |
| T869 |
/workspace/coverage/default/0.chip_sw_usb_ast_clk_calib.1071887535 |
|
|
Jul 05 07:06:53 PM PDT 24 |
Jul 05 07:13:14 PM PDT 24 |
3481999321 ps |
| T870 |
/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_lc.2794944552 |
|
|
Jul 05 07:31:32 PM PDT 24 |
Jul 05 07:38:55 PM PDT 24 |
4707931275 ps |
| T871 |
/workspace/coverage/default/1.chip_sw_pwrmgr_full_aon_reset.4292897634 |
|
|
Jul 05 07:15:00 PM PDT 24 |
Jul 05 07:23:11 PM PDT 24 |
7846878560 ps |
| T872 |
/workspace/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en.1917588245 |
|
|
Jul 05 07:02:32 PM PDT 24 |
Jul 05 07:07:27 PM PDT 24 |
3548476325 ps |
| T372 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en.3767964480 |
|
|
Jul 05 07:13:18 PM PDT 24 |
Jul 05 07:26:53 PM PDT 24 |
3685155117 ps |
| T873 |
/workspace/coverage/default/1.chip_sw_csrng_lc_hw_debug_en_test.1166804578 |
|
|
Jul 05 07:16:32 PM PDT 24 |
Jul 05 07:26:58 PM PDT 24 |
7160374810 ps |
| T874 |
/workspace/coverage/default/2.chip_sw_entropy_src_kat_test.1265362896 |
|
|
Jul 05 07:28:56 PM PDT 24 |
Jul 05 07:33:23 PM PDT 24 |
3105934304 ps |
| T367 |
/workspace/coverage/default/0.chip_sw_i2c_device_tx_rx.1969206333 |
|
|
Jul 05 06:57:47 PM PDT 24 |
Jul 05 07:06:51 PM PDT 24 |
3178271164 ps |
| T875 |
/workspace/coverage/default/0.chip_sw_alert_handler_escalation.4028140810 |
|
|
Jul 05 07:00:42 PM PDT 24 |
Jul 05 07:07:36 PM PDT 24 |
4315080300 ps |
| T876 |
/workspace/coverage/default/1.rom_e2e_asm_init_prod.2888102849 |
|
|
Jul 05 07:25:27 PM PDT 24 |
Jul 05 08:35:40 PM PDT 24 |
15663334668 ps |
| T114 |
/workspace/coverage/default/0.chip_sw_alert_test.3487438896 |
|
|
Jul 05 07:01:30 PM PDT 24 |
Jul 05 07:06:54 PM PDT 24 |
3021712200 ps |
| T543 |
/workspace/coverage/default/75.chip_sw_all_escalation_resets.2711800129 |
|
|
Jul 05 07:42:54 PM PDT 24 |
Jul 05 07:54:03 PM PDT 24 |
4847212540 ps |
| T111 |
/workspace/coverage/default/0.chip_plic_all_irqs_10.4083898760 |
|
|
Jul 05 07:03:51 PM PDT 24 |
Jul 05 07:14:30 PM PDT 24 |
3639851706 ps |
| T877 |
/workspace/coverage/default/2.chip_sw_lc_ctrl_otp_hw_cfg0.543510494 |
|
|
Jul 05 07:23:45 PM PDT 24 |
Jul 05 07:28:02 PM PDT 24 |
2927725672 ps |
| T878 |
/workspace/coverage/default/2.chip_sw_rv_plic_smoketest.3570388379 |
|
|
Jul 05 07:34:22 PM PDT 24 |
Jul 05 07:38:08 PM PDT 24 |
3335489600 ps |
| T879 |
/workspace/coverage/default/1.chip_sw_pwrmgr_usb_clk_disabled_when_active.359146032 |
|
|
Jul 05 07:15:29 PM PDT 24 |
Jul 05 07:22:15 PM PDT 24 |
3600679920 ps |
| T880 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_rma.448730275 |
|
|
Jul 05 07:13:24 PM PDT 24 |
Jul 05 08:16:28 PM PDT 24 |
14382137918 ps |
| T339 |
/workspace/coverage/default/76.chip_sw_alert_handler_lpg_sleep_mode_alerts.1366279203 |
|
|
Jul 05 07:43:52 PM PDT 24 |
Jul 05 07:50:38 PM PDT 24 |
4236286878 ps |
| T545 |
/workspace/coverage/default/19.chip_sw_alert_handler_lpg_sleep_mode_alerts.2540636172 |
|
|
Jul 05 07:38:46 PM PDT 24 |
Jul 05 07:46:39 PM PDT 24 |
3544964960 ps |
| T881 |
/workspace/coverage/default/0.chip_sw_clkmgr_jitter_frequency.3858169595 |
|
|
Jul 05 07:03:38 PM PDT 24 |
Jul 05 07:10:32 PM PDT 24 |
3467651352 ps |
| T882 |
/workspace/coverage/default/0.chip_sw_lc_walkthrough_rma.4121574854 |
|
|
Jul 05 06:58:32 PM PDT 24 |
Jul 05 08:25:59 PM PDT 24 |
46668692595 ps |
| T459 |
/workspace/coverage/default/68.chip_sw_alert_handler_lpg_sleep_mode_alerts.619571296 |
|
|
Jul 05 07:42:20 PM PDT 24 |
Jul 05 07:49:22 PM PDT 24 |
3442306080 ps |
| T883 |
/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.2162188557 |
|
|
Jul 05 06:58:20 PM PDT 24 |
Jul 05 07:19:56 PM PDT 24 |
15311736307 ps |
| T884 |
/workspace/coverage/default/2.chip_sw_pwrmgr_smoketest.1771065335 |
|
|
Jul 05 07:34:27 PM PDT 24 |
Jul 05 07:40:38 PM PDT 24 |
5981338256 ps |
| T885 |
/workspace/coverage/default/0.chip_sw_keymgr_key_derivation.824368335 |
|
|
Jul 05 07:00:52 PM PDT 24 |
Jul 05 07:32:03 PM PDT 24 |
8439793648 ps |
| T886 |
/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.2417347724 |
|
|
Jul 05 07:18:32 PM PDT 24 |
Jul 05 07:30:27 PM PDT 24 |
3935605352 ps |
| T887 |
/workspace/coverage/default/2.chip_sw_kmac_mode_kmac.4121811205 |
|
|
Jul 05 07:29:59 PM PDT 24 |
Jul 05 07:36:39 PM PDT 24 |
3031826000 ps |
| T549 |
/workspace/coverage/default/16.chip_sw_all_escalation_resets.460445190 |
|
|
Jul 05 07:38:46 PM PDT 24 |
Jul 05 07:48:59 PM PDT 24 |
5844077414 ps |
| T888 |
/workspace/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock.1131386682 |
|
|
Jul 05 07:25:46 PM PDT 24 |
Jul 05 07:27:54 PM PDT 24 |
2404941908 ps |
| T889 |
/workspace/coverage/default/1.chip_sw_clkmgr_off_peri.1461590862 |
|
|
Jul 05 07:18:49 PM PDT 24 |
Jul 05 07:48:34 PM PDT 24 |
10224192808 ps |
| T890 |
/workspace/coverage/default/42.chip_sw_alert_handler_lpg_sleep_mode_alerts.2022052616 |
|
|
Jul 05 07:45:46 PM PDT 24 |
Jul 05 07:52:36 PM PDT 24 |
4633686300 ps |
| T891 |
/workspace/coverage/default/1.rom_e2e_asm_init_dev.2517848141 |
|
|
Jul 05 07:26:37 PM PDT 24 |
Jul 05 08:21:49 PM PDT 24 |
15521356551 ps |
| T892 |
/workspace/coverage/default/2.chip_sw_sleep_pwm_pulses.3139748828 |
|
|
Jul 05 07:22:28 PM PDT 24 |
Jul 05 07:43:52 PM PDT 24 |
10075785104 ps |
| T193 |
/workspace/coverage/default/2.chip_plic_all_irqs_0.2940079409 |
|
|
Jul 05 07:30:31 PM PDT 24 |
Jul 05 07:49:09 PM PDT 24 |
6345661382 ps |
| T382 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_ops.3126497226 |
|
|
Jul 05 07:24:27 PM PDT 24 |
Jul 05 07:35:25 PM PDT 24 |
3531440056 ps |
| T416 |
/workspace/coverage/default/1.chip_sw_rv_core_ibex_lockstep_glitch.4003385274 |
|
|
Jul 05 07:21:47 PM PDT 24 |
Jul 05 07:24:24 PM PDT 24 |
2478027118 ps |
| T893 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en.2686856270 |
|
|
Jul 05 07:25:13 PM PDT 24 |
Jul 05 07:38:19 PM PDT 24 |
4164037965 ps |
| T894 |
/workspace/coverage/default/1.chip_sw_hmac_enc_jitter_en_reduced_freq.276909755 |
|
|
Jul 05 07:22:49 PM PDT 24 |
Jul 05 07:27:16 PM PDT 24 |
2845193735 ps |
| T364 |
/workspace/coverage/default/0.chip_sw_entropy_src_csrng.9131266 |
|
|
Jul 05 07:01:37 PM PDT 24 |
Jul 05 07:20:28 PM PDT 24 |
6343480482 ps |
| T895 |
/workspace/coverage/default/14.chip_sw_lc_ctrl_transition.2572185472 |
|
|
Jul 05 07:40:25 PM PDT 24 |
Jul 05 07:47:23 PM PDT 24 |
5122213191 ps |
| T896 |
/workspace/coverage/default/0.chip_sw_aon_timer_sleep_wdog_sleep_pause.3971500255 |
|
|
Jul 05 07:00:00 PM PDT 24 |
Jul 05 07:06:39 PM PDT 24 |
6266320698 ps |
| T897 |
/workspace/coverage/default/1.chip_sw_aes_entropy.3633365278 |
|
|
Jul 05 07:18:37 PM PDT 24 |
Jul 05 07:24:39 PM PDT 24 |
2845745764 ps |
| T898 |
/workspace/coverage/default/29.chip_sw_all_escalation_resets.1590738113 |
|
|
Jul 05 07:40:45 PM PDT 24 |
Jul 05 07:52:23 PM PDT 24 |
4856826528 ps |
| T381 |
/workspace/coverage/default/0.chip_sw_sensor_ctrl_status.3619425130 |
|
|
Jul 05 07:03:24 PM PDT 24 |
Jul 05 07:07:00 PM PDT 24 |
2296220138 ps |
| T536 |
/workspace/coverage/default/3.chip_sw_alert_handler_lpg_sleep_mode_alerts.3565828345 |
|
|
Jul 05 07:34:53 PM PDT 24 |
Jul 05 07:42:11 PM PDT 24 |
4330097552 ps |
| T491 |
/workspace/coverage/default/45.chip_sw_all_escalation_resets.3142971951 |
|
|
Jul 05 07:41:00 PM PDT 24 |
Jul 05 07:52:14 PM PDT 24 |
4527345480 ps |
| T899 |
/workspace/coverage/default/1.chip_sw_alert_handler_lpg_clkoff.2960699366 |
|
|
Jul 05 07:18:50 PM PDT 24 |
Jul 05 07:42:06 PM PDT 24 |
6344045082 ps |
| T900 |
/workspace/coverage/default/52.chip_sw_alert_handler_lpg_sleep_mode_alerts.1383598843 |
|
|
Jul 05 07:41:45 PM PDT 24 |
Jul 05 07:47:36 PM PDT 24 |
3546578372 ps |
| T901 |
/workspace/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en.2853052404 |
|
|
Jul 05 07:19:02 PM PDT 24 |
Jul 05 07:23:35 PM PDT 24 |
3259059321 ps |
| T379 |
/workspace/coverage/default/92.chip_sw_all_escalation_resets.1113658235 |
|
|
Jul 05 07:44:41 PM PDT 24 |
Jul 05 07:57:30 PM PDT 24 |
4886692922 ps |
| T502 |
/workspace/coverage/default/78.chip_sw_all_escalation_resets.3010081882 |
|
|
Jul 05 07:42:35 PM PDT 24 |
Jul 05 07:50:46 PM PDT 24 |
4328974130 ps |
| T902 |
/workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_reset_reqs.1140677180 |
|
|
Jul 05 07:25:59 PM PDT 24 |
Jul 05 08:03:35 PM PDT 24 |
26353909000 ps |
| T526 |
/workspace/coverage/default/29.chip_sw_alert_handler_lpg_sleep_mode_alerts.1692595208 |
|
|
Jul 05 07:40:13 PM PDT 24 |
Jul 05 07:46:33 PM PDT 24 |
3292281300 ps |
| T903 |
/workspace/coverage/default/2.chip_sw_clkmgr_off_hmac_trans.2538251631 |
|
|
Jul 05 07:32:30 PM PDT 24 |
Jul 05 07:41:48 PM PDT 24 |
3650546000 ps |
| T904 |
/workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access.1797331495 |
|
|
Jul 05 07:18:39 PM PDT 24 |
Jul 05 07:32:08 PM PDT 24 |
4030081196 ps |
| T464 |
/workspace/coverage/default/16.chip_sw_alert_handler_lpg_sleep_mode_alerts.8248435 |
|
|
Jul 05 07:38:43 PM PDT 24 |
Jul 05 07:45:32 PM PDT 24 |
3179505024 ps |
| T905 |
/workspace/coverage/default/1.chip_sw_sleep_pwm_pulses.69730541 |
|
|
Jul 05 07:12:08 PM PDT 24 |
Jul 05 07:39:51 PM PDT 24 |
10028139322 ps |
| T906 |
/workspace/coverage/default/1.chip_sw_aes_enc_jitter_en.3599847556 |
|
|
Jul 05 07:17:05 PM PDT 24 |
Jul 05 07:21:34 PM PDT 24 |
3455280326 ps |
| T907 |
/workspace/coverage/default/0.chip_sw_uart_tx_rx_idx1.3974379886 |
|
|
Jul 05 06:56:09 PM PDT 24 |
Jul 05 07:07:15 PM PDT 24 |
3893010664 ps |
| T369 |
/workspace/coverage/default/2.chip_sw_pwrmgr_lowpower_cancel.2528082090 |
|
|
Jul 05 07:34:03 PM PDT 24 |
Jul 05 07:43:46 PM PDT 24 |
4560554506 ps |
| T908 |
/workspace/coverage/default/2.chip_sw_flash_crash_alert.601874859 |
|
|
Jul 05 07:32:52 PM PDT 24 |
Jul 05 07:43:10 PM PDT 24 |
5648572240 ps |
| T909 |
/workspace/coverage/default/1.chip_sw_aes_idle.3486318675 |
|
|
Jul 05 07:16:55 PM PDT 24 |
Jul 05 07:21:44 PM PDT 24 |
3369467806 ps |
| T320 |
/workspace/coverage/default/0.chip_sw_keymgr_sideload_aes.1738123885 |
|
|
Jul 05 07:02:22 PM PDT 24 |
Jul 05 07:49:39 PM PDT 24 |
10548104040 ps |
| T910 |
/workspace/coverage/default/0.chip_sw_alert_handler_reverse_ping_in_deep_sleep.2927458015 |
|
|
Jul 05 07:01:23 PM PDT 24 |
Jul 05 10:43:36 PM PDT 24 |
255973555052 ps |
| T264 |
/workspace/coverage/default/1.chip_sw_rstmgr_cpu_info.1855905226 |
|
|
Jul 05 07:15:29 PM PDT 24 |
Jul 05 07:26:31 PM PDT 24 |
6127317574 ps |
| T911 |
/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_lc.4122211539 |
|
|
Jul 05 07:18:20 PM PDT 24 |
Jul 05 07:37:54 PM PDT 24 |
11369772917 ps |
| T912 |
/workspace/coverage/default/1.rom_e2e_shutdown_exception_c.3070668432 |
|
|
Jul 05 07:26:34 PM PDT 24 |
Jul 05 08:39:16 PM PDT 24 |
15224245639 ps |
| T913 |
/workspace/coverage/default/1.chip_sw_rstmgr_sw_rst.2548571299 |
|
|
Jul 05 07:15:13 PM PDT 24 |
Jul 05 07:18:18 PM PDT 24 |
2570841530 ps |
| T914 |
/workspace/coverage/default/0.chip_sw_aon_timer_smoketest.3064177113 |
|
|
Jul 05 07:09:59 PM PDT 24 |
Jul 05 07:14:34 PM PDT 24 |
3023707038 ps |
| T915 |
/workspace/coverage/default/2.chip_sw_sysrst_ctrl_ec_rst_l.533289511 |
|
|
Jul 05 07:28:26 PM PDT 24 |
Jul 05 08:15:34 PM PDT 24 |
21147694253 ps |
| T916 |
/workspace/coverage/default/1.chip_sw_edn_entropy_reqs.1971516130 |
|
|
Jul 05 07:18:33 PM PDT 24 |
Jul 05 07:37:44 PM PDT 24 |
6770666212 ps |
| T917 |
/workspace/coverage/default/28.chip_sw_alert_handler_lpg_sleep_mode_alerts.3114958775 |
|
|
Jul 05 07:40:32 PM PDT 24 |
Jul 05 07:47:48 PM PDT 24 |
4191744726 ps |
| T918 |
/workspace/coverage/default/1.chip_sw_otp_ctrl_smoketest.4064423681 |
|
|
Jul 05 07:22:10 PM PDT 24 |
Jul 05 07:27:24 PM PDT 24 |
2982072478 ps |
| T919 |
/workspace/coverage/default/0.chip_sw_clkmgr_off_otbn_trans.3732620809 |
|
|
Jul 05 07:02:50 PM PDT 24 |
Jul 05 07:11:35 PM PDT 24 |
4582811520 ps |
| T500 |
/workspace/coverage/default/21.chip_sw_all_escalation_resets.3335667906 |
|
|
Jul 05 07:40:53 PM PDT 24 |
Jul 05 07:54:17 PM PDT 24 |
4692894640 ps |
| T920 |
/workspace/coverage/default/1.rom_volatile_raw_unlock.924810159 |
|
|
Jul 05 07:23:06 PM PDT 24 |
Jul 05 07:25:12 PM PDT 24 |
2457953589 ps |
| T484 |
/workspace/coverage/default/50.chip_sw_all_escalation_resets.1718127100 |
|
|
Jul 05 07:42:51 PM PDT 24 |
Jul 05 07:51:30 PM PDT 24 |
4838517880 ps |
| T921 |
/workspace/coverage/default/0.chip_sw_clkmgr_off_hmac_trans.824719735 |
|
|
Jul 05 07:02:16 PM PDT 24 |
Jul 05 07:08:31 PM PDT 24 |
4590977538 ps |
| T343 |
/workspace/coverage/default/0.chip_sw_rstmgr_alert_info.2960273796 |
|
|
Jul 05 07:00:22 PM PDT 24 |
Jul 05 07:35:30 PM PDT 24 |
14763559052 ps |
| T922 |
/workspace/coverage/default/0.chip_sw_inject_scramble_seed.313047650 |
|
|
Jul 05 06:56:14 PM PDT 24 |
Jul 05 10:23:26 PM PDT 24 |
63544730483 ps |
| T465 |
/workspace/coverage/default/5.chip_sw_alert_handler_lpg_sleep_mode_alerts.2743617592 |
|
|
Jul 05 07:37:57 PM PDT 24 |
Jul 05 07:43:43 PM PDT 24 |
3142582094 ps |
| T923 |
/workspace/coverage/default/0.chip_sw_otp_ctrl_smoketest.1306618804 |
|
|
Jul 05 07:10:34 PM PDT 24 |
Jul 05 07:16:24 PM PDT 24 |
3375303000 ps |
| T924 |
/workspace/coverage/default/1.chip_sw_pwrmgr_sysrst_ctrl_reset.554115225 |
|
|
Jul 05 07:14:54 PM PDT 24 |
Jul 05 07:36:50 PM PDT 24 |
7268229706 ps |
| T925 |
/workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.2009746405 |
|
|
Jul 05 06:58:24 PM PDT 24 |
Jul 05 07:18:06 PM PDT 24 |
12059380867 ps |
| T926 |
/workspace/coverage/default/70.chip_sw_alert_handler_lpg_sleep_mode_alerts.790220495 |
|
|
Jul 05 07:42:31 PM PDT 24 |
Jul 05 07:48:04 PM PDT 24 |
3587879756 ps |
| T927 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_prod_end.2573319666 |
|
|
Jul 05 07:10:28 PM PDT 24 |
Jul 05 08:28:51 PM PDT 24 |
15599319892 ps |
| T928 |
/workspace/coverage/default/2.chip_sw_sysrst_ctrl_inputs.3031771019 |
|
|
Jul 05 07:26:21 PM PDT 24 |
Jul 05 07:30:37 PM PDT 24 |
2569313903 ps |
| T460 |
/workspace/coverage/default/9.chip_sw_alert_handler_lpg_sleep_mode_alerts.3451542513 |
|
|
Jul 05 07:38:35 PM PDT 24 |
Jul 05 07:47:37 PM PDT 24 |
3675516536 ps |
| T929 |
/workspace/coverage/default/2.chip_sw_kmac_mode_cshake.3833926247 |
|
|
Jul 05 07:29:34 PM PDT 24 |
Jul 05 07:33:56 PM PDT 24 |
3397260264 ps |
| T108 |
/workspace/coverage/default/2.chip_sw_spi_device_pass_through_collision.716601151 |
|
|
Jul 05 07:22:55 PM PDT 24 |
Jul 05 07:30:53 PM PDT 24 |
4634893634 ps |
| T930 |
/workspace/coverage/default/2.chip_tap_straps_testunlock0.3387372252 |
|
|
Jul 05 07:30:51 PM PDT 24 |
Jul 05 07:39:00 PM PDT 24 |
5715026995 ps |
| T456 |
/workspace/coverage/default/30.chip_sw_all_escalation_resets.1154776199 |
|
|
Jul 05 07:39:43 PM PDT 24 |
Jul 05 07:52:11 PM PDT 24 |
4898106110 ps |
| T931 |
/workspace/coverage/default/2.chip_sw_alert_handler_ping_ok.3939880503 |
|
|
Jul 05 07:28:59 PM PDT 24 |
Jul 05 07:55:38 PM PDT 24 |
8076998420 ps |
| T52 |
/workspace/coverage/default/0.chip_sw_sysrst_ctrl_ulp_z3_wakeup.836737087 |
|
|
Jul 05 06:59:37 PM PDT 24 |
Jul 05 07:06:22 PM PDT 24 |
5350671314 ps |
| T344 |
/workspace/coverage/default/1.chip_sw_rstmgr_alert_info.1359181936 |
|
|
Jul 05 07:14:21 PM PDT 24 |
Jul 05 07:41:38 PM PDT 24 |
12051727272 ps |
| T49 |
/workspace/coverage/default/1.chip_sw_spi_host_tx_rx.3599520967 |
|
|
Jul 05 07:14:05 PM PDT 24 |
Jul 05 07:18:33 PM PDT 24 |
2756958048 ps |
| T932 |
/workspace/coverage/default/9.chip_sw_lc_ctrl_transition.3045111932 |
|
|
Jul 05 07:37:39 PM PDT 24 |
Jul 05 07:49:19 PM PDT 24 |
5818370154 ps |
| T933 |
/workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_no_meas.3636678847 |
|
|
Jul 05 07:27:33 PM PDT 24 |
Jul 05 08:33:59 PM PDT 24 |
14542230424 ps |
| T934 |
/workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.3158194385 |
|
|
Jul 05 07:15:56 PM PDT 24 |
Jul 05 07:44:48 PM PDT 24 |
13984454132 ps |
| T935 |
/workspace/coverage/default/2.rom_e2e_smoke.494717796 |
|
|
Jul 05 07:36:42 PM PDT 24 |
Jul 05 08:37:56 PM PDT 24 |
14471949780 ps |
| T224 |
/workspace/coverage/default/1.chip_jtag_mem_access.1426574598 |
|
|
Jul 05 07:12:29 PM PDT 24 |
Jul 05 07:41:32 PM PDT 24 |
13659053616 ps |
| T936 |
/workspace/coverage/default/1.chip_sw_uart_rand_baudrate.3616381190 |
|
|
Jul 05 07:12:59 PM PDT 24 |
Jul 05 07:20:36 PM PDT 24 |
3719120702 ps |
| T937 |
/workspace/coverage/default/4.chip_tap_straps_dev.3392806541 |
|
|
Jul 05 07:35:42 PM PDT 24 |
Jul 05 07:38:16 PM PDT 24 |
3073096424 ps |
| T265 |
/workspace/coverage/default/2.chip_sw_rstmgr_cpu_info.2792987870 |
|
|
Jul 05 07:25:36 PM PDT 24 |
Jul 05 07:41:46 PM PDT 24 |
5505179560 ps |
| T201 |
/workspace/coverage/default/1.chip_sw_i2c_host_tx_rx_idx2.2823218999 |
|
|
Jul 05 07:13:18 PM PDT 24 |
Jul 05 07:27:30 PM PDT 24 |
4817503576 ps |
| T938 |
/workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.261211857 |
|
|
Jul 05 07:12:57 PM PDT 24 |
Jul 05 07:47:32 PM PDT 24 |
13137083303 ps |
| T939 |
/workspace/coverage/default/0.chip_sw_flash_scrambling_smoketest.3144196985 |
|
|
Jul 05 07:09:10 PM PDT 24 |
Jul 05 07:13:48 PM PDT 24 |
2750210062 ps |
| T940 |
/workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq.1723045112 |
|
|
Jul 05 07:28:01 PM PDT 24 |
Jul 05 08:26:53 PM PDT 24 |
17396266986 ps |
| T941 |
/workspace/coverage/default/7.chip_sw_lc_ctrl_transition.2036879481 |
|
|
Jul 05 07:37:09 PM PDT 24 |
Jul 05 07:46:32 PM PDT 24 |
5627303149 ps |
| T942 |
/workspace/coverage/default/2.rom_e2e_asm_init_dev.1391009184 |
|
|
Jul 05 07:38:51 PM PDT 24 |
Jul 05 08:33:09 PM PDT 24 |
16134489970 ps |
| T181 |
/workspace/coverage/default/1.chip_sw_flash_rma_unlocked.2064319185 |
|
|
Jul 05 07:13:04 PM PDT 24 |
Jul 05 08:36:37 PM PDT 24 |
43650005000 ps |
| T943 |
/workspace/coverage/default/0.chip_sw_aon_timer_wdog_bite_reset.2486633640 |
|
|
Jul 05 06:59:35 PM PDT 24 |
Jul 05 07:13:26 PM PDT 24 |
10674590600 ps |
| T944 |
/workspace/coverage/default/0.chip_sw_edn_entropy_reqs_jitter.1504455256 |
|
|
Jul 05 07:01:20 PM PDT 24 |
Jul 05 07:23:51 PM PDT 24 |
8359976724 ps |
| T945 |
/workspace/coverage/default/0.chip_sw_hmac_enc_idle.287239382 |
|
|
Jul 05 07:02:31 PM PDT 24 |
Jul 05 07:06:40 PM PDT 24 |
3516215820 ps |
| T12 |
/workspace/coverage/default/2.chip_sw_sleep_pin_wake.2011290648 |
|
|
Jul 05 07:25:38 PM PDT 24 |
Jul 05 07:29:55 PM PDT 24 |
3568665172 ps |
| T199 |
/workspace/coverage/default/1.chip_sw_i2c_host_tx_rx_idx1.786007673 |
|
|
Jul 05 07:13:22 PM PDT 24 |
Jul 05 07:28:32 PM PDT 24 |
5508041328 ps |
| T370 |
/workspace/coverage/default/1.chip_sw_pwrmgr_lowpower_cancel.3929796247 |
|
|
Jul 05 07:19:23 PM PDT 24 |
Jul 05 07:28:01 PM PDT 24 |
4113610388 ps |
| T946 |
/workspace/coverage/default/0.chip_sw_aes_entropy.563227003 |
|
|
Jul 05 07:00:27 PM PDT 24 |
Jul 05 07:04:56 PM PDT 24 |
2735968142 ps |
| T11 |
/workspace/coverage/default/1.chip_rv_dm_ndm_reset_req.1569215980 |
|
|
Jul 05 07:18:28 PM PDT 24 |
Jul 05 07:26:03 PM PDT 24 |
4964834380 ps |
| T487 |
/workspace/coverage/default/88.chip_sw_alert_handler_lpg_sleep_mode_alerts.1718890313 |
|
|
Jul 05 07:46:27 PM PDT 24 |
Jul 05 07:55:40 PM PDT 24 |
4468661628 ps |
| T947 |
/workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.2072917098 |
|
|
Jul 05 07:23:28 PM PDT 24 |
Jul 05 07:41:47 PM PDT 24 |
8874687464 ps |
| T550 |
/workspace/coverage/default/52.chip_sw_all_escalation_resets.452889457 |
|
|
Jul 05 07:41:33 PM PDT 24 |
Jul 05 07:51:05 PM PDT 24 |
4924543136 ps |
| T515 |
/workspace/coverage/default/18.chip_sw_all_escalation_resets.1122215378 |
|
|
Jul 05 07:37:59 PM PDT 24 |
Jul 05 07:51:03 PM PDT 24 |
5066093710 ps |
| T948 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0.4153889567 |
|
|
Jul 05 07:13:26 PM PDT 24 |
Jul 05 08:11:04 PM PDT 24 |
11213399555 ps |
| T949 |
/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.2858779078 |
|
|
Jul 05 07:21:04 PM PDT 24 |
Jul 05 07:33:17 PM PDT 24 |
4113282988 ps |
| T950 |
/workspace/coverage/default/2.chip_sw_uart_tx_rx.1611622046 |
|
|
Jul 05 07:22:38 PM PDT 24 |
Jul 05 07:32:35 PM PDT 24 |
4066833184 ps |
| T399 |
/workspace/coverage/default/1.chip_sw_rv_core_ibex_nmi_irq.3542990736 |
|
|
Jul 05 07:18:04 PM PDT 24 |
Jul 05 07:32:31 PM PDT 24 |
4600144824 ps |
| T951 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_access.2214431210 |
|
|
Jul 05 07:24:47 PM PDT 24 |
Jul 05 07:45:44 PM PDT 24 |
5755047680 ps |
| T197 |
/workspace/coverage/default/1.chip_sw_i2c_host_tx_rx.1852281375 |
|
|
Jul 05 07:12:49 PM PDT 24 |
Jul 05 07:26:50 PM PDT 24 |
4534995000 ps |
| T952 |
/workspace/coverage/default/1.chip_sw_clkmgr_off_hmac_trans.2512721368 |
|
|
Jul 05 07:18:47 PM PDT 24 |
Jul 05 07:30:33 PM PDT 24 |
4753545400 ps |
| T953 |
/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.1999881111 |
|
|
Jul 05 07:20:24 PM PDT 24 |
Jul 05 07:30:23 PM PDT 24 |
3718617250 ps |
| T522 |
/workspace/coverage/default/68.chip_sw_all_escalation_resets.2818389720 |
|
|
Jul 05 07:41:41 PM PDT 24 |
Jul 05 07:51:44 PM PDT 24 |
5484301012 ps |
| T954 |
/workspace/coverage/default/2.chip_sw_data_integrity_escalation.4112606218 |
|
|
Jul 05 07:22:14 PM PDT 24 |
Jul 05 07:30:40 PM PDT 24 |
5722330964 ps |
| T955 |
/workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en.3372738149 |
|
|
Jul 05 06:59:37 PM PDT 24 |
Jul 05 08:05:37 PM PDT 24 |
18920438622 ps |
| T956 |
/workspace/coverage/default/2.chip_sw_uart_tx_rx_bootstrap.3581465222 |
|
|
Jul 05 07:23:14 PM PDT 24 |
Jul 05 11:08:41 PM PDT 24 |
78770639959 ps |
| T957 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_mem_protection.842534177 |
|
|
Jul 05 07:33:42 PM PDT 24 |
Jul 05 07:51:04 PM PDT 24 |
5696036552 ps |
| T958 |
/workspace/coverage/default/0.chip_sw_keymgr_key_derivation_prod.3774878500 |
|
|
Jul 05 07:02:23 PM PDT 24 |
Jul 05 07:35:36 PM PDT 24 |
10004155064 ps |
| T959 |
/workspace/coverage/default/0.chip_sw_rv_timer_irq.2545630217 |
|
|
Jul 05 06:59:48 PM PDT 24 |
Jul 05 07:03:43 PM PDT 24 |
3071657098 ps |
| T960 |
/workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_prod.1722803107 |
|
|
Jul 05 07:13:38 PM PDT 24 |
Jul 05 07:35:15 PM PDT 24 |
8432213100 ps |
| T523 |
/workspace/coverage/default/74.chip_sw_all_escalation_resets.3642696724 |
|
|
Jul 05 07:42:18 PM PDT 24 |
Jul 05 07:53:47 PM PDT 24 |
5290738952 ps |
| T961 |
/workspace/coverage/default/2.chip_sw_rstmgr_sw_req.1734333462 |
|
|
Jul 05 07:25:24 PM PDT 24 |
Jul 05 07:33:44 PM PDT 24 |
5333984686 ps |
| T962 |
/workspace/coverage/default/4.chip_sw_csrng_edn_concurrency.3942143523 |
|
|
Jul 05 07:37:00 PM PDT 24 |
Jul 05 08:27:40 PM PDT 24 |
15416312980 ps |
| T963 |
/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.3936132637 |
|
|
Jul 05 07:30:46 PM PDT 24 |
Jul 05 07:40:51 PM PDT 24 |
3720127314 ps |
| T964 |
/workspace/coverage/default/0.chip_sw_hmac_enc_jitter_en.398349467 |
|
|
Jul 05 07:01:00 PM PDT 24 |
Jul 05 07:06:23 PM PDT 24 |
3357759469 ps |
| T16 |
/workspace/coverage/default/1.chip_sw_sleep_pin_retention.2540038751 |
|
|
Jul 05 07:18:36 PM PDT 24 |
Jul 05 07:22:41 PM PDT 24 |
2875432280 ps |
| T965 |
/workspace/coverage/default/8.chip_sw_lc_ctrl_transition.1436007982 |
|
|
Jul 05 07:38:46 PM PDT 24 |
Jul 05 07:48:41 PM PDT 24 |
7825076231 ps |
| T966 |
/workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_dev.3565859949 |
|
|
Jul 05 06:59:13 PM PDT 24 |
Jul 05 07:18:20 PM PDT 24 |
8147866668 ps |
| T967 |
/workspace/coverage/default/0.chip_sw_csrng_smoketest.1976630460 |
|
|
Jul 05 07:09:20 PM PDT 24 |
Jul 05 07:12:27 PM PDT 24 |
2109498332 ps |
| T182 |
/workspace/coverage/default/0.chip_sw_flash_rma_unlocked.2107529427 |
|
|
Jul 05 06:56:58 PM PDT 24 |
Jul 05 08:28:32 PM PDT 24 |
43812587961 ps |
| T505 |
/workspace/coverage/default/61.chip_sw_alert_handler_lpg_sleep_mode_alerts.991324451 |
|
|
Jul 05 07:43:22 PM PDT 24 |
Jul 05 07:49:17 PM PDT 24 |
3565817072 ps |
| T968 |
/workspace/coverage/default/1.chip_sw_lc_walkthrough_dev.927592311 |
|
|
Jul 05 07:14:59 PM PDT 24 |
Jul 05 08:51:43 PM PDT 24 |
48315214652 ps |
| T969 |
/workspace/coverage/default/1.chip_sw_uart_tx_rx_idx3.1957148407 |
|
|
Jul 05 07:12:22 PM PDT 24 |
Jul 05 07:26:08 PM PDT 24 |
4423938930 ps |
| T970 |
/workspace/coverage/default/0.chip_sw_pwrmgr_main_power_glitch_reset.739353219 |
|
|
Jul 05 06:58:55 PM PDT 24 |
Jul 05 07:03:47 PM PDT 24 |
3670949254 ps |
| T126 |
/workspace/coverage/default/8.chip_sw_alert_handler_lpg_sleep_mode_alerts.1890721779 |
|
|
Jul 05 07:36:29 PM PDT 24 |
Jul 05 07:43:41 PM PDT 24 |
3995743092 ps |
| T971 |
/workspace/coverage/default/1.chip_sw_clkmgr_jitter.3384948255 |
|
|
Jul 05 07:18:08 PM PDT 24 |
Jul 05 07:21:57 PM PDT 24 |
2771208608 ps |
| T972 |
/workspace/coverage/default/69.chip_sw_alert_handler_lpg_sleep_mode_alerts.217766345 |
|
|
Jul 05 07:43:54 PM PDT 24 |
Jul 05 07:51:04 PM PDT 24 |
3701383280 ps |
| T973 |
/workspace/coverage/default/58.chip_sw_all_escalation_resets.4228434931 |
|
|
Jul 05 07:43:05 PM PDT 24 |
Jul 05 07:54:43 PM PDT 24 |
5244298584 ps |
| T974 |
/workspace/coverage/default/66.chip_sw_all_escalation_resets.642192111 |
|
|
Jul 05 07:42:10 PM PDT 24 |
Jul 05 07:54:31 PM PDT 24 |
5506280664 ps |
| T340 |
/workspace/coverage/default/83.chip_sw_all_escalation_resets.256564075 |
|
|
Jul 05 07:43:03 PM PDT 24 |
Jul 05 07:53:39 PM PDT 24 |
6089732732 ps |
| T975 |
/workspace/coverage/default/2.chip_sw_clkmgr_off_kmac_trans.3334456660 |
|
|
Jul 05 07:30:05 PM PDT 24 |
Jul 05 07:38:50 PM PDT 24 |
4335648804 ps |
| T976 |
/workspace/coverage/default/1.chip_sw_example_manufacturer.3915936453 |
|
|
Jul 05 07:21:11 PM PDT 24 |
Jul 05 07:25:35 PM PDT 24 |
2764162536 ps |
| T977 |
/workspace/coverage/default/2.chip_sw_example_flash.3838595589 |
|
|
Jul 05 07:23:41 PM PDT 24 |
Jul 05 07:26:25 PM PDT 24 |
2567094936 ps |
| T978 |
/workspace/coverage/default/0.rom_e2e_shutdown_output.1382062139 |
|
|
Jul 05 07:10:53 PM PDT 24 |
Jul 05 08:11:35 PM PDT 24 |
25731050676 ps |
| T979 |
/workspace/coverage/default/0.chip_sw_clkmgr_sleep_frequency.1279714162 |
|
|
Jul 05 07:03:25 PM PDT 24 |
Jul 05 07:14:12 PM PDT 24 |
4871447736 ps |
| T980 |
/workspace/coverage/default/2.chip_sw_hmac_enc.4227028992 |
|
|
Jul 05 07:29:20 PM PDT 24 |
Jul 05 07:34:37 PM PDT 24 |
2967053504 ps |
| T511 |
/workspace/coverage/default/71.chip_sw_all_escalation_resets.2876613220 |
|
|
Jul 05 07:42:40 PM PDT 24 |
Jul 05 07:52:18 PM PDT 24 |
5374691544 ps |
| T981 |
/workspace/coverage/default/2.chip_sw_alert_handler_ping_timeout.1841325698 |
|
|
Jul 05 07:27:55 PM PDT 24 |
Jul 05 07:35:06 PM PDT 24 |
3704491934 ps |
| T982 |
/workspace/coverage/default/0.chip_sw_rv_timer_smoketest.351397228 |
|
|
Jul 05 07:10:30 PM PDT 24 |
Jul 05 07:14:16 PM PDT 24 |
2688261240 ps |
| T983 |
/workspace/coverage/default/0.rom_e2e_asm_init_prod.2230602620 |
|
|
Jul 05 07:12:06 PM PDT 24 |
Jul 05 08:17:45 PM PDT 24 |
15935464699 ps |
| T984 |
/workspace/coverage/default/1.chip_sw_flash_init.281710477 |
|
|
Jul 05 07:12:06 PM PDT 24 |
Jul 05 07:47:28 PM PDT 24 |
17376608700 ps |
| T985 |
/workspace/coverage/default/98.chip_sw_all_escalation_resets.1518322016 |
|
|
Jul 05 07:45:28 PM PDT 24 |
Jul 05 07:53:53 PM PDT 24 |
5501795372 ps |
| T986 |
/workspace/coverage/default/73.chip_sw_alert_handler_lpg_sleep_mode_alerts.77265704 |
|
|
Jul 05 07:42:18 PM PDT 24 |
Jul 05 07:48:28 PM PDT 24 |
3102649480 ps |
| T987 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_clock_freqs.1008487569 |
|
|
Jul 05 07:24:43 PM PDT 24 |
Jul 05 07:45:27 PM PDT 24 |
5963347010 ps |
| T103 |
/workspace/coverage/default/0.chip_jtag_csr_rw.3884699716 |
|
|
Jul 05 06:56:29 PM PDT 24 |
Jul 05 07:38:23 PM PDT 24 |
20648556618 ps |
| T55 |
/workspace/coverage/default/2.chip_sw_spi_device_tpm.24548047 |
|
|
Jul 05 07:23:05 PM PDT 24 |
Jul 05 07:30:21 PM PDT 24 |
4165193483 ps |
| T988 |
/workspace/coverage/default/1.chip_sw_otbn_randomness.3000561180 |
|
|
Jul 05 07:16:48 PM PDT 24 |
Jul 05 07:31:34 PM PDT 24 |
5904308648 ps |
| T989 |
/workspace/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.3541076071 |
|
|
Jul 05 07:13:56 PM PDT 24 |
Jul 05 07:16:26 PM PDT 24 |
2362393151 ps |
| T990 |
/workspace/coverage/default/2.rom_e2e_asm_init_prod.3651207533 |
|
|
Jul 05 07:37:27 PM PDT 24 |
Jul 05 08:34:54 PM PDT 24 |
15622117036 ps |
| T322 |
/workspace/coverage/default/1.chip_sw_keymgr_sideload_otbn.1800976534 |
|
|
Jul 05 07:17:10 PM PDT 24 |
Jul 05 08:18:09 PM PDT 24 |
11297539416 ps |
| T365 |
/workspace/coverage/default/1.chip_sw_entropy_src_csrng.1751633840 |
|
|
Jul 05 07:18:46 PM PDT 24 |
Jul 05 07:43:52 PM PDT 24 |
6623161372 ps |
| T991 |
/workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_por_reset.2513692492 |
|
|
Jul 05 07:26:15 PM PDT 24 |
Jul 05 07:39:41 PM PDT 24 |
6974513720 ps |
| T992 |
/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_power_glitch_reset.1978250521 |
|
|
Jul 05 06:59:10 PM PDT 24 |
Jul 05 07:06:11 PM PDT 24 |
5618778174 ps |
| T993 |
/workspace/coverage/default/0.chip_sw_lc_ctrl_transition.224489575 |
|
|
Jul 05 06:58:34 PM PDT 24 |
Jul 05 07:04:48 PM PDT 24 |
4666273035 ps |
| T994 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.2424243822 |
|
|
Jul 05 07:11:52 PM PDT 24 |
Jul 05 08:24:37 PM PDT 24 |
15165758464 ps |
| T995 |
/workspace/coverage/default/1.chip_sw_pwrmgr_usbdev_smoketest.1364789321 |
|
|
Jul 05 07:22:23 PM PDT 24 |
Jul 05 07:31:33 PM PDT 24 |
5576026752 ps |
| T428 |
/workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_wake_ups.783083995 |
|
|
Jul 05 07:03:12 PM PDT 24 |
Jul 05 07:10:28 PM PDT 24 |
6886800250 ps |
| T401 |
/workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en.1140882929 |
|
|
Jul 05 07:17:34 PM PDT 24 |
Jul 05 07:27:43 PM PDT 24 |
4158025845 ps |
| T996 |
/workspace/coverage/default/0.chip_sw_data_integrity_escalation.944191236 |
|
|
Jul 05 06:55:57 PM PDT 24 |
Jul 05 07:11:17 PM PDT 24 |
6385261932 ps |
| T997 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.1367031245 |
|
|
Jul 05 07:12:36 PM PDT 24 |
Jul 05 08:43:19 PM PDT 24 |
18935576088 ps |
| T998 |
/workspace/coverage/default/2.chip_sw_exit_test_unlocked_bootstrap.1552084428 |
|
|
Jul 05 07:22:50 PM PDT 24 |
Jul 05 10:08:15 PM PDT 24 |
58442234412 ps |
| T999 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_idle_low_power.902183154 |
|
|
Jul 05 07:14:11 PM PDT 24 |
Jul 05 07:20:25 PM PDT 24 |
3456599628 ps |
| T1000 |
/workspace/coverage/default/2.chip_sw_clkmgr_smoketest.676667543 |
|
|
Jul 05 07:34:56 PM PDT 24 |
Jul 05 07:38:32 PM PDT 24 |
2675611810 ps |
| T1001 |
/workspace/coverage/default/1.chip_sw_pwrmgr_main_power_glitch_reset.3625992396 |
|
|
Jul 05 07:15:49 PM PDT 24 |
Jul 05 07:20:31 PM PDT 24 |
3823853840 ps |
| T373 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.726222296 |
|
|
Jul 05 07:21:26 PM PDT 24 |
Jul 05 07:33:18 PM PDT 24 |
5228358784 ps |
| T1002 |
/workspace/coverage/default/0.chip_sw_pwrmgr_b2b_sleep_reset_req.2052709418 |
|
|
Jul 05 07:01:46 PM PDT 24 |
Jul 05 07:44:31 PM PDT 24 |
28701988432 ps |
| T121 |
/workspace/coverage/default/1.chip_jtag_csr_rw.1033013839 |
|
|
Jul 05 07:11:54 PM PDT 24 |
Jul 05 07:27:51 PM PDT 24 |
9599131475 ps |
| T194 |
/workspace/coverage/default/1.chip_plic_all_irqs_0.1075464342 |
|
|
Jul 05 07:20:06 PM PDT 24 |
Jul 05 07:41:46 PM PDT 24 |
6064430440 ps |
| T1003 |
/workspace/coverage/default/2.chip_sw_sensor_ctrl_status.2838591415 |
|
|
Jul 05 07:31:13 PM PDT 24 |
Jul 05 07:36:04 PM PDT 24 |
2690966150 ps |
| T1004 |
/workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_prod.841360388 |
|
|
Jul 05 07:24:54 PM PDT 24 |
Jul 05 07:47:58 PM PDT 24 |
8611200578 ps |
| T1005 |
/workspace/coverage/default/2.rom_e2e_static_critical.4166678100 |
|
|
Jul 05 07:39:01 PM PDT 24 |
Jul 05 08:46:05 PM PDT 24 |
17581401816 ps |
| T1006 |
/workspace/coverage/default/0.chip_sw_aes_enc.3404617084 |
|
|
Jul 05 06:59:23 PM PDT 24 |
Jul 05 07:03:55 PM PDT 24 |
3132307522 ps |
| T1007 |
/workspace/coverage/default/2.chip_sival_flash_info_access.3284789778 |
|
|
Jul 05 07:22:48 PM PDT 24 |
Jul 05 07:28:22 PM PDT 24 |
3178078462 ps |
| T535 |
/workspace/coverage/default/1.chip_sw_all_escalation_resets.2045699845 |
|
|
Jul 05 07:11:42 PM PDT 24 |
Jul 05 07:27:00 PM PDT 24 |
6071721064 ps |
| T1008 |
/workspace/coverage/default/2.chip_sw_clkmgr_jitter_frequency.2710973720 |
|
|
Jul 05 07:31:09 PM PDT 24 |
Jul 05 07:42:08 PM PDT 24 |
4174234796 ps |
| T1009 |
/workspace/coverage/default/0.chip_sw_lc_ctrl_rand_to_scrap.4294605408 |
|
|
Jul 05 06:57:36 PM PDT 24 |
Jul 05 07:00:05 PM PDT 24 |
3439858130 ps |
| T1010 |
/workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_invalid_meas.2085899415 |
|
|
Jul 05 07:40:28 PM PDT 24 |
Jul 05 08:31:12 PM PDT 24 |
14856408592 ps |
| T533 |
/workspace/coverage/default/46.chip_sw_all_escalation_resets.1841523450 |
|
|
Jul 05 07:40:15 PM PDT 24 |
Jul 05 07:48:51 PM PDT 24 |
4647387020 ps |