Unified Coverage Report :: Module :: prim_mubi4_sync

Module : prim_mubi4_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_por_scanmode_sync	100.00						100.00

---

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_por_scanmode_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.83	99.34	100.00			100.00	100.00	u_pinmux_strap_sampling

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : prim_mubi4_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	1013	1013	0	0
OutputsKnown_A	130996603	130297006	0	0
gen_no_flops.OutputDelay_A	130996603	130297006	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1013	1013	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T45	1	1	0	0
T55	1	1	0	0
T63	1	1	0	0
T66	1	1	0	0
T85	1	1	0	0
T86	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	130996603	130297006	0	0
T4	20538	20092	0	0
T5	59690	59236	0	0
T6	113625	112878	0	0
T17	73043	72466	0	0
T45	61743	61024	0	0
T55	359407	359078	0	0
T63	37634	37108	0	0
T66	66931	66019	0	0
T85	24644	24090	0	0
T86	91610	91205	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	130996603	130297006	0	0
T4	20538	20092	0	0
T5	59690	59236	0	0
T6	113625	112878	0	0
T17	73043	72466	0	0
T45	61743	61024	0	0
T55	359407	359078	0	0
T63	37634	37108	0	0
T66	66931	66019	0	0
T85	24644	24090	0	0
T86	91610	91205	0	0

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_por_scanmode_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	1013	1013	0	0
OutputsKnown_A	130996603	130297006	0	0
gen_no_flops.OutputDelay_A	130996603	130297006	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1013	1013	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T45	1	1	0	0
T55	1	1	0	0
T63	1	1	0	0
T66	1	1	0	0
T85	1	1	0	0
T86	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	130996603	130297006	0	0
T4	20538	20092	0	0
T5	59690	59236	0	0
T6	113625	112878	0	0
T17	73043	72466	0	0
T45	61743	61024	0	0
T55	359407	359078	0	0
T63	37634	37108	0	0
T66	66931	66019	0	0
T85	24644	24090	0	0
T86	91610	91205	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	130996603	130297006	0	0
T4	20538	20092	0	0
T5	59690	59236	0	0
T6	113625	112878	0	0
T17	73043	72466	0	0
T45	61743	61024	0	0
T55	359407	359078	0	0
T63	37634	37108	0	0
T66	66931	66019	0	0
T85	24644	24090	0	0
T86	91610	91205	0	0