Module Definition
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Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.gen_alert_senders[0].u_alert_sender

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
75.00 75.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
75.00 75.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
90.50 95.29 89.29 99.75 100.00 68.18 u_rv_core_ibex


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.gen_alert_senders[3].u_alert_sender

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
75.00 75.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
75.00 75.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
90.50 95.29 89.29 99.75 100.00 68.18 u_rv_core_ibex


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_alert_tx[0].u_prim_alert_sender

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
91.67 91.67


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
91.67 91.67


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
91.97 99.03 86.84 98.84 83.16 92.00 u_pinmux_aon


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.top_earlgrey.u_rv_plic.gen_alert_tx[0].u_prim_alert_sender

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.97 99.83 100.00 100.00 100.00 90.00 u_rv_plic


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.gen_alert_senders[1].u_alert_sender

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
90.50 95.29 89.29 99.75 100.00 68.18 u_rv_core_ibex


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.gen_alert_senders[2].u_alert_sender

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
90.50 95.29 89.29 99.75 100.00 68.18 u_rv_core_ibex


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Toggle Coverage for Module : prim_alert_sender
TotalCoveredPercent
Totals 12 12 100.00
Total Bits 24 24 100.00
Total Bits 0->1 12 12 100.00
Total Bits 1->0 12 12 100.00

Ports 12 12 100.00
Port Bits 24 24 100.00
Port Bits 0->1 12 12 100.00
Port Bits 1->0 12 12 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
rst_ni Yes Yes T4,T5,T44 Yes T4,T5,T6 INPUT
alert_test_i Yes Yes T73,T61,T62 Yes T73,T61,T62 INPUT
alert_req_i Yes Yes T259,T274,T255 Yes T259,T274,T255 INPUT
alert_ack_o Yes Yes T259,T255,T125 Yes T259,T255,T125 OUTPUT
alert_state_o Yes Yes T259,T255,T125 Yes T259,T274,T255 OUTPUT
alert_rx_i.ack_n Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
alert_rx_i.ack_p Yes Yes T73,T259,T255 Yes T73,T259,T255 INPUT
alert_rx_i.ping_n Yes Yes T226,T88,T89 Yes T226,T88,T89 INPUT
alert_rx_i.ping_p Yes Yes T226,T88,T89 Yes T226,T88,T89 INPUT
alert_tx_o.alert_n Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
alert_tx_o.alert_p Yes Yes T73,T259,T255 Yes T73,T259,T274 OUTPUT

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.gen_alert_senders[0].u_alert_sender
TotalCoveredPercent
Totals 12 9 75.00
Total Bits 24 18 75.00
Total Bits 0->1 12 9 75.00
Total Bits 1->0 12 9 75.00

Ports 12 9 75.00
Port Bits 24 18 75.00
Port Bits 0->1 12 9 75.00
Port Bits 1->0 12 9 75.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
rst_ni Yes Yes T4,T5,T44 Yes T4,T5,T6 INPUT
alert_test_i Yes Yes T61,T62,T8 Yes T61,T62,T8 INPUT
alert_req_i No No No INPUT
alert_ack_o No No No OUTPUT
alert_state_o No No No OUTPUT
alert_rx_i.ack_n Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
alert_rx_i.ack_p Yes Yes T61,T62,T8 Yes T61,T62,T8 INPUT
alert_rx_i.ping_n Yes Yes T226,T88,T89 Yes T226,T88,T89 INPUT
alert_rx_i.ping_p Yes Yes T226,T88,T89 Yes T226,T88,T89 INPUT
alert_tx_o.alert_n Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
alert_tx_o.alert_p Yes Yes T61,T62,T8 Yes T61,T62,T8 OUTPUT

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.gen_alert_senders[3].u_alert_sender
TotalCoveredPercent
Totals 12 9 75.00
Total Bits 24 18 75.00
Total Bits 0->1 12 9 75.00
Total Bits 1->0 12 9 75.00

Ports 12 9 75.00
Port Bits 24 18 75.00
Port Bits 0->1 12 9 75.00
Port Bits 1->0 12 9 75.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
rst_ni Yes Yes T4,T5,T44 Yes T4,T5,T6 INPUT
alert_test_i Yes Yes T61,T62,T8 Yes T61,T62,T8 INPUT
alert_req_i No No No INPUT
alert_ack_o No No No OUTPUT
alert_state_o No No No OUTPUT
alert_rx_i.ack_n Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
alert_rx_i.ack_p Yes Yes T61,T62,T8 Yes T61,T62,T8 INPUT
alert_rx_i.ping_n Yes Yes T88,T89,T90 Yes T88,T89,T90 INPUT
alert_rx_i.ping_p Yes Yes T88,T89,T90 Yes T88,T89,T90 INPUT
alert_tx_o.alert_n Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
alert_tx_o.alert_p Yes Yes T61,T62,T8 Yes T61,T62,T8 OUTPUT

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.gen_alert_tx[0].u_prim_alert_sender
TotalCoveredPercent
Totals 12 10 83.33
Total Bits 24 22 91.67
Total Bits 0->1 12 12 100.00
Total Bits 1->0 12 10 83.33

Ports 12 10 83.33
Port Bits 24 22 91.67
Port Bits 0->1 12 12 100.00
Port Bits 1->0 12 10 83.33

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
rst_ni Yes Yes T4,T5,T44 Yes T4,T5,T6 INPUT
alert_test_i Yes Yes T61,T62,T63 Yes T61,T62,T63 INPUT
alert_req_i No No Yes T95 INPUT
alert_ack_o Yes Yes T95 Yes T95 OUTPUT
alert_state_o No No Yes T95 OUTPUT
alert_rx_i.ack_n Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
alert_rx_i.ack_p Yes Yes T61,T62,T88 Yes T61,T62,T88 INPUT
alert_rx_i.ping_n Yes Yes T88,T89,T90 Yes T88,T89,T90 INPUT
alert_rx_i.ping_p Yes Yes T88,T89,T90 Yes T88,T89,T90 INPUT
alert_tx_o.alert_n Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
alert_tx_o.alert_p Yes Yes T61,T62,T88 Yes T61,T62,T88 OUTPUT

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_rv_plic.gen_alert_tx[0].u_prim_alert_sender
TotalCoveredPercent
Totals 12 12 100.00
Total Bits 24 24 100.00
Total Bits 0->1 12 12 100.00
Total Bits 1->0 12 12 100.00

Ports 12 12 100.00
Port Bits 24 24 100.00
Port Bits 0->1 12 12 100.00
Port Bits 1->0 12 12 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
rst_ni Yes Yes T4,T5,T44 Yes T4,T5,T6 INPUT
alert_test_i Yes Yes T61,T62,T63 Yes T61,T62,T63 INPUT
alert_req_i Yes Yes T428 Yes T428 INPUT
alert_ack_o Yes Yes T428 Yes T428 OUTPUT
alert_state_o Yes Yes T428 Yes T428 OUTPUT
alert_rx_i.ack_n Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
alert_rx_i.ack_p Yes Yes T61,T62,T428 Yes T61,T62,T428 INPUT
alert_rx_i.ping_n Yes Yes T88,T89,T90 Yes T88,T89,T90 INPUT
alert_rx_i.ping_p Yes Yes T88,T89,T90 Yes T88,T89,T90 INPUT
alert_tx_o.alert_n Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
alert_tx_o.alert_p Yes Yes T61,T62,T428 Yes T61,T62,T428 OUTPUT

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.gen_alert_senders[1].u_alert_sender
TotalCoveredPercent
Totals 12 12 100.00
Total Bits 24 24 100.00
Total Bits 0->1 12 12 100.00
Total Bits 1->0 12 12 100.00

Ports 12 12 100.00
Port Bits 24 24 100.00
Port Bits 0->1 12 12 100.00
Port Bits 1->0 12 12 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
rst_ni Yes Yes T4,T5,T44 Yes T4,T5,T6 INPUT
alert_test_i Yes Yes T73,T61,T62 Yes T73,T61,T62 INPUT
alert_req_i Yes Yes T8,T9 Yes T8,T9 INPUT
alert_ack_o Yes Yes T8,T9 Yes T8,T9 OUTPUT
alert_state_o Yes Yes T8,T9 Yes T8,T9 OUTPUT
alert_rx_i.ack_n Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
alert_rx_i.ack_p Yes Yes T73,T61,T62 Yes T73,T61,T62 INPUT
alert_rx_i.ping_n Yes Yes T88,T89,T90 Yes T88,T89,T90 INPUT
alert_rx_i.ping_p Yes Yes T88,T89,T90 Yes T88,T89,T90 INPUT
alert_tx_o.alert_n Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
alert_tx_o.alert_p Yes Yes T73,T61,T62 Yes T73,T61,T62 OUTPUT

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.gen_alert_senders[2].u_alert_sender
TotalCoveredPercent
Totals 12 12 100.00
Total Bits 24 24 100.00
Total Bits 0->1 12 12 100.00
Total Bits 1->0 12 12 100.00

Ports 12 12 100.00
Port Bits 24 24 100.00
Port Bits 0->1 12 12 100.00
Port Bits 1->0 12 12 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
rst_ni Yes Yes T4,T5,T44 Yes T4,T5,T6 INPUT
alert_test_i Yes Yes T61,T62,T8 Yes T61,T62,T8 INPUT
alert_req_i Yes Yes T259,T274,T255 Yes T259,T274,T255 INPUT
alert_ack_o Yes Yes T259,T255,T125 Yes T259,T255,T125 OUTPUT
alert_state_o Yes Yes T259,T255,T125 Yes T259,T274,T255 OUTPUT
alert_rx_i.ack_n Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
alert_rx_i.ack_p Yes Yes T259,T255,T125 Yes T259,T255,T125 INPUT
alert_rx_i.ping_n Yes Yes T88,T89,T90 Yes T88,T89,T90 INPUT
alert_rx_i.ping_p Yes Yes T88,T89,T90 Yes T88,T89,T90 INPUT
alert_tx_o.alert_n Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
alert_tx_o.alert_p Yes Yes T259,T255,T125 Yes T259,T274,T255 OUTPUT

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