Unified Coverage Report :: Module :: prim_sync_reqack_data

Module : prim_sync_reqack_data

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack_data.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_rv_core_ibex.u_prim_sync_reqack_data	100.00	100.00					100.00
tb.dut.top_earlgrey.u_rv_core_ibex.u_edn_if.u_prim_sync_reqack_data	100.00	100.00					100.00

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_prim_sync_reqack_data

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.67	100.00	66.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
89.83	96.47	89.29	99.75		100.00	63.64	u_rv_core_ibex

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_sync_reqack	91.67	100.00	66.67			100.00	100.00

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_edn_if.u_prim_sync_reqack_data

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.67	100.00	66.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	84.62			100.00	100.00	u_edn_if

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_sync_reqack	91.67	100.00	66.67			100.00	100.00

Line Coverage for Module : prim_sync_reqack_data

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	153	0	0
CONT_ASSIGN	156	0	0
ALWAYS	159	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack_data.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack_data.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
93	1	1
153		unreachable
156		unreachable
159		unreachable
160		unreachable
162		unreachable

---

Assert Coverage for Module : prim_sync_reqack_data

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcA	1056226560	4343	0	0
gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcB	1056226560	4343	0	0

gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcA

Name	Attempts	Real Successes	Failures	Incomplete
Total	1056226560	4343	0	0
T4	194917	1	0	0
T5	146344	2	0	0
T6	71289	1	0	0
T16	253587	4	0	0
T18	126530	14	0	0
T42	180164	2	0	0
T60	100192	1	0	0
T86	72106	1	0	0
T87	72119	1	0	0
T88	79830	1	0	0
T176	64713	3	0	0
T177	0	8	0	0
T178	0	7	0	0
T266	0	8	0	0
T267	0	8	0	0
T268	0	4	0	0
T269	125615	0	0	0
T270	65254	0	0	0
T271	136572	0	0	0
T272	144197	0	0	0
T273	98484	0	0	0
T274	131574	0	0	0
T275	298628	0	0	0
T276	598829	0	0	0
T277	139983	0	0	0

gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcB

Name	Attempts	Real Successes	Failures	Incomplete
Total	1056226560	4343	0	0
T4	194917	1	0	0
T5	146344	2	0	0
T6	71289	1	0	0
T16	253587	4	0	0
T18	126530	14	0	0
T42	180164	2	0	0
T60	100192	1	0	0
T86	72106	1	0	0
T87	72119	1	0	0
T88	79830	1	0	0
T176	64713	3	0	0
T177	0	8	0	0
T178	0	7	0	0
T266	0	8	0	0
T267	0	8	0	0
T268	0	4	0	0
T269	125615	0	0	0
T270	65254	0	0	0
T271	136572	0	0	0
T272	144197	0	0	0
T273	98484	0	0	0
T274	131574	0	0	0
T275	298628	0	0	0
T276	598829	0	0	0
T277	139983	0	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_prim_sync_reqack_data

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	153	0	0
CONT_ASSIGN	156	0	0
ALWAYS	159	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack_data.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack_data.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
93	1	1
153		unreachable
156		unreachable
159		unreachable
160		unreachable
162		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_prim_sync_reqack_data

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcA	528113280	38	0	0
gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcB	528113280	38	0	0

gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcA

Name	Attempts	Real Successes	Failures	Incomplete
Total	528113280	38	0	0
T176	64713	3	0	0
T177	0	8	0	0
T178	0	7	0	0
T266	0	8	0	0
T267	0	8	0	0
T268	0	4	0	0
T269	125615	0	0	0
T270	65254	0	0	0
T271	136572	0	0	0
T272	144197	0	0	0
T273	98484	0	0	0
T274	131574	0	0	0
T275	298628	0	0	0
T276	598829	0	0	0
T277	139983	0	0	0

gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcB

Name	Attempts	Real Successes	Failures	Incomplete
Total	528113280	38	0	0
T176	64713	3	0	0
T177	0	8	0	0
T178	0	7	0	0
T266	0	8	0	0
T267	0	8	0	0
T268	0	4	0	0
T269	125615	0	0	0
T270	65254	0	0	0
T271	136572	0	0	0
T272	144197	0	0	0
T273	98484	0	0	0
T274	131574	0	0	0
T275	298628	0	0	0
T276	598829	0	0	0
T277	139983	0	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_edn_if.u_prim_sync_reqack_data

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	153	0	0
CONT_ASSIGN	156	0	0
ALWAYS	159	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack_data.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack_data.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
93	1	1
153		unreachable
156		unreachable
159		unreachable
160		unreachable
162		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_edn_if.u_prim_sync_reqack_data

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcA	528113280	4305	0	0
gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcB	528113280	4305	0	0

gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcA

Name	Attempts	Real Successes	Failures	Incomplete
Total	528113280	4305	0	0
T4	194917	1	0	0
T5	146344	2	0	0
T6	71289	1	0	0
T16	253587	4	0	0
T18	126530	14	0	0
T42	180164	2	0	0
T60	100192	1	0	0
T86	72106	1	0	0
T87	72119	1	0	0
T88	79830	1	0	0

gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcB

Name	Attempts	Real Successes	Failures	Incomplete
Total	528113280	4305	0	0
T4	194917	1	0	0
T5	146344	2	0	0
T6	71289	1	0	0
T16	253587	4	0	0
T18	126530	14	0	0
T42	180164	2	0	0
T60	100192	1	0	0
T86	72106	1	0	0
T87	72119	1	0	0
T88	79830	1	0	0