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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.14 95.59 94.04 95.50 94.82 97.35 99.53


Total test records in report: 2903
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T1027 /workspace/coverage/default/1.chip_sw_hmac_multistream.39597149 Jul 10 08:08:36 PM PDT 24 Jul 10 08:37:52 PM PDT 24 7748931724 ps
T794 /workspace/coverage/default/74.chip_sw_all_escalation_resets.849950490 Jul 10 08:30:00 PM PDT 24 Jul 10 08:41:37 PM PDT 24 6259416792 ps
T34 /workspace/coverage/default/0.chip_sw_usbdev_dpi.4035598274 Jul 10 07:56:48 PM PDT 24 Jul 10 08:44:14 PM PDT 24 11693617834 ps
T201 /workspace/coverage/default/1.chip_sw_uart_tx_rx_bootstrap.2642333552 Jul 10 08:04:39 PM PDT 24 Jul 11 12:04:48 AM PDT 24 77801990296 ps
T311 /workspace/coverage/default/2.chip_sw_alert_handler_ping_timeout.1012327666 Jul 10 08:16:10 PM PDT 24 Jul 10 08:23:04 PM PDT 24 3861442856 ps
T797 /workspace/coverage/default/52.chip_sw_all_escalation_resets.4036286476 Jul 10 08:29:03 PM PDT 24 Jul 10 08:39:21 PM PDT 24 5622083544 ps
T10 /workspace/coverage/default/0.chip_sw_sleep_pin_wake.2996293033 Jul 10 07:56:46 PM PDT 24 Jul 10 08:02:34 PM PDT 24 3875191424 ps
T205 /workspace/coverage/default/0.chip_sw_sysrst_ctrl_inputs.2213882445 Jul 10 07:57:54 PM PDT 24 Jul 10 08:04:37 PM PDT 24 3514271686 ps
T35 /workspace/coverage/default/0.chip_sw_usbdev_pincfg.1368927705 Jul 10 07:56:15 PM PDT 24 Jul 10 10:01:48 PM PDT 24 31930274320 ps
T1028 /workspace/coverage/default/2.chip_sw_alert_handler_escalation.4248865643 Jul 10 08:16:23 PM PDT 24 Jul 10 08:25:34 PM PDT 24 5530996042 ps
T517 /workspace/coverage/default/0.chip_sw_pwrmgr_all_reset_reqs.3612036924 Jul 10 07:56:59 PM PDT 24 Jul 10 08:24:12 PM PDT 24 12115886240 ps
T376 /workspace/coverage/default/0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.2597336928 Jul 10 07:59:16 PM PDT 24 Jul 10 08:07:22 PM PDT 24 5389084136 ps
T674 /workspace/coverage/default/1.chip_sw_alert_handler_ping_ok.1577483632 Jul 10 08:06:33 PM PDT 24 Jul 10 08:29:56 PM PDT 24 7286409602 ps
T379 /workspace/coverage/default/0.chip_sw_power_idle_load.2562487407 Jul 10 07:59:54 PM PDT 24 Jul 10 08:11:38 PM PDT 24 4803070948 ps
T252 /workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access.3084528847 Jul 10 08:16:21 PM PDT 24 Jul 10 08:24:08 PM PDT 24 3859231400 ps
T782 /workspace/coverage/default/77.chip_sw_alert_handler_lpg_sleep_mode_alerts.2234661739 Jul 10 08:30:28 PM PDT 24 Jul 10 08:35:41 PM PDT 24 3644026010 ps
T1029 /workspace/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en.4294615905 Jul 10 08:13:50 PM PDT 24 Jul 10 08:32:28 PM PDT 24 6277694067 ps
T83 /workspace/coverage/default/0.chip_sw_alert_handler_entropy.2171052800 Jul 10 07:57:37 PM PDT 24 Jul 10 08:04:26 PM PDT 24 2852604671 ps
T741 /workspace/coverage/default/98.chip_sw_all_escalation_resets.3319463055 Jul 10 08:43:07 PM PDT 24 Jul 10 08:53:13 PM PDT 24 5180763034 ps
T1030 /workspace/coverage/default/2.chip_sw_uart_tx_rx.1827640858 Jul 10 08:17:57 PM PDT 24 Jul 10 08:29:46 PM PDT 24 4587918780 ps
T1031 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.2611471711 Jul 10 07:57:18 PM PDT 24 Jul 10 08:06:49 PM PDT 24 4570985592 ps
T706 /workspace/coverage/default/0.rom_e2e_jtag_debug_dev.1168200094 Jul 10 08:00:42 PM PDT 24 Jul 10 08:35:51 PM PDT 24 11284773356 ps
T792 /workspace/coverage/default/7.chip_sw_alert_handler_lpg_sleep_mode_alerts.2344000161 Jul 10 08:23:32 PM PDT 24 Jul 10 08:29:09 PM PDT 24 3222950838 ps
T69 /workspace/coverage/default/3.chip_tap_straps_dev.3711368658 Jul 10 08:22:40 PM PDT 24 Jul 10 08:49:19 PM PDT 24 16446251003 ps
T1032 /workspace/coverage/default/0.rom_e2e_static_critical.2632980623 Jul 10 08:04:04 PM PDT 24 Jul 10 09:07:38 PM PDT 24 16629658510 ps
T1033 /workspace/coverage/default/2.chip_sw_entropy_src_smoketest.3913834199 Jul 10 08:21:53 PM PDT 24 Jul 10 08:30:51 PM PDT 24 4085407632 ps
T1034 /workspace/coverage/default/1.chip_sw_otbn_smoketest.2455562627 Jul 10 08:12:34 PM PDT 24 Jul 10 08:38:21 PM PDT 24 7246249776 ps
T1035 /workspace/coverage/default/0.chip_sw_lc_walkthrough_prodend.789092937 Jul 10 07:57:04 PM PDT 24 Jul 10 08:11:41 PM PDT 24 9302526722 ps
T755 /workspace/coverage/default/3.chip_sw_all_escalation_resets.3917049309 Jul 10 08:22:46 PM PDT 24 Jul 10 08:32:39 PM PDT 24 4477475390 ps
T1036 /workspace/coverage/default/1.rom_e2e_shutdown_output.1877782106 Jul 10 08:17:33 PM PDT 24 Jul 10 09:05:19 PM PDT 24 27503004670 ps
T721 /workspace/coverage/default/3.chip_sw_alert_handler_lpg_sleep_mode_alerts.2856571089 Jul 10 08:22:36 PM PDT 24 Jul 10 08:29:31 PM PDT 24 4258961440 ps
T436 /workspace/coverage/default/88.chip_sw_alert_handler_lpg_sleep_mode_alerts.2512190632 Jul 10 08:41:49 PM PDT 24 Jul 10 08:47:46 PM PDT 24 3448707162 ps
T1037 /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_disabled.2708468152 Jul 10 08:15:02 PM PDT 24 Jul 10 08:18:34 PM PDT 24 2297409816 ps
T446 /workspace/coverage/default/0.chip_sw_edn_entropy_reqs_jitter.259007092 Jul 10 07:57:47 PM PDT 24 Jul 10 08:20:18 PM PDT 24 6844913129 ps
T683 /workspace/coverage/default/20.chip_sw_all_escalation_resets.272435521 Jul 10 08:25:10 PM PDT 24 Jul 10 08:35:35 PM PDT 24 6489571960 ps
T1038 /workspace/coverage/default/2.chip_sw_hmac_enc_jitter_en_reduced_freq.1955235653 Jul 10 08:20:36 PM PDT 24 Jul 10 08:24:59 PM PDT 24 2632166890 ps
T380 /workspace/coverage/default/36.chip_sw_alert_handler_lpg_sleep_mode_alerts.1206953925 Jul 10 08:27:58 PM PDT 24 Jul 10 08:34:46 PM PDT 24 3689881660 ps
T1039 /workspace/coverage/default/0.chip_sw_pwrmgr_main_power_glitch_reset.3236438279 Jul 10 08:00:32 PM PDT 24 Jul 10 08:05:10 PM PDT 24 3439388945 ps
T1040 /workspace/coverage/default/85.chip_sw_alert_handler_lpg_sleep_mode_alerts.3945365547 Jul 10 08:43:11 PM PDT 24 Jul 10 08:48:57 PM PDT 24 3151536202 ps
T36 /workspace/coverage/default/0.chip_sw_usbdev_setuprx.2990098688 Jul 10 07:56:53 PM PDT 24 Jul 10 08:06:37 PM PDT 24 3712837572 ps
T1041 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.208835588 Jul 10 08:05:47 PM PDT 24 Jul 10 08:59:59 PM PDT 24 14607863984 ps
T1042 /workspace/coverage/default/0.chip_sw_hmac_oneshot.1134177032 Jul 10 08:00:10 PM PDT 24 Jul 10 08:06:38 PM PDT 24 3048977762 ps
T762 /workspace/coverage/default/30.chip_sw_all_escalation_resets.4271328696 Jul 10 08:26:31 PM PDT 24 Jul 10 08:35:34 PM PDT 24 4936489448 ps
T1043 /workspace/coverage/default/1.chip_sw_kmac_smoketest.542824704 Jul 10 08:11:55 PM PDT 24 Jul 10 08:17:31 PM PDT 24 2645426556 ps
T260 /workspace/coverage/default/65.chip_sw_all_escalation_resets.1622039142 Jul 10 08:30:12 PM PDT 24 Jul 10 08:39:52 PM PDT 24 5884149704 ps
T1044 /workspace/coverage/default/10.chip_sw_uart_rand_baudrate.510663872 Jul 10 08:24:13 PM PDT 24 Jul 10 08:45:26 PM PDT 24 7958328644 ps
T377 /workspace/coverage/default/1.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.962443865 Jul 10 08:11:25 PM PDT 24 Jul 10 08:17:53 PM PDT 24 5823446600 ps
T318 /workspace/coverage/default/0.chip_plic_all_irqs_0.1503478464 Jul 10 07:58:21 PM PDT 24 Jul 10 08:17:09 PM PDT 24 5802855260 ps
T1045 /workspace/coverage/default/2.chip_sw_clkmgr_off_aes_trans.1196964641 Jul 10 08:18:53 PM PDT 24 Jul 10 08:27:36 PM PDT 24 5061192766 ps
T1046 /workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.364262781 Jul 10 08:16:28 PM PDT 24 Jul 10 08:34:26 PM PDT 24 10709495506 ps
T1047 /workspace/coverage/default/1.rom_e2e_asm_init_prod.2944091826 Jul 10 08:17:42 PM PDT 24 Jul 10 09:29:06 PM PDT 24 15367553560 ps
T1048 /workspace/coverage/default/2.chip_sw_edn_sw_mode.1651757399 Jul 10 08:17:26 PM PDT 24 Jul 10 08:54:14 PM PDT 24 8288082000 ps
T11 /workspace/coverage/default/0.chip_sw_sleep_pin_retention.3265535231 Jul 10 07:56:40 PM PDT 24 Jul 10 08:02:38 PM PDT 24 3038667668 ps
T1049 /workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq.3183043627 Jul 10 08:23:54 PM PDT 24 Jul 10 08:31:44 PM PDT 24 3565982015 ps
T722 /workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_alerts.1576945219 Jul 10 08:15:40 PM PDT 24 Jul 10 08:22:30 PM PDT 24 4464367720 ps
T90 /workspace/coverage/default/69.chip_sw_alert_handler_lpg_sleep_mode_alerts.2909077950 Jul 10 08:31:57 PM PDT 24 Jul 10 08:39:00 PM PDT 24 3757923256 ps
T1050 /workspace/coverage/default/0.rom_volatile_raw_unlock.3404803394 Jul 10 08:04:00 PM PDT 24 Jul 10 08:05:46 PM PDT 24 2503237825 ps
T1051 /workspace/coverage/default/2.chip_sw_otbn_randomness.923981890 Jul 10 08:25:09 PM PDT 24 Jul 10 08:39:40 PM PDT 24 5602511790 ps
T1052 /workspace/coverage/default/1.chip_sw_flash_ctrl_clock_freqs.1872145123 Jul 10 08:03:25 PM PDT 24 Jul 10 08:26:40 PM PDT 24 5715045641 ps
T1053 /workspace/coverage/default/2.chip_sw_uart_smoketest.2587306376 Jul 10 08:22:10 PM PDT 24 Jul 10 08:26:30 PM PDT 24 2566977460 ps
T773 /workspace/coverage/default/45.chip_sw_alert_handler_lpg_sleep_mode_alerts.2441253100 Jul 10 08:28:13 PM PDT 24 Jul 10 08:34:56 PM PDT 24 3348951944 ps
T1054 /workspace/coverage/default/2.chip_sw_rstmgr_sw_req.3896655096 Jul 10 08:16:25 PM PDT 24 Jul 10 08:24:56 PM PDT 24 3823384792 ps
T1055 /workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_reset_reqs.2195933787 Jul 10 08:14:44 PM PDT 24 Jul 10 08:48:20 PM PDT 24 22729107591 ps
T50 /workspace/coverage/default/1.chip_sw_spi_device_tpm.2859019434 Jul 10 08:02:41 PM PDT 24 Jul 10 08:09:11 PM PDT 24 3633552118 ps
T1056 /workspace/coverage/default/4.chip_sw_uart_tx_rx.721981916 Jul 10 08:22:12 PM PDT 24 Jul 10 08:33:14 PM PDT 24 4106924336 ps
T26 /workspace/coverage/default/2.chip_sw_spi_device_pass_through_collision.3875617571 Jul 10 08:14:00 PM PDT 24 Jul 10 08:23:51 PM PDT 24 4962667808 ps
T365 /workspace/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.3962515392 Jul 10 08:20:56 PM PDT 24 Jul 10 08:31:37 PM PDT 24 4492355874 ps
T1057 /workspace/coverage/default/2.rom_e2e_shutdown_output.3272191451 Jul 10 08:25:02 PM PDT 24 Jul 10 09:21:59 PM PDT 24 27890449996 ps
T1058 /workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_power_glitch_reset.3241360746 Jul 10 08:04:51 PM PDT 24 Jul 10 09:03:51 PM PDT 24 38476180664 ps
T330 /workspace/coverage/default/1.chip_sw_i2c_host_tx_rx_idx2.1519918838 Jul 10 08:01:11 PM PDT 24 Jul 10 08:16:23 PM PDT 24 5515396600 ps
T1059 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_rma.3604826503 Jul 10 08:06:52 PM PDT 24 Jul 10 09:21:26 PM PDT 24 13744768440 ps
T1060 /workspace/coverage/default/1.chip_sw_uart_tx_rx_idx3.3633954333 Jul 10 08:02:53 PM PDT 24 Jul 10 08:14:55 PM PDT 24 4888715342 ps
T765 /workspace/coverage/default/66.chip_sw_alert_handler_lpg_sleep_mode_alerts.3269979967 Jul 10 08:30:37 PM PDT 24 Jul 10 08:36:34 PM PDT 24 4398170020 ps
T101 /workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_wake_ups.1955868365 Jul 10 08:10:45 PM PDT 24 Jul 10 08:18:26 PM PDT 24 6822982648 ps
T1061 /workspace/coverage/default/2.chip_sw_flash_ctrl_access.3912219567 Jul 10 08:15:08 PM PDT 24 Jul 10 08:35:30 PM PDT 24 5144501340 ps
T1062 /workspace/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.2274563180 Jul 10 08:11:14 PM PDT 24 Jul 10 08:16:16 PM PDT 24 2782820053 ps
T1063 /workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_no_scramble.3046549907 Jul 10 07:58:55 PM PDT 24 Jul 10 08:07:20 PM PDT 24 7374200232 ps
T1064 /workspace/coverage/default/48.chip_sw_all_escalation_resets.1635578564 Jul 10 08:28:33 PM PDT 24 Jul 10 08:38:08 PM PDT 24 5017979952 ps
T1065 /workspace/coverage/default/0.chip_sw_kmac_mode_kmac.4287299820 Jul 10 07:58:07 PM PDT 24 Jul 10 08:02:59 PM PDT 24 3400172432 ps
T1066 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.74203170 Jul 10 08:05:47 PM PDT 24 Jul 10 09:51:58 PM PDT 24 23978392040 ps
T1067 /workspace/coverage/default/1.rom_e2e_asm_init_rma.3505807920 Jul 10 08:16:58 PM PDT 24 Jul 10 09:11:06 PM PDT 24 15355219008 ps
T1068 /workspace/coverage/default/1.chip_sw_aes_smoketest.156560564 Jul 10 08:12:48 PM PDT 24 Jul 10 08:16:47 PM PDT 24 3207805712 ps
T780 /workspace/coverage/default/71.chip_sw_all_escalation_resets.2390872292 Jul 10 08:30:02 PM PDT 24 Jul 10 08:40:06 PM PDT 24 5072734092 ps
T1069 /workspace/coverage/default/41.chip_sw_all_escalation_resets.3703177247 Jul 10 08:29:53 PM PDT 24 Jul 10 08:41:05 PM PDT 24 4402687400 ps
T350 /workspace/coverage/default/1.chip_sw_pattgen_ios.487711949 Jul 10 08:01:06 PM PDT 24 Jul 10 08:05:32 PM PDT 24 2451548748 ps
T1070 /workspace/coverage/default/0.chip_sw_coremark.835560537 Jul 10 07:59:46 PM PDT 24 Jul 11 12:01:32 AM PDT 24 72180197000 ps
T1071 /workspace/coverage/default/56.chip_sw_all_escalation_resets.3227978022 Jul 10 08:30:26 PM PDT 24 Jul 10 08:37:53 PM PDT 24 4521439514 ps
T800 /workspace/coverage/default/23.chip_sw_alert_handler_lpg_sleep_mode_alerts.1920598745 Jul 10 08:26:47 PM PDT 24 Jul 10 08:32:15 PM PDT 24 4422675766 ps
T1072 /workspace/coverage/default/14.chip_sw_all_escalation_resets.3523074929 Jul 10 08:24:50 PM PDT 24 Jul 10 08:35:02 PM PDT 24 5398726872 ps
T1073 /workspace/coverage/default/1.chip_sw_kmac_mode_kmac.1811365816 Jul 10 08:10:27 PM PDT 24 Jul 10 08:15:54 PM PDT 24 3442305656 ps
T437 /workspace/coverage/default/10.chip_sw_alert_handler_lpg_sleep_mode_alerts.1592768353 Jul 10 08:26:05 PM PDT 24 Jul 10 08:33:41 PM PDT 24 3503565710 ps
T1074 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_dev.1791673769 Jul 10 08:06:32 PM PDT 24 Jul 10 09:16:31 PM PDT 24 14324078578 ps
T1075 /workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_scramble.3236215940 Jul 10 08:00:53 PM PDT 24 Jul 10 08:15:17 PM PDT 24 7986362700 ps
T1076 /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_por_reset.4290264748 Jul 10 07:58:56 PM PDT 24 Jul 10 08:09:59 PM PDT 24 6729731040 ps
T745 /workspace/coverage/default/85.chip_sw_all_escalation_resets.3285365982 Jul 10 08:42:58 PM PDT 24 Jul 10 08:52:26 PM PDT 24 5648418600 ps
T1077 /workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_no_meas.1367219497 Jul 10 08:15:45 PM PDT 24 Jul 10 09:22:24 PM PDT 24 14449104780 ps
T1078 /workspace/coverage/default/1.chip_sw_uart_rand_baudrate.76455155 Jul 10 08:04:03 PM PDT 24 Jul 10 08:13:10 PM PDT 24 3564046040 ps
T1079 /workspace/coverage/default/1.rom_volatile_raw_unlock.1869555495 Jul 10 08:13:56 PM PDT 24 Jul 10 08:16:13 PM PDT 24 2673189640 ps
T1080 /workspace/coverage/default/0.chip_sw_aes_enc.1123365498 Jul 10 07:57:59 PM PDT 24 Jul 10 08:04:24 PM PDT 24 3018113596 ps
T1081 /workspace/coverage/default/0.chip_sw_clkmgr_off_kmac_trans.2000973295 Jul 10 07:59:02 PM PDT 24 Jul 10 08:12:01 PM PDT 24 5174127620 ps
T158 /workspace/coverage/default/1.chip_sw_otp_ctrl_vendor_test_csr_access.1482028508 Jul 10 08:02:57 PM PDT 24 Jul 10 08:07:25 PM PDT 24 3376260764 ps
T1082 /workspace/coverage/default/0.chip_sw_clkmgr_off_aes_trans.427111964 Jul 10 07:58:09 PM PDT 24 Jul 10 08:06:52 PM PDT 24 4141946300 ps
T1083 /workspace/coverage/default/2.chip_sw_lc_ctrl_otp_hw_cfg0.3808676384 Jul 10 08:14:43 PM PDT 24 Jul 10 08:19:34 PM PDT 24 3005441660 ps
T1084 /workspace/coverage/default/20.chip_sw_alert_handler_lpg_sleep_mode_alerts.879142733 Jul 10 08:25:08 PM PDT 24 Jul 10 08:33:01 PM PDT 24 4101560632 ps
T675 /workspace/coverage/default/0.chip_sw_rv_dm_access_after_escalation_reset.9945956 Jul 10 07:59:29 PM PDT 24 Jul 10 08:05:56 PM PDT 24 4826417600 ps
T764 /workspace/coverage/default/59.chip_sw_alert_handler_lpg_sleep_mode_alerts.2703540760 Jul 10 08:28:11 PM PDT 24 Jul 10 08:33:13 PM PDT 24 3947049800 ps
T193 /workspace/coverage/default/1.chip_sw_spi_device_pass_through_collision.3542184174 Jul 10 08:05:06 PM PDT 24 Jul 10 08:13:06 PM PDT 24 4273804877 ps
T514 /workspace/coverage/default/2.chip_sw_rv_core_ibex_nmi_irq.2949809725 Jul 10 08:15:44 PM PDT 24 Jul 10 08:28:17 PM PDT 24 4984775336 ps
T1085 /workspace/coverage/default/0.chip_sw_lc_ctrl_raw_to_scrap.3373401705 Jul 10 07:57:34 PM PDT 24 Jul 10 08:00:29 PM PDT 24 3597093914 ps
T771 /workspace/coverage/default/36.chip_sw_all_escalation_resets.2808706888 Jul 10 08:27:14 PM PDT 24 Jul 10 08:37:31 PM PDT 24 6403111136 ps
T743 /workspace/coverage/default/22.chip_sw_all_escalation_resets.2674124556 Jul 10 08:28:49 PM PDT 24 Jul 10 08:37:50 PM PDT 24 4460319708 ps
T1086 /workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.3614094737 Jul 10 08:12:49 PM PDT 24 Jul 10 09:08:42 PM PDT 24 24415207757 ps
T785 /workspace/coverage/default/28.chip_sw_all_escalation_resets.3521063303 Jul 10 08:26:34 PM PDT 24 Jul 10 08:34:43 PM PDT 24 5823427400 ps
T759 /workspace/coverage/default/42.chip_sw_all_escalation_resets.903905959 Jul 10 08:27:42 PM PDT 24 Jul 10 08:38:10 PM PDT 24 4432233212 ps
T1087 /workspace/coverage/default/0.chip_sw_flash_scrambling_smoketest.1445150666 Jul 10 08:03:22 PM PDT 24 Jul 10 08:06:59 PM PDT 24 2557580068 ps
T407 /workspace/coverage/default/0.chip_sw_usbdev_stream.1656774924 Jul 10 07:56:30 PM PDT 24 Jul 10 09:23:17 PM PDT 24 18856105616 ps
T707 /workspace/coverage/default/0.rom_e2e_jtag_debug_rma.1239990185 Jul 10 08:00:30 PM PDT 24 Jul 10 08:36:42 PM PDT 24 11825826926 ps
T1088 /workspace/coverage/default/34.chip_sw_alert_handler_lpg_sleep_mode_alerts.2965144189 Jul 10 08:26:10 PM PDT 24 Jul 10 08:32:34 PM PDT 24 3932432200 ps
T12 /workspace/coverage/default/1.chip_sw_sleep_pin_wake.3863885730 Jul 10 08:03:38 PM PDT 24 Jul 10 08:08:35 PM PDT 24 2773513284 ps
T1089 /workspace/coverage/default/0.rom_e2e_asm_init_test_unlocked0.2982008043 Jul 10 08:07:48 PM PDT 24 Jul 10 09:00:09 PM PDT 24 10986412170 ps
T310 /workspace/coverage/default/1.chip_sw_flash_ctrl_lc_rw_en.1567101398 Jul 10 08:02:05 PM PDT 24 Jul 10 08:08:28 PM PDT 24 3989554916 ps
T441 /workspace/coverage/default/1.chip_sw_alert_handler_entropy.1557742783 Jul 10 08:06:42 PM PDT 24 Jul 10 08:14:41 PM PDT 24 3091876238 ps
T1090 /workspace/coverage/default/1.chip_sw_rv_timer_smoketest.828450887 Jul 10 08:11:42 PM PDT 24 Jul 10 08:16:49 PM PDT 24 2660094120 ps
T746 /workspace/coverage/default/62.chip_sw_all_escalation_resets.3357912112 Jul 10 08:28:53 PM PDT 24 Jul 10 08:43:30 PM PDT 24 5818582304 ps
T414 /workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_wake_ups.341186171 Jul 10 08:11:06 PM PDT 24 Jul 10 08:29:24 PM PDT 24 21125301460 ps
T1091 /workspace/coverage/default/2.chip_sw_keymgr_sideload_kmac.3638161340 Jul 10 08:16:59 PM PDT 24 Jul 10 08:45:34 PM PDT 24 8825370738 ps
T1092 /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_prod.1702001956 Jul 10 08:15:27 PM PDT 24 Jul 10 08:32:44 PM PDT 24 7931123612 ps
T1093 /workspace/coverage/default/2.chip_sw_kmac_smoketest.2394309799 Jul 10 08:23:17 PM PDT 24 Jul 10 08:29:52 PM PDT 24 3017779040 ps
T1094 /workspace/coverage/default/2.chip_sw_uart_tx_rx_idx2.3677520185 Jul 10 08:13:05 PM PDT 24 Jul 10 08:22:38 PM PDT 24 4003239182 ps
T240 /workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_pings.3365486728 Jul 10 08:16:44 PM PDT 24 Jul 10 08:45:51 PM PDT 24 13088857136 ps
T789 /workspace/coverage/default/73.chip_sw_alert_handler_lpg_sleep_mode_alerts.2573976289 Jul 10 08:30:43 PM PDT 24 Jul 10 08:37:01 PM PDT 24 3485563604 ps
T793 /workspace/coverage/default/87.chip_sw_alert_handler_lpg_sleep_mode_alerts.3019076327 Jul 10 08:42:48 PM PDT 24 Jul 10 08:47:49 PM PDT 24 3618961736 ps
T1095 /workspace/coverage/default/0.chip_sw_example_rom.2944566821 Jul 10 07:55:44 PM PDT 24 Jul 10 07:58:02 PM PDT 24 2276879270 ps
T415 /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_wake_ups.2338762569 Jul 10 08:00:16 PM PDT 24 Jul 10 08:28:30 PM PDT 24 22185109288 ps
T1096 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod.1649172967 Jul 10 08:05:13 PM PDT 24 Jul 10 09:00:27 PM PDT 24 14925855824 ps
T1097 /workspace/coverage/default/0.chip_sw_alert_handler_ping_timeout.1789920436 Jul 10 07:58:13 PM PDT 24 Jul 10 08:05:19 PM PDT 24 4153078260 ps
T1098 /workspace/coverage/default/0.chip_sw_hmac_enc.3579483930 Jul 10 07:58:25 PM PDT 24 Jul 10 08:02:09 PM PDT 24 2912078948 ps
T1099 /workspace/coverage/default/2.chip_sw_sram_ctrl_smoketest.1434116599 Jul 10 08:22:29 PM PDT 24 Jul 10 08:26:40 PM PDT 24 2612204694 ps
T1100 /workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en.3477550618 Jul 10 07:57:11 PM PDT 24 Jul 10 08:06:48 PM PDT 24 4511694270 ps
T132 /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.1954998836 Jul 10 07:59:56 PM PDT 24 Jul 10 08:06:46 PM PDT 24 4472443182 ps
T1101 /workspace/coverage/default/0.chip_sw_clkmgr_off_hmac_trans.2809292975 Jul 10 07:58:45 PM PDT 24 Jul 10 08:05:14 PM PDT 24 3712463150 ps
T1102 /workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.3838015704 Jul 10 08:00:18 PM PDT 24 Jul 10 08:11:09 PM PDT 24 5132773379 ps
T1103 /workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.1677444298 Jul 10 08:04:01 PM PDT 24 Jul 10 08:40:11 PM PDT 24 13232123149 ps
T113 /workspace/coverage/default/2.chip_sw_csrng_edn_concurrency_reduced_freq.3626805591 Jul 10 08:20:35 PM PDT 24 Jul 11 03:16:03 AM PDT 24 167139981846 ps
T1104 /workspace/coverage/default/2.chip_sw_otp_ctrl_ecc_error_vendor_test.3933254008 Jul 10 08:16:14 PM PDT 24 Jul 10 08:20:34 PM PDT 24 2994839251 ps
T1105 /workspace/coverage/default/1.chip_sw_example_rom.3537034797 Jul 10 08:02:48 PM PDT 24 Jul 10 08:05:33 PM PDT 24 2248238720 ps
T153 /workspace/coverage/default/2.chip_plic_all_irqs_10.1060680388 Jul 10 08:17:28 PM PDT 24 Jul 10 08:27:35 PM PDT 24 4495711500 ps
T1106 /workspace/coverage/default/0.chip_sw_lc_walkthrough_testunlocks.646055327 Jul 10 07:58:02 PM PDT 24 Jul 10 08:47:25 PM PDT 24 27313045632 ps
T222 /workspace/coverage/default/53.chip_sw_all_escalation_resets.3643421632 Jul 10 08:28:27 PM PDT 24 Jul 10 08:42:54 PM PDT 24 6108971666 ps
T1107 /workspace/coverage/default/4.chip_sw_uart_rand_baudrate.849045906 Jul 10 08:22:56 PM PDT 24 Jul 10 09:17:40 PM PDT 24 13554072280 ps
T58 /workspace/coverage/default/1.chip_sw_sleep_pin_retention.1006864932 Jul 10 08:04:35 PM PDT 24 Jul 10 08:10:17 PM PDT 24 4053607650 ps
T1108 /workspace/coverage/default/1.chip_sw_csrng_edn_concurrency.2655525524 Jul 10 08:08:21 PM PDT 24 Jul 10 09:22:35 PM PDT 24 16788133208 ps
T1109 /workspace/coverage/default/26.chip_sw_alert_handler_lpg_sleep_mode_alerts.1451128873 Jul 10 08:29:08 PM PDT 24 Jul 10 08:35:25 PM PDT 24 3873559860 ps
T1110 /workspace/coverage/default/2.chip_sw_pwrmgr_full_aon_reset.2240793081 Jul 10 08:14:09 PM PDT 24 Jul 10 08:24:44 PM PDT 24 7108298235 ps
T1111 /workspace/coverage/default/0.chip_sw_rstmgr_smoketest.1031052906 Jul 10 08:01:37 PM PDT 24 Jul 10 08:07:18 PM PDT 24 2705343638 ps
T1112 /workspace/coverage/default/1.chip_sw_aes_entropy.616801278 Jul 10 08:07:27 PM PDT 24 Jul 10 08:12:23 PM PDT 24 3114377784 ps
T1113 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_rma.2447484033 Jul 10 08:03:32 PM PDT 24 Jul 10 09:02:33 PM PDT 24 14700643960 ps
T1114 /workspace/coverage/default/0.chip_sw_csrng_smoketest.636597164 Jul 10 08:00:12 PM PDT 24 Jul 10 08:03:30 PM PDT 24 2520804000 ps
T253 /workspace/coverage/default/3.chip_sw_data_integrity_escalation.4186616731 Jul 10 08:22:22 PM PDT 24 Jul 10 08:32:10 PM PDT 24 5972976652 ps
T1115 /workspace/coverage/default/0.chip_sw_flash_init_reduced_freq.526054981 Jul 10 07:59:02 PM PDT 24 Jul 10 08:32:21 PM PDT 24 25353226136 ps
T1116 /workspace/coverage/default/2.chip_sw_sleep_pwm_pulses.1808787652 Jul 10 08:13:16 PM PDT 24 Jul 10 08:34:59 PM PDT 24 9336203650 ps
T1117 /workspace/coverage/default/2.chip_sw_rv_timer_smoketest.4157093387 Jul 10 08:21:28 PM PDT 24 Jul 10 08:25:09 PM PDT 24 2831223800 ps
T1118 /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_test_unlocked0.2845260916 Jul 10 08:14:53 PM PDT 24 Jul 10 08:25:22 PM PDT 24 4349994508 ps
T178 /workspace/coverage/default/1.chip_sw_rv_core_ibex_icache_invalidate.2032855698 Jul 10 08:11:50 PM PDT 24 Jul 10 08:16:58 PM PDT 24 2631111420 ps
T1119 /workspace/coverage/default/0.chip_sw_clkmgr_smoketest.178214361 Jul 10 08:00:23 PM PDT 24 Jul 10 08:04:41 PM PDT 24 3038909120 ps
T742 /workspace/coverage/default/25.chip_sw_all_escalation_resets.846206141 Jul 10 08:26:32 PM PDT 24 Jul 10 08:36:27 PM PDT 24 4966482750 ps
T1120 /workspace/coverage/default/0.chip_sw_rstmgr_sw_req.1246382373 Jul 10 07:57:43 PM PDT 24 Jul 10 08:03:49 PM PDT 24 3654326840 ps
T266 /workspace/coverage/default/2.chip_sw_rv_core_ibex_address_translation.340026177 Jul 10 08:19:41 PM PDT 24 Jul 10 08:25:31 PM PDT 24 2513240846 ps
T1121 /workspace/coverage/default/2.chip_sw_power_sleep_load.630864162 Jul 10 08:21:15 PM PDT 24 Jul 10 08:32:29 PM PDT 24 10254655788 ps
T412 /workspace/coverage/default/0.chip_sw_rom_ctrl_integrity_check.4202174864 Jul 10 07:57:48 PM PDT 24 Jul 10 08:08:23 PM PDT 24 8634789778 ps
T137 /workspace/coverage/default/4.chip_sw_sensor_ctrl_alert.1717115488 Jul 10 08:22:54 PM PDT 24 Jul 10 08:40:42 PM PDT 24 10117231224 ps
T138 /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.814101818 Jul 10 08:08:52 PM PDT 24 Jul 10 08:15:09 PM PDT 24 5699511352 ps
T1122 /workspace/coverage/default/0.chip_sw_data_integrity_escalation.1872555544 Jul 10 07:54:44 PM PDT 24 Jul 10 08:02:42 PM PDT 24 5284807648 ps
T1123 /workspace/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.3562127771 Jul 10 08:00:07 PM PDT 24 Jul 10 08:20:01 PM PDT 24 7446065407 ps
T1124 /workspace/coverage/default/2.chip_sw_flash_scrambling_smoketest.748008274 Jul 10 08:23:11 PM PDT 24 Jul 10 08:27:11 PM PDT 24 2859459330 ps
T64 /workspace/coverage/default/1.chip_tap_straps_testunlock0.1860522822 Jul 10 08:10:24 PM PDT 24 Jul 10 08:14:17 PM PDT 24 3522824029 ps
T1125 /workspace/coverage/default/2.chip_sw_aes_enc.2682440601 Jul 10 08:14:40 PM PDT 24 Jul 10 08:19:30 PM PDT 24 3515143694 ps
T1126 /workspace/coverage/default/2.chip_sw_aes_entropy.1246664274 Jul 10 08:15:15 PM PDT 24 Jul 10 08:19:59 PM PDT 24 3516304712 ps
T1127 /workspace/coverage/default/1.chip_sw_alert_handler_ping_timeout.4166449615 Jul 10 08:09:18 PM PDT 24 Jul 10 08:19:36 PM PDT 24 4854944128 ps
T1128 /workspace/coverage/default/4.chip_tap_straps_dev.2775258132 Jul 10 08:23:07 PM PDT 24 Jul 10 08:25:52 PM PDT 24 2481689310 ps
T1129 /workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_reset_reqs.895907599 Jul 10 08:01:58 PM PDT 24 Jul 10 08:41:45 PM PDT 24 26075460697 ps
T779 /workspace/coverage/default/54.chip_sw_alert_handler_lpg_sleep_mode_alerts.2940939142 Jul 10 08:30:29 PM PDT 24 Jul 10 08:36:55 PM PDT 24 3533528062 ps
T1130 /workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_por_reset.4160719314 Jul 10 07:56:02 PM PDT 24 Jul 10 08:04:49 PM PDT 24 6292729252 ps
T766 /workspace/coverage/default/27.chip_sw_all_escalation_resets.2899149200 Jul 10 08:25:47 PM PDT 24 Jul 10 08:40:40 PM PDT 24 6171650690 ps
T784 /workspace/coverage/default/60.chip_sw_alert_handler_lpg_sleep_mode_alerts.1765994431 Jul 10 08:29:59 PM PDT 24 Jul 10 08:37:01 PM PDT 24 3796308016 ps
T1131 /workspace/coverage/default/0.chip_sw_aon_timer_smoketest.1742920500 Jul 10 08:00:50 PM PDT 24 Jul 10 08:06:56 PM PDT 24 2942611658 ps
T751 /workspace/coverage/default/7.chip_sw_all_escalation_resets.938054682 Jul 10 08:25:12 PM PDT 24 Jul 10 08:35:55 PM PDT 24 5601227668 ps
T1132 /workspace/coverage/default/0.chip_sw_sram_ctrl_smoketest.4216471308 Jul 10 08:01:53 PM PDT 24 Jul 10 08:05:47 PM PDT 24 2379853848 ps
T206 /workspace/coverage/default/2.chip_sw_sysrst_ctrl_reset.2476157353 Jul 10 08:14:38 PM PDT 24 Jul 10 08:42:05 PM PDT 24 24311482522 ps
T241 /workspace/coverage/default/23.chip_sw_all_escalation_resets.3427539042 Jul 10 08:27:20 PM PDT 24 Jul 10 08:38:47 PM PDT 24 5340923352 ps
T1133 /workspace/coverage/default/0.chip_sw_example_manufacturer.3555361330 Jul 10 07:56:12 PM PDT 24 Jul 10 07:59:58 PM PDT 24 2649756150 ps
T1134 /workspace/coverage/default/3.chip_sw_csrng_edn_concurrency.3556123219 Jul 10 08:22:03 PM PDT 24 Jul 10 09:54:16 PM PDT 24 26754698184 ps
T1135 /workspace/coverage/default/2.rom_e2e_smoke.1463169294 Jul 10 08:26:05 PM PDT 24 Jul 10 09:23:03 PM PDT 24 15224228600 ps
T1136 /workspace/coverage/default/4.chip_sw_lc_ctrl_transition.4138006740 Jul 10 08:23:00 PM PDT 24 Jul 10 08:41:40 PM PDT 24 10896857969 ps
T1137 /workspace/coverage/default/1.chip_sw_pwrmgr_smoketest.3872269076 Jul 10 08:13:19 PM PDT 24 Jul 10 08:17:52 PM PDT 24 5727328050 ps
T1138 /workspace/coverage/default/1.chip_sw_otbn_mem_scramble.355188009 Jul 10 08:07:21 PM PDT 24 Jul 10 08:16:09 PM PDT 24 3625984500 ps
T1139 /workspace/coverage/default/1.chip_sw_power_idle_load.85559171 Jul 10 08:10:52 PM PDT 24 Jul 10 08:21:29 PM PDT 24 4719268446 ps
T65 /workspace/coverage/default/2.chip_tap_straps_rma.2115057529 Jul 10 08:18:36 PM PDT 24 Jul 10 08:23:27 PM PDT 24 3769509142 ps
T1140 /workspace/coverage/default/11.chip_sw_alert_handler_lpg_sleep_mode_alerts.75561884 Jul 10 08:24:47 PM PDT 24 Jul 10 08:32:23 PM PDT 24 4221441060 ps
T1141 /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_rma.1805395744 Jul 10 08:04:22 PM PDT 24 Jul 10 08:24:03 PM PDT 24 6330160068 ps
T425 /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_wake_ups.898380144 Jul 10 08:19:42 PM PDT 24 Jul 10 08:44:02 PM PDT 24 24273241544 ps
T1142 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.3872533192 Jul 10 08:02:43 PM PDT 24 Jul 10 09:03:03 PM PDT 24 15759543290 ps
T801 /workspace/coverage/default/39.chip_sw_all_escalation_resets.3727614130 Jul 10 08:26:48 PM PDT 24 Jul 10 08:36:32 PM PDT 24 4471371100 ps
T1143 /workspace/coverage/default/2.chip_sw_flash_ctrl_mem_protection.1094477440 Jul 10 08:20:55 PM PDT 24 Jul 10 08:40:48 PM PDT 24 6282937500 ps
T1144 /workspace/coverage/default/4.chip_tap_straps_testunlock0.2390230996 Jul 10 08:22:51 PM PDT 24 Jul 10 08:28:48 PM PDT 24 3654787108 ps
T1145 /workspace/coverage/default/1.chip_sival_flash_info_access.270930914 Jul 10 08:01:36 PM PDT 24 Jul 10 08:07:25 PM PDT 24 3633558908 ps
T1146 /workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en.3362838972 Jul 10 08:08:55 PM PDT 24 Jul 10 08:20:48 PM PDT 24 5532389984 ps
T328 /workspace/coverage/default/2.chip_sw_entropy_src_csrng.3766491091 Jul 10 08:17:26 PM PDT 24 Jul 10 08:31:31 PM PDT 24 5743351336 ps
T1147 /workspace/coverage/default/3.chip_tap_straps_prod.29144799 Jul 10 08:21:25 PM PDT 24 Jul 10 08:31:38 PM PDT 24 6390972685 ps
T207 /workspace/coverage/default/1.chip_sw_sysrst_ctrl_reset.3984955136 Jul 10 08:04:29 PM PDT 24 Jul 10 08:34:56 PM PDT 24 23702309294 ps
T298 /workspace/coverage/default/2.chip_sw_keymgr_sideload_aes.767015131 Jul 10 08:16:33 PM PDT 24 Jul 10 08:36:21 PM PDT 24 7783161662 ps
T723 /workspace/coverage/default/48.chip_sw_alert_handler_lpg_sleep_mode_alerts.1179942864 Jul 10 08:29:24 PM PDT 24 Jul 10 08:34:44 PM PDT 24 3622691920 ps
T438 /workspace/coverage/default/21.chip_sw_all_escalation_resets.2215346163 Jul 10 08:25:11 PM PDT 24 Jul 10 08:34:09 PM PDT 24 5774212634 ps
T1148 /workspace/coverage/default/2.chip_sw_alert_handler_reverse_ping_in_deep_sleep.949616809 Jul 10 08:16:24 PM PDT 24 Jul 10 11:37:01 PM PDT 24 255132955432 ps
T1149 /workspace/coverage/default/2.chip_sw_csrng_kat_test.3899628805 Jul 10 08:17:23 PM PDT 24 Jul 10 08:21:24 PM PDT 24 2363788228 ps
T1150 /workspace/coverage/default/0.chip_sw_pwrmgr_wdog_reset.3517459138 Jul 10 07:57:46 PM PDT 24 Jul 10 08:07:32 PM PDT 24 5247497524 ps
T23 /workspace/coverage/default/1.chip_sw_sleep_pin_mio_dio_val.36343321 Jul 10 08:01:59 PM PDT 24 Jul 10 08:07:31 PM PDT 24 2885361678 ps
T1151 /workspace/coverage/default/0.chip_sw_alert_handler_ping_ok.3007914442 Jul 10 07:58:41 PM PDT 24 Jul 10 08:25:26 PM PDT 24 7836817800 ps
T1152 /workspace/coverage/default/2.chip_sw_rv_timer_irq.1836372279 Jul 10 08:15:53 PM PDT 24 Jul 10 08:20:09 PM PDT 24 2858443880 ps
T1153 /workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access.3996437525 Jul 10 08:10:42 PM PDT 24 Jul 10 08:19:41 PM PDT 24 4138659444 ps
T1154 /workspace/coverage/default/0.chip_sw_edn_kat.2495770399 Jul 10 07:56:48 PM PDT 24 Jul 10 08:05:55 PM PDT 24 3098749460 ps
T242 /workspace/coverage/default/1.chip_sw_rstmgr_cpu_info.2312141831 Jul 10 08:08:14 PM PDT 24 Jul 10 08:23:32 PM PDT 24 6990872864 ps
T1155 /workspace/coverage/default/0.chip_sw_aes_masking_off.3977165359 Jul 10 07:56:44 PM PDT 24 Jul 10 08:00:57 PM PDT 24 2903402806 ps
T1156 /workspace/coverage/default/1.chip_sw_otbn_randomness.3765422411 Jul 10 08:05:56 PM PDT 24 Jul 10 08:21:16 PM PDT 24 6166433892 ps
T1157 /workspace/coverage/default/1.chip_sw_flash_crash_alert.443036359 Jul 10 08:12:30 PM PDT 24 Jul 10 08:24:23 PM PDT 24 5299457316 ps
T208 /workspace/coverage/default/0.chip_sw_sysrst_ctrl_outputs.3641414051 Jul 10 07:57:52 PM PDT 24 Jul 10 08:03:43 PM PDT 24 2958187501 ps
T750 /workspace/coverage/default/11.chip_sw_all_escalation_resets.1614908152 Jul 10 08:26:09 PM PDT 24 Jul 10 08:37:05 PM PDT 24 6558752184 ps
T194 /workspace/coverage/default/0.chip_sw_spi_device_pass_through_collision.629060682 Jul 10 07:55:53 PM PDT 24 Jul 10 08:04:09 PM PDT 24 3801774533 ps
T47 /workspace/coverage/default/2.chip_sw_sysrst_ctrl_ulp_z3_wakeup.1884312782 Jul 10 08:16:34 PM PDT 24 Jul 10 08:25:22 PM PDT 24 5635780824 ps
T114 /workspace/coverage/default/0.chip_sw_csrng_edn_concurrency_reduced_freq.3234678051 Jul 10 07:59:49 PM PDT 24 Jul 11 12:30:28 AM PDT 24 103994749480 ps
T1158 /workspace/coverage/default/0.chip_sw_kmac_app_rom.3808270389 Jul 10 08:00:45 PM PDT 24 Jul 10 08:03:56 PM PDT 24 3068291500 ps
T1159 /workspace/coverage/default/2.chip_sw_inject_scramble_seed.1895776198 Jul 10 08:13:30 PM PDT 24 Jul 10 11:11:27 PM PDT 24 64910948171 ps
T1160 /workspace/coverage/default/1.chip_sw_rv_dm_access_after_wakeup.1940560534 Jul 10 08:11:09 PM PDT 24 Jul 10 08:22:11 PM PDT 24 5387889080 ps
T1161 /workspace/coverage/default/1.chip_sw_entropy_src_smoketest.2107488725 Jul 10 08:12:04 PM PDT 24 Jul 10 08:19:51 PM PDT 24 3056443640 ps
T1162 /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.1439676782 Jul 10 08:17:20 PM PDT 24 Jul 10 08:25:08 PM PDT 24 6239836206 ps
T1163 /workspace/coverage/default/0.rom_e2e_shutdown_exception_c.1636123815 Jul 10 08:03:11 PM PDT 24 Jul 10 09:00:53 PM PDT 24 14920575071 ps
T320 /workspace/coverage/default/2.chip_plic_all_irqs_0.1925181867 Jul 10 08:17:01 PM PDT 24 Jul 10 08:37:20 PM PDT 24 5976875492 ps
T408 /workspace/coverage/default/0.chip_sw_usbdev_config_host.97815649 Jul 10 07:56:42 PM PDT 24 Jul 10 08:28:37 PM PDT 24 8273860524 ps
T363 /workspace/coverage/default/1.chip_sw_aon_timer_irq.1557252368 Jul 10 08:04:35 PM PDT 24 Jul 10 08:11:43 PM PDT 24 4848162456 ps
T1164 /workspace/coverage/default/18.chip_sw_uart_rand_baudrate.1370886000 Jul 10 08:25:54 PM PDT 24 Jul 10 08:50:29 PM PDT 24 8375769704 ps
T209 /workspace/coverage/default/1.chip_sw_sysrst_ctrl_outputs.1792516450 Jul 10 08:06:48 PM PDT 24 Jul 10 08:13:06 PM PDT 24 3818053496 ps
T357 /workspace/coverage/default/2.chip_sw_i2c_host_tx_rx_idx2.154299097 Jul 10 08:14:54 PM PDT 24 Jul 10 08:26:59 PM PDT 24 5339712504 ps
T795 /workspace/coverage/default/88.chip_sw_all_escalation_resets.1435850277 Jul 10 08:42:12 PM PDT 24 Jul 10 08:50:44 PM PDT 24 6029169960 ps
T1165 /workspace/coverage/default/97.chip_sw_all_escalation_resets.1466874415 Jul 10 08:43:07 PM PDT 24 Jul 10 08:51:23 PM PDT 24 4636884432 ps
T778 /workspace/coverage/default/53.chip_sw_alert_handler_lpg_sleep_mode_alerts.3832781435 Jul 10 08:30:57 PM PDT 24 Jul 10 08:36:41 PM PDT 24 3307534536 ps
T515 /workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.2099300619 Jul 10 08:19:50 PM PDT 24 Jul 10 08:29:10 PM PDT 24 5505689234 ps
T1166 /workspace/coverage/default/0.chip_sw_clkmgr_jitter_frequency.2115007255 Jul 10 07:59:06 PM PDT 24 Jul 10 08:05:00 PM PDT 24 4004135900 ps
T708 /workspace/coverage/default/2.chip_sw_pattgen_ios.1725897636 Jul 10 08:14:21 PM PDT 24 Jul 10 08:18:48 PM PDT 24 3210105670 ps
T1167 /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_lc.3769538066 Jul 10 08:08:58 PM PDT 24 Jul 10 08:16:56 PM PDT 24 6670132236 ps
T278 /workspace/coverage/default/1.chip_sw_sram_ctrl_execution_main.3924646743 Jul 10 08:08:41 PM PDT 24 Jul 10 08:20:11 PM PDT 24 8024789563 ps
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