Toggle Coverage for Module :
pwm
| Total | Covered | Percent |
Totals |
32 |
32 |
100.00 |
Total Bits |
306 |
306 |
100.00 |
Total Bits 0->1 |
153 |
153 |
100.00 |
Total Bits 1->0 |
153 |
153 |
100.00 |
| | | |
Ports |
32 |
32 |
100.00 |
Port Bits |
306 |
306 |
100.00 |
Port Bits 0->1 |
153 |
153 |
100.00 |
Port Bits 1->0 |
153 |
153 |
100.00 |
Port Details
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
clk_i |
Yes |
Yes |
T4,T5,T6 |
Yes |
T4,T5,T6 |
INPUT |
rst_ni |
Yes |
Yes |
T5,T43,T19 |
Yes |
T4,T5,T6 |
INPUT |
clk_core_i |
Yes |
Yes |
T4,T5,T6 |
Yes |
T4,T5,T6 |
INPUT |
rst_core_ni |
Yes |
Yes |
T5,T43,T19 |
Yes |
T4,T5,T6 |
INPUT |
tl_i.d_ready |
Yes |
Yes |
T4,T5,T6 |
Yes |
T4,T5,T6 |
INPUT |
tl_i.a_user.data_intg[6:0] |
Yes |
Yes |
T116,T218,T730 |
Yes |
T116,T218,T730 |
INPUT |
tl_i.a_user.cmd_intg[6:0] |
Yes |
Yes |
T4,T5,T6 |
Yes |
T4,T5,T6 |
INPUT |
tl_i.a_user.instr_type[3:0] |
Yes |
Yes |
T4,T5,T6 |
Yes |
T4,T5,T6 |
INPUT |
tl_i.a_user.rsvd[4:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_i.a_data[31:0] |
Yes |
Yes |
T116,T218,T730 |
Yes |
T116,T218,T730 |
INPUT |
tl_i.a_mask[3:0] |
Yes |
Yes |
T4,T5,T6 |
Yes |
T4,T5,T6 |
INPUT |
tl_i.a_address[6:0] |
Yes |
Yes |
*T78,*T79,*T80 |
Yes |
T78,T79,T80 |
INPUT |
tl_i.a_address[15:7] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_i.a_address[16] |
Yes |
Yes |
*T4,*T5,*T6 |
Yes |
T4,T5,T6 |
INPUT |
tl_i.a_address[17] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_i.a_address[18] |
Yes |
Yes |
*T4,*T5,*T6 |
Yes |
T4,T5,T6 |
INPUT |
tl_i.a_address[21:19] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_i.a_address[22] |
Yes |
Yes |
*T4,*T5,*T6 |
Yes |
T4,T5,T6 |
INPUT |
tl_i.a_address[29:23] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_i.a_address[30] |
Yes |
Yes |
*T4,*T5,*T6 |
Yes |
T4,T5,T6 |
INPUT |
tl_i.a_address[31] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_i.a_source[5:0] |
Yes |
Yes |
*T58,*T70,*T71 |
Yes |
T58,T70,T71 |
INPUT |
tl_i.a_source[7:6] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_i.a_size[1:0] |
Yes |
Yes |
T78,T79,T80 |
Yes |
T78,T79,T80 |
INPUT |
tl_i.a_param[2:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_i.a_opcode[2:0] |
Yes |
Yes |
T58,T71,T81 |
Yes |
T58,T71,T81 |
INPUT |
tl_i.a_valid |
Yes |
Yes |
T116,T218,T730 |
Yes |
T116,T218,T730 |
INPUT |
tl_o.a_ready |
Yes |
Yes |
T116,T218,T730 |
Yes |
T116,T218,T730 |
OUTPUT |
tl_o.d_error |
Yes |
Yes |
T78,T79,T80 |
Yes |
T78,T79,T80 |
OUTPUT |
tl_o.d_user.data_intg[6:0] |
Yes |
Yes |
T116,T218,T730 |
Yes |
T116,T218,T730 |
OUTPUT |
tl_o.d_user.rsp_intg[6:0] |
Yes |
Yes |
T116,T218,T730 |
Yes |
T116,T218,T730 |
OUTPUT |
tl_o.d_data[31:0] |
Yes |
Yes |
T116,T218,T730 |
Yes |
T116,T218,T730 |
OUTPUT |
tl_o.d_sink |
Yes |
Yes |
T78,T80,T82 |
Yes |
T78,T79,T80 |
OUTPUT |
tl_o.d_source[5:0] |
Yes |
Yes |
T78,*T80,*T82 |
Yes |
T78,T79,T80 |
OUTPUT |
tl_o.d_source[7:6] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_o.d_size[1:0] |
Yes |
Yes |
T78,T80,T82 |
Yes |
T78,T79,T80 |
OUTPUT |
tl_o.d_param[2:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_o.d_opcode[0] |
Yes |
Yes |
*T116,*T218,*T730 |
Yes |
T116,T218,T730 |
OUTPUT |
tl_o.d_opcode[2:1] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_o.d_valid |
Yes |
Yes |
T116,T218,T730 |
Yes |
T116,T218,T730 |
OUTPUT |
alert_rx_i[0].ack_n |
Yes |
Yes |
T4,T5,T6 |
Yes |
T4,T5,T6 |
INPUT |
alert_rx_i[0].ack_p |
Yes |
Yes |
T65,T66,T163 |
Yes |
T65,T66,T163 |
INPUT |
alert_rx_i[0].ping_n |
Yes |
Yes |
T163,T85,T86 |
Yes |
T163,T85,T86 |
INPUT |
alert_rx_i[0].ping_p |
Yes |
Yes |
T163,T85,T86 |
Yes |
T163,T85,T86 |
INPUT |
alert_tx_o[0].alert_n |
Yes |
Yes |
T4,T5,T6 |
Yes |
T4,T5,T6 |
OUTPUT |
alert_tx_o[0].alert_p |
Yes |
Yes |
T65,T66,T163 |
Yes |
T65,T66,T163 |
OUTPUT |
cio_pwm_o[5:0] |
Yes |
Yes |
T116,T218,T730 |
Yes |
T116,T218,T730 |
OUTPUT |
cio_pwm_en_o[5:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
*Tests covering at least one bit in the range