Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : top_earlgrey
SCORELINECONDTOGGLEFSMBRANCHASSERT
83.48 90.68 59.77 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_systems_top_earlgrey_0.1/rtl/autogen/top_earlgrey.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.top_earlgrey 93.31 90.68 89.25 100.00



Module Instance : tb.dut.top_earlgrey

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.31 90.68 89.25 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.01 95.33 93.08 95.44 94.16 97.02


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
92.83 80.00 100.00 98.48 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
clk_ctrl_and_main_pd_sva_if 100.00 100.00
u_adc_ctrl_aon 100.00 100.00
u_aes 100.00 100.00
u_alert_handler 100.00 100.00
u_aon_timer_aon 100.00 100.00
u_clkmgr_aon 100.00 100.00
u_csrng 99.27 99.27
u_dft_tap_breakout 100.00 100.00 100.00
u_edn0 99.25 99.25
u_edn1 99.02 99.02
u_entropy_src 99.18 99.18
u_flash_ctrl 99.96 99.96
u_gpio 100.00 100.00
u_hmac 100.00 100.00
u_i2c0 93.10 93.10
u_i2c1 93.14 93.14
u_i2c2 93.14 93.14
u_keymgr 89.72 89.72
u_kmac 99.94 99.94
u_lc_ctrl 93.07 93.07
u_otbn 99.84 99.84
u_otp_ctrl 85.13 85.13
u_pattgen 100.00 100.00
u_pinmux_aon 96.81 96.13 94.67 98.85 95.10 99.30
u_pwm_aon 100.00 100.00
u_pwrmgr_aon 99.57 99.57
u_rom_ctrl 99.89 99.89
u_rstmgr_aon 100.00 100.00
u_rv_core_ibex 96.37 97.34 95.97 97.74 98.66 92.14
u_rv_dm 100.00 100.00
u_rv_plic 94.84 94.00 91.02 100.00 92.73 96.43
u_rv_timer 100.00 100.00
u_sensor_ctrl_aon 90.15 92.68 84.28 79.23 94.56 100.00
u_spi_device 96.39 96.39
u_spi_host0 96.59 96.59
u_spi_host1 96.30 96.30
u_sram_ctrl_main 99.65 99.65
u_sram_ctrl_ret_aon 99.64 99.64
u_sysrst_ctrl_aon 100.00 100.00
u_uart0 100.00 100.00
u_uart1 100.00 100.00
u_uart2 100.00 100.00
u_uart3 100.00 100.00
u_usbdev 94.12 94.12
u_xbar_main 100.00 100.00
u_xbar_peri 100.00 100.00

Line Coverage for Module : top_earlgrey
Line No.TotalCoveredPercent
TOTAL27925390.68
CONT_ASSIGN75811100.00
CONT_ASSIGN75911100.00
CONT_ASSIGN76011100.00
CONT_ASSIGN761100.00
CONT_ASSIGN762100.00
CONT_ASSIGN763100.00
CONT_ASSIGN764100.00
CONT_ASSIGN765100.00
CONT_ASSIGN77811100.00
CONT_ASSIGN779100.00
CONT_ASSIGN780100.00
CONT_ASSIGN781100.00
CONT_ASSIGN782100.00
CONT_ASSIGN783100.00
CONT_ASSIGN784100.00
CONT_ASSIGN785100.00
CONT_ASSIGN79911100.00
CONT_ASSIGN80111100.00
CONT_ASSIGN80311100.00
CONT_ASSIGN80511100.00
CONT_ASSIGN80711100.00
CONT_ASSIGN80911100.00
CONT_ASSIGN81311100.00
CONT_ASSIGN82311100.00
CONT_ASSIGN82411100.00
CONT_ASSIGN82811100.00
CONT_ASSIGN85211100.00
CONT_ASSIGN85311100.00
CONT_ASSIGN85511100.00
CONT_ASSIGN85611100.00
CONT_ASSIGN85811100.00
CONT_ASSIGN85911100.00
CONT_ASSIGN86111100.00
CONT_ASSIGN86211100.00
CONT_ASSIGN86411100.00
CONT_ASSIGN86511100.00
CONT_ASSIGN86711100.00
CONT_ASSIGN86811100.00
CONT_ASSIGN87011100.00
CONT_ASSIGN87111100.00
CONT_ASSIGN87311100.00
CONT_ASSIGN87411100.00
CONT_ASSIGN87611100.00
CONT_ASSIGN87711100.00
CONT_ASSIGN87911100.00
CONT_ASSIGN88011100.00
CONT_ASSIGN882100.00
CONT_ASSIGN88311100.00
CONT_ASSIGN885100.00
CONT_ASSIGN88611100.00
CONT_ASSIGN88811100.00
CONT_ASSIGN88911100.00
CONT_ASSIGN89111100.00
CONT_ASSIGN89211100.00
CONT_ASSIGN89411100.00
CONT_ASSIGN89511100.00
CONT_ASSIGN89711100.00
CONT_ASSIGN89811100.00
CONT_ASSIGN90011100.00
CONT_ASSIGN90111100.00
CONT_ASSIGN90311100.00
CONT_ASSIGN90411100.00
CONT_ASSIGN90611100.00
CONT_ASSIGN90711100.00
CONT_ASSIGN90911100.00
CONT_ASSIGN91011100.00
CONT_ASSIGN91211100.00
CONT_ASSIGN91311100.00
CONT_ASSIGN91511100.00
CONT_ASSIGN91611100.00
CONT_ASSIGN91811100.00
CONT_ASSIGN91911100.00
CONT_ASSIGN92111100.00
CONT_ASSIGN92211100.00
CONT_ASSIGN92800
CONT_ASSIGN93000
CONT_ASSIGN93200
CONT_ASSIGN93400
CONT_ASSIGN93600
CONT_ASSIGN93800
CONT_ASSIGN94000
CONT_ASSIGN94200
CONT_ASSIGN94400
CONT_ASSIGN94600
CONT_ASSIGN94800
CONT_ASSIGN95000
CONT_ASSIGN95200
CONT_ASSIGN95400
CONT_ASSIGN95600
CONT_ASSIGN95800
CONT_ASSIGN96000
CONT_ASSIGN96200
CONT_ASSIGN96400
CONT_ASSIGN96600
CONT_ASSIGN96800
CONT_ASSIGN97000
CONT_ASSIGN97200
CONT_ASSIGN97400
CONT_ASSIGN97600
CONT_ASSIGN97800
CONT_ASSIGN98000
CONT_ASSIGN98200
CONT_ASSIGN98400
CONT_ASSIGN98600
CONT_ASSIGN98800
CONT_ASSIGN99000
CONT_ASSIGN99200
CONT_ASSIGN99400
CONT_ASSIGN99600
CONT_ASSIGN99800
CONT_ASSIGN100000
CONT_ASSIGN100200
CONT_ASSIGN100400
CONT_ASSIGN100600
CONT_ASSIGN100800
CONT_ASSIGN101000
CONT_ASSIGN101200
CONT_ASSIGN101400
CONT_ASSIGN101600
CONT_ASSIGN101800
CONT_ASSIGN102000
CONT_ASSIGN266411100.00
CONT_ASSIGN306811100.00
CONT_ASSIGN306911100.00
CONT_ASSIGN307011100.00
CONT_ASSIGN307111100.00
CONT_ASSIGN307211100.00
CONT_ASSIGN307311100.00
CONT_ASSIGN307411100.00
CONT_ASSIGN307511100.00
CONT_ASSIGN307611100.00
CONT_ASSIGN307711100.00
CONT_ASSIGN307811100.00
CONT_ASSIGN307911100.00
CONT_ASSIGN308011100.00
CONT_ASSIGN308111100.00
CONT_ASSIGN308211100.00
CONT_ASSIGN308311100.00
CONT_ASSIGN308411100.00
CONT_ASSIGN308511100.00
CONT_ASSIGN308611100.00
CONT_ASSIGN308711100.00
CONT_ASSIGN308811100.00
CONT_ASSIGN308911100.00
CONT_ASSIGN309011100.00
CONT_ASSIGN309111100.00
CONT_ASSIGN309211100.00
CONT_ASSIGN309311100.00
CONT_ASSIGN309411100.00
CONT_ASSIGN309511100.00
CONT_ASSIGN309611100.00
CONT_ASSIGN309711100.00
CONT_ASSIGN309811100.00
CONT_ASSIGN309911100.00
CONT_ASSIGN310011100.00
CONT_ASSIGN310111100.00
CONT_ASSIGN310211100.00
CONT_ASSIGN310311100.00
CONT_ASSIGN310411100.00
CONT_ASSIGN310511100.00
CONT_ASSIGN310611100.00
CONT_ASSIGN310711100.00
CONT_ASSIGN310811100.00
CONT_ASSIGN310911100.00
CONT_ASSIGN311011100.00
CONT_ASSIGN311111100.00
CONT_ASSIGN311211100.00
CONT_ASSIGN311311100.00
CONT_ASSIGN311411100.00
CONT_ASSIGN311511100.00
CONT_ASSIGN311611100.00
CONT_ASSIGN311711100.00
CONT_ASSIGN311811100.00
CONT_ASSIGN311911100.00
CONT_ASSIGN312011100.00
CONT_ASSIGN312111100.00
CONT_ASSIGN312211100.00
CONT_ASSIGN312311100.00
CONT_ASSIGN312411100.00
CONT_ASSIGN312711100.00
CONT_ASSIGN312811100.00
CONT_ASSIGN312911100.00
CONT_ASSIGN313011100.00
CONT_ASSIGN313111100.00
CONT_ASSIGN313211100.00
CONT_ASSIGN313311100.00
CONT_ASSIGN313411100.00
CONT_ASSIGN313511100.00
CONT_ASSIGN313611100.00
CONT_ASSIGN313711100.00
CONT_ASSIGN313811100.00
CONT_ASSIGN313911100.00
CONT_ASSIGN314011100.00
CONT_ASSIGN314111100.00
CONT_ASSIGN314211100.00
CONT_ASSIGN314311100.00
CONT_ASSIGN314411100.00
CONT_ASSIGN314511100.00
CONT_ASSIGN314611100.00
CONT_ASSIGN314711100.00
CONT_ASSIGN314811100.00
CONT_ASSIGN314911100.00
CONT_ASSIGN315011100.00
CONT_ASSIGN315111100.00
CONT_ASSIGN315211100.00
CONT_ASSIGN315311100.00
CONT_ASSIGN315411100.00
CONT_ASSIGN315511100.00
CONT_ASSIGN315611100.00
CONT_ASSIGN315711100.00
CONT_ASSIGN315811100.00
CONT_ASSIGN315900
CONT_ASSIGN316000
CONT_ASSIGN316100
CONT_ASSIGN316200
CONT_ASSIGN316300
CONT_ASSIGN316400
CONT_ASSIGN316511100.00
CONT_ASSIGN3166100.00
CONT_ASSIGN3167100.00
CONT_ASSIGN3168100.00
CONT_ASSIGN316911100.00
CONT_ASSIGN317011100.00
CONT_ASSIGN317111100.00
CONT_ASSIGN317211100.00
CONT_ASSIGN317311100.00
CONT_ASSIGN317411100.00
CONT_ASSIGN317511100.00
CONT_ASSIGN317611100.00
CONT_ASSIGN317711100.00
CONT_ASSIGN317811100.00
CONT_ASSIGN3179100.00
CONT_ASSIGN318000
CONT_ASSIGN318100
CONT_ASSIGN318200
CONT_ASSIGN318300
CONT_ASSIGN318400
CONT_ASSIGN318500
CONT_ASSIGN318600
CONT_ASSIGN318700
CONT_ASSIGN318800
CONT_ASSIGN318911100.00
CONT_ASSIGN319011100.00
CONT_ASSIGN319111100.00
CONT_ASSIGN319211100.00
CONT_ASSIGN319311100.00
CONT_ASSIGN319411100.00
CONT_ASSIGN3195100.00
CONT_ASSIGN319611100.00
CONT_ASSIGN319711100.00
CONT_ASSIGN319811100.00
CONT_ASSIGN319911100.00
CONT_ASSIGN320011100.00
CONT_ASSIGN320111100.00
CONT_ASSIGN320411100.00
CONT_ASSIGN320511100.00
CONT_ASSIGN320611100.00
CONT_ASSIGN320711100.00
CONT_ASSIGN320811100.00
CONT_ASSIGN320911100.00
CONT_ASSIGN321011100.00
CONT_ASSIGN321111100.00
CONT_ASSIGN321211100.00
CONT_ASSIGN321311100.00
CONT_ASSIGN321411100.00
CONT_ASSIGN321511100.00
CONT_ASSIGN321611100.00
CONT_ASSIGN321711100.00
CONT_ASSIGN321811100.00
CONT_ASSIGN321911100.00
CONT_ASSIGN322011100.00
CONT_ASSIGN322111100.00
CONT_ASSIGN322211100.00
CONT_ASSIGN322311100.00
CONT_ASSIGN322411100.00
CONT_ASSIGN322511100.00
CONT_ASSIGN322611100.00
CONT_ASSIGN322711100.00
CONT_ASSIGN322811100.00
CONT_ASSIGN322911100.00
CONT_ASSIGN323011100.00
CONT_ASSIGN323111100.00
CONT_ASSIGN323211100.00
CONT_ASSIGN323311100.00
CONT_ASSIGN323411100.00
CONT_ASSIGN323511100.00
CONT_ASSIGN323611100.00
CONT_ASSIGN323711100.00
CONT_ASSIGN323811100.00
CONT_ASSIGN323911100.00
CONT_ASSIGN324011100.00
CONT_ASSIGN324111100.00
CONT_ASSIGN324211100.00
CONT_ASSIGN3243100.00
CONT_ASSIGN3244100.00
CONT_ASSIGN3245100.00
CONT_ASSIGN324600
CONT_ASSIGN324700
CONT_ASSIGN324800
CONT_ASSIGN324900
CONT_ASSIGN325000
CONT_ASSIGN325100
CONT_ASSIGN325200
CONT_ASSIGN325300
CONT_ASSIGN325411100.00
CONT_ASSIGN325511100.00
CONT_ASSIGN3256100.00
CONT_ASSIGN325700
CONT_ASSIGN325800
CONT_ASSIGN325900
CONT_ASSIGN326000
CONT_ASSIGN326100
CONT_ASSIGN326200
CONT_ASSIGN326300
CONT_ASSIGN326400
CONT_ASSIGN326500
CONT_ASSIGN326600
CONT_ASSIGN326700
CONT_ASSIGN326800
CONT_ASSIGN326900
CONT_ASSIGN327000
CONT_ASSIGN327100
CONT_ASSIGN327211100.00
CONT_ASSIGN327300
CONT_ASSIGN327400
CONT_ASSIGN327500
CONT_ASSIGN327600
CONT_ASSIGN327700
CONT_ASSIGN327800
CONT_ASSIGN328211100.00
CONT_ASSIGN328311100.00
CONT_ASSIGN328411100.00
CONT_ASSIGN328511100.00
CONT_ASSIGN328611100.00
CONT_ASSIGN328711100.00
CONT_ASSIGN328811100.00
CONT_ASSIGN328911100.00
CONT_ASSIGN329011100.00
CONT_ASSIGN329111100.00
CONT_ASSIGN329211100.00
CONT_ASSIGN329311100.00
CONT_ASSIGN329411100.00
CONT_ASSIGN329511100.00
CONT_ASSIGN329611100.00
CONT_ASSIGN329911100.00
CONT_ASSIGN330011100.00
CONT_ASSIGN330111100.00
CONT_ASSIGN330211100.00
CONT_ASSIGN330311100.00
CONT_ASSIGN330411100.00
CONT_ASSIGN330511100.00
CONT_ASSIGN330611100.00
CONT_ASSIGN330711100.00
CONT_ASSIGN330811100.00
CONT_ASSIGN330911100.00
CONT_ASSIGN331011100.00
CONT_ASSIGN331311100.00
CONT_ASSIGN331411100.00
CONT_ASSIGN331711100.00
CONT_ASSIGN331811100.00
CONT_ASSIGN331911100.00
CONT_ASSIGN3320100.00
CONT_ASSIGN3321100.00
CONT_ASSIGN3322100.00
CONT_ASSIGN332311100.00
CONT_ASSIGN332411100.00
CONT_ASSIGN332511100.00
CONT_ASSIGN332611100.00
CONT_ASSIGN332700
CONT_ASSIGN332800
CONT_ASSIGN333111100.00
CONT_ASSIGN333211100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_systems_top_earlgrey_0.1/rtl/autogen/top_earlgrey.sv' or '../src/lowrisc_systems_top_earlgrey_0.1/rtl/autogen/top_earlgrey.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
758 1 1
759 1 1
760 1 1
761 0 1
762 0 1
763 0 1
764 0 1
765 0 1
778 1 1
779 0 1
780 0 1
781 0 1
782 0 1
783 0 1
784 0 1
785 0 1
799 1 1
801 1 1
803 1 1
805 1 1
807 1 1
809 1 1
813 1 1
823 1 1
824 1 1
828 1 1
852 1 1
853 1 1
855 1 1
856 1 1
858 1 1
859 1 1
861 1 1
862 1 1
864 1 1
865 1 1
867 1 1
868 1 1
870 1 1
871 1 1
873 1 1
874 1 1
876 1 1
877 1 1
879 1 1
880 1 1
882 0 1
883 1 1
885 0 1
886 1 1
888 1 1
889 1 1
891 1 1
892 1 1
894 1 1
895 1 1
897 1 1
898 1 1
900 1 1
901 1 1
903 1 1
904 1 1
906 1 1
907 1 1
909 1 1
910 1 1
912 1 1
913 1 1
915 1 1
916 1 1
918 1 1
919 1 1
921 1 1
922 1 1
928 unreachable
930 unreachable
932 unreachable
934 unreachable
936 unreachable
938 unreachable
940 unreachable
942 unreachable
944 unreachable
946 unreachable
948 unreachable
950 unreachable
952 unreachable
954 unreachable
956 unreachable
958 unreachable
960 unreachable
962 unreachable
964 unreachable
966 unreachable
968 unreachable
970 unreachable
972 unreachable
974 unreachable
976 unreachable
978 unreachable
980 unreachable
982 unreachable
984 unreachable
986 unreachable
988 unreachable
990 unreachable
992 unreachable
994 unreachable
996 unreachable
998 unreachable
1000 unreachable
1002 unreachable
1004 unreachable
1006 unreachable
1008 unreachable
1010 unreachable
1012 unreachable
1014 unreachable
1016 unreachable
1018 unreachable
1020 unreachable
2664 1 1
3068 1 1
3069 1 1
3070 1 1
3071 1 1
3072 1 1
3073 1 1
3074 1 1
3075 1 1
3076 1 1
3077 1 1
3078 1 1
3079 1 1
3080 1 1
3081 1 1
3082 1 1
3083 1 1
3084 1 1
3085 1 1
3086 1 1
3087 1 1
3088 1 1
3089 1 1
3090 1 1
3091 1 1
3092 1 1
3093 1 1
3094 1 1
3095 1 1
3096 1 1
3097 1 1
3098 1 1
3099 1 1
3100 1 1
3101 1 1
3102 1 1
3103 1 1
3104 1 1
3105 1 1
3106 1 1
3107 1 1
3108 1 1
3109 1 1
3110 1 1
3111 1 1
3112 1 1
3113 1 1
3114 1 1
3115 1 1
3116 1 1
3117 1 1
3118 1 1
3119 1 1
3120 1 1
3121 1 1
3122 1 1
3123 1 1
3124 1 1
3127 1 1
3128 1 1
3129 1 1
3130 1 1
3131 1 1
3132 1 1
3133 1 1
3134 1 1
3135 1 1
3136 1 1
3137 1 1
3138 1 1
3139 1 1
3140 1 1
3141 1 1
3142 1 1
3143 1 1
3144 1 1
3145 1 1
3146 1 1
3147 1 1
3148 1 1
3149 1 1
3150 1 1
3151 1 1
3152 1 1
3153 1 1
3154 1 1
3155 1 1
3156 1 1
3157 1 1
3158 1 1
3159 unreachable
3160 unreachable
3161 unreachable
3162 unreachable
3163 unreachable
3164 unreachable
3165 1 1
3166 0 1
3167 0 1
3168 0 1
3169 1 1
3170 1 1
3171 1 1
3172 1 1
3173 1 1
3174 1 1
3175 1 1
3176 1 1
3177 1 1
3178 1 1
3179 0 1
3180 unreachable
3181 unreachable
3182 unreachable
3183 unreachable
3184 unreachable
3185 unreachable
3186 unreachable
3187 unreachable
3188 unreachable
3189 1 1
3190 1 1
3191 1 1
3192 1 1
3193 1 1
3194 1 1
3195 0 1
3196 1 1
3197 1 1
3198 1 1
3199 1 1
3200 1 1
3201 1 1
3204 1 1
3205 1 1
3206 1 1
3207 1 1
3208 1 1
3209 1 1
3210 1 1
3211 1 1
3212 1 1
3213 1 1
3214 1 1
3215 1 1
3216 1 1
3217 1 1
3218 1 1
3219 1 1
3220 1 1
3221 1 1
3222 1 1
3223 1 1
3224 1 1
3225 1 1
3226 1 1
3227 1 1
3228 1 1
3229 1 1
3230 1 1
3231 1 1
3232 1 1
3233 1 1
3234 1 1
3235 1 1
3236 1 1
3237 1 1
3238 1 1
3239 1 1
3240 1 1
3241 1 1
3242 1 1
3243 0 1
3244 0 1
3245 0 1
3246 unreachable
3247 unreachable
3248 unreachable
3249 unreachable
3250 unreachable
3251 unreachable
3252 unreachable
3253 unreachable
3254 1 1
3255 1 1
3256 0 1
3257 unreachable
3258 unreachable
3259 unreachable
3260 unreachable
3261 unreachable
3262 unreachable
3263 unreachable
3264 unreachable
3265 unreachable
3266 unreachable
3267 unreachable
3268 unreachable
3269 unreachable
3270 unreachable
3271 unreachable
3272 1 1
3273 unreachable
3274 unreachable
3275 unreachable
3276 unreachable
3277 unreachable
3278 unreachable
3282 1 1
3283 1 1
3284 1 1
3285 1 1
3286 1 1
3287 1 1
3288 1 1
3289 1 1
3290 1 1
3291 1 1
3292 1 1
3293 1 1
3294 1 1
3295 1 1
3296 1 1
3299 1 1
3300 1 1
3301 1 1
3302 1 1
3303 1 1
3304 1 1
3305 1 1
3306 1 1
3307 1 1
3308 1 1
3309 1 1
3310 1 1
3313 1 1
3314 1 1
3317 1 1
3318 1 1
3319 1 1
3320 0 1
3321 0 1
3322 0 1
3323 1 1
3324 1 1
3325 1 1
3326 1 1
3327 unreachable
3328 unreachable
3331 1 1
3332 1 1


Toggle Coverage for Module : top_earlgrey
TotalCoveredPercent
Totals 900 500 55.56
Total Bits 3194 1909 59.77
Total Bits 0->1 1597 958 59.99
Total Bits 1->0 1597 951 59.55

Ports 900 500 55.56
Port Bits 3194 1909 59.77
Port Bits 0->1 1597 958 59.99
Port Bits 1->0 1597 951 59.55

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
mio_in_i[46:0] Yes Yes T16,T27,T28 Yes T16,T27,T28 INPUT
mio_out_o[46:0] Yes Yes T28,T36,T37 Yes T28,T22,T36 OUTPUT
mio_oe_o[46:0] Yes Yes T37,T38,T39 Yes T21,T28,T22 OUTPUT
dio_in_i[15:0] Yes Yes T29,T21,T22 Yes T29,T21,T22 INPUT
dio_out_o[11:0] Yes Yes *T29,*T21,*T30 Yes T29,T30,T1 OUTPUT
dio_out_o[13:12] No No No OUTPUT
dio_out_o[15:14] Yes Yes T24,T25,T26 Yes T24,T25,T26 OUTPUT
dio_oe_o[15:0] Yes Yes T29,T34,T35 Yes T29,T34,T35 OUTPUT
mio_attr_o[0].invert Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[0].virt_od_en Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[0].pull_en Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[0].pull_select Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[0].keep_en No No No OUTPUT
mio_attr_o[0].schmitt_en No No No OUTPUT
mio_attr_o[0].od_en No No No OUTPUT
mio_attr_o[0].input_disable Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[0].slew_rate[1:0] No No No OUTPUT
mio_attr_o[0].drive_strength[0] Yes Yes *T40,*T41,*T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[0].drive_strength[3:1] No No No OUTPUT
mio_attr_o[1].invert Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[1].virt_od_en Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[1].pull_en Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[1].pull_select Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[1].keep_en No No No OUTPUT
mio_attr_o[1].schmitt_en No No No OUTPUT
mio_attr_o[1].od_en No No No OUTPUT
mio_attr_o[1].input_disable Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[1].slew_rate[1:0] No No No OUTPUT
mio_attr_o[1].drive_strength[0] Yes Yes *T40,*T41,*T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[1].drive_strength[3:1] No No No OUTPUT
mio_attr_o[2].invert Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[2].virt_od_en Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[2].pull_en Yes Yes T40,T41,T42 Yes T45,T46,T47 OUTPUT
mio_attr_o[2].pull_select Yes Yes T40,T41,T42 Yes T45,T46,T47 OUTPUT
mio_attr_o[2].keep_en No No No OUTPUT
mio_attr_o[2].schmitt_en No No No OUTPUT
mio_attr_o[2].od_en No No No OUTPUT
mio_attr_o[2].input_disable Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[2].slew_rate[1:0] No No No OUTPUT
mio_attr_o[2].drive_strength[0] Yes Yes *T40,*T41,*T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[2].drive_strength[3:1] No No No OUTPUT
mio_attr_o[3].invert Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[3].virt_od_en Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[3].pull_en Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[3].pull_select Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[3].keep_en No No No OUTPUT
mio_attr_o[3].schmitt_en No No No OUTPUT
mio_attr_o[3].od_en No No No OUTPUT
mio_attr_o[3].input_disable Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[3].slew_rate[1:0] No No No OUTPUT
mio_attr_o[3].drive_strength[0] Yes Yes *T40,*T41,*T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[3].drive_strength[3:1] No No No OUTPUT
mio_attr_o[4].invert Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[4].virt_od_en Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[4].pull_en Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[4].pull_select Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[4].keep_en No No No OUTPUT
mio_attr_o[4].schmitt_en No No No OUTPUT
mio_attr_o[4].od_en No No No OUTPUT
mio_attr_o[4].input_disable Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[4].slew_rate[1:0] No No No OUTPUT
mio_attr_o[4].drive_strength[0] Yes Yes *T40,*T41,*T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[4].drive_strength[3:1] No No No OUTPUT
mio_attr_o[5].invert Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[5].virt_od_en Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[5].pull_en Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[5].pull_select Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[5].keep_en No No No OUTPUT
mio_attr_o[5].schmitt_en No No No OUTPUT
mio_attr_o[5].od_en No No No OUTPUT
mio_attr_o[5].input_disable Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[5].slew_rate[1:0] No No No OUTPUT
mio_attr_o[5].drive_strength[0] Yes Yes *T40,*T41,*T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[5].drive_strength[3:1] No No No OUTPUT
mio_attr_o[6].invert Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[6].virt_od_en Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[6].pull_en Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[6].pull_select Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[6].keep_en No No No OUTPUT
mio_attr_o[6].schmitt_en No No No OUTPUT
mio_attr_o[6].od_en No No No OUTPUT
mio_attr_o[6].input_disable Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[6].slew_rate[1:0] No No No OUTPUT
mio_attr_o[6].drive_strength[0] Yes Yes *T40,*T41,*T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[6].drive_strength[3:1] No No No OUTPUT
mio_attr_o[7].invert Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[7].virt_od_en Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[7].pull_en Yes Yes T40,T41,T42 Yes T51,T52,T53 OUTPUT
mio_attr_o[7].pull_select Yes Yes T40,T41,T42 Yes T51,T52,T53 OUTPUT
mio_attr_o[7].keep_en No No No OUTPUT
mio_attr_o[7].schmitt_en No No No OUTPUT
mio_attr_o[7].od_en No No No OUTPUT
mio_attr_o[7].input_disable Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[7].slew_rate[1:0] No No No OUTPUT
mio_attr_o[7].drive_strength[0] Yes Yes *T40,*T41,*T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[7].drive_strength[3:1] No No No OUTPUT
mio_attr_o[8].invert Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[8].virt_od_en Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[8].pull_en Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[8].pull_select Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[8].keep_en No No No OUTPUT
mio_attr_o[8].schmitt_en No No No OUTPUT
mio_attr_o[8].od_en No No No OUTPUT
mio_attr_o[8].input_disable Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[8].slew_rate[1:0] No No No OUTPUT
mio_attr_o[8].drive_strength[0] Yes Yes *T40,*T41,*T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[8].drive_strength[3:1] No No No OUTPUT
mio_attr_o[9].invert Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[9].virt_od_en Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[9].pull_en Yes Yes T40,T41,T42 Yes T45,T46,T47 OUTPUT
mio_attr_o[9].pull_select Yes Yes T40,T41,T42 Yes T45,T46,T47 OUTPUT
mio_attr_o[9].keep_en No No No OUTPUT
mio_attr_o[9].schmitt_en No No No OUTPUT
mio_attr_o[9].od_en No No No OUTPUT
mio_attr_o[9].input_disable Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[9].slew_rate[1:0] No No No OUTPUT
mio_attr_o[9].drive_strength[0] Yes Yes *T40,*T41,*T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[9].drive_strength[3:1] No No No OUTPUT
mio_attr_o[10].invert Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[10].virt_od_en Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[10].pull_en Yes Yes T40,T41,T42 Yes T45,T24,T25 OUTPUT
mio_attr_o[10].pull_select Yes Yes T40,T41,T42 Yes T45,T24,T25 OUTPUT
mio_attr_o[10].keep_en No No No OUTPUT
mio_attr_o[10].schmitt_en No No No OUTPUT
mio_attr_o[10].od_en No No No OUTPUT
mio_attr_o[10].input_disable Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[10].slew_rate[1:0] No No No OUTPUT
mio_attr_o[10].drive_strength[0] Yes Yes *T40,*T41,*T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[10].drive_strength[3:1] No No No OUTPUT
mio_attr_o[11].invert Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[11].virt_od_en Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[11].pull_en Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[11].pull_select Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[11].keep_en No No No OUTPUT
mio_attr_o[11].schmitt_en No No No OUTPUT
mio_attr_o[11].od_en No No No OUTPUT
mio_attr_o[11].input_disable Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[11].slew_rate[1:0] No No No OUTPUT
mio_attr_o[11].drive_strength[0] Yes Yes *T40,*T41,*T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[11].drive_strength[3:1] No No No OUTPUT
mio_attr_o[12].invert Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[12].virt_od_en Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[12].pull_en Yes Yes T40,T41,T42 Yes T45,T24,T25 OUTPUT
mio_attr_o[12].pull_select Yes Yes T40,T41,T42 Yes T45,T24,T25 OUTPUT
mio_attr_o[12].keep_en No No No OUTPUT
mio_attr_o[12].schmitt_en No No No OUTPUT
mio_attr_o[12].od_en No No No OUTPUT
mio_attr_o[12].input_disable Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[12].slew_rate[1:0] No No No OUTPUT
mio_attr_o[12].drive_strength[0] Yes Yes *T40,*T41,*T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[12].drive_strength[3:1] No No No OUTPUT
mio_attr_o[13].invert Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[13].virt_od_en Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[13].pull_en Yes Yes T40,T41,T42 Yes T45,T46,T47 OUTPUT
mio_attr_o[13].pull_select Yes Yes T40,T41,T42 Yes T45,T46,T47 OUTPUT
mio_attr_o[13].keep_en No No No OUTPUT
mio_attr_o[13].schmitt_en No No No OUTPUT
mio_attr_o[13].od_en No No No OUTPUT
mio_attr_o[13].input_disable Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[13].slew_rate[1:0] No No No OUTPUT
mio_attr_o[13].drive_strength[0] Yes Yes *T40,*T41,*T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[13].drive_strength[3:1] No No No OUTPUT
mio_attr_o[14].invert Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[14].virt_od_en Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[14].pull_en Yes Yes T40,T41,T42 Yes T45,T46,T47 OUTPUT
mio_attr_o[14].pull_select Yes Yes T40,T41,T42 Yes T45,T46,T47 OUTPUT
mio_attr_o[14].keep_en No No No OUTPUT
mio_attr_o[14].schmitt_en No No No OUTPUT
mio_attr_o[14].od_en No No No OUTPUT
mio_attr_o[14].input_disable Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[14].slew_rate[1:0] No No No OUTPUT
mio_attr_o[14].drive_strength[0] Yes Yes *T40,*T41,*T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[14].drive_strength[3:1] No No No OUTPUT
mio_attr_o[15].invert Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[15].virt_od_en Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[15].pull_en Yes Yes T40,T41,T42 Yes T45,T46,T47 OUTPUT
mio_attr_o[15].pull_select Yes Yes T40,T41,T42 Yes T45,T46,T47 OUTPUT
mio_attr_o[15].keep_en No No No OUTPUT
mio_attr_o[15].schmitt_en No No No OUTPUT
mio_attr_o[15].od_en No No No OUTPUT
mio_attr_o[15].input_disable Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[15].slew_rate[1:0] No No No OUTPUT
mio_attr_o[15].drive_strength[0] Yes Yes *T40,*T41,*T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[15].drive_strength[3:1] No No No OUTPUT
mio_attr_o[16].invert Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[16].virt_od_en Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[16].pull_en Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[16].pull_select Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[16].keep_en No No No OUTPUT
mio_attr_o[16].schmitt_en No No No OUTPUT
mio_attr_o[16].od_en No No No OUTPUT
mio_attr_o[16].input_disable Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[16].slew_rate[1:0] No No No OUTPUT
mio_attr_o[16].drive_strength[0] Yes Yes *T40,*T41,*T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[16].drive_strength[3:1] No No No OUTPUT
mio_attr_o[17].invert Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[17].virt_od_en Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[17].pull_en Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[17].pull_select Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[17].keep_en No No No OUTPUT
mio_attr_o[17].schmitt_en No No No OUTPUT
mio_attr_o[17].od_en No No No OUTPUT
mio_attr_o[17].input_disable Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[17].slew_rate[1:0] No No No OUTPUT
mio_attr_o[17].drive_strength[0] Yes Yes *T40,*T41,*T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[17].drive_strength[3:1] No No No OUTPUT
mio_attr_o[18].invert Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[18].virt_od_en Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[18].pull_en Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[18].pull_select Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[18].keep_en No No No OUTPUT
mio_attr_o[18].schmitt_en No No No OUTPUT
mio_attr_o[18].od_en No No No OUTPUT
mio_attr_o[18].input_disable Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[18].slew_rate[1:0] No No No OUTPUT
mio_attr_o[18].drive_strength[0] Yes Yes *T40,*T41,*T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[18].drive_strength[3:1] No No No OUTPUT
mio_attr_o[19].invert Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[19].virt_od_en Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[19].pull_en Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[19].pull_select Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[19].keep_en No No No OUTPUT
mio_attr_o[19].schmitt_en No No No OUTPUT
mio_attr_o[19].od_en No No No OUTPUT
mio_attr_o[19].input_disable Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[19].slew_rate[1:0] No No No OUTPUT
mio_attr_o[19].drive_strength[0] Yes Yes *T40,*T41,*T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[19].drive_strength[3:1] No No No OUTPUT
mio_attr_o[20].invert Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[20].virt_od_en Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[20].pull_en Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[20].pull_select Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[20].keep_en No No No OUTPUT
mio_attr_o[20].schmitt_en No No No OUTPUT
mio_attr_o[20].od_en No No No OUTPUT
mio_attr_o[20].input_disable Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[20].slew_rate[1:0] No No No OUTPUT
mio_attr_o[20].drive_strength[0] Yes Yes *T40,*T41,*T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[20].drive_strength[3:1] No No No OUTPUT
mio_attr_o[21].invert Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[21].virt_od_en Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[21].pull_en Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[21].pull_select Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[21].keep_en No No No OUTPUT
mio_attr_o[21].schmitt_en No No No OUTPUT
mio_attr_o[21].od_en No No No OUTPUT
mio_attr_o[21].input_disable Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[21].slew_rate[1:0] No No No OUTPUT
mio_attr_o[21].drive_strength[0] Yes Yes *T40,*T41,*T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[21].drive_strength[3:1] No No No OUTPUT
mio_attr_o[22].invert Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[22].virt_od_en Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[22].pull_en Yes Yes T54,T55,T56 Yes T4,T6,T57 OUTPUT
mio_attr_o[22].pull_select Yes Yes T4,T6,T57 Yes T4,T6,T57 OUTPUT
mio_attr_o[22].keep_en No No No OUTPUT
mio_attr_o[22].schmitt_en No No No OUTPUT
mio_attr_o[22].od_en No No No OUTPUT
mio_attr_o[22].input_disable Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[22].slew_rate[1:0] No No No OUTPUT
mio_attr_o[22].drive_strength[0] Yes Yes *T40,*T41,*T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[22].drive_strength[3:1] No No No OUTPUT
mio_attr_o[23].invert Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[23].virt_od_en Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[23].pull_en Yes Yes T54,T55,T56 Yes T4,T6,T57 OUTPUT
mio_attr_o[23].pull_select Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[23].keep_en No No No OUTPUT
mio_attr_o[23].schmitt_en No No No OUTPUT
mio_attr_o[23].od_en No No No OUTPUT
mio_attr_o[23].input_disable Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[23].slew_rate[1:0] No No No OUTPUT
mio_attr_o[23].drive_strength[0] Yes Yes *T40,*T41,*T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[23].drive_strength[3:1] No No No OUTPUT
mio_attr_o[24].invert Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[24].virt_od_en Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[24].pull_en Yes Yes T54,T55,T56 Yes T4,T6,T57 OUTPUT
mio_attr_o[24].pull_select Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[24].keep_en No No No OUTPUT
mio_attr_o[24].schmitt_en No No No OUTPUT
mio_attr_o[24].od_en No No No OUTPUT
mio_attr_o[24].input_disable Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[24].slew_rate[1:0] No No No OUTPUT
mio_attr_o[24].drive_strength[0] Yes Yes *T40,*T41,*T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[24].drive_strength[3:1] No No No OUTPUT
mio_attr_o[25].invert Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[25].virt_od_en Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[25].pull_en Yes Yes T5,T43,T19 Yes T5,T43,T44 OUTPUT
mio_attr_o[25].pull_select Yes Yes T5,T43,T19 Yes T5,T43,T44 OUTPUT
mio_attr_o[25].keep_en No No No OUTPUT
mio_attr_o[25].schmitt_en No No No OUTPUT
mio_attr_o[25].od_en No No No OUTPUT
mio_attr_o[25].input_disable Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[25].slew_rate[1:0] No No No OUTPUT
mio_attr_o[25].drive_strength[0] Yes Yes *T40,*T41,*T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[25].drive_strength[3:1] No No No OUTPUT
mio_attr_o[26].invert Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[26].virt_od_en Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[26].pull_en Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[26].pull_select Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[26].keep_en No No No OUTPUT
mio_attr_o[26].schmitt_en No No No OUTPUT
mio_attr_o[26].od_en No No No OUTPUT
mio_attr_o[26].input_disable Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[26].slew_rate[1:0] No No No OUTPUT
mio_attr_o[26].drive_strength[0] Yes Yes *T40,*T41,*T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[26].drive_strength[3:1] No No No OUTPUT
mio_attr_o[27].invert Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[27].virt_od_en Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[27].pull_en Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[27].pull_select Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[27].keep_en No No No OUTPUT
mio_attr_o[27].schmitt_en No No No OUTPUT
mio_attr_o[27].od_en No No No OUTPUT
mio_attr_o[27].input_disable Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[27].slew_rate[1:0] No No No OUTPUT
mio_attr_o[27].drive_strength[0] Yes Yes *T40,*T41,*T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[27].drive_strength[3:1] No No No OUTPUT
mio_attr_o[28].invert Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[28].virt_od_en Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[28].pull_en Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[28].pull_select Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[28].keep_en No No No OUTPUT
mio_attr_o[28].schmitt_en No No No OUTPUT
mio_attr_o[28].od_en No No No OUTPUT
mio_attr_o[28].input_disable Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[28].slew_rate[1:0] No No No OUTPUT
mio_attr_o[28].drive_strength[0] Yes Yes *T40,*T41,*T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[28].drive_strength[3:1] No No No OUTPUT
mio_attr_o[29].invert Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[29].virt_od_en Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[29].pull_en Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[29].pull_select Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[29].keep_en No No No OUTPUT
mio_attr_o[29].schmitt_en No No No OUTPUT
mio_attr_o[29].od_en No No No OUTPUT
mio_attr_o[29].input_disable Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[29].slew_rate[1:0] No No No OUTPUT
mio_attr_o[29].drive_strength[0] Yes Yes *T40,*T41,*T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[29].drive_strength[3:1] No No No OUTPUT
mio_attr_o[30].invert Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[30].virt_od_en Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[30].pull_en Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[30].pull_select Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[30].keep_en No No No OUTPUT
mio_attr_o[30].schmitt_en No No No OUTPUT
mio_attr_o[30].od_en No No No OUTPUT
mio_attr_o[30].input_disable Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[30].slew_rate[1:0] No No No OUTPUT
mio_attr_o[30].drive_strength[0] Yes Yes *T40,*T41,*T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[30].drive_strength[3:1] No No No OUTPUT
mio_attr_o[31].invert Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[31].virt_od_en Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[31].pull_en Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[31].pull_select Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[31].keep_en No No No OUTPUT
mio_attr_o[31].schmitt_en No No No OUTPUT
mio_attr_o[31].od_en No No No OUTPUT
mio_attr_o[31].input_disable Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[31].slew_rate[1:0] No No No OUTPUT
mio_attr_o[31].drive_strength[0] Yes Yes *T40,*T41,*T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[31].drive_strength[3:1] No No No OUTPUT
mio_attr_o[32].invert Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[32].virt_od_en Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[32].pull_en Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[32].pull_select Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[32].keep_en No No No OUTPUT
mio_attr_o[32].schmitt_en No No No OUTPUT
mio_attr_o[32].od_en No No No OUTPUT
mio_attr_o[32].input_disable Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[32].slew_rate[1:0] No No No OUTPUT
mio_attr_o[32].drive_strength[0] Yes Yes *T40,*T41,*T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[32].drive_strength[3:1] No No No OUTPUT
mio_attr_o[33].invert Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[33].virt_od_en Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[33].pull_en Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[33].pull_select Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[33].keep_en No No No OUTPUT
mio_attr_o[33].schmitt_en No No No OUTPUT
mio_attr_o[33].od_en No No No OUTPUT
mio_attr_o[33].input_disable Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[33].slew_rate[1:0] No No No OUTPUT
mio_attr_o[33].drive_strength[0] Yes Yes *T40,*T41,*T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[33].drive_strength[3:1] No No No OUTPUT
mio_attr_o[34].invert Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[34].virt_od_en Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[34].pull_en Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[34].pull_select Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[34].keep_en No No No OUTPUT
mio_attr_o[34].schmitt_en No No No OUTPUT
mio_attr_o[34].od_en No No No OUTPUT
mio_attr_o[34].input_disable Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[34].slew_rate[1:0] No No No OUTPUT
mio_attr_o[34].drive_strength[0] Yes Yes *T40,*T41,*T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[34].drive_strength[3:1] No No No OUTPUT
mio_attr_o[35].invert Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[35].virt_od_en Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[35].pull_en Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[35].pull_select Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[35].keep_en No No No OUTPUT
mio_attr_o[35].schmitt_en No No No OUTPUT
mio_attr_o[35].od_en No No No OUTPUT
mio_attr_o[35].input_disable Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[35].slew_rate[1:0] No No No OUTPUT
mio_attr_o[35].drive_strength[0] Yes Yes *T40,*T41,*T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[35].drive_strength[3:1] No No No OUTPUT
mio_attr_o[36].invert Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[36].virt_od_en Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[36].pull_en Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[36].pull_select Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[36].keep_en No No No OUTPUT
mio_attr_o[36].schmitt_en No No No OUTPUT
mio_attr_o[36].od_en No No No OUTPUT
mio_attr_o[36].input_disable Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[36].slew_rate[1:0] No No No OUTPUT
mio_attr_o[36].drive_strength[0] Yes Yes *T40,*T41,*T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[36].drive_strength[3:1] No No No OUTPUT
mio_attr_o[37].invert Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[37].virt_od_en Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[37].pull_en Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[37].pull_select Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[37].keep_en No No No OUTPUT
mio_attr_o[37].schmitt_en No No No OUTPUT
mio_attr_o[37].od_en No No No OUTPUT
mio_attr_o[37].input_disable Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[37].slew_rate[1:0] No No No OUTPUT
mio_attr_o[37].drive_strength[0] Yes Yes *T40,*T41,*T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[37].drive_strength[3:1] No No No OUTPUT
mio_attr_o[38].invert Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[38].virt_od_en Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[38].pull_en Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[38].pull_select Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[38].keep_en No No No OUTPUT
mio_attr_o[38].schmitt_en Yes Yes T5,T20,T58 Yes T5,T44,T20 OUTPUT
mio_attr_o[38].od_en No No No OUTPUT
mio_attr_o[38].input_disable Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[38].slew_rate[1:0] No No No OUTPUT
mio_attr_o[38].drive_strength[0] Yes Yes *T40,*T41,*T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[38].drive_strength[3:1] No No No OUTPUT
mio_attr_o[39].invert Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[39].virt_od_en Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[39].pull_en Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[39].pull_select Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[39].keep_en No No No OUTPUT
mio_attr_o[39].schmitt_en Yes Yes T5,T20,T58 Yes T5,T44,T20 OUTPUT
mio_attr_o[39].od_en No No No OUTPUT
mio_attr_o[39].input_disable Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[39].slew_rate[1:0] No No No OUTPUT
mio_attr_o[39].drive_strength[0] Yes Yes *T40,*T41,*T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[39].drive_strength[3:1] No No No OUTPUT
mio_attr_o[40].invert Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[40].virt_od_en Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[40].pull_en Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[40].pull_select Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[40].keep_en No No No OUTPUT
mio_attr_o[40].schmitt_en No No No OUTPUT
mio_attr_o[40].od_en No No No OUTPUT
mio_attr_o[40].input_disable Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[40].slew_rate[1:0] No No No OUTPUT
mio_attr_o[40].drive_strength[0] Yes Yes *T40,*T41,*T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[40].drive_strength[3:1] No No No OUTPUT
mio_attr_o[41].invert Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[41].virt_od_en Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[41].pull_en Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[41].pull_select Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[41].keep_en No No No OUTPUT
mio_attr_o[41].schmitt_en No No No OUTPUT
mio_attr_o[41].od_en No No No OUTPUT
mio_attr_o[41].input_disable Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[41].slew_rate[1:0] No No No OUTPUT
mio_attr_o[41].drive_strength[0] Yes Yes *T40,*T41,*T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[41].drive_strength[3:1] No No No OUTPUT
mio_attr_o[42].invert Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[42].virt_od_en Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[42].pull_en Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[42].pull_select Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[42].keep_en No No No OUTPUT
mio_attr_o[42].schmitt_en No No No OUTPUT
mio_attr_o[42].od_en No No No OUTPUT
mio_attr_o[42].input_disable Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[42].slew_rate[1:0] No No No OUTPUT
mio_attr_o[42].drive_strength[0] Yes Yes *T40,*T41,*T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[42].drive_strength[3:1] No No No OUTPUT
mio_attr_o[43].invert Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[43].virt_od_en Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[43].pull_en Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[43].pull_select Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[43].keep_en No No No OUTPUT
mio_attr_o[43].schmitt_en No No No OUTPUT
mio_attr_o[43].od_en No No No OUTPUT
mio_attr_o[43].input_disable Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[43].slew_rate[1:0] No No No OUTPUT
mio_attr_o[43].drive_strength[0] Yes Yes *T40,*T41,*T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[43].drive_strength[3:1] No No No OUTPUT
mio_attr_o[44].invert Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[44].virt_od_en Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[44].pull_en Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[44].pull_select Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[44].keep_en No No No OUTPUT
mio_attr_o[44].schmitt_en No No No OUTPUT
mio_attr_o[44].od_en No No No OUTPUT
mio_attr_o[44].input_disable Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[44].slew_rate[1:0] No No No OUTPUT
mio_attr_o[44].drive_strength[0] Yes Yes *T40,*T41,*T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[44].drive_strength[3:1] No No No OUTPUT
mio_attr_o[45].invert Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[45].virt_od_en Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[45].pull_en Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[45].pull_select Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[45].keep_en No No No OUTPUT
mio_attr_o[45].schmitt_en No No No OUTPUT
mio_attr_o[45].od_en No No No OUTPUT
mio_attr_o[45].input_disable Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[45].slew_rate[1:0] No No No OUTPUT
mio_attr_o[45].drive_strength[0] Yes Yes *T40,*T41,*T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[45].drive_strength[3:1] No No No OUTPUT
mio_attr_o[46].invert Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[46].virt_od_en Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[46].pull_en Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[46].pull_select Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[46].keep_en No No No OUTPUT
mio_attr_o[46].schmitt_en No No No OUTPUT
mio_attr_o[46].od_en No No No OUTPUT
mio_attr_o[46].input_disable Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[46].slew_rate[1:0] No No No OUTPUT
mio_attr_o[46].drive_strength[0] Yes Yes *T40,*T41,*T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[46].drive_strength[3:1] No No No OUTPUT
dio_attr_o[0].invert Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
dio_attr_o[0].virt_od_en Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
dio_attr_o[0].pull_en Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
dio_attr_o[0].pull_select Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
dio_attr_o[0].keep_en No No No OUTPUT
dio_attr_o[0].schmitt_en No No No OUTPUT
dio_attr_o[0].od_en No No No OUTPUT
dio_attr_o[0].input_disable Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
dio_attr_o[0].slew_rate[1:0] No No No OUTPUT
dio_attr_o[0].drive_strength[0] Yes Yes *T5,*T43,*T19 Yes T5,T43,T44 OUTPUT
dio_attr_o[0].drive_strength[3:1] No No No OUTPUT
dio_attr_o[1].invert Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
dio_attr_o[1].virt_od_en Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
dio_attr_o[1].pull_en Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
dio_attr_o[1].pull_select Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
dio_attr_o[1].keep_en No No No OUTPUT
dio_attr_o[1].schmitt_en No No No OUTPUT
dio_attr_o[1].od_en No No No OUTPUT
dio_attr_o[1].input_disable Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
dio_attr_o[1].slew_rate[1:0] No No No OUTPUT
dio_attr_o[1].drive_strength[0] Yes Yes *T5,*T43,*T19 Yes T5,T43,T44 OUTPUT
dio_attr_o[1].drive_strength[3:1] No No No OUTPUT
dio_attr_o[2].invert Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
dio_attr_o[2].virt_od_en Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
dio_attr_o[2].pull_en Yes Yes T40,T41,T42 Yes T45,T24,T25 OUTPUT
dio_attr_o[2].pull_select Yes Yes T40,T41,T42 Yes T45,T24,T25 OUTPUT
dio_attr_o[2].keep_en No No No OUTPUT
dio_attr_o[2].schmitt_en No No No OUTPUT
dio_attr_o[2].od_en No No No OUTPUT
dio_attr_o[2].input_disable Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
dio_attr_o[2].slew_rate[1:0] No No No OUTPUT
dio_attr_o[2].drive_strength[0] Yes Yes *T40,*T41,*T42 Yes T40,T41,T42 OUTPUT
dio_attr_o[2].drive_strength[3:1] No No No OUTPUT
dio_attr_o[3].invert Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
dio_attr_o[3].virt_od_en Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
dio_attr_o[3].pull_en Yes Yes T40,T41,T42 Yes T45,T24,T25 OUTPUT
dio_attr_o[3].pull_select Yes Yes T40,T41,T42 Yes T45,T24,T25 OUTPUT
dio_attr_o[3].keep_en No No No OUTPUT
dio_attr_o[3].schmitt_en No No No OUTPUT
dio_attr_o[3].od_en No No No OUTPUT
dio_attr_o[3].input_disable Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
dio_attr_o[3].slew_rate[1:0] No No No OUTPUT
dio_attr_o[3].drive_strength[0] Yes Yes *T40,*T41,*T42 Yes T40,T41,T42 OUTPUT
dio_attr_o[3].drive_strength[3:1] No No No OUTPUT
dio_attr_o[4].invert Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
dio_attr_o[4].virt_od_en Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
dio_attr_o[4].pull_en Yes Yes T40,T41,T42 Yes T45,T24,T25 OUTPUT
dio_attr_o[4].pull_select Yes Yes T40,T41,T42 Yes T45,T24,T25 OUTPUT
dio_attr_o[4].keep_en No No No OUTPUT
dio_attr_o[4].schmitt_en No No No OUTPUT
dio_attr_o[4].od_en No No No OUTPUT
dio_attr_o[4].input_disable Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
dio_attr_o[4].slew_rate[1:0] No No No OUTPUT
dio_attr_o[4].drive_strength[0] Yes Yes *T40,*T41,*T42 Yes T40,T41,T42 OUTPUT
dio_attr_o[4].drive_strength[3:1] No No No OUTPUT
dio_attr_o[5].invert Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
dio_attr_o[5].virt_od_en Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
dio_attr_o[5].pull_en Yes Yes T40,T41,T42 Yes T45,T24,T25 OUTPUT
dio_attr_o[5].pull_select Yes Yes T40,T41,T42 Yes T45,T24,T25 OUTPUT
dio_attr_o[5].keep_en No No No OUTPUT
dio_attr_o[5].schmitt_en No No No OUTPUT
dio_attr_o[5].od_en No No No OUTPUT
dio_attr_o[5].input_disable Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
dio_attr_o[5].slew_rate[1:0] No No No OUTPUT
dio_attr_o[5].drive_strength[0] Yes Yes *T40,*T41,*T42 Yes T40,T41,T42 OUTPUT
dio_attr_o[5].drive_strength[3:1] No No No OUTPUT
dio_attr_o[6].invert Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
dio_attr_o[6].virt_od_en Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
dio_attr_o[6].pull_en Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
dio_attr_o[6].pull_select Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
dio_attr_o[6].keep_en No No No OUTPUT
dio_attr_o[6].schmitt_en No No No OUTPUT
dio_attr_o[6].od_en No No No OUTPUT
dio_attr_o[6].input_disable Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
dio_attr_o[6].slew_rate[1:0] No No No OUTPUT
dio_attr_o[6].drive_strength[0] Yes Yes *T40,*T41,*T42 Yes T40,T41,T42 OUTPUT
dio_attr_o[6].drive_strength[3:1] No No No OUTPUT
dio_attr_o[7].invert Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
dio_attr_o[7].virt_od_en Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
dio_attr_o[7].pull_en Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
dio_attr_o[7].pull_select Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
dio_attr_o[7].keep_en No No No OUTPUT
dio_attr_o[7].schmitt_en No No No OUTPUT
dio_attr_o[7].od_en No No No OUTPUT
dio_attr_o[7].input_disable Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
dio_attr_o[7].slew_rate[1:0] No No No OUTPUT
dio_attr_o[7].drive_strength[0] Yes Yes *T40,*T41,*T42 Yes T40,T41,T42 OUTPUT
dio_attr_o[7].drive_strength[3:1] No No No OUTPUT
dio_attr_o[8].invert Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
dio_attr_o[8].virt_od_en Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
dio_attr_o[8].pull_en Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
dio_attr_o[8].pull_select Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
dio_attr_o[8].keep_en No No No OUTPUT
dio_attr_o[8].schmitt_en No No No OUTPUT
dio_attr_o[8].od_en No No No OUTPUT
dio_attr_o[8].input_disable Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
dio_attr_o[8].slew_rate[1:0] No No No OUTPUT
dio_attr_o[8].drive_strength[0] Yes Yes *T40,*T41,*T42 Yes T40,T41,T42 OUTPUT
dio_attr_o[8].drive_strength[3:1] No No No OUTPUT
dio_attr_o[9].invert Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
dio_attr_o[9].virt_od_en Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
dio_attr_o[9].pull_en Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
dio_attr_o[9].pull_select Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
dio_attr_o[9].keep_en No No No OUTPUT
dio_attr_o[9].schmitt_en No No No OUTPUT
dio_attr_o[9].od_en No No No OUTPUT
dio_attr_o[9].input_disable Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
dio_attr_o[9].slew_rate[1:0] No No No OUTPUT
dio_attr_o[9].drive_strength[0] Yes Yes *T40,*T41,*T42 Yes T40,T41,T42 OUTPUT
dio_attr_o[9].drive_strength[3:1] No No No OUTPUT
dio_attr_o[10].invert Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
dio_attr_o[10].virt_od_en Yes Yes T40,T41,T42 Yes T48,T49,T50 OUTPUT
dio_attr_o[10].pull_en Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
dio_attr_o[10].pull_select Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
dio_attr_o[10].keep_en No No No OUTPUT
dio_attr_o[10].schmitt_en No No No OUTPUT
dio_attr_o[10].od_en No No No OUTPUT
dio_attr_o[10].input_disable Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
dio_attr_o[10].slew_rate[1:0] No No No OUTPUT
dio_attr_o[10].drive_strength[0] Yes Yes *T40,*T41,*T42 Yes T40,T41,T42 OUTPUT
dio_attr_o[10].drive_strength[3:1] No No No OUTPUT
dio_attr_o[11].invert Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
dio_attr_o[11].virt_od_en Yes Yes T40,T41,T42 Yes T48,T49,T50 OUTPUT
dio_attr_o[11].pull_en Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
dio_attr_o[11].pull_select Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
dio_attr_o[11].keep_en No No No OUTPUT
dio_attr_o[11].schmitt_en No No No OUTPUT
dio_attr_o[11].od_en No No No OUTPUT
dio_attr_o[11].input_disable Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
dio_attr_o[11].slew_rate[1:0] No No No OUTPUT
dio_attr_o[11].drive_strength[0] Yes Yes *T40,*T41,*T42 Yes T40,T41,T42 OUTPUT
dio_attr_o[11].drive_strength[3:1] No No No OUTPUT
dio_attr_o[12].invert Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
dio_attr_o[12].virt_od_en No No No OUTPUT
dio_attr_o[12].pull_en Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
dio_attr_o[12].pull_select Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
dio_attr_o[12].keep_en No No No OUTPUT
dio_attr_o[12].schmitt_en No No No OUTPUT
dio_attr_o[12].od_en No No No OUTPUT
dio_attr_o[12].input_disable Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
dio_attr_o[12].slew_rate[1:0] No No No OUTPUT
dio_attr_o[12].drive_strength[3:0] No No No OUTPUT
dio_attr_o[13].invert Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
dio_attr_o[13].virt_od_en No No No OUTPUT
dio_attr_o[13].pull_en Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
dio_attr_o[13].pull_select Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
dio_attr_o[13].keep_en No No No OUTPUT
dio_attr_o[13].schmitt_en No No No OUTPUT
dio_attr_o[13].od_en No No No OUTPUT
dio_attr_o[13].input_disable Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
dio_attr_o[13].slew_rate[1:0] No No No OUTPUT
dio_attr_o[13].drive_strength[3:0] No No No OUTPUT
dio_attr_o[14].invert Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
dio_attr_o[14].virt_od_en Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
dio_attr_o[14].pull_en Yes Yes T40,T41,T42 Yes T45,T46,T47 OUTPUT
dio_attr_o[14].pull_select Yes Yes T40,T41,T42 Yes T45,T46,T47 OUTPUT
dio_attr_o[14].keep_en No No No OUTPUT
dio_attr_o[14].schmitt_en No No No OUTPUT
dio_attr_o[14].od_en No No No OUTPUT
dio_attr_o[14].input_disable Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
dio_attr_o[14].slew_rate[1:0] No No No OUTPUT
dio_attr_o[14].drive_strength[0] Yes Yes *T40,*T41,*T42 Yes T40,T41,T42 OUTPUT
dio_attr_o[14].drive_strength[3:1] No No No OUTPUT
dio_attr_o[15].invert Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
dio_attr_o[15].virt_od_en Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
dio_attr_o[15].pull_en Yes Yes T40,T41,T42 Yes T45,T46,T47 OUTPUT
dio_attr_o[15].pull_select Yes Yes T40,T41,T42 Yes T45,T46,T47 OUTPUT
dio_attr_o[15].keep_en No No No OUTPUT
dio_attr_o[15].schmitt_en No No No OUTPUT
dio_attr_o[15].od_en No No No OUTPUT
dio_attr_o[15].input_disable Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
dio_attr_o[15].slew_rate[1:0] No No No OUTPUT
dio_attr_o[15].drive_strength[0] Yes Yes *T40,*T41,*T42 Yes T40,T41,T42 OUTPUT
dio_attr_o[15].drive_strength[3:1] No No No OUTPUT
adc_req_o.pd Yes Yes T115,T1,T116 Yes T115,T1,T116 OUTPUT
adc_req_o.channel_sel[1:0] Yes Yes T115,T1,T116 Yes T115,T1,T116 OUTPUT
adc_rsp_i.data_valid Yes Yes T115,T1,T116 Yes T115,T1,T116 INPUT
adc_rsp_i.data[9:0] Yes Yes T115,T1,T3 Yes T115,T1,T3 INPUT
ast_edn_req_i.edn_req Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
ast_edn_rsp_o.edn_bus[31:0] Yes Yes T4,T5,T43 Yes T4,T5,T43 OUTPUT
ast_edn_rsp_o.edn_fips Yes Yes T117,T118 Yes T43,T119,T120 OUTPUT
ast_edn_rsp_o.edn_ack Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
ast_lc_dft_en_o[3:0] Yes Yes T43,T20,T62 Yes T5,T6,T43 OUTPUT
obs_ctrl_i.obmen[3:0] No No No INPUT
obs_ctrl_i.obmsl[3:0] No No No INPUT
obs_ctrl_i.obgsl[3:0] No No No INPUT
ram_1p_cfg_i.rf_cfg.cfg[3:0] No No No INPUT
ram_1p_cfg_i.rf_cfg.cfg_en No No No INPUT
ram_1p_cfg_i.rf_cfg.test No No No INPUT
ram_1p_cfg_i.ram_cfg.cfg[3:0] No No No INPUT
ram_1p_cfg_i.ram_cfg.cfg_en No No No INPUT
ram_1p_cfg_i.ram_cfg.test No No No INPUT
spi_ram_2p_cfg_i.b_ram_lcfg.cfg[3:0] No No No INPUT
spi_ram_2p_cfg_i.b_ram_lcfg.cfg_en No No No INPUT
spi_ram_2p_cfg_i.b_ram_lcfg.test No No No INPUT
spi_ram_2p_cfg_i.a_ram_lcfg.cfg[3:0] No No No INPUT
spi_ram_2p_cfg_i.a_ram_lcfg.cfg_en No No No INPUT
spi_ram_2p_cfg_i.a_ram_lcfg.test No No No INPUT
spi_ram_2p_cfg_i.b_ram_fcfg.cfg[3:0] No No No INPUT
spi_ram_2p_cfg_i.b_ram_fcfg.cfg_en No No No INPUT
spi_ram_2p_cfg_i.b_ram_fcfg.test No No No INPUT
spi_ram_2p_cfg_i.a_ram_fcfg.cfg[3:0] No No No INPUT
spi_ram_2p_cfg_i.a_ram_fcfg.cfg_en No No No INPUT
spi_ram_2p_cfg_i.a_ram_fcfg.test No No No INPUT
usb_ram_1p_cfg_i.rf_cfg.cfg[3:0] No No No INPUT
usb_ram_1p_cfg_i.rf_cfg.cfg_en No No No INPUT
usb_ram_1p_cfg_i.rf_cfg.test No No No INPUT
usb_ram_1p_cfg_i.ram_cfg.cfg[3:0] No No No INPUT
usb_ram_1p_cfg_i.ram_cfg.cfg_en No No No INPUT
usb_ram_1p_cfg_i.ram_cfg.test No No No INPUT
rom_cfg_i.cfg[3:0] No No No INPUT
rom_cfg_i.cfg_en No No No INPUT
rom_cfg_i.test No No No INPUT
clk_main_jitter_en_o[3:0] Yes Yes T43,T17,T121 Yes T43,T122,T119 OUTPUT
io_clk_byp_req_o[3:0] Yes Yes T20,T63,T123 Yes T20,T63,T123 OUTPUT
io_clk_byp_ack_i[3:0] Yes Yes T20,T63,T123 Yes T20,T63,T123 INPUT
all_clk_byp_req_o[3:0] Yes Yes T44,T124,T125 Yes T44,T124,T125 OUTPUT
all_clk_byp_ack_i[3:0] Yes Yes T44,T124,T125 Yes T44,T124,T125 INPUT
hi_speed_sel_o[3:0] Yes Yes T5,T43,T44 Yes T4,T5,T6 OUTPUT
div_step_down_req_i[3:0] Yes Yes T44,T20,T63 Yes T44,T20,T63 INPUT
calib_rdy_i[3:0] Yes Yes T4,T5,T6 Yes T5,T43,T19 INPUT
flash_bist_enable_i[3:0] Unreachable Unreachable Unreachable INPUT
flash_power_down_h_i Yes Yes T4,T5,T6 Yes T64,T126,T127 INPUT
flash_power_ready_h_i No No Yes T4,T5,T6 INPUT
flash_test_mode_a_io[1:0] No No Yes T21,T22,T23 INOUT
flash_test_voltage_h_io No No Yes T21,T22,T23 INOUT
flash_obs_o[7:0] Unreachable Unreachable Unreachable OUTPUT
es_rng_req_o.rng_enable Yes Yes T5,T43,T19 Yes T4,T5,T6 OUTPUT
es_rng_rsp_i.rng_b[3:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
es_rng_rsp_i.rng_valid Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
es_rng_fips_o Yes Yes T128,T129,T130 Yes T43,T131,T128 OUTPUT
ast_tl_req_o.d_ready Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
ast_tl_req_o.a_user.data_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
ast_tl_req_o.a_user.cmd_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
ast_tl_req_o.a_user.instr_type[3:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
ast_tl_req_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
ast_tl_req_o.a_data[31:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
ast_tl_req_o.a_mask[3:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
ast_tl_req_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
ast_tl_req_o.a_source[5:0] Yes Yes *T58,*T70,*T71 Yes T58,T70,T71 OUTPUT
ast_tl_req_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
ast_tl_req_o.a_size[1:0] Yes Yes T78,T79,T80 Yes T78,T79,T80 OUTPUT
ast_tl_req_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
ast_tl_req_o.a_opcode[2:0] Yes Yes T58,T71,T81 Yes T58,T71,T81 OUTPUT
ast_tl_req_o.a_valid Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
ast_tl_rsp_i.a_ready Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
ast_tl_rsp_i.d_error Yes Yes T78,T80,T82 Yes T78,T79,T80 INPUT
ast_tl_rsp_i.d_user.data_intg[6:0] Yes Yes T78,T79,T132 Yes T78,T79,T132 INPUT
ast_tl_rsp_i.d_user.rsp_intg[6:0] Yes Yes T5,T43,T19 Yes T4,T5,T6 INPUT
ast_tl_rsp_i.d_data[31:0] Yes Yes T5,T43,T19 Yes T4,T5,T6 INPUT
ast_tl_rsp_i.d_sink Yes Yes T78,T79,T80 Yes T78,T79,T80 INPUT
ast_tl_rsp_i.d_source[5:0] Yes Yes *T79,*T80,*T82 Yes T78,T79,T80 INPUT
ast_tl_rsp_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
ast_tl_rsp_i.d_size[1:0] Yes Yes T78,T79,T80 Yes T78,T79,T80 INPUT
ast_tl_rsp_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
ast_tl_rsp_i.d_opcode[0] Yes Yes *T78,*T79,*T132 Yes T78,T79,T132 INPUT
ast_tl_rsp_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
ast_tl_rsp_i.d_valid Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
dft_strap_test_o.straps[1:0] No No Yes T67,T68,T69 OUTPUT
dft_strap_test_o.valid Yes Yes T43,T20,T62 Yes T5,T6,T43 OUTPUT
dft_hold_tap_sel_i Unreachable Unreachable Unreachable INPUT
usb_dp_pullup_en_o Yes Yes T1,T3,T7 Yes T29,T30,T1 OUTPUT
usb_dn_pullup_en_o Yes Yes T75,T76,T77 Yes T75,T76,T77 OUTPUT
pwrmgr_ast_req_o.usb_clk_en Yes Yes T5,T18,T19 Yes T4,T5,T6 OUTPUT
pwrmgr_ast_req_o.io_clk_en Yes Yes T5,T18,T19 Yes T4,T5,T6 OUTPUT
pwrmgr_ast_req_o.core_clk_en Yes Yes T5,T18,T19 Yes T4,T5,T6 OUTPUT
pwrmgr_ast_req_o.slow_clk_en No No No OUTPUT
pwrmgr_ast_req_o.pwr_clamp Yes Yes T4,T5,T6 Yes T5,T19,T20 OUTPUT
pwrmgr_ast_req_o.pwr_clamp_env Yes Yes T4,T5,T6 Yes T5,T19,T20 OUTPUT
pwrmgr_ast_req_o.main_pd_n Yes Yes T64,T126,T127 Yes T64,T126,T127 OUTPUT
pwrmgr_ast_rsp_i.main_pok Yes Yes T5,T19,T20 Yes T4,T5,T6 INPUT
pwrmgr_ast_rsp_i.usb_clk_val Yes Yes T5,T44,T18 Yes T4,T5,T6 INPUT
pwrmgr_ast_rsp_i.io_clk_val Yes Yes T5,T44,T18 Yes T4,T5,T6 INPUT
pwrmgr_ast_rsp_i.core_clk_val Yes Yes T5,T44,T18 Yes T4,T5,T6 INPUT
pwrmgr_ast_rsp_i.slow_clk_val Yes Yes T44,T124,T125 Yes T4,T5,T6 INPUT
otp_ctrl_otp_ast_pwr_seq_o.pwr_seq[1:0] No No No OUTPUT
otp_ctrl_otp_ast_pwr_seq_h_i.pwr_seq_h[0] No No No INPUT
otp_ctrl_otp_ast_pwr_seq_h_i.pwr_seq_h[1] Yes Yes T4,T5,T6 Yes T64,T126,T127 INPUT
otp_ext_voltage_h_io No No Yes T21,T22,T23 INOUT
otp_obs_o[7:0] Unreachable Unreachable Unreachable OUTPUT
por_n_i[1:0] Yes Yes T5,T19,T20 Yes T4,T5,T6 INPUT
fpga_info_i[31:0] Unreachable Unreachable Unreachable INPUT
sensor_ctrl_ast_alert_req_i.alerts[0].n Yes Yes T133,T134,T7 Yes T134,T7,T103 INPUT
sensor_ctrl_ast_alert_req_i.alerts[0].p Yes Yes T134,T7,T103 Yes T133,T134,T7 INPUT
sensor_ctrl_ast_alert_req_i.alerts[1].n Yes Yes T133,T135,T136 Yes T135,T137,T138 INPUT
sensor_ctrl_ast_alert_req_i.alerts[1].p Yes Yes T135,T137,T138 Yes T133,T135,T136 INPUT
sensor_ctrl_ast_alert_req_i.alerts[2].n Yes Yes T133,T139,T134 Yes T139,T134,T140 INPUT
sensor_ctrl_ast_alert_req_i.alerts[2].p Yes Yes T139,T134,T140 Yes T133,T139,T134 INPUT
sensor_ctrl_ast_alert_req_i.alerts[3].n No Yes T133,T136,T141 No INPUT
sensor_ctrl_ast_alert_req_i.alerts[3].p No No Yes T133,T136,T141 INPUT
sensor_ctrl_ast_alert_req_i.alerts[4].n Yes Yes T133,T135,T134 Yes T135,T134,T140 INPUT
sensor_ctrl_ast_alert_req_i.alerts[4].p Yes Yes T135,T134,T140 Yes T133,T135,T134 INPUT
sensor_ctrl_ast_alert_req_i.alerts[5].n Yes Yes T133,T142,T136 Yes T142,T137,T138 INPUT
sensor_ctrl_ast_alert_req_i.alerts[5].p Yes Yes T142,T137,T138 Yes T133,T142,T136 INPUT
sensor_ctrl_ast_alert_req_i.alerts[6].n Yes Yes T133,T139,T136 Yes T139,T137,T138 INPUT
sensor_ctrl_ast_alert_req_i.alerts[6].p Yes Yes T139,T137,T138 Yes T133,T139,T136 INPUT
sensor_ctrl_ast_alert_req_i.alerts[7].n Yes Yes T133,T136,T141 Yes T138,T143,T144 INPUT
sensor_ctrl_ast_alert_req_i.alerts[7].p Yes Yes T138,T143,T144 Yes T133,T136,T141 INPUT
sensor_ctrl_ast_alert_req_i.alerts[8].n Yes Yes T133,T136,T141 Yes T137,T144 INPUT
sensor_ctrl_ast_alert_req_i.alerts[8].p Yes Yes T137,T144 Yes T133,T136,T141 INPUT
sensor_ctrl_ast_alert_req_i.alerts[9].n Yes Yes T133,T136,T141 Yes T137,T138,T144 INPUT
sensor_ctrl_ast_alert_req_i.alerts[9].p Yes Yes T137,T138,T144 Yes T133,T136,T141 INPUT
sensor_ctrl_ast_alert_req_i.alerts[10].n Yes Yes T133,T136,T141 Yes T143 INPUT
sensor_ctrl_ast_alert_req_i.alerts[10].p Yes Yes T143 Yes T133,T136,T141 INPUT
sensor_ctrl_ast_alert_rsp_o.alerts_trig[0].n Yes Yes T133,T134,T7 Yes T133,T134,T7 OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_trig[0].p Yes Yes T133,T134,T7 Yes T133,T134,T7 OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_trig[1].n Yes Yes T133,T135,T136 Yes T133,T135,T136 OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_trig[1].p Yes Yes T133,T135,T136 Yes T133,T135,T136 OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_trig[2].n Yes Yes T133,T139,T134 Yes T133,T139,T134 OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_trig[2].p Yes Yes T133,T139,T134 Yes T133,T139,T134 OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_trig[3].n Yes Yes T133,T136,T141 Yes T133,T136,T141 OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_trig[3].p Yes Yes T133,T136,T141 Yes T133,T136,T141 OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_trig[4].n Yes Yes T133,T135,T134 Yes T133,T135,T134 OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_trig[4].p Yes Yes T133,T135,T134 Yes T133,T135,T134 OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_trig[5].n Yes Yes T133,T142,T136 Yes T133,T142,T136 OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_trig[5].p Yes Yes T133,T142,T136 Yes T133,T142,T136 OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_trig[6].n Yes Yes T133,T139,T136 Yes T133,T139,T136 OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_trig[6].p Yes Yes T133,T139,T136 Yes T133,T139,T136 OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_trig[7].n Yes Yes T133,T136,T141 Yes T133,T136,T141 OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_trig[7].p Yes Yes T133,T136,T141 Yes T133,T136,T141 OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_trig[8].n Yes Yes T133,T136,T141 Yes T133,T136,T141 OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_trig[8].p Yes Yes T133,T136,T141 Yes T133,T136,T141 OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_trig[9].n Yes Yes T133,T136,T141 Yes T133,T136,T141 OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_trig[9].p Yes Yes T133,T136,T141 Yes T133,T136,T141 OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_trig[10].n Yes Yes T133,T136,T141 Yes T133,T136,T141 OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_trig[10].p Yes Yes T133,T136,T141 Yes T133,T136,T141 OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_ack[0].n Yes Yes T133,T134,T7 Yes T133,T134,T7 OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_ack[0].p Yes Yes T133,T134,T7 Yes T133,T134,T7 OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_ack[1].n Yes Yes T133,T135,T136 Yes T133,T135,T136 OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_ack[1].p Yes Yes T133,T135,T136 Yes T133,T135,T136 OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_ack[2].n Yes Yes T133,T139,T134 Yes T133,T139,T134 OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_ack[2].p Yes Yes T133,T139,T134 Yes T133,T139,T134 OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_ack[3].n Yes Yes T133,T136,T141 Yes T133,T136,T141 OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_ack[3].p Yes Yes T133,T136,T141 Yes T133,T136,T141 OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_ack[4].n Yes Yes T133,T135,T134 Yes T133,T135,T134 OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_ack[4].p Yes Yes T133,T135,T134 Yes T133,T135,T134 OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_ack[5].n Yes Yes T133,T142,T136 Yes T133,T142,T136 OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_ack[5].p Yes Yes T133,T142,T136 Yes T133,T142,T136 OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_ack[6].n Yes Yes T133,T139,T136 Yes T133,T139,T136 OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_ack[6].p Yes Yes T133,T139,T136 Yes T133,T139,T136 OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_ack[7].n Yes Yes T133,T136,T141 Yes T133,T136,T141 OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_ack[7].p Yes Yes T133,T136,T141 Yes T133,T136,T141 OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_ack[8].n Yes Yes T133,T136,T141 Yes T133,T136,T141 OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_ack[8].p Yes Yes T133,T136,T141 Yes T133,T136,T141 OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_ack[9].n Yes Yes T133,T136,T141 Yes T133,T136,T141 OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_ack[9].p Yes Yes T133,T136,T141 Yes T133,T136,T141 OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_ack[10].n Yes Yes T133,T136,T141 Yes T133,T136,T141 OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_ack[10].p Yes Yes T133,T136,T141 Yes T133,T136,T141 OUTPUT
sensor_ctrl_ast_status_i.io_pok[1:0] Yes Yes T101,T145,T146 Yes T4,T5,T6 INPUT
ast2pinmux_i[8:0] Unreachable Unreachable Unreachable INPUT
ast_init_done_i[3:0] Yes Yes T4,T5,T6 Yes T5,T43,T19 INPUT
sensor_ctrl_manual_pad_attr_o[0].invert No No No OUTPUT
sensor_ctrl_manual_pad_attr_o[0].virt_od_en No No No OUTPUT
sensor_ctrl_manual_pad_attr_o[0].pull_en Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
sensor_ctrl_manual_pad_attr_o[0].pull_select Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
sensor_ctrl_manual_pad_attr_o[0].keep_en No No No OUTPUT
sensor_ctrl_manual_pad_attr_o[0].schmitt_en No No No OUTPUT
sensor_ctrl_manual_pad_attr_o[0].od_en No No No OUTPUT
sensor_ctrl_manual_pad_attr_o[0].input_disable Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
sensor_ctrl_manual_pad_attr_o[0].slew_rate[1:0] No No No OUTPUT
sensor_ctrl_manual_pad_attr_o[0].drive_strength[3:0] No No No OUTPUT
sensor_ctrl_manual_pad_attr_o[1].invert No No No OUTPUT
sensor_ctrl_manual_pad_attr_o[1].virt_od_en No No No OUTPUT
sensor_ctrl_manual_pad_attr_o[1].pull_en Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
sensor_ctrl_manual_pad_attr_o[1].pull_select Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
sensor_ctrl_manual_pad_attr_o[1].keep_en No No No OUTPUT
sensor_ctrl_manual_pad_attr_o[1].schmitt_en No No No OUTPUT
sensor_ctrl_manual_pad_attr_o[1].od_en No No No OUTPUT
sensor_ctrl_manual_pad_attr_o[1].input_disable Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
sensor_ctrl_manual_pad_attr_o[1].slew_rate[1:0] No No No OUTPUT
sensor_ctrl_manual_pad_attr_o[1].drive_strength[3:0] No No No OUTPUT
sensor_ctrl_manual_pad_attr_o[2].invert No No No OUTPUT
sensor_ctrl_manual_pad_attr_o[2].virt_od_en No No No OUTPUT
sensor_ctrl_manual_pad_attr_o[2].pull_en Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
sensor_ctrl_manual_pad_attr_o[2].pull_select Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
sensor_ctrl_manual_pad_attr_o[2].keep_en No No No OUTPUT
sensor_ctrl_manual_pad_attr_o[2].schmitt_en No No No OUTPUT
sensor_ctrl_manual_pad_attr_o[2].od_en No No No OUTPUT
sensor_ctrl_manual_pad_attr_o[2].input_disable Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
sensor_ctrl_manual_pad_attr_o[2].slew_rate[1:0] No No No OUTPUT
sensor_ctrl_manual_pad_attr_o[2].drive_strength[3:0] No No No OUTPUT
sensor_ctrl_manual_pad_attr_o[3].invert No No No OUTPUT
sensor_ctrl_manual_pad_attr_o[3].virt_od_en No No No OUTPUT
sensor_ctrl_manual_pad_attr_o[3].pull_en Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
sensor_ctrl_manual_pad_attr_o[3].pull_select Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
sensor_ctrl_manual_pad_attr_o[3].keep_en No No No OUTPUT
sensor_ctrl_manual_pad_attr_o[3].schmitt_en No No No OUTPUT
sensor_ctrl_manual_pad_attr_o[3].od_en No No No OUTPUT
sensor_ctrl_manual_pad_attr_o[3].input_disable Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
sensor_ctrl_manual_pad_attr_o[3].slew_rate[1:0] No No No OUTPUT
sensor_ctrl_manual_pad_attr_o[3].drive_strength[3:0] No No No OUTPUT
sck_monitor_o Yes Yes T24,T25,T147 Yes T21,T22,T24 OUTPUT
usbdev_usb_rx_d_i Yes Yes T29,T34,T35 Yes T29,T34,T35 INPUT
usbdev_usb_tx_d_o Yes Yes T29,T30,T1 Yes T29,T30,T1 OUTPUT
usbdev_usb_tx_se0_o Yes Yes T29,T34,T35 Yes T29,T34,T35 OUTPUT
usbdev_usb_tx_use_d_se0_o Yes Yes T148,T132,T149 Yes T148,T132,T149 OUTPUT
usbdev_usb_rx_enable_o Yes Yes T76,T137,T138 Yes T29,T34,T35 OUTPUT
usbdev_usb_ref_val_o Yes Yes T34,T35,T150 Yes T29,T34,T35 OUTPUT
usbdev_usb_ref_pulse_o Yes Yes T29,T34,T35 Yes T29,T34,T35 OUTPUT
clk_main_i Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
clk_io_i Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
clk_usb_i Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
clk_aon_i Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
clks_ast_o.clk_usb_peri Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
clks_ast_o.clk_io_peri Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
clks_ast_o.clk_io_div2_peri Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
clks_ast_o.clk_io_div4_peri Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
clks_ast_o.clk_io_div4_timers Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
clks_ast_o.clk_main_secure Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
clks_ast_o.clk_io_div4_secure Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
clks_ast_o.clk_io_div2_infra Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
clks_ast_o.clk_io_infra Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
clks_ast_o.clk_usb_infra Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
clks_ast_o.clk_main_infra Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
clks_ast_o.clk_io_div4_infra Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
clks_ast_o.clk_main_otbn Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
clks_ast_o.clk_main_kmac Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
clks_ast_o.clk_main_hmac Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
clks_ast_o.clk_main_aes Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
clks_ast_o.clk_aon_timers Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
clks_ast_o.clk_aon_peri Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
clks_ast_o.clk_aon_secure Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
clks_ast_o.clk_io_div2_powerup Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
clks_ast_o.clk_usb_powerup Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
clks_ast_o.clk_io_powerup Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
clks_ast_o.clk_main_powerup Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
clks_ast_o.clk_aon_powerup Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
clks_ast_o.clk_io_div4_powerup Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
rsts_ast_o.rst_i2c2_n[0] No No No OUTPUT
rsts_ast_o.rst_i2c2_n[1] Yes Yes T5,T43,T19 Yes T4,T5,T6 OUTPUT
rsts_ast_o.rst_i2c1_n[0] No No No OUTPUT
rsts_ast_o.rst_i2c1_n[1] Yes Yes T5,T43,T19 Yes T4,T5,T6 OUTPUT
rsts_ast_o.rst_i2c0_n[0] No No No OUTPUT
rsts_ast_o.rst_i2c0_n[1] Yes Yes T5,T43,T19 Yes T4,T5,T6 OUTPUT
rsts_ast_o.rst_usb_aon_n[0] No No No OUTPUT
rsts_ast_o.rst_usb_aon_n[1] Yes Yes T5,T43,T19 Yes T4,T5,T6 OUTPUT
rsts_ast_o.rst_usb_n[0] No No No OUTPUT
rsts_ast_o.rst_usb_n[1] Yes Yes T5,T43,T19 Yes T4,T5,T6 OUTPUT
rsts_ast_o.rst_spi_host1_n[0] No No No OUTPUT
rsts_ast_o.rst_spi_host1_n[1] Yes Yes T5,T43,T19 Yes T4,T5,T6 OUTPUT
rsts_ast_o.rst_spi_host0_n[0] No No No OUTPUT
rsts_ast_o.rst_spi_host0_n[1] Yes Yes T5,T43,T19 Yes T4,T5,T6 OUTPUT
rsts_ast_o.rst_spi_device_n[0] No No No OUTPUT
rsts_ast_o.rst_spi_device_n[1] Yes Yes T5,T43,T19 Yes T4,T5,T6 OUTPUT
rsts_ast_o.rst_sys_io_div4_n[0] Yes Yes *T5,*T43,*T19 Yes T4,T5,T6 OUTPUT
rsts_ast_o.rst_sys_io_div4_n[1] No No No OUTPUT
rsts_ast_o.rst_sys_n[0] No No No OUTPUT
rsts_ast_o.rst_sys_n[1] Yes Yes T5,T43,T19 Yes T4,T5,T6 OUTPUT
rsts_ast_o.rst_lc_usb_n[1:0] Yes Yes T5,T43,T19 Yes T4,T5,T6 OUTPUT
rsts_ast_o.rst_lc_io_div4_n[1:0] Yes Yes T5,T43,T19 Yes T4,T5,T6 OUTPUT
rsts_ast_o.rst_lc_io_div4_shadowed_n[1:0] Yes Yes T5,T43,T19 Yes T4,T5,T6 OUTPUT
rsts_ast_o.rst_lc_io_div2_n[1:0] Yes Yes T5,T43,T19 Yes T4,T5,T6 OUTPUT
rsts_ast_o.rst_lc_io_n[1:0] Yes Yes T5,T43,T19 Yes T4,T5,T6 OUTPUT
rsts_ast_o.rst_lc_aon_n[0] Yes Yes *T5,*T43,*T19 Yes T4,T5,T6 OUTPUT
rsts_ast_o.rst_lc_aon_n[1] No No No OUTPUT
rsts_ast_o.rst_lc_n[1:0] Yes Yes T5,T43,T19 Yes T4,T5,T6 OUTPUT
rsts_ast_o.rst_lc_shadowed_n[1:0] Yes Yes T5,T43,T19 Yes T4,T5,T6 OUTPUT
rsts_ast_o.rst_por_usb_n[0] Yes Yes *T5,*T19,*T20 Yes T4,T5,T6 OUTPUT
rsts_ast_o.rst_por_usb_n[1] No No No OUTPUT
rsts_ast_o.rst_por_io_div4_n[0] Yes Yes *T5,*T19,*T20 Yes T4,T5,T6 OUTPUT
rsts_ast_o.rst_por_io_div4_n[1] No No No OUTPUT
rsts_ast_o.rst_por_io_div2_n[0] Yes Yes *T5,*T19,*T20 Yes T4,T5,T6 OUTPUT
rsts_ast_o.rst_por_io_div2_n[1] No No No OUTPUT
rsts_ast_o.rst_por_io_n[0] Yes Yes *T5,*T19,*T20 Yes T4,T5,T6 OUTPUT
rsts_ast_o.rst_por_io_n[1] No No No OUTPUT
rsts_ast_o.rst_por_n[0] Yes Yes *T5,*T19,*T20 Yes T4,T5,T6 OUTPUT
rsts_ast_o.rst_por_n[1] No No No OUTPUT
rsts_ast_o.rst_por_aon_n[1:0] Yes Yes T5,T19,T20 Yes T4,T5,T6 OUTPUT
scan_rst_ni Unreachable Unreachable Unreachable INPUT
scan_en_i Unreachable Unreachable Unreachable INPUT
scanmode_i[3:0] Unreachable Unreachable Unreachable INPUT

*Tests covering at least one bit in the range

Assert Coverage for Module : top_earlgrey
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
scanmodeKnown 525316944 525316944 0 0


scanmodeKnown
NameAttemptsReal SuccessesFailuresIncomplete
Total 525316944 525316944 0 0
T4 223564 223564 0 0
T5 398161 398161 0 0
T6 129945 129945 0 0
T16 183981 183981 0 0
T17 76093 76093 0 0
T18 175576 175576 0 0
T43 389326 389326 0 0
T44 194386 194386 0 0
T88 102619 102619 0 0
T89 82258 82258 0 0

Line Coverage for Instance : tb.dut.top_earlgrey
Line No.TotalCoveredPercent
TOTAL27925390.68
CONT_ASSIGN75811100.00
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CONT_ASSIGN96400
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CONT_ASSIGN97000
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CONT_ASSIGN97400
CONT_ASSIGN97600
CONT_ASSIGN97800
CONT_ASSIGN98000
CONT_ASSIGN98200
CONT_ASSIGN98400
CONT_ASSIGN98600
CONT_ASSIGN98800
CONT_ASSIGN99000
CONT_ASSIGN99200
CONT_ASSIGN99400
CONT_ASSIGN99600
CONT_ASSIGN99800
CONT_ASSIGN100000
CONT_ASSIGN100200
CONT_ASSIGN100400
CONT_ASSIGN100600
CONT_ASSIGN100800
CONT_ASSIGN101000
CONT_ASSIGN101200
CONT_ASSIGN101400
CONT_ASSIGN101600
CONT_ASSIGN101800
CONT_ASSIGN102000
CONT_ASSIGN266411100.00
CONT_ASSIGN306811100.00
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CONT_ASSIGN311011100.00
CONT_ASSIGN311111100.00
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CONT_ASSIGN313011100.00
CONT_ASSIGN313111100.00
CONT_ASSIGN313211100.00
CONT_ASSIGN313311100.00
CONT_ASSIGN313411100.00
CONT_ASSIGN313511100.00
CONT_ASSIGN313611100.00
CONT_ASSIGN313711100.00
CONT_ASSIGN313811100.00
CONT_ASSIGN313911100.00
CONT_ASSIGN314011100.00
CONT_ASSIGN314111100.00
CONT_ASSIGN314211100.00
CONT_ASSIGN314311100.00
CONT_ASSIGN314411100.00
CONT_ASSIGN314511100.00
CONT_ASSIGN314611100.00
CONT_ASSIGN314711100.00
CONT_ASSIGN314811100.00
CONT_ASSIGN314911100.00
CONT_ASSIGN315011100.00
CONT_ASSIGN315111100.00
CONT_ASSIGN315211100.00
CONT_ASSIGN315311100.00
CONT_ASSIGN315411100.00
CONT_ASSIGN315511100.00
CONT_ASSIGN315611100.00
CONT_ASSIGN315711100.00
CONT_ASSIGN315811100.00
CONT_ASSIGN315900
CONT_ASSIGN316000
CONT_ASSIGN316100
CONT_ASSIGN316200
CONT_ASSIGN316300
CONT_ASSIGN316400
CONT_ASSIGN316511100.00
CONT_ASSIGN3166100.00
CONT_ASSIGN3167100.00
CONT_ASSIGN3168100.00
CONT_ASSIGN316911100.00
CONT_ASSIGN317011100.00
CONT_ASSIGN317111100.00
CONT_ASSIGN317211100.00
CONT_ASSIGN317311100.00
CONT_ASSIGN317411100.00
CONT_ASSIGN317511100.00
CONT_ASSIGN317611100.00
CONT_ASSIGN317711100.00
CONT_ASSIGN317811100.00
CONT_ASSIGN3179100.00
CONT_ASSIGN318000
CONT_ASSIGN318100
CONT_ASSIGN318200
CONT_ASSIGN318300
CONT_ASSIGN318400
CONT_ASSIGN318500
CONT_ASSIGN318600
CONT_ASSIGN318700
CONT_ASSIGN318800
CONT_ASSIGN318911100.00
CONT_ASSIGN319011100.00
CONT_ASSIGN319111100.00
CONT_ASSIGN319211100.00
CONT_ASSIGN319311100.00
CONT_ASSIGN319411100.00
CONT_ASSIGN3195100.00
CONT_ASSIGN319611100.00
CONT_ASSIGN319711100.00
CONT_ASSIGN319811100.00
CONT_ASSIGN319911100.00
CONT_ASSIGN320011100.00
CONT_ASSIGN320111100.00
CONT_ASSIGN320411100.00
CONT_ASSIGN320511100.00
CONT_ASSIGN320611100.00
CONT_ASSIGN320711100.00
CONT_ASSIGN320811100.00
CONT_ASSIGN320911100.00
CONT_ASSIGN321011100.00
CONT_ASSIGN321111100.00
CONT_ASSIGN321211100.00
CONT_ASSIGN321311100.00
CONT_ASSIGN321411100.00
CONT_ASSIGN321511100.00
CONT_ASSIGN321611100.00
CONT_ASSIGN321711100.00
CONT_ASSIGN321811100.00
CONT_ASSIGN321911100.00
CONT_ASSIGN322011100.00
CONT_ASSIGN322111100.00
CONT_ASSIGN322211100.00
CONT_ASSIGN322311100.00
CONT_ASSIGN322411100.00
CONT_ASSIGN322511100.00
CONT_ASSIGN322611100.00
CONT_ASSIGN322711100.00
CONT_ASSIGN322811100.00
CONT_ASSIGN322911100.00
CONT_ASSIGN323011100.00
CONT_ASSIGN323111100.00
CONT_ASSIGN323211100.00
CONT_ASSIGN323311100.00
CONT_ASSIGN323411100.00
CONT_ASSIGN323511100.00
CONT_ASSIGN323611100.00
CONT_ASSIGN323711100.00
CONT_ASSIGN323811100.00
CONT_ASSIGN323911100.00
CONT_ASSIGN324011100.00
CONT_ASSIGN324111100.00
CONT_ASSIGN324211100.00
CONT_ASSIGN3243100.00
CONT_ASSIGN3244100.00
CONT_ASSIGN3245100.00
CONT_ASSIGN324600
CONT_ASSIGN324700
CONT_ASSIGN324800
CONT_ASSIGN324900
CONT_ASSIGN325000
CONT_ASSIGN325100
CONT_ASSIGN325200
CONT_ASSIGN325300
CONT_ASSIGN325411100.00
CONT_ASSIGN325511100.00
CONT_ASSIGN3256100.00
CONT_ASSIGN325700
CONT_ASSIGN325800
CONT_ASSIGN325900
CONT_ASSIGN326000
CONT_ASSIGN326100
CONT_ASSIGN326200
CONT_ASSIGN326300
CONT_ASSIGN326400
CONT_ASSIGN326500
CONT_ASSIGN326600
CONT_ASSIGN326700
CONT_ASSIGN326800
CONT_ASSIGN326900
CONT_ASSIGN327000
CONT_ASSIGN327100
CONT_ASSIGN327211100.00
CONT_ASSIGN327300
CONT_ASSIGN327400
CONT_ASSIGN327500
CONT_ASSIGN327600
CONT_ASSIGN327700
CONT_ASSIGN327800
CONT_ASSIGN328211100.00
CONT_ASSIGN328311100.00
CONT_ASSIGN328411100.00
CONT_ASSIGN328511100.00
CONT_ASSIGN328611100.00
CONT_ASSIGN328711100.00
CONT_ASSIGN328811100.00
CONT_ASSIGN328911100.00
CONT_ASSIGN329011100.00
CONT_ASSIGN329111100.00
CONT_ASSIGN329211100.00
CONT_ASSIGN329311100.00
CONT_ASSIGN329411100.00
CONT_ASSIGN329511100.00
CONT_ASSIGN329611100.00
CONT_ASSIGN329911100.00
CONT_ASSIGN330011100.00
CONT_ASSIGN330111100.00
CONT_ASSIGN330211100.00
CONT_ASSIGN330311100.00
CONT_ASSIGN330411100.00
CONT_ASSIGN330511100.00
CONT_ASSIGN330611100.00
CONT_ASSIGN330711100.00
CONT_ASSIGN330811100.00
CONT_ASSIGN330911100.00
CONT_ASSIGN331011100.00
CONT_ASSIGN331311100.00
CONT_ASSIGN331411100.00
CONT_ASSIGN331711100.00
CONT_ASSIGN331811100.00
CONT_ASSIGN331911100.00
CONT_ASSIGN3320100.00
CONT_ASSIGN3321100.00
CONT_ASSIGN3322100.00
CONT_ASSIGN332311100.00
CONT_ASSIGN332411100.00
CONT_ASSIGN332511100.00
CONT_ASSIGN332611100.00
CONT_ASSIGN332700
CONT_ASSIGN332800
CONT_ASSIGN333111100.00
CONT_ASSIGN333211100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_systems_top_earlgrey_0.1/rtl/autogen/top_earlgrey.sv' or '../src/lowrisc_systems_top_earlgrey_0.1/rtl/autogen/top_earlgrey.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
758 1 1
759 1 1
760 1 1
761 0 1
762 0 1
763 0 1
764 0 1
765 0 1
778 1 1
779 0 1
780 0 1
781 0 1
782 0 1
783 0 1
784 0 1
785 0 1
799 1 1
801 1 1
803 1 1
805 1 1
807 1 1
809 1 1
813 1 1
823 1 1
824 1 1
828 1 1
852 1 1
853 1 1
855 1 1
856 1 1
858 1 1
859 1 1
861 1 1
862 1 1
864 1 1
865 1 1
867 1 1
868 1 1
870 1 1
871 1 1
873 1 1
874 1 1
876 1 1
877 1 1
879 1 1
880 1 1
882 0 1
883 1 1
885 0 1
886 1 1
888 1 1
889 1 1
891 1 1
892 1 1
894 1 1
895 1 1
897 1 1
898 1 1
900 1 1
901 1 1
903 1 1
904 1 1
906 1 1
907 1 1
909 1 1
910 1 1
912 1 1
913 1 1
915 1 1
916 1 1
918 1 1
919 1 1
921 1 1
922 1 1
928 unreachable
930 unreachable
932 unreachable
934 unreachable
936 unreachable
938 unreachable
940 unreachable
942 unreachable
944 unreachable
946 unreachable
948 unreachable
950 unreachable
952 unreachable
954 unreachable
956 unreachable
958 unreachable
960 unreachable
962 unreachable
964 unreachable
966 unreachable
968 unreachable
970 unreachable
972 unreachable
974 unreachable
976 unreachable
978 unreachable
980 unreachable
982 unreachable
984 unreachable
986 unreachable
988 unreachable
990 unreachable
992 unreachable
994 unreachable
996 unreachable
998 unreachable
1000 unreachable
1002 unreachable
1004 unreachable
1006 unreachable
1008 unreachable
1010 unreachable
1012 unreachable
1014 unreachable
1016 unreachable
1018 unreachable
1020 unreachable
2664 1 1
3068 1 1
3069 1 1
3070 1 1
3071 1 1
3072 1 1
3073 1 1
3074 1 1
3075 1 1
3076 1 1
3077 1 1
3078 1 1
3079 1 1
3080 1 1
3081 1 1
3082 1 1
3083 1 1
3084 1 1
3085 1 1
3086 1 1
3087 1 1
3088 1 1
3089 1 1
3090 1 1
3091 1 1
3092 1 1
3093 1 1
3094 1 1
3095 1 1
3096 1 1
3097 1 1
3098 1 1
3099 1 1
3100 1 1
3101 1 1
3102 1 1
3103 1 1
3104 1 1
3105 1 1
3106 1 1
3107 1 1
3108 1 1
3109 1 1
3110 1 1
3111 1 1
3112 1 1
3113 1 1
3114 1 1
3115 1 1
3116 1 1
3117 1 1
3118 1 1
3119 1 1
3120 1 1
3121 1 1
3122 1 1
3123 1 1
3124 1 1
3127 1 1
3128 1 1
3129 1 1
3130 1 1
3131 1 1
3132 1 1
3133 1 1
3134 1 1
3135 1 1
3136 1 1
3137 1 1
3138 1 1
3139 1 1
3140 1 1
3141 1 1
3142 1 1
3143 1 1
3144 1 1
3145 1 1
3146 1 1
3147 1 1
3148 1 1
3149 1 1
3150 1 1
3151 1 1
3152 1 1
3153 1 1
3154 1 1
3155 1 1
3156 1 1
3157 1 1
3158 1 1
3159 unreachable
3160 unreachable
3161 unreachable
3162 unreachable
3163 unreachable
3164 unreachable
3165 1 1
3166 0 1
3167 0 1
3168 0 1
3169 1 1
3170 1 1
3171 1 1
3172 1 1
3173 1 1
3174 1 1
3175 1 1
3176 1 1
3177 1 1
3178 1 1
3179 0 1
3180 unreachable
3181 unreachable
3182 unreachable
3183 unreachable
3184 unreachable
3185 unreachable
3186 unreachable
3187 unreachable
3188 unreachable
3189 1 1
3190 1 1
3191 1 1
3192 1 1
3193 1 1
3194 1 1
3195 0 1
3196 1 1
3197 1 1
3198 1 1
3199 1 1
3200 1 1
3201 1 1
3204 1 1
3205 1 1
3206 1 1
3207 1 1
3208 1 1
3209 1 1
3210 1 1
3211 1 1
3212 1 1
3213 1 1
3214 1 1
3215 1 1
3216 1 1
3217 1 1
3218 1 1
3219 1 1
3220 1 1
3221 1 1
3222 1 1
3223 1 1
3224 1 1
3225 1 1
3226 1 1
3227 1 1
3228 1 1
3229 1 1
3230 1 1
3231 1 1
3232 1 1
3233 1 1
3234 1 1
3235 1 1
3236 1 1
3237 1 1
3238 1 1
3239 1 1
3240 1 1
3241 1 1
3242 1 1
3243 0 1
3244 0 1
3245 0 1
3246 unreachable
3247 unreachable
3248 unreachable
3249 unreachable
3250 unreachable
3251 unreachable
3252 unreachable
3253 unreachable
3254 1 1
3255 1 1
3256 0 1
3257 unreachable
3258 unreachable
3259 unreachable
3260 unreachable
3261 unreachable
3262 unreachable
3263 unreachable
3264 unreachable
3265 unreachable
3266 unreachable
3267 unreachable
3268 unreachable
3269 unreachable
3270 unreachable
3271 unreachable
3272 1 1
3273 unreachable
3274 unreachable
3275 unreachable
3276 unreachable
3277 unreachable
3278 unreachable
3282 1 1
3283 1 1
3284 1 1
3285 1 1
3286 1 1
3287 1 1
3288 1 1
3289 1 1
3290 1 1
3291 1 1
3292 1 1
3293 1 1
3294 1 1
3295 1 1
3296 1 1
3299 1 1
3300 1 1
3301 1 1
3302 1 1
3303 1 1
3304 1 1
3305 1 1
3306 1 1
3307 1 1
3308 1 1
3309 1 1
3310 1 1
3313 1 1
3314 1 1
3317 1 1
3318 1 1
3319 1 1
3320 0 1
3321 0 1
3322 0 1
3323 1 1
3324 1 1
3325 1 1
3326 1 1
3327 unreachable
3328 unreachable
3331 1 1
3332 1 1


Toggle Coverage for Instance : tb.dut.top_earlgrey
TotalCoveredPercent
Totals 638 559 87.62
Total Bits 2130 1901 89.25
Total Bits 0->1 1065 952 89.39
Total Bits 1->0 1065 949 89.11

Ports 638 559 87.62
Port Bits 2130 1901 89.25
Port Bits 0->1 1065 952 89.39
Port Bits 1->0 1065 949 89.11

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
mio_in_i[46:0] Yes Yes T16,T27,T28 Yes T16,T27,T28 INPUT
mio_out_o[46:0] Yes Yes T28,T36,T37 Yes T28,T22,T36 OUTPUT
mio_oe_o[46:0] Yes Yes T37,T38,T39 Yes T21,T28,T22 OUTPUT
dio_in_i[15:0] Yes Yes T29,T21,T22 Yes T29,T21,T22 INPUT
dio_out_o[11:0] Yes Yes *T29,*T21,*T30 Yes T29,T30,T1 OUTPUT
dio_out_o[13:12] No No No OUTPUT
dio_out_o[15:14] Yes Yes T24,T25,T26 Yes T24,T25,T26 OUTPUT
dio_oe_o[15:0] Yes Yes T29,T34,T35 Yes T29,T34,T35 OUTPUT
mio_attr_o[0].invert Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[0].virt_od_en Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[0].pull_en Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[0].pull_select Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[0].keep_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[0].schmitt_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[0].od_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[0].input_disable Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[0].slew_rate[1:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[0].drive_strength[0] Yes Yes *T40,*T41,*T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[0].drive_strength[3:1] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[1].invert Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[1].virt_od_en Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[1].pull_en Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[1].pull_select Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[1].keep_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[1].schmitt_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[1].od_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[1].input_disable Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[1].slew_rate[1:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[1].drive_strength[0] Yes Yes *T40,*T41,*T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[1].drive_strength[3:1] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[2].invert Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[2].virt_od_en Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[2].pull_en Yes Yes T40,T41,T42 Yes T45,T46,T47 OUTPUT
mio_attr_o[2].pull_select Yes Yes T40,T41,T42 Yes T45,T46,T47 OUTPUT
mio_attr_o[2].keep_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[2].schmitt_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[2].od_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[2].input_disable Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[2].slew_rate[1:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[2].drive_strength[0] Yes Yes *T40,*T41,*T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[2].drive_strength[3:1] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[3].invert Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[3].virt_od_en Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[3].pull_en Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[3].pull_select Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[3].keep_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[3].schmitt_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[3].od_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[3].input_disable Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[3].slew_rate[1:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[3].drive_strength[0] Yes Yes *T40,*T41,*T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[3].drive_strength[3:1] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[4].invert Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[4].virt_od_en Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[4].pull_en Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[4].pull_select Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[4].keep_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[4].schmitt_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[4].od_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[4].input_disable Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[4].slew_rate[1:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[4].drive_strength[0] Yes Yes *T40,*T41,*T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[4].drive_strength[3:1] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[5].invert Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[5].virt_od_en Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[5].pull_en Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[5].pull_select Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[5].keep_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[5].schmitt_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[5].od_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[5].input_disable Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[5].slew_rate[1:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[5].drive_strength[0] Yes Yes *T40,*T41,*T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[5].drive_strength[3:1] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[6].invert Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[6].virt_od_en Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[6].pull_en Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[6].pull_select Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[6].keep_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[6].schmitt_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[6].od_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[6].input_disable Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[6].slew_rate[1:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[6].drive_strength[0] Yes Yes *T40,*T41,*T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[6].drive_strength[3:1] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[7].invert Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[7].virt_od_en Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[7].pull_en Yes Yes T40,T41,T42 Yes T51,T52,T53 OUTPUT
mio_attr_o[7].pull_select Yes Yes T40,T41,T42 Yes T51,T52,T53 OUTPUT
mio_attr_o[7].keep_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[7].schmitt_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[7].od_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[7].input_disable Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[7].slew_rate[1:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[7].drive_strength[0] Yes Yes *T40,*T41,*T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[7].drive_strength[3:1] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[8].invert Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[8].virt_od_en Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[8].pull_en Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[8].pull_select Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[8].keep_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[8].schmitt_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[8].od_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[8].input_disable Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[8].slew_rate[1:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[8].drive_strength[0] Yes Yes *T40,*T41,*T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[8].drive_strength[3:1] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[9].invert Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[9].virt_od_en Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[9].pull_en Yes Yes T40,T41,T42 Yes T45,T46,T47 OUTPUT
mio_attr_o[9].pull_select Yes Yes T40,T41,T42 Yes T45,T46,T47 OUTPUT
mio_attr_o[9].keep_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[9].schmitt_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[9].od_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[9].input_disable Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[9].slew_rate[1:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[9].drive_strength[0] Yes Yes *T40,*T41,*T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[9].drive_strength[3:1] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[10].invert Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[10].virt_od_en Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[10].pull_en Yes Yes T40,T41,T42 Yes T45,T24,T25 OUTPUT
mio_attr_o[10].pull_select Yes Yes T40,T41,T42 Yes T45,T24,T25 OUTPUT
mio_attr_o[10].keep_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[10].schmitt_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[10].od_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[10].input_disable Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[10].slew_rate[1:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[10].drive_strength[0] Yes Yes *T40,*T41,*T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[10].drive_strength[3:1] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[11].invert Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[11].virt_od_en Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[11].pull_en Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[11].pull_select Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[11].keep_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[11].schmitt_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[11].od_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[11].input_disable Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[11].slew_rate[1:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[11].drive_strength[0] Yes Yes *T40,*T41,*T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[11].drive_strength[3:1] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[12].invert Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[12].virt_od_en Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[12].pull_en Yes Yes T40,T41,T42 Yes T45,T24,T25 OUTPUT
mio_attr_o[12].pull_select Yes Yes T40,T41,T42 Yes T45,T24,T25 OUTPUT
mio_attr_o[12].keep_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[12].schmitt_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[12].od_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[12].input_disable Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[12].slew_rate[1:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[12].drive_strength[0] Yes Yes *T40,*T41,*T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[12].drive_strength[3:1] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[13].invert Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[13].virt_od_en Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[13].pull_en Yes Yes T40,T41,T42 Yes T45,T46,T47 OUTPUT
mio_attr_o[13].pull_select Yes Yes T40,T41,T42 Yes T45,T46,T47 OUTPUT
mio_attr_o[13].keep_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[13].schmitt_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[13].od_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[13].input_disable Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[13].slew_rate[1:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[13].drive_strength[0] Yes Yes *T40,*T41,*T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[13].drive_strength[3:1] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[14].invert Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[14].virt_od_en Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[14].pull_en Yes Yes T40,T41,T42 Yes T45,T46,T47 OUTPUT
mio_attr_o[14].pull_select Yes Yes T40,T41,T42 Yes T45,T46,T47 OUTPUT
mio_attr_o[14].keep_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[14].schmitt_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[14].od_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[14].input_disable Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[14].slew_rate[1:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[14].drive_strength[0] Yes Yes *T40,*T41,*T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[14].drive_strength[3:1] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[15].invert Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[15].virt_od_en Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[15].pull_en Yes Yes T40,T41,T42 Yes T45,T46,T47 OUTPUT
mio_attr_o[15].pull_select Yes Yes T40,T41,T42 Yes T45,T46,T47 OUTPUT
mio_attr_o[15].keep_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[15].schmitt_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[15].od_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[15].input_disable Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[15].slew_rate[1:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[15].drive_strength[0] Yes Yes *T40,*T41,*T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[15].drive_strength[3:1] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[16].invert Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[16].virt_od_en Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[16].pull_en Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[16].pull_select Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[16].keep_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[16].schmitt_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[16].od_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[16].input_disable Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[16].slew_rate[1:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[16].drive_strength[0] Yes Yes *T40,*T41,*T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[16].drive_strength[3:1] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[17].invert Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[17].virt_od_en Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[17].pull_en Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[17].pull_select Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[17].keep_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[17].schmitt_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[17].od_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[17].input_disable Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[17].slew_rate[1:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[17].drive_strength[0] Yes Yes *T40,*T41,*T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[17].drive_strength[3:1] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[18].invert Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[18].virt_od_en Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[18].pull_en Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[18].pull_select Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[18].keep_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[18].schmitt_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[18].od_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[18].input_disable Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[18].slew_rate[1:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[18].drive_strength[0] Yes Yes *T40,*T41,*T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[18].drive_strength[3:1] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[19].invert Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[19].virt_od_en Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[19].pull_en Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[19].pull_select Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[19].keep_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[19].schmitt_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[19].od_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[19].input_disable Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[19].slew_rate[1:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[19].drive_strength[0] Yes Yes *T40,*T41,*T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[19].drive_strength[3:1] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[20].invert Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[20].virt_od_en Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[20].pull_en Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[20].pull_select Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[20].keep_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[20].schmitt_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[20].od_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[20].input_disable Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[20].slew_rate[1:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[20].drive_strength[0] Yes Yes *T40,*T41,*T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[20].drive_strength[3:1] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[21].invert Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[21].virt_od_en Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[21].pull_en Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[21].pull_select Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[21].keep_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[21].schmitt_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[21].od_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[21].input_disable Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[21].slew_rate[1:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[21].drive_strength[0] Yes Yes *T40,*T41,*T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[21].drive_strength[3:1] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[22].invert Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[22].virt_od_en Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[22].pull_en Yes Yes T54,T55,T56 Yes T4,T6,T57 OUTPUT
mio_attr_o[22].pull_select Yes Yes T4,T6,T57 Yes T4,T6,T57 OUTPUT
mio_attr_o[22].keep_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[22].schmitt_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[22].od_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[22].input_disable Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[22].slew_rate[1:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[22].drive_strength[0] Yes Yes *T40,*T41,*T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[22].drive_strength[3:1] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[23].invert Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[23].virt_od_en Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[23].pull_en Yes Yes T54,T55,T56 Yes T4,T6,T57 OUTPUT
mio_attr_o[23].pull_select Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[23].keep_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[23].schmitt_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[23].od_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[23].input_disable Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[23].slew_rate[1:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[23].drive_strength[0] Yes Yes *T40,*T41,*T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[23].drive_strength[3:1] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[24].invert Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[24].virt_od_en Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[24].pull_en Yes Yes T54,T55,T56 Yes T4,T6,T57 OUTPUT
mio_attr_o[24].pull_select Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[24].keep_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[24].schmitt_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[24].od_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[24].input_disable Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[24].slew_rate[1:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[24].drive_strength[0] Yes Yes *T40,*T41,*T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[24].drive_strength[3:1] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[25].invert Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[25].virt_od_en Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[25].pull_en Yes Yes T5,T43,T19 Yes T5,T43,T44 OUTPUT
mio_attr_o[25].pull_select Yes Yes T5,T43,T19 Yes T5,T43,T44 OUTPUT
mio_attr_o[25].keep_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[25].schmitt_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[25].od_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[25].input_disable Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[25].slew_rate[1:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[25].drive_strength[0] Yes Yes *T40,*T41,*T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[25].drive_strength[3:1] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[26].invert Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[26].virt_od_en Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[26].pull_en Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[26].pull_select Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[26].keep_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[26].schmitt_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[26].od_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[26].input_disable Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[26].slew_rate[1:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[26].drive_strength[0] Yes Yes *T40,*T41,*T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[26].drive_strength[3:1] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[27].invert Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[27].virt_od_en Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[27].pull_en Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[27].pull_select Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[27].keep_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[27].schmitt_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[27].od_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[27].input_disable Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[27].slew_rate[1:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[27].drive_strength[0] Yes Yes *T40,*T41,*T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[27].drive_strength[3:1] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[28].invert Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[28].virt_od_en Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[28].pull_en Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[28].pull_select Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[28].keep_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[28].schmitt_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[28].od_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[28].input_disable Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[28].slew_rate[1:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[28].drive_strength[0] Yes Yes *T40,*T41,*T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[28].drive_strength[3:1] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[29].invert Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[29].virt_od_en Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[29].pull_en Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[29].pull_select Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[29].keep_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[29].schmitt_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[29].od_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[29].input_disable Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[29].slew_rate[1:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[29].drive_strength[0] Yes Yes *T40,*T41,*T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[29].drive_strength[3:1] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[30].invert Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[30].virt_od_en Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[30].pull_en Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[30].pull_select Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[30].keep_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[30].schmitt_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[30].od_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[30].input_disable Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[30].slew_rate[1:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[30].drive_strength[0] Yes Yes *T40,*T41,*T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[30].drive_strength[3:1] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[31].invert Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[31].virt_od_en Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[31].pull_en Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[31].pull_select Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[31].keep_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[31].schmitt_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[31].od_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[31].input_disable Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[31].slew_rate[1:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[31].drive_strength[0] Yes Yes *T40,*T41,*T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[31].drive_strength[3:1] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[32].invert Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[32].virt_od_en Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[32].pull_en Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[32].pull_select Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[32].keep_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[32].schmitt_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[32].od_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[32].input_disable Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[32].slew_rate[1:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[32].drive_strength[0] Yes Yes *T40,*T41,*T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[32].drive_strength[3:1] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[33].invert Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[33].virt_od_en Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[33].pull_en Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[33].pull_select Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[33].keep_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[33].schmitt_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[33].od_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[33].input_disable Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[33].slew_rate[1:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[33].drive_strength[0] Yes Yes *T40,*T41,*T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[33].drive_strength[3:1] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[34].invert Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[34].virt_od_en Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[34].pull_en Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[34].pull_select Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[34].keep_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[34].schmitt_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[34].od_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[34].input_disable Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[34].slew_rate[1:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[34].drive_strength[0] Yes Yes *T40,*T41,*T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[34].drive_strength[3:1] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[35].invert Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[35].virt_od_en Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[35].pull_en Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[35].pull_select Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[35].keep_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[35].schmitt_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[35].od_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[35].input_disable Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[35].slew_rate[1:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[35].drive_strength[0] Yes Yes *T40,*T41,*T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[35].drive_strength[3:1] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[36].invert Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[36].virt_od_en Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[36].pull_en Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[36].pull_select Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[36].keep_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[36].schmitt_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[36].od_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[36].input_disable Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[36].slew_rate[1:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[36].drive_strength[0] Yes Yes *T40,*T41,*T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[36].drive_strength[3:1] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[37].invert Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[37].virt_od_en Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[37].pull_en Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[37].pull_select Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[37].keep_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[37].schmitt_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[37].od_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[37].input_disable Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[37].slew_rate[1:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[37].drive_strength[0] Yes Yes *T40,*T41,*T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[37].drive_strength[3:1] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[38].invert Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[38].virt_od_en Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[38].pull_en Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[38].pull_select Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[38].keep_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[38].schmitt_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[38].od_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[38].input_disable Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[38].slew_rate[1:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[38].drive_strength[0] Yes Yes *T40,*T41,*T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[38].drive_strength[3:1] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[39].invert Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[39].virt_od_en Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[39].pull_en Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[39].pull_select Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[39].keep_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[39].schmitt_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[39].od_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[39].input_disable Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[39].slew_rate[1:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[39].drive_strength[0] Yes Yes *T40,*T41,*T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[39].drive_strength[3:1] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[40].invert Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[40].virt_od_en Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[40].pull_en Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[40].pull_select Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[40].keep_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[40].schmitt_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[40].od_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[40].input_disable Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[40].slew_rate[1:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[40].drive_strength[0] Yes Yes *T40,*T41,*T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[40].drive_strength[3:1] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[41].invert Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[41].virt_od_en Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[41].pull_en Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[41].pull_select Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[41].keep_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[41].schmitt_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[41].od_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[41].input_disable Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[41].slew_rate[1:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[41].drive_strength[0] Yes Yes *T40,*T41,*T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[41].drive_strength[3:1] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[42].invert Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[42].virt_od_en Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[42].pull_en Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[42].pull_select Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[42].keep_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[42].schmitt_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[42].od_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[42].input_disable Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[42].slew_rate[1:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[42].drive_strength[0] Yes Yes *T40,*T41,*T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[42].drive_strength[3:1] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[43].invert Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[43].virt_od_en Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[43].pull_en Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[43].pull_select Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[43].keep_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[43].schmitt_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[43].od_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[43].input_disable Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[43].slew_rate[1:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[43].drive_strength[0] Yes Yes *T40,*T41,*T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[43].drive_strength[3:1] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[44].invert Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[44].virt_od_en Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[44].pull_en Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[44].pull_select Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[44].keep_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[44].schmitt_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[44].od_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[44].input_disable Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[44].slew_rate[1:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[44].drive_strength[0] Yes Yes *T40,*T41,*T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[44].drive_strength[3:1] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[45].invert Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[45].virt_od_en Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[45].pull_en Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[45].pull_select Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[45].keep_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[45].schmitt_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[45].od_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[45].input_disable Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[45].slew_rate[1:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[45].drive_strength[0] Yes Yes *T40,*T41,*T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[45].drive_strength[3:1] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[46].invert Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[46].virt_od_en Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[46].pull_en Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[46].pull_select Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[46].keep_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[46].schmitt_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[46].od_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[46].input_disable Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[46].slew_rate[1:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
mio_attr_o[46].drive_strength[0] Yes Yes *T40,*T41,*T42 Yes T40,T41,T42 OUTPUT
mio_attr_o[46].drive_strength[3:1] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[0].invert Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
dio_attr_o[0].virt_od_en Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
dio_attr_o[0].pull_en Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
dio_attr_o[0].pull_select Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
dio_attr_o[0].keep_en No No No OUTPUT
dio_attr_o[0].schmitt_en No No No OUTPUT
dio_attr_o[0].od_en No No No OUTPUT
dio_attr_o[0].input_disable Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
dio_attr_o[0].slew_rate[1:0] No No No OUTPUT
dio_attr_o[0].drive_strength[0] Yes Yes *T5,*T43,*T19 Yes T5,T43,T44 OUTPUT
dio_attr_o[0].drive_strength[3:1] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[1].invert Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
dio_attr_o[1].virt_od_en Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
dio_attr_o[1].pull_en Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
dio_attr_o[1].pull_select Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
dio_attr_o[1].keep_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[1].schmitt_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[1].od_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[1].input_disable Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
dio_attr_o[1].slew_rate[1:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[1].drive_strength[0] Yes Yes *T5,*T43,*T19 Yes T5,T43,T44 OUTPUT
dio_attr_o[1].drive_strength[3:1] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[2].invert Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
dio_attr_o[2].virt_od_en Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
dio_attr_o[2].pull_en Yes Yes T40,T41,T42 Yes T45,T24,T25 OUTPUT
dio_attr_o[2].pull_select Yes Yes T40,T41,T42 Yes T45,T24,T25 OUTPUT
dio_attr_o[2].keep_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[2].schmitt_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[2].od_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[2].input_disable Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
dio_attr_o[2].slew_rate[1:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[2].drive_strength[0] Yes Yes *T40,*T41,*T42 Yes T40,T41,T42 OUTPUT
dio_attr_o[2].drive_strength[3:1] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[3].invert Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
dio_attr_o[3].virt_od_en Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
dio_attr_o[3].pull_en Yes Yes T40,T41,T42 Yes T45,T24,T25 OUTPUT
dio_attr_o[3].pull_select Yes Yes T40,T41,T42 Yes T45,T24,T25 OUTPUT
dio_attr_o[3].keep_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[3].schmitt_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[3].od_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[3].input_disable Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
dio_attr_o[3].slew_rate[1:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[3].drive_strength[0] Yes Yes *T40,*T41,*T42 Yes T40,T41,T42 OUTPUT
dio_attr_o[3].drive_strength[3:1] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[4].invert Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
dio_attr_o[4].virt_od_en Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
dio_attr_o[4].pull_en Yes Yes T40,T41,T42 Yes T45,T24,T25 OUTPUT
dio_attr_o[4].pull_select Yes Yes T40,T41,T42 Yes T45,T24,T25 OUTPUT
dio_attr_o[4].keep_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[4].schmitt_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[4].od_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[4].input_disable Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
dio_attr_o[4].slew_rate[1:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[4].drive_strength[0] Yes Yes *T40,*T41,*T42 Yes T40,T41,T42 OUTPUT
dio_attr_o[4].drive_strength[3:1] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[5].invert Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
dio_attr_o[5].virt_od_en Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
dio_attr_o[5].pull_en Yes Yes T40,T41,T42 Yes T45,T24,T25 OUTPUT
dio_attr_o[5].pull_select Yes Yes T40,T41,T42 Yes T45,T24,T25 OUTPUT
dio_attr_o[5].keep_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[5].schmitt_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[5].od_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[5].input_disable Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
dio_attr_o[5].slew_rate[1:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[5].drive_strength[0] Yes Yes *T40,*T41,*T42 Yes T40,T41,T42 OUTPUT
dio_attr_o[5].drive_strength[3:1] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[6].invert Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
dio_attr_o[6].virt_od_en Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
dio_attr_o[6].pull_en Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
dio_attr_o[6].pull_select Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
dio_attr_o[6].keep_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[6].schmitt_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[6].od_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[6].input_disable Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
dio_attr_o[6].slew_rate[1:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[6].drive_strength[0] Yes Yes *T40,*T41,*T42 Yes T40,T41,T42 OUTPUT
dio_attr_o[6].drive_strength[3:1] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[7].invert Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
dio_attr_o[7].virt_od_en Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
dio_attr_o[7].pull_en Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
dio_attr_o[7].pull_select Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
dio_attr_o[7].keep_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[7].schmitt_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[7].od_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[7].input_disable Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
dio_attr_o[7].slew_rate[1:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[7].drive_strength[0] Yes Yes *T40,*T41,*T42 Yes T40,T41,T42 OUTPUT
dio_attr_o[7].drive_strength[3:1] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[8].invert Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
dio_attr_o[8].virt_od_en Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
dio_attr_o[8].pull_en Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
dio_attr_o[8].pull_select Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
dio_attr_o[8].keep_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[8].schmitt_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[8].od_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[8].input_disable Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
dio_attr_o[8].slew_rate[1:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[8].drive_strength[0] Yes Yes *T40,*T41,*T42 Yes T40,T41,T42 OUTPUT
dio_attr_o[8].drive_strength[3:1] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[9].invert Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
dio_attr_o[9].virt_od_en Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
dio_attr_o[9].pull_en Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
dio_attr_o[9].pull_select Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
dio_attr_o[9].keep_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[9].schmitt_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[9].od_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[9].input_disable Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
dio_attr_o[9].slew_rate[1:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[9].drive_strength[0] Yes Yes *T40,*T41,*T42 Yes T40,T41,T42 OUTPUT
dio_attr_o[9].drive_strength[3:1] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[10].invert Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
dio_attr_o[10].virt_od_en Yes Yes T40,T41,T42 Yes T48,T49,T50 OUTPUT
dio_attr_o[10].pull_en Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
dio_attr_o[10].pull_select Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
dio_attr_o[10].keep_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[10].schmitt_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[10].od_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[10].input_disable Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
dio_attr_o[10].slew_rate[1:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[10].drive_strength[0] Yes Yes *T40,*T41,*T42 Yes T40,T41,T42 OUTPUT
dio_attr_o[10].drive_strength[3:1] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[11].invert Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
dio_attr_o[11].virt_od_en Yes Yes T40,T41,T42 Yes T48,T49,T50 OUTPUT
dio_attr_o[11].pull_en Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
dio_attr_o[11].pull_select Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
dio_attr_o[11].keep_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[11].schmitt_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[11].od_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[11].input_disable Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
dio_attr_o[11].slew_rate[1:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[11].drive_strength[0] Yes Yes *T40,*T41,*T42 Yes T40,T41,T42 OUTPUT
dio_attr_o[11].drive_strength[3:1] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[12].invert Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
dio_attr_o[12].virt_od_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[12].pull_en Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
dio_attr_o[12].pull_select Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
dio_attr_o[12].keep_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[12].schmitt_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[12].od_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[12].input_disable Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
dio_attr_o[12].slew_rate[1:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[12].drive_strength[0] No No No OUTPUT
dio_attr_o[12].drive_strength[3:1] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[13].invert Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
dio_attr_o[13].virt_od_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[13].pull_en Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
dio_attr_o[13].pull_select Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
dio_attr_o[13].keep_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[13].schmitt_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[13].od_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[13].input_disable Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
dio_attr_o[13].slew_rate[1:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[13].drive_strength[0] No No No OUTPUT
dio_attr_o[13].drive_strength[3:1] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[14].invert Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
dio_attr_o[14].virt_od_en Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
dio_attr_o[14].pull_en Yes Yes T40,T41,T42 Yes T45,T46,T47 OUTPUT
dio_attr_o[14].pull_select Yes Yes T40,T41,T42 Yes T45,T46,T47 OUTPUT
dio_attr_o[14].keep_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[14].schmitt_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[14].od_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[14].input_disable Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
dio_attr_o[14].slew_rate[1:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[14].drive_strength[0] Yes Yes *T40,*T41,*T42 Yes T40,T41,T42 OUTPUT
dio_attr_o[14].drive_strength[3:1] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[15].invert Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
dio_attr_o[15].virt_od_en Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
dio_attr_o[15].pull_en Yes Yes T40,T41,T42 Yes T45,T46,T47 OUTPUT
dio_attr_o[15].pull_select Yes Yes T40,T41,T42 Yes T45,T46,T47 OUTPUT
dio_attr_o[15].keep_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[15].schmitt_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[15].od_en[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[15].input_disable Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
dio_attr_o[15].slew_rate[1:0] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
dio_attr_o[15].drive_strength[0] Yes Yes *T40,*T41,*T42 Yes T40,T41,T42 OUTPUT
dio_attr_o[15].drive_strength[3:1] Excluded Excluded Excluded OUTPUT [UNR] Tie offs.
adc_req_o.pd Yes Yes T115,T1,T116 Yes T115,T1,T116 OUTPUT
adc_req_o.channel_sel[1:0] Yes Yes T115,T1,T116 Yes T115,T1,T116 OUTPUT
adc_rsp_i.data_valid Yes Yes T115,T1,T116 Yes T115,T1,T116 INPUT
adc_rsp_i.data[9:0] Yes Yes T115,T1,T3 Yes T115,T1,T3 INPUT
ast_edn_req_i.edn_req Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
ast_edn_rsp_o.edn_bus[31:0] Yes Yes T4,T5,T43 Yes T4,T5,T43 OUTPUT
ast_edn_rsp_o.edn_fips Yes Yes T117,T118 Yes T43,T119,T120 OUTPUT
ast_edn_rsp_o.edn_ack Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
ast_lc_dft_en_o[3:0] Yes Yes T43,T20,T62 Yes T5,T6,T43 OUTPUT
obs_ctrl_i.obmen[3:0] Excluded Excluded Excluded INPUT [LOW_RISK] Covered via connectivity. Cannot be covered in open source DV due to behavioral models of AST and flash. Must be covered in vendor closed source DV.
obs_ctrl_i.obmsl[3:0] Excluded Excluded Excluded INPUT [LOW_RISK] Covered via connectivity. Cannot be covered in open source DV due to behavioral models of AST and flash. Must be covered in vendor closed source DV.
obs_ctrl_i.obgsl[3:0] Excluded Excluded Excluded INPUT [LOW_RISK] Covered via connectivity. Cannot be covered in open source DV due to behavioral models of AST and flash. Must be covered in vendor closed source DV.
ram_1p_cfg_i.rf_cfg.cfg[3:0] Excluded Excluded Excluded INPUT [LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
ram_1p_cfg_i.rf_cfg.cfg_en[0:0] Excluded Excluded Excluded INPUT [LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
ram_1p_cfg_i.rf_cfg.test No No No INPUT
ram_1p_cfg_i.ram_cfg.cfg[3:0] Excluded Excluded Excluded INPUT [LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
ram_1p_cfg_i.ram_cfg.cfg_en[0:0] Excluded Excluded Excluded INPUT [LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
ram_1p_cfg_i.ram_cfg.test No No No INPUT
spi_ram_2p_cfg_i.b_ram_lcfg.cfg[3:0] No No No INPUT
spi_ram_2p_cfg_i.b_ram_lcfg.cfg_en No No No INPUT
spi_ram_2p_cfg_i.b_ram_lcfg.test No No No INPUT
spi_ram_2p_cfg_i.a_ram_lcfg.cfg[3:0] No No No INPUT
spi_ram_2p_cfg_i.a_ram_lcfg.cfg_en No No No INPUT
spi_ram_2p_cfg_i.a_ram_lcfg.test No No No INPUT
spi_ram_2p_cfg_i.b_ram_fcfg.cfg[3:0] No No No INPUT
spi_ram_2p_cfg_i.b_ram_fcfg.cfg_en No No No INPUT
spi_ram_2p_cfg_i.b_ram_fcfg.test No No No INPUT
spi_ram_2p_cfg_i.a_ram_fcfg.cfg[3:0] No No No INPUT
spi_ram_2p_cfg_i.a_ram_fcfg.cfg_en No No No INPUT
spi_ram_2p_cfg_i.a_ram_fcfg.test No No No INPUT
usb_ram_1p_cfg_i.rf_cfg.cfg[3:0] No No No INPUT
usb_ram_1p_cfg_i.rf_cfg.cfg_en No No No INPUT
usb_ram_1p_cfg_i.rf_cfg.test No No No INPUT
usb_ram_1p_cfg_i.ram_cfg.cfg[3:0] No No No INPUT
usb_ram_1p_cfg_i.ram_cfg.cfg_en No No No INPUT
usb_ram_1p_cfg_i.ram_cfg.test No No No INPUT
rom_cfg_i.cfg[3:0] Excluded Excluded Excluded INPUT [LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
rom_cfg_i.cfg_en[0:0] Excluded Excluded Excluded INPUT [LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
rom_cfg_i.test No No No INPUT
clk_main_jitter_en_o[3:0] Yes Yes T43,T17,T121 Yes T43,T122,T119 OUTPUT
io_clk_byp_req_o[3:0] Yes Yes T20,T63,T123 Yes T20,T63,T123 OUTPUT
io_clk_byp_ack_i[3:0] Yes Yes T20,T63,T123 Yes T20,T63,T123 INPUT
all_clk_byp_req_o[3:0] Yes Yes T44,T124,T125 Yes T44,T124,T125 OUTPUT
all_clk_byp_ack_i[3:0] Yes Yes T44,T124,T125 Yes T44,T124,T125 INPUT
hi_speed_sel_o[3:0] Yes Yes T5,T43,T44 Yes T4,T5,T6 OUTPUT
div_step_down_req_i[3:0] Yes Yes T44,T20,T63 Yes T44,T20,T63 INPUT
calib_rdy_i[3:0] Yes Yes T4,T5,T6 Yes T5,T43,T19 INPUT
flash_bist_enable_i[3:0] Unreachable Unreachable Unreachable INPUT
flash_power_down_h_i Yes Yes T4,T5,T6 Yes T64,T126,T127 INPUT
flash_power_ready_h_i No No Yes T4,T5,T6 INPUT
flash_test_mode_a_io[1:0] Excluded Excluded Excluded INOUT [LOW_RISK] Covered via connectivity. Cannot be covered in open source DV due to behavioral models of AST and flash. Must be covered in vendor closed source DV.
flash_test_voltage_h_io[0:0] Excluded Excluded Excluded INOUT [LOW_RISK] Covered via connectivity. Cannot be covered in open source DV due to behavioral models of AST and flash. Must be covered in vendor closed source DV.
flash_obs_o[7:0] Unreachable Unreachable Unreachable OUTPUT
es_rng_req_o.rng_enable Yes Yes T5,T43,T19 Yes T4,T5,T6 OUTPUT
es_rng_rsp_i.rng_b[3:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
es_rng_rsp_i.rng_valid Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
es_rng_fips_o Yes Yes T128,T129,T130 Yes T43,T131,T128 OUTPUT
ast_tl_req_o.d_ready Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
ast_tl_req_o.a_user.data_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
ast_tl_req_o.a_user.cmd_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
ast_tl_req_o.a_user.instr_type[3:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
ast_tl_req_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
ast_tl_req_o.a_data[31:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
ast_tl_req_o.a_mask[3:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
ast_tl_req_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
ast_tl_req_o.a_source[5:0] Yes Yes *T58,*T70,*T71 Yes T58,T70,T71 OUTPUT
ast_tl_req_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
ast_tl_req_o.a_size[1:0] Yes Yes T78,T79,T80 Yes T78,T79,T80 OUTPUT
ast_tl_req_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
ast_tl_req_o.a_opcode[2:0] Yes Yes T58,T71,T81 Yes T58,T71,T81 OUTPUT
ast_tl_req_o.a_valid Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
ast_tl_rsp_i.a_ready Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
ast_tl_rsp_i.d_error Yes Yes T78,T80,T82 Yes T78,T79,T80 INPUT
ast_tl_rsp_i.d_user.data_intg[6:0] Yes Yes T78,T79,T132 Yes T78,T79,T132 INPUT
ast_tl_rsp_i.d_user.rsp_intg[6:0] Yes Yes T5,T43,T19 Yes T4,T5,T6 INPUT
ast_tl_rsp_i.d_data[31:0] Yes Yes T5,T43,T19 Yes T4,T5,T6 INPUT
ast_tl_rsp_i.d_sink Yes Yes T78,T79,T80 Yes T78,T79,T80 INPUT
ast_tl_rsp_i.d_source[5:0] Yes Yes *T79,*T80,*T82 Yes T78,T79,T80 INPUT
ast_tl_rsp_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
ast_tl_rsp_i.d_size[1:0] Yes Yes T78,T79,T80 Yes T78,T79,T80 INPUT
ast_tl_rsp_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
ast_tl_rsp_i.d_opcode[0] Yes Yes *T78,*T79,*T132 Yes T78,T79,T132 INPUT
ast_tl_rsp_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
ast_tl_rsp_i.d_valid Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
dft_strap_test_o.straps[1:0] No No Yes T67,T68,T69 OUTPUT
dft_strap_test_o.valid Yes Yes T43,T20,T62 Yes T5,T6,T43 OUTPUT
dft_hold_tap_sel_i Unreachable Unreachable Unreachable INPUT
usb_dp_pullup_en_o Yes Yes T1,T3,T7 Yes T29,T30,T1 OUTPUT
usb_dn_pullup_en_o Yes Yes T75,T76,T77 Yes T75,T76,T77 OUTPUT
pwrmgr_ast_req_o.usb_clk_en Yes Yes T5,T18,T19 Yes T4,T5,T6 OUTPUT
pwrmgr_ast_req_o.io_clk_en Yes Yes T5,T18,T19 Yes T4,T5,T6 OUTPUT
pwrmgr_ast_req_o.core_clk_en Yes Yes T5,T18,T19 Yes T4,T5,T6 OUTPUT
pwrmgr_ast_req_o.slow_clk_en No No No OUTPUT
pwrmgr_ast_req_o.pwr_clamp Yes Yes T4,T5,T6 Yes T5,T19,T20 OUTPUT
pwrmgr_ast_req_o.pwr_clamp_env Yes Yes T4,T5,T6 Yes T5,T19,T20 OUTPUT
pwrmgr_ast_req_o.main_pd_n Yes Yes T64,T126,T127 Yes T64,T126,T127 OUTPUT
pwrmgr_ast_rsp_i.main_pok Yes Yes T5,T19,T20 Yes T4,T5,T6 INPUT
pwrmgr_ast_rsp_i.usb_clk_val Yes Yes T5,T44,T18 Yes T4,T5,T6 INPUT
pwrmgr_ast_rsp_i.io_clk_val Yes Yes T5,T44,T18 Yes T4,T5,T6 INPUT
pwrmgr_ast_rsp_i.core_clk_val Yes Yes T5,T44,T18 Yes T4,T5,T6 INPUT
pwrmgr_ast_rsp_i.slow_clk_val Yes Yes T44,T124,T125 Yes T4,T5,T6 INPUT
otp_ctrl_otp_ast_pwr_seq_o.pwr_seq[1:0] No No No OUTPUT
otp_ctrl_otp_ast_pwr_seq_h_i.pwr_seq_h[0] No No No INPUT
otp_ctrl_otp_ast_pwr_seq_h_i.pwr_seq_h[1] Yes Yes T4,T5,T6 Yes T64,T126,T127 INPUT
otp_ext_voltage_h_io[0:0] Excluded Excluded Excluded INOUT [LOW_RISK] Covered via connectivity. Cannot be covered in open source DV due to behavioral models of AST and OTP. Must be covered in vendor closed source DV.
otp_obs_o[7:0] Unreachable Unreachable Unreachable OUTPUT
por_n_i[1:0] Yes Yes T5,T19,T20 Yes T4,T5,T6 INPUT
fpga_info_i[31:0] Unreachable Unreachable Unreachable INPUT
sensor_ctrl_ast_alert_req_i.alerts[0].n Yes Yes T133,T134,T7 Yes T134,T7,T103 INPUT
sensor_ctrl_ast_alert_req_i.alerts[0].p Yes Yes T134,T7,T103 Yes T133,T134,T7 INPUT
sensor_ctrl_ast_alert_req_i.alerts[1].n Yes Yes T133,T135,T136 Yes T135,T137,T138 INPUT
sensor_ctrl_ast_alert_req_i.alerts[1].p Yes Yes T135,T137,T138 Yes T133,T135,T136 INPUT
sensor_ctrl_ast_alert_req_i.alerts[2].n Yes Yes T133,T139,T134 Yes T139,T134,T140 INPUT
sensor_ctrl_ast_alert_req_i.alerts[2].p Yes Yes T139,T134,T140 Yes T133,T139,T134 INPUT
sensor_ctrl_ast_alert_req_i.alerts[3].n No Yes T133,T136,T141 No INPUT
sensor_ctrl_ast_alert_req_i.alerts[3].p No No Yes T133,T136,T141 INPUT
sensor_ctrl_ast_alert_req_i.alerts[4].n Yes Yes T133,T135,T134 Yes T135,T134,T140 INPUT
sensor_ctrl_ast_alert_req_i.alerts[4].p Yes Yes T135,T134,T140 Yes T133,T135,T134 INPUT
sensor_ctrl_ast_alert_req_i.alerts[5].n Yes Yes T133,T142,T136 Yes T142,T137,T138 INPUT
sensor_ctrl_ast_alert_req_i.alerts[5].p Yes Yes T142,T137,T138 Yes T133,T142,T136 INPUT
sensor_ctrl_ast_alert_req_i.alerts[6].n Yes Yes T133,T139,T136 Yes T139,T137,T138 INPUT
sensor_ctrl_ast_alert_req_i.alerts[6].p Yes Yes T139,T137,T138 Yes T133,T139,T136 INPUT
sensor_ctrl_ast_alert_req_i.alerts[7].n Yes Yes T133,T136,T141 Yes T138,T143,T144 INPUT
sensor_ctrl_ast_alert_req_i.alerts[7].p Yes Yes T138,T143,T144 Yes T133,T136,T141 INPUT
sensor_ctrl_ast_alert_req_i.alerts[8].n Yes Yes T133,T136,T141 Yes T137,T144 INPUT
sensor_ctrl_ast_alert_req_i.alerts[8].p Yes Yes T137,T144 Yes T133,T136,T141 INPUT
sensor_ctrl_ast_alert_req_i.alerts[9].n Yes Yes T133,T136,T141 Yes T137,T138,T144 INPUT
sensor_ctrl_ast_alert_req_i.alerts[9].p Yes Yes T137,T138,T144 Yes T133,T136,T141 INPUT
sensor_ctrl_ast_alert_req_i.alerts[10].n Yes Yes T133,T136,T141 Yes T143 INPUT
sensor_ctrl_ast_alert_req_i.alerts[10].p Yes Yes T143 Yes T133,T136,T141 INPUT
sensor_ctrl_ast_alert_rsp_o.alerts_trig[0].n Yes Yes T133,T134,T7 Yes T133,T134,T7 OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_trig[0].p Yes Yes T133,T134,T7 Yes T133,T134,T7 OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_trig[1].n Yes Yes T133,T135,T136 Yes T133,T135,T136 OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_trig[1].p Yes Yes T133,T135,T136 Yes T133,T135,T136 OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_trig[2].n Yes Yes T133,T139,T134 Yes T133,T139,T134 OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_trig[2].p Yes Yes T133,T139,T134 Yes T133,T139,T134 OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_trig[3].n Yes Yes T133,T136,T141 Yes T133,T136,T141 OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_trig[3].p Yes Yes T133,T136,T141 Yes T133,T136,T141 OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_trig[4].n Yes Yes T133,T135,T134 Yes T133,T135,T134 OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_trig[4].p Yes Yes T133,T135,T134 Yes T133,T135,T134 OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_trig[5].n Yes Yes T133,T142,T136 Yes T133,T142,T136 OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_trig[5].p Yes Yes T133,T142,T136 Yes T133,T142,T136 OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_trig[6].n Yes Yes T133,T139,T136 Yes T133,T139,T136 OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_trig[6].p Yes Yes T133,T139,T136 Yes T133,T139,T136 OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_trig[7].n Yes Yes T133,T136,T141 Yes T133,T136,T141 OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_trig[7].p Yes Yes T133,T136,T141 Yes T133,T136,T141 OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_trig[8].n Yes Yes T133,T136,T141 Yes T133,T136,T141 OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_trig[8].p Yes Yes T133,T136,T141 Yes T133,T136,T141 OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_trig[9].n Yes Yes T133,T136,T141 Yes T133,T136,T141 OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_trig[9].p Yes Yes T133,T136,T141 Yes T133,T136,T141 OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_trig[10].n Yes Yes T133,T136,T141 Yes T133,T136,T141 OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_trig[10].p Yes Yes T133,T136,T141 Yes T133,T136,T141 OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_ack[0].n Yes Yes T133,T134,T7 Yes T133,T134,T7 OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_ack[0].p Yes Yes T133,T134,T7 Yes T133,T134,T7 OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_ack[1].n Yes Yes T133,T135,T136 Yes T133,T135,T136 OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_ack[1].p Yes Yes T133,T135,T136 Yes T133,T135,T136 OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_ack[2].n Yes Yes T133,T139,T134 Yes T133,T139,T134 OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_ack[2].p Yes Yes T133,T139,T134 Yes T133,T139,T134 OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_ack[3].n Yes Yes T133,T136,T141 Yes T133,T136,T141 OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_ack[3].p Yes Yes T133,T136,T141 Yes T133,T136,T141 OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_ack[4].n Yes Yes T133,T135,T134 Yes T133,T135,T134 OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_ack[4].p Yes Yes T133,T135,T134 Yes T133,T135,T134 OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_ack[5].n Yes Yes T133,T142,T136 Yes T133,T142,T136 OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_ack[5].p Yes Yes T133,T142,T136 Yes T133,T142,T136 OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_ack[6].n Yes Yes T133,T139,T136 Yes T133,T139,T136 OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_ack[6].p Yes Yes T133,T139,T136 Yes T133,T139,T136 OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_ack[7].n Yes Yes T133,T136,T141 Yes T133,T136,T141 OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_ack[7].p Yes Yes T133,T136,T141 Yes T133,T136,T141 OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_ack[8].n Yes Yes T133,T136,T141 Yes T133,T136,T141 OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_ack[8].p Yes Yes T133,T136,T141 Yes T133,T136,T141 OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_ack[9].n Yes Yes T133,T136,T141 Yes T133,T136,T141 OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_ack[9].p Yes Yes T133,T136,T141 Yes T133,T136,T141 OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_ack[10].n Yes Yes T133,T136,T141 Yes T133,T136,T141 OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_ack[10].p Yes Yes T133,T136,T141 Yes T133,T136,T141 OUTPUT
sensor_ctrl_ast_status_i.io_pok[1:0] Yes Yes T101,T145,T146 Yes T4,T5,T6 INPUT
ast2pinmux_i[8:0] Unreachable Unreachable Unreachable INPUT
ast_init_done_i[3:0] Yes Yes T4,T5,T6 Yes T5,T43,T19 INPUT
sensor_ctrl_manual_pad_attr_o[0].invert No No No OUTPUT
sensor_ctrl_manual_pad_attr_o[0].virt_od_en No No No OUTPUT
sensor_ctrl_manual_pad_attr_o[0].pull_en Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
sensor_ctrl_manual_pad_attr_o[0].pull_select Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
sensor_ctrl_manual_pad_attr_o[0].keep_en No No No OUTPUT
sensor_ctrl_manual_pad_attr_o[0].schmitt_en No No No OUTPUT
sensor_ctrl_manual_pad_attr_o[0].od_en No No No OUTPUT
sensor_ctrl_manual_pad_attr_o[0].input_disable Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
sensor_ctrl_manual_pad_attr_o[0].slew_rate[1:0] No No No OUTPUT
sensor_ctrl_manual_pad_attr_o[0].drive_strength[3:0] No No No OUTPUT
sensor_ctrl_manual_pad_attr_o[1].invert No No No OUTPUT
sensor_ctrl_manual_pad_attr_o[1].virt_od_en No No No OUTPUT
sensor_ctrl_manual_pad_attr_o[1].pull_en Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
sensor_ctrl_manual_pad_attr_o[1].pull_select Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
sensor_ctrl_manual_pad_attr_o[1].keep_en No No No OUTPUT
sensor_ctrl_manual_pad_attr_o[1].schmitt_en No No No OUTPUT
sensor_ctrl_manual_pad_attr_o[1].od_en No No No OUTPUT
sensor_ctrl_manual_pad_attr_o[1].input_disable Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
sensor_ctrl_manual_pad_attr_o[1].slew_rate[1:0] No No No OUTPUT
sensor_ctrl_manual_pad_attr_o[1].drive_strength[3:0] No No No OUTPUT
sensor_ctrl_manual_pad_attr_o[2].invert No No No OUTPUT
sensor_ctrl_manual_pad_attr_o[2].virt_od_en No No No OUTPUT
sensor_ctrl_manual_pad_attr_o[2].pull_en Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
sensor_ctrl_manual_pad_attr_o[2].pull_select Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
sensor_ctrl_manual_pad_attr_o[2].keep_en No No No OUTPUT
sensor_ctrl_manual_pad_attr_o[2].schmitt_en No No No OUTPUT
sensor_ctrl_manual_pad_attr_o[2].od_en No No No OUTPUT
sensor_ctrl_manual_pad_attr_o[2].input_disable Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
sensor_ctrl_manual_pad_attr_o[2].slew_rate[1:0] No No No OUTPUT
sensor_ctrl_manual_pad_attr_o[2].drive_strength[3:0] No No No OUTPUT
sensor_ctrl_manual_pad_attr_o[3].invert No No No OUTPUT
sensor_ctrl_manual_pad_attr_o[3].virt_od_en No No No OUTPUT
sensor_ctrl_manual_pad_attr_o[3].pull_en Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
sensor_ctrl_manual_pad_attr_o[3].pull_select Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
sensor_ctrl_manual_pad_attr_o[3].keep_en No No No OUTPUT
sensor_ctrl_manual_pad_attr_o[3].schmitt_en No No No OUTPUT
sensor_ctrl_manual_pad_attr_o[3].od_en No No No OUTPUT
sensor_ctrl_manual_pad_attr_o[3].input_disable Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
sensor_ctrl_manual_pad_attr_o[3].slew_rate[1:0] No No No OUTPUT
sensor_ctrl_manual_pad_attr_o[3].drive_strength[3:0] No No No OUTPUT
sck_monitor_o Yes Yes T24,T25,T147 Yes T21,T22,T24 OUTPUT
usbdev_usb_rx_d_i Yes Yes T29,T34,T35 Yes T29,T34,T35 INPUT
usbdev_usb_tx_d_o Yes Yes T29,T30,T1 Yes T29,T30,T1 OUTPUT
usbdev_usb_tx_se0_o Yes Yes T29,T34,T35 Yes T29,T34,T35 OUTPUT
usbdev_usb_tx_use_d_se0_o Yes Yes T148,T132,T149 Yes T148,T132,T149 OUTPUT
usbdev_usb_rx_enable_o Yes Yes T76,T137,T138 Yes T29,T34,T35 OUTPUT
usbdev_usb_ref_val_o Yes Yes T34,T35,T150 Yes T29,T34,T35 OUTPUT
usbdev_usb_ref_pulse_o Yes Yes T29,T34,T35 Yes T29,T34,T35 OUTPUT
clk_main_i Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
clk_io_i Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
clk_usb_i Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
clk_aon_i Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
clks_ast_o.clk_usb_peri Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
clks_ast_o.clk_io_peri Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
clks_ast_o.clk_io_div2_peri Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
clks_ast_o.clk_io_div4_peri Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
clks_ast_o.clk_io_div4_timers Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
clks_ast_o.clk_main_secure Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
clks_ast_o.clk_io_div4_secure Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
clks_ast_o.clk_io_div2_infra Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
clks_ast_o.clk_io_infra Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
clks_ast_o.clk_usb_infra Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
clks_ast_o.clk_main_infra Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
clks_ast_o.clk_io_div4_infra Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
clks_ast_o.clk_main_otbn Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
clks_ast_o.clk_main_kmac Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
clks_ast_o.clk_main_hmac Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
clks_ast_o.clk_main_aes Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
clks_ast_o.clk_aon_timers Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
clks_ast_o.clk_aon_peri Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
clks_ast_o.clk_aon_secure Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
clks_ast_o.clk_io_div2_powerup Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
clks_ast_o.clk_usb_powerup Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
clks_ast_o.clk_io_powerup Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
clks_ast_o.clk_main_powerup Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
clks_ast_o.clk_aon_powerup Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
clks_ast_o.clk_io_div4_powerup Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
rsts_ast_o.rst_i2c2_n[0] No No No OUTPUT
rsts_ast_o.rst_i2c2_n[1] Yes Yes T5,T43,T19 Yes T4,T5,T6 OUTPUT
rsts_ast_o.rst_i2c1_n[0] No No No OUTPUT
rsts_ast_o.rst_i2c1_n[1] Yes Yes T5,T43,T19 Yes T4,T5,T6 OUTPUT
rsts_ast_o.rst_i2c0_n[0] No No No OUTPUT
rsts_ast_o.rst_i2c0_n[1] Yes Yes T5,T43,T19 Yes T4,T5,T6 OUTPUT
rsts_ast_o.rst_usb_aon_n[0] No No No OUTPUT
rsts_ast_o.rst_usb_aon_n[1] Yes Yes T5,T43,T19 Yes T4,T5,T6 OUTPUT
rsts_ast_o.rst_usb_n[0] No No No OUTPUT
rsts_ast_o.rst_usb_n[1] Yes Yes T5,T43,T19 Yes T4,T5,T6 OUTPUT
rsts_ast_o.rst_spi_host1_n[0] No No No OUTPUT
rsts_ast_o.rst_spi_host1_n[1] Yes Yes T5,T43,T19 Yes T4,T5,T6 OUTPUT
rsts_ast_o.rst_spi_host0_n[0] No No No OUTPUT
rsts_ast_o.rst_spi_host0_n[1] Yes Yes T5,T43,T19 Yes T4,T5,T6 OUTPUT
rsts_ast_o.rst_spi_device_n[0] No No No OUTPUT
rsts_ast_o.rst_spi_device_n[1] Yes Yes T5,T43,T19 Yes T4,T5,T6 OUTPUT
rsts_ast_o.rst_sys_io_div4_n[0] Yes Yes *T5,*T43,*T19 Yes T4,T5,T6 OUTPUT
rsts_ast_o.rst_sys_io_div4_n[1] No No No OUTPUT
rsts_ast_o.rst_sys_n[0] No No No OUTPUT
rsts_ast_o.rst_sys_n[1] Yes Yes T5,T43,T19 Yes T4,T5,T6 OUTPUT
rsts_ast_o.rst_lc_usb_n[1:0] Yes Yes T5,T43,T19 Yes T4,T5,T6 OUTPUT
rsts_ast_o.rst_lc_io_div4_n[1:0] Yes Yes T5,T43,T19 Yes T4,T5,T6 OUTPUT
rsts_ast_o.rst_lc_io_div4_shadowed_n[1:0] Yes Yes T5,T43,T19 Yes T4,T5,T6 OUTPUT
rsts_ast_o.rst_lc_io_div2_n[1:0] Yes Yes T5,T43,T19 Yes T4,T5,T6 OUTPUT
rsts_ast_o.rst_lc_io_n[1:0] Yes Yes T5,T43,T19 Yes T4,T5,T6 OUTPUT
rsts_ast_o.rst_lc_aon_n[0] Yes Yes *T5,*T43,*T19 Yes T4,T5,T6 OUTPUT
rsts_ast_o.rst_lc_aon_n[1] No No No OUTPUT
rsts_ast_o.rst_lc_n[1:0] Yes Yes T5,T43,T19 Yes T4,T5,T6 OUTPUT
rsts_ast_o.rst_lc_shadowed_n[1:0] Yes Yes T5,T43,T19 Yes T4,T5,T6 OUTPUT
rsts_ast_o.rst_por_usb_n[0] Yes Yes *T5,*T19,*T20 Yes T4,T5,T6 OUTPUT
rsts_ast_o.rst_por_usb_n[1] No No No OUTPUT
rsts_ast_o.rst_por_io_div4_n[0] Yes Yes *T5,*T19,*T20 Yes T4,T5,T6 OUTPUT
rsts_ast_o.rst_por_io_div4_n[1] No No No OUTPUT
rsts_ast_o.rst_por_io_div2_n[0] Yes Yes *T5,*T19,*T20 Yes T4,T5,T6 OUTPUT
rsts_ast_o.rst_por_io_div2_n[1] No No No OUTPUT
rsts_ast_o.rst_por_io_n[0] Yes Yes *T5,*T19,*T20 Yes T4,T5,T6 OUTPUT
rsts_ast_o.rst_por_io_n[1] No No No OUTPUT
rsts_ast_o.rst_por_n[0] Yes Yes *T5,*T19,*T20 Yes T4,T5,T6 OUTPUT
rsts_ast_o.rst_por_n[1] No No No OUTPUT
rsts_ast_o.rst_por_aon_n[1:0] Yes Yes T5,T19,T20 Yes T4,T5,T6 OUTPUT
scan_rst_ni Unreachable Unreachable Unreachable INPUT
scan_en_i Unreachable Unreachable Unreachable INPUT
scanmode_i[3:0] Unreachable Unreachable Unreachable INPUT

*Tests covering at least one bit in the range

Assert Coverage for Instance : tb.dut.top_earlgrey
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
scanmodeKnown 525316944 525316944 0 0


scanmodeKnown
NameAttemptsReal SuccessesFailuresIncomplete
Total 525316944 525316944 0 0
T4 223564 223564 0 0
T5 398161 398161 0 0
T6 129945 129945 0 0
T16 183981 183981 0 0
T17 76093 76093 0 0
T18 175576 175576 0 0
T43 389326 389326 0 0
T44 194386 194386 0 0
T88 102619 102619 0 0
T89 82258 82258 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%