Unified Coverage Report :: Module :: clkmgr

Module : clkmgr

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_clkmgr_0.1/rtl/clkmgr.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_clkmgr_aon	100.00			100.00

---

Module Instance : tb.dut.top_earlgrey.u_clkmgr_aon

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.31	90.68		89.25			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Toggle Coverage for Module : clkmgr

	Total	Covered	Percent
Totals	110	110	100.00
Total Bits	612	612	100.00
Total Bits 0->1	306	306	100.00
Total Bits 1->0	306	306	100.00

Ports	110	110	100.00
Port Bits	612	612	100.00
Port Bits 0->1	306	306	100.00
Port Bits 1->0	306	306	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_ni	Yes	Yes	T5,T43,T19	Yes	T4,T5,T6	INPUT
rst_shadowed_ni	Yes	Yes	T5,T43,T19	Yes	T4,T5,T6	INPUT
clk_main_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_main_ni	Yes	Yes	T5,T43,T19	Yes	T4,T5,T6	INPUT
clk_io_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_io_ni	Yes	Yes	T5,T43,T19	Yes	T4,T5,T6	INPUT
clk_usb_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_usb_ni	Yes	Yes	T5,T43,T19	Yes	T4,T5,T6	INPUT
clk_aon_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_aon_ni	Yes	Yes	T5,T43,T19	Yes	T4,T5,T6	INPUT
rst_io_div2_ni	Yes	Yes	T5,T43,T19	Yes	T4,T5,T6	INPUT
rst_io_div4_ni	Yes	Yes	T5,T43,T19	Yes	T4,T5,T6	INPUT
rst_root_ni	Yes	Yes	T5,T19,T20	Yes	T4,T5,T6	INPUT
rst_root_main_ni	Yes	Yes	T5,T19,T20	Yes	T4,T5,T6	INPUT
rst_root_io_ni	Yes	Yes	T5,T19,T20	Yes	T4,T5,T6	INPUT
rst_root_io_div2_ni	Yes	Yes	T5,T19,T20	Yes	T4,T5,T6	INPUT
rst_root_io_div4_ni	Yes	Yes	T5,T19,T20	Yes	T4,T5,T6	INPUT
rst_root_usb_ni	Yes	Yes	T5,T19,T20	Yes	T4,T5,T6	INPUT
tl_i.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T44,T16,T196	Yes	T44,T16,T196	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T43,T44,T16	Yes	T43,T44,T16	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[6:0]	Yes	Yes	*T78,*T79,*T80	Yes	T78,T79,T80	INPUT
tl_i.a_address[16:7]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[21:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[22]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[29:23]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T58,*T70,*T71	Yes	T58,T70,T71	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T58,T71,T81	Yes	T58,T71,T81	INPUT
tl_i.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_o.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_o.d_error	Yes	Yes	T79,T80,T82	Yes	T79,T80,T82	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T44,T16,T196	Yes	T44,T16,T196	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T5,T43,T44	Yes	T4,T5,T6	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T5,T43,T44	Yes	T4,T5,T6	OUTPUT
tl_o.d_sink	Yes	Yes	T78,T79,T80	Yes	T78,T80,T82	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T80,*T82,*T83	Yes	T156,T157,T158	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T44,*T16,*T196	Yes	T44,T16,T196	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T85,T743,T86	Yes	T85,T743,T86	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	INPUT
alert_rx_i[1].ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[1].ack_p	Yes	Yes	T163,T744,T85	Yes	T163,T744,T85	INPUT
alert_rx_i[1].ping_n	Yes	Yes	T163,T85,T86	Yes	T163,T85,T86	INPUT
alert_rx_i[1].ping_p	Yes	Yes	T163,T85,T86	Yes	T163,T85,T86	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T85,T743,T86	Yes	T85,T743,T86	OUTPUT
alert_tx_o[1].alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o[1].alert_p	Yes	Yes	T163,T744,T85	Yes	T163,T744,T85	OUTPUT
pwr_i.usb_ip_clk_en	Yes	Yes	T5,T43,T18	Yes	T4,T5,T6	INPUT
pwr_i.io_ip_clk_en	Yes	Yes	T5,T43,T18	Yes	T4,T5,T6	INPUT
pwr_i.main_ip_clk_en	Yes	Yes	T5,T43,T18	Yes	T4,T5,T6	INPUT
pwr_o.usb_status	Yes	Yes	T5,T43,T18	Yes	T4,T5,T6	OUTPUT
pwr_o.io_status	Yes	Yes	T5,T43,T18	Yes	T4,T5,T6	OUTPUT
pwr_o.main_status	Yes	Yes	T5,T43,T18	Yes	T4,T5,T6	OUTPUT
scanmode_i[3:0]	Unreachable	Unreachable		Unreachable		INPUT
lc_hw_debug_en_i[3:0]	Yes	Yes	T43,T20,T62	Yes	T4,T5,T6	INPUT
lc_clk_byp_req_i[3:0]	Yes	Yes	T20,T63,T123	Yes	T20,T63,T123	INPUT
lc_clk_byp_ack_o[3:0]	Yes	Yes	T20,T63,T123	Yes	T20,T63,T123	OUTPUT
io_clk_byp_req_o[3:0]	Yes	Yes	T20,T63,T123	Yes	T20,T63,T123	OUTPUT
io_clk_byp_ack_i[3:0]	Yes	Yes	T20,T63,T123	Yes	T20,T63,T123	INPUT
all_clk_byp_req_o[3:0]	Yes	Yes	T44,T124,T125	Yes	T44,T124,T125	OUTPUT
all_clk_byp_ack_i[3:0]	Yes	Yes	T44,T124,T125	Yes	T44,T124,T125	INPUT
hi_speed_sel_o[3:0]	Yes	Yes	T5,T43,T44	Yes	T4,T5,T6	OUTPUT
calib_rdy_i[3:0]	Yes	Yes	T4,T5,T6	Yes	T5,T43,T19	INPUT
jitter_en_o[3:0]	Yes	Yes	T43,T17,T121	Yes	T43,T122,T119	OUTPUT
div_step_down_req_i[3:0]	Yes	Yes	T44,T20,T63	Yes	T44,T20,T63	INPUT
cg_en_o.usb_peri[3:0]	Yes	Yes	T5,T43,T18	Yes	T4,T5,T6	OUTPUT
cg_en_o.io_peri[3:0]	Yes	Yes	T5,T43,T18	Yes	T4,T5,T6	OUTPUT
cg_en_o.io_div2_peri[3:0]	Yes	Yes	T5,T43,T18	Yes	T4,T5,T6	OUTPUT
cg_en_o.io_div4_peri[3:0]	Yes	Yes	T5,T43,T18	Yes	T4,T5,T6	OUTPUT
cg_en_o.io_div4_timers[3:0]	Yes	Yes	T5,T43,T18	Yes	T4,T5,T6	OUTPUT
cg_en_o.main_secure[3:0]	Yes	Yes	T5,T43,T18	Yes	T4,T5,T6	OUTPUT
cg_en_o.io_div4_secure[3:0]	Yes	Yes	T5,T43,T18	Yes	T4,T5,T6	OUTPUT
cg_en_o.io_div2_infra[3:0]	Yes	Yes	T5,T43,T18	Yes	T4,T5,T6	OUTPUT
cg_en_o.io_infra[3:0]	Yes	Yes	T5,T43,T18	Yes	T4,T5,T6	OUTPUT
cg_en_o.usb_infra[3:0]	Yes	Yes	T5,T43,T18	Yes	T4,T5,T6	OUTPUT
cg_en_o.main_infra[3:0]	Yes	Yes	T5,T43,T18	Yes	T4,T5,T6	OUTPUT
cg_en_o.io_div4_infra[3:0]	Yes	Yes	T5,T43,T18	Yes	T4,T5,T6	OUTPUT
cg_en_o.main_otbn[3:0]	Yes	Yes	T5,T43,T18	Yes	T4,T5,T6	OUTPUT
cg_en_o.main_kmac[3:0]	Yes	Yes	T5,T43,T18	Yes	T4,T5,T6	OUTPUT
cg_en_o.main_hmac[3:0]	Yes	Yes	T5,T43,T18	Yes	T4,T5,T6	OUTPUT
cg_en_o.main_aes[3:0]	Yes	Yes	T5,T43,T18	Yes	T4,T5,T6	OUTPUT
cg_en_o.aon_timers[3:0]	Unreachable	Unreachable		Unreachable		OUTPUT
cg_en_o.aon_peri[3:0]	Unreachable	Unreachable		Unreachable		OUTPUT
cg_en_o.aon_secure[3:0]	Unreachable	Unreachable		Unreachable		OUTPUT
cg_en_o.io_div2_powerup[3:0]	Unreachable	Unreachable		Unreachable		OUTPUT
cg_en_o.usb_powerup[3:0]	Unreachable	Unreachable		Unreachable		OUTPUT
cg_en_o.io_powerup[3:0]	Unreachable	Unreachable		Unreachable		OUTPUT
cg_en_o.main_powerup[3:0]	Unreachable	Unreachable		Unreachable		OUTPUT
cg_en_o.aon_powerup[3:0]	Unreachable	Unreachable		Unreachable		OUTPUT
cg_en_o.io_div4_powerup[3:0]	Unreachable	Unreachable		Unreachable		OUTPUT
clocks_o.clk_usb_peri	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
clocks_o.clk_io_peri	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
clocks_o.clk_io_div2_peri	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
clocks_o.clk_io_div4_peri	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
clocks_o.clk_io_div4_timers	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
clocks_o.clk_main_secure	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
clocks_o.clk_io_div4_secure	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
clocks_o.clk_io_div2_infra	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
clocks_o.clk_io_infra	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
clocks_o.clk_usb_infra	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
clocks_o.clk_main_infra	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
clocks_o.clk_io_div4_infra	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
clocks_o.clk_main_otbn	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
clocks_o.clk_main_kmac	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
clocks_o.clk_main_hmac	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
clocks_o.clk_main_aes	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
clocks_o.clk_aon_timers	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
clocks_o.clk_aon_peri	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
clocks_o.clk_aon_secure	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
clocks_o.clk_io_div2_powerup	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
clocks_o.clk_usb_powerup	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
clocks_o.clk_io_powerup	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
clocks_o.clk_main_powerup	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
clocks_o.clk_aon_powerup	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
clocks_o.clk_io_div4_powerup	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT

*Tests covering at least one bit in the range