Unified Coverage Report :: Module :: uart

Module : uart

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_uart_0.1/rtl/uart.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_uart0	100.00			100.00
tb.dut.top_earlgrey.u_uart1	100.00			100.00
tb.dut.top_earlgrey.u_uart2	100.00			100.00
tb.dut.top_earlgrey.u_uart3	100.00			100.00

---

Module Instance : tb.dut.top_earlgrey.u_uart0

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.31	90.68		89.25			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_uart1

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.31	90.68		89.25			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_uart2

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.31	90.68		89.25			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_uart3

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.31	90.68		89.25			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Toggle Coverage for Module : uart

	Total	Covered	Percent
Totals	40	40	100.00
Total Bits	308	308	100.00
Total Bits 0->1	154	154	100.00
Total Bits 1->0	154	154	100.00

Ports	40	40	100.00
Port Bits	308	308	100.00
Port Bits 0->1	154	154	100.00
Port Bits 1->0	154	154	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_ni	Yes	Yes	T5,T43,T19	Yes	T4,T5,T6	INPUT
tl_i.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T4,T6,T57	Yes	T4,T6,T57	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T4,T6,T57	Yes	T4,T6,T57	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T78,*T79,*T80	Yes	T78,T79,T80	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17:16]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[29:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T58,*T70,*T71	Yes	T58,T70,T71	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T58,T71,T81	Yes	T58,T71,T81	INPUT
tl_i.a_valid	Yes	Yes	T4,T6,T57	Yes	T4,T6,T57	INPUT
tl_o.a_ready	Yes	Yes	T4,T6,T57	Yes	T4,T6,T57	OUTPUT
tl_o.d_error	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T4,T6,T57	Yes	T4,T6,T57	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T4,T6,T57	Yes	T4,T6,T57	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T4,T6,T57	Yes	T4,T6,T57	OUTPUT
tl_o.d_sink	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T745,*T456,*T148	Yes	T745,T456,T148	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T4,*T6,*T57	Yes	T4,T6,T57	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T4,T6,T57	Yes	T4,T6,T57	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T752,T163,T744	Yes	T752,T163,T744	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T163,T744,T85	Yes	T163,T85,T86	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T163,T85,T86	Yes	T163,T744,T85	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T752,T163,T744	Yes	T752,T163,T744	OUTPUT
cio_rx_i	Yes	Yes	T5,T43,T19	Yes	T5,T43,T44	INPUT
cio_tx_o	Yes	Yes	T4,T6,T57	Yes	T4,T6,T57	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T151,T243,T100	Yes	T151,T243,T100	OUTPUT
intr_tx_empty_o	Yes	Yes	T151,T100,T303	Yes	T151,T100,T303	OUTPUT
intr_rx_watermark_o	Yes	Yes	T151,T100,T303	Yes	T151,T100,T303	OUTPUT
intr_tx_done_o	Yes	Yes	T151,T100,T303	Yes	T151,T100,T303	OUTPUT
intr_rx_overflow_o	Yes	Yes	T151,T100,T303	Yes	T151,T100,T303	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T323,T324,T325	Yes	T323,T324,T325	OUTPUT
intr_rx_break_err_o	Yes	Yes	T323,T324,T325	Yes	T323,T324,T325	OUTPUT
intr_rx_timeout_o	Yes	Yes	T323,T324,T325	Yes	T323,T324,T325	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T323,T324,T325	Yes	T323,T324,T325	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart0

	Total	Covered	Percent
Totals	40	40	100.00
Total Bits	304	304	100.00
Total Bits 0->1	152	152	100.00
Total Bits 1->0	152	152	100.00

Ports	40	40	100.00
Port Bits	304	304	100.00
Port Bits 0->1	152	152	100.00
Port Bits 1->0	152	152	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_ni	Yes	Yes	T5,T43,T19	Yes	T4,T5,T6	INPUT
tl_i.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T4,T6,T57	Yes	T4,T6,T57	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T4,T6,T57	Yes	T4,T6,T57	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T78,*T79,*T80	Yes	T78,T79,T80	INPUT
tl_i.a_address[29:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T58,*T70,*T71	Yes	T58,T70,T71	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T58,T71,T81	Yes	T58,T71,T81	INPUT
tl_i.a_valid	Yes	Yes	T4,T6,T57	Yes	T4,T6,T57	INPUT
tl_o.a_ready	Yes	Yes	T4,T6,T57	Yes	T4,T6,T57	OUTPUT
tl_o.d_error	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T4,T6,T57	Yes	T4,T6,T57	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T4,T6,T57	Yes	T4,T6,T57	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T4,T6,T57	Yes	T4,T6,T57	OUTPUT
tl_o.d_sink	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T745,*T456,*T148	Yes	T745,T456,T148	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T4,*T6,*T57	Yes	T4,T6,T57	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T4,T6,T57	Yes	T4,T6,T57	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T85,T86,T166	Yes	T85,T86,T166	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T85,T86,T166	Yes	T85,T86,T166	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T85,T86,T166	Yes	T85,T86,T166	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T85,T86,T166	Yes	T85,T86,T166	OUTPUT
cio_rx_i	Yes	Yes	T5,T43,T19	Yes	T5,T43,T44	INPUT
cio_tx_o	Yes	Yes	T4,T6,T57	Yes	T4,T6,T57	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T243,T100,T303	Yes	T243,T100,T303	OUTPUT
intr_tx_empty_o	Yes	Yes	T100,T303,T336	Yes	T100,T303,T336	OUTPUT
intr_rx_watermark_o	Yes	Yes	T100,T303,T336	Yes	T100,T303,T336	OUTPUT
intr_tx_done_o	Yes	Yes	T100,T303,T266	Yes	T100,T303,T266	OUTPUT
intr_rx_overflow_o	Yes	Yes	T100,T303,T266	Yes	T100,T303,T266	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T323,T324,T325	Yes	T323,T324,T325	OUTPUT
intr_rx_break_err_o	Yes	Yes	T323,T324,T325	Yes	T323,T324,T325	OUTPUT
intr_rx_timeout_o	Yes	Yes	T323,T324,T325	Yes	T323,T324,T325	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T323,T324,T325	Yes	T323,T324,T325	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart1

	Total	Covered	Percent
Totals	40	40	100.00
Total Bits	306	306	100.00
Total Bits 0->1	153	153	100.00
Total Bits 1->0	153	153	100.00

Ports	40	40	100.00
Port Bits	306	306	100.00
Port Bits 0->1	153	153	100.00
Port Bits 1->0	153	153	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_ni	Yes	Yes	T5,T43,T19	Yes	T4,T5,T6	INPUT
tl_i.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T295,T297,T114	Yes	T295,T297,T114	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T295,T297,T114	Yes	T295,T297,T114	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T78,*T79,*T80	Yes	T78,T79,T80	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[16]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[29:17]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T58,*T70,*T71	Yes	T58,T70,T71	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T58,T71,T81	Yes	T58,T71,T81	INPUT
tl_i.a_valid	Yes	Yes	T295,T297,T114	Yes	T295,T297,T114	INPUT
tl_o.a_ready	Yes	Yes	T295,T297,T114	Yes	T295,T297,T114	OUTPUT
tl_o.d_error	Yes	Yes	T79,T80,T82	Yes	T78,T79,T80	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T295,T297,T114	Yes	T295,T297,T114	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T295,T297,T114	Yes	T295,T297,T114	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T295,T297,T114	Yes	T295,T297,T114	OUTPUT
tl_o.d_sink	Yes	Yes	T79,T80,T82	Yes	T79,T80,T82	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T148,*T79,*T80	Yes	T148,T78,T79	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T79,T80,T82	Yes	T79,T80,T82	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T295,*T297,*T114	Yes	T295,T297,T114	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T295,T297,T114	Yes	T295,T297,T114	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T744,T85,T86	Yes	T744,T85,T86	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T744,T85,T86	Yes	T85,T86,T166	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T85,T86,T166	Yes	T744,T85,T86	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T744,T85,T86	Yes	T744,T85,T86	OUTPUT
cio_rx_i	Yes	Yes	T45,T295,T297	Yes	T21,T45,T22	INPUT
cio_tx_o	Yes	Yes	T295,T297,T114	Yes	T295,T297,T114	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T295,T297,T114	Yes	T295,T297,T114	OUTPUT
intr_tx_empty_o	Yes	Yes	T295,T297,T114	Yes	T295,T297,T114	OUTPUT
intr_rx_watermark_o	Yes	Yes	T295,T297,T114	Yes	T295,T297,T114	OUTPUT
intr_tx_done_o	Yes	Yes	T295,T297,T114	Yes	T295,T297,T114	OUTPUT
intr_rx_overflow_o	Yes	Yes	T295,T297,T114	Yes	T295,T297,T114	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T323,T324,T325	Yes	T323,T324,T325	OUTPUT
intr_rx_break_err_o	Yes	Yes	T323,T324,T325	Yes	T323,T324,T325	OUTPUT
intr_rx_timeout_o	Yes	Yes	T323,T324,T325	Yes	T323,T324,T325	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T323,T324,T325	Yes	T323,T324,T325	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart2

	Total	Covered	Percent
Totals	40	40	100.00
Total Bits	306	306	100.00
Total Bits 0->1	153	153	100.00
Total Bits 1->0	153	153	100.00

Ports	40	40	100.00
Port Bits	306	306	100.00
Port Bits 0->1	153	153	100.00
Port Bits 1->0	153	153	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_ni	Yes	Yes	T5,T43,T19	Yes	T4,T5,T6	INPUT
tl_i.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T151,T152,T337	Yes	T151,T152,T337	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T151,T152,T337	Yes	T151,T152,T337	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T78,*T79,*T80	Yes	T78,T79,T80	INPUT
tl_i.a_address[16:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[29:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T58,*T70,*T71	Yes	T58,T70,T71	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T58,T71,T81	Yes	T58,T71,T81	INPUT
tl_i.a_valid	Yes	Yes	T151,T152,T337	Yes	T151,T152,T337	INPUT
tl_o.a_ready	Yes	Yes	T151,T152,T337	Yes	T151,T152,T337	OUTPUT
tl_o.d_error	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T151,T152,T337	Yes	T151,T152,T337	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T151,T152,T337	Yes	T151,T152,T337	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T151,T152,T337	Yes	T151,T152,T337	OUTPUT
tl_o.d_sink	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T148,*T78,*T79	Yes	T148,T78,T79	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T151,*T152,*T337	Yes	T151,T152,T337	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T151,T152,T337	Yes	T151,T152,T337	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T85,T753,T86	Yes	T85,T753,T86	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T85,T86,T166	Yes	T85,T86,T166	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T85,T86,T166	Yes	T85,T86,T166	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T85,T753,T86	Yes	T85,T753,T86	OUTPUT
cio_rx_i	Yes	Yes	T151,T152,T337	Yes	T151,T152,T337	INPUT
cio_tx_o	Yes	Yes	T151,T152,T337	Yes	T151,T152,T337	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T151,T152,T337	Yes	T151,T152,T337	OUTPUT
intr_tx_empty_o	Yes	Yes	T151,T152,T337	Yes	T151,T152,T337	OUTPUT
intr_rx_watermark_o	Yes	Yes	T151,T152,T337	Yes	T151,T152,T337	OUTPUT
intr_tx_done_o	Yes	Yes	T151,T152,T337	Yes	T151,T152,T337	OUTPUT
intr_rx_overflow_o	Yes	Yes	T151,T152,T337	Yes	T151,T152,T337	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T323,T324,T325	Yes	T323,T324,T325	OUTPUT
intr_rx_break_err_o	Yes	Yes	T323,T324,T325	Yes	T323,T324,T325	OUTPUT
intr_rx_timeout_o	Yes	Yes	T323,T324,T325	Yes	T323,T324,T325	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T323,T324,T325	Yes	T323,T324,T325	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart3

	Total	Covered	Percent
Totals	40	40	100.00
Total Bits	308	308	100.00
Total Bits 0->1	154	154	100.00
Total Bits 1->0	154	154	100.00

Ports	40	40	100.00
Port Bits	308	308	100.00
Port Bits 0->1	154	154	100.00
Port Bits 1->0	154	154	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_ni	Yes	Yes	T5,T43,T19	Yes	T4,T5,T6	INPUT
tl_i.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T16,T27,T265	Yes	T16,T27,T265	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T16,T27,T265	Yes	T16,T27,T265	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T78,*T79,*T80	Yes	T78,T79,T80	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17:16]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[29:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T58,*T70,*T71	Yes	T58,T70,T71	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T58,T71,T81	Yes	T58,T71,T81	INPUT
tl_i.a_valid	Yes	Yes	T16,T27,T265	Yes	T16,T27,T265	INPUT
tl_o.a_ready	Yes	Yes	T16,T27,T265	Yes	T16,T27,T265	OUTPUT
tl_o.d_error	Yes	Yes	T78,T79,T80	Yes	T79,T80,T82	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T16,T27,T265	Yes	T16,T27,T265	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T16,T27,T265	Yes	T16,T27,T265	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T16,T27,T265	Yes	T16,T27,T265	OUTPUT
tl_o.d_sink	Yes	Yes	T78,T80,T82	Yes	T78,T79,T80	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T148,*T80,*T82	Yes	T148,T78,T79	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T80,T82	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T16,*T27,*T265	Yes	T16,T27,T265	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T16,T27,T265	Yes	T16,T27,T265	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T752,T163,T279	Yes	T752,T163,T279	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T163,T85,T86	Yes	T163,T85,T86	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T163,T85,T86	Yes	T163,T85,T86	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T752,T163,T279	Yes	T752,T163,T279	OUTPUT
cio_rx_i	Yes	Yes	T16,T27,T265	Yes	T16,T27,T265	INPUT
cio_tx_o	Yes	Yes	T16,T27,T265	Yes	T16,T27,T265	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T16,T27,T265	Yes	T16,T27,T265	OUTPUT
intr_tx_empty_o	Yes	Yes	T16,T27,T265	Yes	T16,T27,T265	OUTPUT
intr_rx_watermark_o	Yes	Yes	T16,T27,T265	Yes	T16,T27,T265	OUTPUT
intr_tx_done_o	Yes	Yes	T16,T27,T265	Yes	T16,T27,T265	OUTPUT
intr_rx_overflow_o	Yes	Yes	T16,T27,T265	Yes	T16,T27,T265	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T323,T324,T325	Yes	T323,T324,T325	OUTPUT
intr_rx_break_err_o	Yes	Yes	T323,T324,T325	Yes	T323,T324,T325	OUTPUT
intr_rx_timeout_o	Yes	Yes	T323,T324,T325	Yes	T323,T324,T325	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T323,T324,T325	Yes	T323,T324,T325	OUTPUT

*Tests covering at least one bit in the range