Unified Coverage Report :: Module :: xbar_main

Module : xbar_main

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_top_earlgrey_xbar_main_0.1/rtl/autogen/xbar_main.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_xbar_main	100.00			100.00

---

Module Instance : tb.dut.top_earlgrey.u_xbar_main

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.31	90.68		89.25			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Toggle Coverage for Module : xbar_main

	Total	Covered	Percent
Totals	550	550	100.00
Total Bits	6824	6824	100.00
Total Bits 0->1	3412	3412	100.00
Total Bits 1->0	3412	3412	100.00

Ports	550	550	100.00
Port Bits	6824	6824	100.00
Port Bits 0->1	3412	3412	100.00
Port Bits 1->0	3412	3412	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_main_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
clk_fixed_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
clk_usb_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
clk_spi_host0_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
clk_spi_host1_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
rst_main_ni	Yes	Yes	T5,T43,T19	Yes	T4,T5,T6	INPUT
rst_fixed_ni	Yes	Yes	T5,T43,T19	Yes	T4,T5,T6	INPUT
rst_usb_ni	Yes	Yes	T5,T43,T19	Yes	T4,T5,T6	INPUT
rst_spi_host0_ni	Yes	Yes	T5,T43,T19	Yes	T4,T5,T6	INPUT
rst_spi_host1_ni	Yes	Yes	T5,T43,T19	Yes	T4,T5,T6	INPUT
tl_rv_core_ibex__corei_i.d_ready	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_rv_core_ibex__corei_i.a_user.data_intg[6:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_rv_core_ibex__corei_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rv_core_ibex__corei_i.a_user.instr_type[3:0]	Yes	Yes	T79,T80,T82	Yes	T79,T80,T82	INPUT
tl_rv_core_ibex__corei_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_data[31:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_rv_core_ibex__corei_i.a_mask[3:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_rv_core_ibex__corei_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_source[5:0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_rv_core_ibex__corei_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_rv_core_ibex__corei_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_opcode[2:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_rv_core_ibex__corei_i.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rv_core_ibex__corei_o.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__corei_o.d_error	Yes	Yes	T54,T220,T70	Yes	T54,T220,T70	OUTPUT
tl_rv_core_ibex__corei_o.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__corei_o.d_user.rsp_intg[6:0]	Yes	Yes	T54,T220,T70	Yes	T54,T220,T70	OUTPUT
tl_rv_core_ibex__corei_o.d_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__corei_o.d_sink	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_rv_core_ibex__corei_o.d_source[5:0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__corei_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__corei_o.d_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_rv_core_ibex__corei_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__corei_o.d_opcode[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__corei_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__corei_o.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__cored_i.d_ready	Yes	Yes	T58,T71,T81	Yes	T58,T71,T81	INPUT
tl_rv_core_ibex__cored_i.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rv_core_ibex__cored_i.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rv_core_ibex__cored_i.a_user.instr_type[3:0]	Yes	Yes	T58,T81,T79	Yes	T58,T81,T79	INPUT
tl_rv_core_ibex__cored_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rv_core_ibex__cored_i.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rv_core_ibex__cored_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_source[5:0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_rv_core_ibex__cored_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_size[1:0]	Yes	Yes	T58,T81,T78	Yes	T58,T81,T78	INPUT
tl_rv_core_ibex__cored_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_opcode[2:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rv_core_ibex__cored_i.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rv_core_ibex__cored_o.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__cored_o.d_error	Yes	Yes	T64,T54,T65	Yes	T64,T54,T65	OUTPUT
tl_rv_core_ibex__cored_o.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__cored_o.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__cored_o.d_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__cored_o.d_sink	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_rv_core_ibex__cored_o.d_source[5:0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__cored_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cored_o.d_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_rv_core_ibex__cored_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cored_o.d_opcode[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__cored_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cored_o.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_dm__sba_i.d_ready	Yes	Yes	T43,T20,T62	Yes	T4,T5,T6	INPUT
tl_rv_dm__sba_i.a_user.data_intg[6:0]	Yes	Yes	T58,T69,T70	Yes	T58,T69,T70	INPUT
tl_rv_dm__sba_i.a_user.cmd_intg[6:0]	Yes	Yes	T43,T20,T62	Yes	T4,T5,T6	INPUT
tl_rv_dm__sba_i.a_user.instr_type[3:0]	Yes	Yes	T43,T20,T62	Yes	T4,T5,T6	INPUT
tl_rv_dm__sba_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_data[31:0]	Yes	Yes	T58,T69,T70	Yes	T58,T69,T70	INPUT
tl_rv_dm__sba_i.a_mask[3:0]	Yes	Yes	T43,T20,T62	Yes	T4,T5,T6	INPUT
tl_rv_dm__sba_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_source[5:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_rv_dm__sba_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_rv_dm__sba_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_opcode[2:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_rv_dm__sba_i.a_valid	Yes	Yes	T58,T69,T70	Yes	T58,T69,T70	INPUT
tl_rv_dm__sba_o.a_ready	Yes	Yes	T5,T43,T19	Yes	T4,T5,T6	OUTPUT
tl_rv_dm__sba_o.d_error	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_rv_dm__sba_o.d_user.data_intg[6:0]	Yes	Yes	T58,T69,T70	Yes	T58,T69,T70	OUTPUT
tl_rv_dm__sba_o.d_user.rsp_intg[6:0]	Yes	Yes	T58,T69,T71	Yes	T58,T69,T71	OUTPUT
tl_rv_dm__sba_o.d_data[31:0]	Yes	Yes	T58,T69,T70	Yes	T58,T69,T70	OUTPUT
tl_rv_dm__sba_o.d_sink	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_rv_dm__sba_o.d_source[5:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_rv_dm__sba_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__sba_o.d_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_rv_dm__sba_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__sba_o.d_opcode[0]	Yes	Yes	*T58,*T69,*T70	Yes	T58,T69,T70	OUTPUT
tl_rv_dm__sba_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__sba_o.d_valid	Yes	Yes	T58,T69,T70	Yes	T58,T69,T70	OUTPUT
tl_rv_dm__regs_o.d_ready	Yes	Yes	T5,T43,T19	Yes	T4,T5,T6	OUTPUT
tl_rv_dm__regs_o.a_user.data_intg[6:0]	Yes	Yes	T78,T132,T80	Yes	T78,T132,T80	OUTPUT
tl_rv_dm__regs_o.a_user.cmd_intg[6:0]	Yes	Yes	T78,T79,T132	Yes	T78,T79,T132	OUTPUT
tl_rv_dm__regs_o.a_user.instr_type[3:0]	Yes	Yes	T78,T79,T132	Yes	T78,T79,T132	OUTPUT
tl_rv_dm__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_data[31:0]	Yes	Yes	T78,T79,T132	Yes	T78,T79,T132	OUTPUT
tl_rv_dm__regs_o.a_mask[3:0]	Yes	Yes	T78,T79,T132	Yes	T78,T79,T132	OUTPUT
tl_rv_dm__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_source[5:0]	Yes	Yes	T78,T80,T82	Yes	T78,T80,T82	OUTPUT
tl_rv_dm__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_rv_dm__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_opcode[2:0]	Yes	Yes	T78,T79,T132	Yes	T78,T79,T132	OUTPUT
tl_rv_dm__regs_o.a_valid	Yes	Yes	T78,T79,T132	Yes	T78,T79,T132	OUTPUT
tl_rv_dm__regs_i.a_ready	Yes	Yes	T78,T79,T132	Yes	T78,T79,T132	INPUT
tl_rv_dm__regs_i.d_error	Yes	Yes	T78,T80,T82	Yes	T78,T79,T80	INPUT
tl_rv_dm__regs_i.d_user.data_intg[6:0]	Yes	Yes	T78,T79,T80	Yes	T78,T80,T82	INPUT
tl_rv_dm__regs_i.d_user.rsp_intg[6:0]	Yes	Yes	T78,T79,T132	Yes	T78,T79,T132	INPUT
tl_rv_dm__regs_i.d_data[31:0]	Yes	Yes	T78,T132,T80	Yes	T78,T132,T80	INPUT
tl_rv_dm__regs_i.d_sink	Yes	Yes	T78,T79,T80	Yes	T78,T80,T82	INPUT
tl_rv_dm__regs_i.d_source[5:0]	Yes	Yes	T80,T82,T83	Yes	T78,T80,T82	INPUT
tl_rv_dm__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__regs_i.d_size[1:0]	Yes	Yes	T80,T82,T213	Yes	T78,T79,T80	INPUT
tl_rv_dm__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__regs_i.d_opcode[0]	Yes	Yes	*T78,*T132,*T80	Yes	T78,T132,T80	INPUT
tl_rv_dm__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__regs_i.d_valid	Yes	Yes	T78,T79,T132	Yes	T78,T79,T132	INPUT
tl_rv_dm__mem_o.d_ready	Yes	Yes	T5,T43,T19	Yes	T4,T5,T6	OUTPUT
tl_rv_dm__mem_o.a_user.data_intg[6:0]	Yes	Yes	T70,T97,T256	Yes	T70,T97,T256	OUTPUT
tl_rv_dm__mem_o.a_user.cmd_intg[6:0]	Yes	Yes	T70,T97,T256	Yes	T70,T97,T256	OUTPUT
tl_rv_dm__mem_o.a_user.instr_type[3:0]	Yes	Yes	T70,T97,T256	Yes	T70,T97,T256	OUTPUT
tl_rv_dm__mem_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_data[31:0]	Yes	Yes	T70,T97,T256	Yes	T70,T97,T256	OUTPUT
tl_rv_dm__mem_o.a_mask[3:0]	Yes	Yes	T70,T97,T256	Yes	T70,T97,T256	OUTPUT
tl_rv_dm__mem_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_source[5:0]	Yes	Yes	*T70,*T97,*T256	Yes	T70,T97,T256	OUTPUT
tl_rv_dm__mem_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_rv_dm__mem_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_opcode[2:0]	Yes	Yes	T78,T79,T132	Yes	T78,T79,T132	OUTPUT
tl_rv_dm__mem_o.a_valid	Yes	Yes	T70,T97,T256	Yes	T70,T97,T256	OUTPUT
tl_rv_dm__mem_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rv_dm__mem_i.d_error	Yes	Yes	T4,T5,T6	Yes	T43,T20,T62	INPUT
tl_rv_dm__mem_i.d_user.data_intg[6:0]	Yes	Yes	T70,T97,T256	Yes	T70,T97,T256	INPUT
tl_rv_dm__mem_i.d_user.rsp_intg[6:0]	Yes	Yes	T70,T97,T256	Yes	T70,T97,T256	INPUT
tl_rv_dm__mem_i.d_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T43,T20,T62	INPUT
tl_rv_dm__mem_i.d_sink	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_rv_dm__mem_i.d_source[5:0]	Yes	Yes	*T70,*T97,*T256	Yes	T70,T97,T256	INPUT
tl_rv_dm__mem_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__mem_i.d_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_rv_dm__mem_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__mem_i.d_opcode[0]	Yes	Yes	*T4,*T5,*T6	Yes	T43,T20,T62	INPUT
tl_rv_dm__mem_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__mem_i.d_valid	Yes	Yes	T70,T97,T256	Yes	T70,T97,T256	INPUT
tl_rom_ctrl__rom_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rom_ctrl__rom_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rom_ctrl__rom_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rom_ctrl__rom_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rom_ctrl__rom_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_data[31:0]	Yes	Yes	T4,T6,T19	Yes	T4,T6,T19	OUTPUT
tl_rom_ctrl__rom_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rom_ctrl__rom_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_source[5:0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
tl_rom_ctrl__rom_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_rom_ctrl__rom_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_opcode[2:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_rom_ctrl__rom_o.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rom_ctrl__rom_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rom_ctrl__rom_i.d_error	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_rom_ctrl__rom_i.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rom_ctrl__rom_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rom_ctrl__rom_i.d_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rom_ctrl__rom_i.d_sink	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_rom_ctrl__rom_i.d_source[5:0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_rom_ctrl__rom_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__rom_i.d_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_rom_ctrl__rom_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__rom_i.d_opcode[0]	Yes	Yes	*T78,*T79,*T80	Yes	T78,T79,T80	INPUT
tl_rom_ctrl__rom_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__rom_i.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rom_ctrl__regs_o.d_ready	Yes	Yes	T5,T43,T19	Yes	T4,T5,T6	OUTPUT
tl_rom_ctrl__regs_o.a_user.data_intg[6:0]	Yes	Yes	T59,T60,T61	Yes	T59,T60,T61	OUTPUT
tl_rom_ctrl__regs_o.a_user.cmd_intg[6:0]	Yes	Yes	T401,T402,T403	Yes	T401,T402,T403	OUTPUT
tl_rom_ctrl__regs_o.a_user.instr_type[3:0]	Yes	Yes	T401,T402,T403	Yes	T401,T402,T403	OUTPUT
tl_rom_ctrl__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_data[31:0]	Yes	Yes	T59,T60,T61	Yes	T59,T60,T61	OUTPUT
tl_rom_ctrl__regs_o.a_mask[3:0]	Yes	Yes	T401,T402,T403	Yes	T401,T402,T403	OUTPUT
tl_rom_ctrl__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_source[5:0]	Yes	Yes	*T78,*T79,*T80	Yes	T78,T79,T80	OUTPUT
tl_rom_ctrl__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_rom_ctrl__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_opcode[2:0]	Yes	Yes	T79,T132,T80	Yes	T79,T132,T80	OUTPUT
tl_rom_ctrl__regs_o.a_valid	Yes	Yes	T401,T402,T403	Yes	T401,T402,T403	OUTPUT
tl_rom_ctrl__regs_i.a_ready	Yes	Yes	T401,T402,T403	Yes	T401,T402,T403	INPUT
tl_rom_ctrl__regs_i.d_error	Yes	Yes	T78,T80,T82	Yes	T78,T80,T82	INPUT
tl_rom_ctrl__regs_i.d_user.data_intg[6:0]	Yes	Yes	T401,T404,T405	Yes	T401,T404,T405	INPUT
tl_rom_ctrl__regs_i.d_user.rsp_intg[6:0]	Yes	Yes	T78,T79,T132	Yes	T59,T60,T61	INPUT
tl_rom_ctrl__regs_i.d_data[31:0]	Yes	Yes	T401,T404,T405	Yes	T401,T404,T405	INPUT
tl_rom_ctrl__regs_i.d_sink	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_rom_ctrl__regs_i.d_source[5:0]	Yes	Yes	T78,*T80,*T82	Yes	T78,T79,T80	INPUT
tl_rom_ctrl__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__regs_i.d_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_rom_ctrl__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__regs_i.d_opcode[0]	Yes	Yes	*T402,*T403,*T404	Yes	T401,T402,T403	INPUT
tl_rom_ctrl__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__regs_i.d_valid	Yes	Yes	T401,T402,T403	Yes	T401,T402,T403	INPUT
tl_peri_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_peri_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_peri_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_peri_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_peri_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_peri_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_peri_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_source[5:0]	Yes	Yes	*T58,*T70,*T71	Yes	T58,T70,T71	OUTPUT
tl_peri_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_peri_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_opcode[2:0]	Yes	Yes	T58,T71,T81	Yes	T58,T71,T81	OUTPUT
tl_peri_o.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_peri_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_peri_i.d_error	Yes	Yes	T65,T66,T220	Yes	T65,T66,T220	INPUT
tl_peri_i.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_peri_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_peri_i.d_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_peri_i.d_sink	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_peri_i.d_source[5:0]	Yes	Yes	*T58,*T70,*T71	Yes	T58,T70,T71	INPUT
tl_peri_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_peri_i.d_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_peri_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_peri_i.d_opcode[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_peri_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_peri_i.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_spi_host0_o.d_ready	Yes	Yes	T159,T243,T24	Yes	T159,T243,T24	OUTPUT
tl_spi_host0_o.a_user.data_intg[6:0]	Yes	Yes	T159,T24,T212	Yes	T159,T24,T212	OUTPUT
tl_spi_host0_o.a_user.cmd_intg[6:0]	Yes	Yes	T159,T243,T24	Yes	T159,T243,T24	OUTPUT
tl_spi_host0_o.a_user.instr_type[3:0]	Yes	Yes	T159,T243,T24	Yes	T159,T243,T24	OUTPUT
tl_spi_host0_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_data[31:0]	Yes	Yes	T159,T24,T212	Yes	T159,T24,T212	OUTPUT
tl_spi_host0_o.a_mask[3:0]	Yes	Yes	T159,T243,T24	Yes	T159,T243,T24	OUTPUT
tl_spi_host0_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_source[5:0]	Yes	Yes	*T78,*T79,*T80	Yes	T78,T79,T80	OUTPUT
tl_spi_host0_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_size[1:0]	Yes	Yes	T79,T80,T82	Yes	T79,T80,T82	OUTPUT
tl_spi_host0_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_opcode[2:0]	Yes	Yes	T25,T26,T197	Yes	T25,T26,T197	OUTPUT
tl_spi_host0_o.a_valid	Yes	Yes	T159,T243,T24	Yes	T159,T243,T24	OUTPUT
tl_spi_host0_i.a_ready	Yes	Yes	T159,T243,T24	Yes	T159,T243,T24	INPUT
tl_spi_host0_i.d_error	Yes	Yes	T79,T80,T82	Yes	T78,T79,T80	INPUT
tl_spi_host0_i.d_user.data_intg[6:0]	Yes	Yes	T159,T24,T212	Yes	T159,T24,T212	INPUT
tl_spi_host0_i.d_user.rsp_intg[6:0]	Yes	Yes	T159,T243,T24	Yes	T159,T243,T24	INPUT
tl_spi_host0_i.d_data[31:0]	Yes	Yes	T159,T24,T212	Yes	T159,T24,T212	INPUT
tl_spi_host0_i.d_sink	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_spi_host0_i.d_source[5:0]	Yes	Yes	*T79,*T80,*T82	Yes	T79,T80,T82	INPUT
tl_spi_host0_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host0_i.d_size[1:0]	Yes	Yes	T79,T80,T82	Yes	T79,T80,T82	INPUT
tl_spi_host0_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host0_i.d_opcode[0]	Yes	Yes	*T159,*T243,*T24	Yes	T159,T243,T24	INPUT
tl_spi_host0_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host0_i.d_valid	Yes	Yes	T159,T243,T24	Yes	T159,T243,T24	INPUT
tl_spi_host1_o.d_ready	Yes	Yes	T159,T243,T45	Yes	T159,T243,T45	OUTPUT
tl_spi_host1_o.a_user.data_intg[6:0]	Yes	Yes	T159,T45,T212	Yes	T159,T45,T212	OUTPUT
tl_spi_host1_o.a_user.cmd_intg[6:0]	Yes	Yes	T159,T243,T45	Yes	T159,T243,T45	OUTPUT
tl_spi_host1_o.a_user.instr_type[3:0]	Yes	Yes	T159,T243,T45	Yes	T159,T243,T45	OUTPUT
tl_spi_host1_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_data[31:0]	Yes	Yes	T159,T45,T212	Yes	T159,T45,T212	OUTPUT
tl_spi_host1_o.a_mask[3:0]	Yes	Yes	T159,T243,T45	Yes	T159,T243,T45	OUTPUT
tl_spi_host1_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_source[5:0]	Yes	Yes	*T78,*T79,*T80	Yes	T78,T79,T80	OUTPUT
tl_spi_host1_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_spi_host1_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_opcode[2:0]	Yes	Yes	T79,T132,T80	Yes	T79,T132,T80	OUTPUT
tl_spi_host1_o.a_valid	Yes	Yes	T159,T243,T45	Yes	T159,T243,T45	OUTPUT
tl_spi_host1_i.a_ready	Yes	Yes	T159,T243,T45	Yes	T159,T243,T45	INPUT
tl_spi_host1_i.d_error	Yes	Yes	T79,T80,T82	Yes	T78,T79,T80	INPUT
tl_spi_host1_i.d_user.data_intg[6:0]	Yes	Yes	T159,T45,T212	Yes	T159,T45,T212	INPUT
tl_spi_host1_i.d_user.rsp_intg[6:0]	Yes	Yes	T159,T243,T45	Yes	T159,T243,T45	INPUT
tl_spi_host1_i.d_data[31:0]	Yes	Yes	T159,T45,T212	Yes	T159,T45,T212	INPUT
tl_spi_host1_i.d_sink	Yes	Yes	T79,T80,T82	Yes	T79,T80,T82	INPUT
tl_spi_host1_i.d_source[5:0]	Yes	Yes	*T80,*T82,*T83	Yes	T78,T79,T80	INPUT
tl_spi_host1_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host1_i.d_size[1:0]	Yes	Yes	T78,T80,T82	Yes	T79,T80,T82	INPUT
tl_spi_host1_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host1_i.d_opcode[0]	Yes	Yes	*T159,*T243,*T45	Yes	T159,T243,T45	INPUT
tl_spi_host1_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host1_i.d_valid	Yes	Yes	T159,T243,T45	Yes	T159,T243,T45	INPUT
tl_usbdev_o.d_ready	Yes	Yes	T243,T96,T29	Yes	T243,T96,T29	OUTPUT
tl_usbdev_o.a_user.data_intg[6:0]	Yes	Yes	T243,T96,T29	Yes	T243,T96,T29	OUTPUT
tl_usbdev_o.a_user.cmd_intg[6:0]	Yes	Yes	T243,T96,T29	Yes	T243,T96,T29	OUTPUT
tl_usbdev_o.a_user.instr_type[3:0]	Yes	Yes	T243,T96,T29	Yes	T243,T96,T29	OUTPUT
tl_usbdev_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_data[31:0]	Yes	Yes	T29,T30,T1	Yes	T29,T30,T1	OUTPUT
tl_usbdev_o.a_mask[3:0]	Yes	Yes	T243,T96,T29	Yes	T243,T96,T29	OUTPUT
tl_usbdev_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_source[5:0]	Yes	Yes	*T148,*T78,*T79	Yes	T148,T78,T79	OUTPUT
tl_usbdev_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_usbdev_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_opcode[2:0]	Yes	Yes	T78,T79,T132	Yes	T78,T79,T132	OUTPUT
tl_usbdev_o.a_valid	Yes	Yes	T243,T96,T29	Yes	T243,T96,T29	OUTPUT
tl_usbdev_i.a_ready	Yes	Yes	T243,T96,T29	Yes	T243,T96,T29	INPUT
tl_usbdev_i.d_error	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_usbdev_i.d_user.data_intg[6:0]	Yes	Yes	T243,T96,T29	Yes	T243,T96,T29	INPUT
tl_usbdev_i.d_user.rsp_intg[6:0]	Yes	Yes	T243,T96,T29	Yes	T243,T96,T29	INPUT
tl_usbdev_i.d_data[31:0]	Yes	Yes	T243,T96,T29	Yes	T243,T96,T29	INPUT
tl_usbdev_i.d_sink	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_usbdev_i.d_source[5:0]	Yes	Yes	*T148,*T78,*T79	Yes	T148,T78,T79	INPUT
tl_usbdev_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_usbdev_i.d_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_usbdev_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_usbdev_i.d_opcode[0]	Yes	Yes	*T243,*T96,*T29	Yes	T243,T96,T29	INPUT
tl_usbdev_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_usbdev_i.d_valid	Yes	Yes	T243,T96,T29	Yes	T243,T96,T29	INPUT
tl_flash_ctrl__core_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__core_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__core_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__core_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__core_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__core_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__core_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_source[5:0]	Yes	Yes	*T58,*T71,*T148	Yes	T58,T71,T148	OUTPUT
tl_flash_ctrl__core_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_flash_ctrl__core_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_opcode[2:0]	Yes	Yes	T78,T79,T132	Yes	T78,T79,T132	OUTPUT
tl_flash_ctrl__core_o.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__core_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_flash_ctrl__core_i.d_error	Yes	Yes	T4,T5,T6	Yes	T5,T43,T19	INPUT
tl_flash_ctrl__core_i.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_flash_ctrl__core_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_flash_ctrl__core_i.d_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_flash_ctrl__core_i.d_sink	Yes	Yes	T78,T80,T82	Yes	T78,T79,T80	INPUT
tl_flash_ctrl__core_i.d_source[5:0]	Yes	Yes	*T58,*T71,*T148	Yes	T58,T71,T148	INPUT
tl_flash_ctrl__core_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__core_i.d_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_flash_ctrl__core_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__core_i.d_opcode[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_flash_ctrl__core_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__core_i.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_flash_ctrl__prim_o.d_ready	Yes	Yes	T5,T43,T19	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__prim_o.a_user.data_intg[6:0]	Yes	Yes	T58,T71,T148	Yes	T58,T71,T148	OUTPUT
tl_flash_ctrl__prim_o.a_user.cmd_intg[6:0]	Yes	Yes	T58,T71,T148	Yes	T58,T71,T148	OUTPUT
tl_flash_ctrl__prim_o.a_user.instr_type[3:0]	Yes	Yes	T58,T71,T148	Yes	T58,T71,T148	OUTPUT
tl_flash_ctrl__prim_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_data[31:0]	Yes	Yes	T58,T71,T148	Yes	T58,T71,T148	OUTPUT
tl_flash_ctrl__prim_o.a_mask[3:0]	Yes	Yes	T58,T71,T148	Yes	T58,T71,T148	OUTPUT
tl_flash_ctrl__prim_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_source[5:0]	Yes	Yes	*T58,*T71,*T148	Yes	T58,T71,T148	OUTPUT
tl_flash_ctrl__prim_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_size[1:0]	Yes	Yes	T79,T80,T82	Yes	T79,T80,T82	OUTPUT
tl_flash_ctrl__prim_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_opcode[2:0]	Yes	Yes	T78,T79,T132	Yes	T78,T79,T132	OUTPUT
tl_flash_ctrl__prim_o.a_valid	Yes	Yes	T58,T71,T148	Yes	T58,T71,T148	OUTPUT
tl_flash_ctrl__prim_i.a_ready	Yes	Yes	T58,T71,T148	Yes	T58,T71,T148	INPUT
tl_flash_ctrl__prim_i.d_error	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_flash_ctrl__prim_i.d_user.data_intg[6:0]	Yes	Yes	T58,T71,T148	Yes	T58,T71,T148	INPUT
tl_flash_ctrl__prim_i.d_user.rsp_intg[6:0]	Yes	Yes	T58,T71,T148	Yes	T58,T71,T148	INPUT
tl_flash_ctrl__prim_i.d_data[31:0]	Yes	Yes	T58,T71,T148	Yes	T58,T71,T148	INPUT
tl_flash_ctrl__prim_i.d_sink	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_flash_ctrl__prim_i.d_source[5:0]	Yes	Yes	*T58,*T71,*T148	Yes	T58,T71,T148	INPUT
tl_flash_ctrl__prim_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__prim_i.d_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_flash_ctrl__prim_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__prim_i.d_opcode[0]	Yes	Yes	*T58,*T71,*T148	Yes	T58,T71,T148	INPUT
tl_flash_ctrl__prim_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__prim_i.d_valid	Yes	Yes	T58,T71,T148	Yes	T58,T71,T148	INPUT
tl_flash_ctrl__mem_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_flash_ctrl__mem_o.a_user.data_intg[6:0]	Yes	Yes	T4,T6,T43	Yes	T4,T6,T43	OUTPUT
tl_flash_ctrl__mem_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T6,T43	Yes	T4,T6,T43	OUTPUT
tl_flash_ctrl__mem_o.a_user.instr_type[3:0]	Yes	Yes	T4,T6,T43	Yes	T4,T6,T43	OUTPUT
tl_flash_ctrl__mem_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_data[31:0]	Yes	Yes	T4,T6,T43	Yes	T4,T6,T43	OUTPUT
tl_flash_ctrl__mem_o.a_mask[3:0]	Yes	Yes	T4,T6,T43	Yes	T4,T6,T43	OUTPUT
tl_flash_ctrl__mem_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_source[5:0]	Yes	Yes	*T4,*T6,*T43	Yes	T4,T6,T43	OUTPUT
tl_flash_ctrl__mem_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_flash_ctrl__mem_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_opcode[2:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_flash_ctrl__mem_o.a_valid	Yes	Yes	T4,T6,T43	Yes	T4,T6,T43	OUTPUT
tl_flash_ctrl__mem_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_flash_ctrl__mem_i.d_error	Yes	Yes	T4,T5,T6	Yes	T5,T43,T19	INPUT
tl_flash_ctrl__mem_i.d_user.data_intg[6:0]	Yes	Yes	T4,T6,T43	Yes	T4,T6,T43	INPUT
tl_flash_ctrl__mem_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_flash_ctrl__mem_i.d_data[31:0]	Yes	Yes	T4,T6,T43	Yes	T4,T6,T43	INPUT
tl_flash_ctrl__mem_i.d_sink	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_flash_ctrl__mem_i.d_source[5:0]	Yes	Yes	*T4,*T6,*T43	Yes	T4,T6,T43	INPUT
tl_flash_ctrl__mem_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__mem_i.d_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_flash_ctrl__mem_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__mem_i.d_opcode[0]	Yes	Yes	*T78,*T79,*T80	Yes	T78,T79,T80	INPUT
tl_flash_ctrl__mem_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__mem_i.d_valid	Yes	Yes	T4,T6,T43	Yes	T4,T6,T43	INPUT
tl_hmac_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_hmac_o.a_user.data_intg[6:0]	Yes	Yes	T4,T6,T17	Yes	T4,T6,T17	OUTPUT
tl_hmac_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T6,T17	Yes	T4,T6,T17	OUTPUT
tl_hmac_o.a_user.instr_type[3:0]	Yes	Yes	T4,T6,T17	Yes	T4,T6,T17	OUTPUT
tl_hmac_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_data[31:0]	Yes	Yes	T4,T6,T17	Yes	T4,T6,T17	OUTPUT
tl_hmac_o.a_mask[3:0]	Yes	Yes	T4,T6,T17	Yes	T4,T6,T17	OUTPUT
tl_hmac_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_source[5:0]	Yes	Yes	*T58,*T71,*T148	Yes	T58,T71,T148	OUTPUT
tl_hmac_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_size[1:0]	Yes	Yes	T78,T80,T82	Yes	T78,T80,T82	OUTPUT
tl_hmac_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_opcode[2:0]	Yes	Yes	T17,T322,T288	Yes	T17,T322,T288	OUTPUT
tl_hmac_o.a_valid	Yes	Yes	T4,T6,T17	Yes	T4,T6,T17	OUTPUT
tl_hmac_i.a_ready	Yes	Yes	T4,T6,T17	Yes	T4,T6,T17	INPUT
tl_hmac_i.d_error	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_hmac_i.d_user.data_intg[6:0]	Yes	Yes	T4,T6,T17	Yes	T4,T6,T17	INPUT
tl_hmac_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T6,T17	Yes	T4,T6,T17	INPUT
tl_hmac_i.d_data[31:0]	Yes	Yes	T4,T6,T17	Yes	T4,T6,T17	INPUT
tl_hmac_i.d_sink	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_hmac_i.d_source[5:0]	Yes	Yes	*T58,*T71,*T148	Yes	T58,T71,T148	INPUT
tl_hmac_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_hmac_i.d_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_hmac_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_hmac_i.d_opcode[0]	Yes	Yes	*T4,*T6,*T17	Yes	T4,T6,T17	INPUT
tl_hmac_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_hmac_i.d_valid	Yes	Yes	T4,T6,T17	Yes	T4,T6,T17	INPUT
tl_kmac_o.d_ready	Yes	Yes	T5,T43,T88	Yes	T4,T5,T6	OUTPUT
tl_kmac_o.a_user.data_intg[6:0]	Yes	Yes	T88,T159,T58	Yes	T88,T159,T58	OUTPUT
tl_kmac_o.a_user.cmd_intg[6:0]	Yes	Yes	T43,T88,T159	Yes	T43,T88,T159	OUTPUT
tl_kmac_o.a_user.instr_type[3:0]	Yes	Yes	T43,T88,T159	Yes	T43,T88,T159	OUTPUT
tl_kmac_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_data[31:0]	Yes	Yes	T88,T159,T58	Yes	T88,T159,T58	OUTPUT
tl_kmac_o.a_mask[3:0]	Yes	Yes	T43,T88,T159	Yes	T43,T88,T159	OUTPUT
tl_kmac_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_source[5:0]	Yes	Yes	*T58,*T71,*T148	Yes	T58,T71,T148	OUTPUT
tl_kmac_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_kmac_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_opcode[2:0]	Yes	Yes	T88,T269,T460	Yes	T88,T269,T460	OUTPUT
tl_kmac_o.a_valid	Yes	Yes	T43,T88,T159	Yes	T43,T88,T159	OUTPUT
tl_kmac_i.a_ready	Yes	Yes	T43,T88,T159	Yes	T43,T88,T159	INPUT
tl_kmac_i.d_error	Yes	Yes	T79,T80,T82	Yes	T79,T80,T82	INPUT
tl_kmac_i.d_user.data_intg[6:0]	Yes	Yes	T43,T88,T159	Yes	T43,T88,T159	INPUT
tl_kmac_i.d_user.rsp_intg[6:0]	Yes	Yes	T43,T88,T159	Yes	T43,T88,T159	INPUT
tl_kmac_i.d_data[31:0]	Yes	Yes	T43,T88,T159	Yes	T88,T159,T58	INPUT
tl_kmac_i.d_sink	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_kmac_i.d_source[5:0]	Yes	Yes	*T58,*T71,*T148	Yes	T58,T71,T148	INPUT
tl_kmac_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_kmac_i.d_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_kmac_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_kmac_i.d_opcode[0]	Yes	Yes	*T43,*T88,*T159	Yes	T88,T159,T58	INPUT
tl_kmac_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_kmac_i.d_valid	Yes	Yes	T43,T88,T159	Yes	T43,T88,T159	INPUT
tl_aes_o.d_ready	Yes	Yes	T5,T43,T196	Yes	T4,T5,T6	OUTPUT
tl_aes_o.a_user.data_intg[6:0]	Yes	Yes	T43,T196,T121	Yes	T43,T196,T121	OUTPUT
tl_aes_o.a_user.cmd_intg[6:0]	Yes	Yes	T43,T196,T121	Yes	T43,T196,T121	OUTPUT
tl_aes_o.a_user.instr_type[3:0]	Yes	Yes	T43,T196,T121	Yes	T43,T196,T121	OUTPUT
tl_aes_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_data[31:0]	Yes	Yes	T43,T196,T121	Yes	T43,T196,T121	OUTPUT
tl_aes_o.a_mask[3:0]	Yes	Yes	T43,T196,T121	Yes	T43,T196,T121	OUTPUT
tl_aes_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_source[5:0]	Yes	Yes	*T78,*T79,*T80	Yes	T78,T79,T80	OUTPUT
tl_aes_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_aes_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_opcode[2:0]	Yes	Yes	T78,T79,T132	Yes	T78,T79,T132	OUTPUT
tl_aes_o.a_valid	Yes	Yes	T43,T196,T121	Yes	T43,T196,T121	OUTPUT
tl_aes_i.a_ready	Yes	Yes	T43,T196,T121	Yes	T43,T196,T121	INPUT
tl_aes_i.d_error	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_aes_i.d_user.data_intg[6:0]	Yes	Yes	T43,T196,T121	Yes	T43,T196,T121	INPUT
tl_aes_i.d_user.rsp_intg[6:0]	Yes	Yes	T43,T196,T121	Yes	T43,T196,T121	INPUT
tl_aes_i.d_data[31:0]	Yes	Yes	T196,T121,T728	Yes	T43,T196,T121	INPUT
tl_aes_i.d_sink	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_aes_i.d_source[5:0]	Yes	Yes	*T78,*T79,*T80	Yes	T78,T79,T80	INPUT
tl_aes_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_aes_i.d_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_aes_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_aes_i.d_opcode[0]	Yes	Yes	*T43,*T196,*T121	Yes	T43,T196,T121	INPUT
tl_aes_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_aes_i.d_valid	Yes	Yes	T43,T196,T121	Yes	T43,T196,T121	INPUT
tl_entropy_src_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_entropy_src_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_entropy_src_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_entropy_src_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_entropy_src_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_entropy_src_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_entropy_src_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_source[5:0]	Yes	Yes	*T58,*T71,*T148	Yes	T58,T71,T148	OUTPUT
tl_entropy_src_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_entropy_src_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_opcode[2:0]	Yes	Yes	T78,T79,T132	Yes	T78,T79,T132	OUTPUT
tl_entropy_src_o.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_entropy_src_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_entropy_src_i.d_error	Yes	Yes	T78,T80,T82	Yes	T78,T80,T82	INPUT
tl_entropy_src_i.d_user.data_intg[6:0]	Yes	Yes	T43,T58,T71	Yes	T43,T58,T71	INPUT
tl_entropy_src_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_entropy_src_i.d_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_entropy_src_i.d_sink	Yes	Yes	T79,T80,T82	Yes	T78,T79,T80	INPUT
tl_entropy_src_i.d_source[5:0]	Yes	Yes	*T58,*T71,*T148	Yes	T58,T71,T148	INPUT
tl_entropy_src_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_entropy_src_i.d_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_entropy_src_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_entropy_src_i.d_opcode[0]	Yes	Yes	*T43,*T54,*T58	Yes	T4,T6,T43	INPUT
tl_entropy_src_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_entropy_src_i.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_csrng_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_csrng_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_csrng_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_csrng_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_csrng_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_data[31:0]	Yes	Yes	T43,T62,T58	Yes	T43,T62,T58	OUTPUT
tl_csrng_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_csrng_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_source[5:0]	Yes	Yes	*T58,*T71,*T148	Yes	T58,T71,T148	OUTPUT
tl_csrng_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_csrng_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_opcode[2:0]	Yes	Yes	T78,T79,T132	Yes	T78,T79,T132	OUTPUT
tl_csrng_o.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_csrng_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_csrng_i.d_error	Yes	Yes	T78,T80,T82	Yes	T78,T80,T82	INPUT
tl_csrng_i.d_user.data_intg[6:0]	Yes	Yes	T43,T62,T58	Yes	T43,T62,T58	INPUT
tl_csrng_i.d_user.rsp_intg[6:0]	Yes	Yes	T5,T43,T19	Yes	T4,T5,T6	INPUT
tl_csrng_i.d_data[31:0]	Yes	Yes	T5,T43,T19	Yes	T4,T5,T6	INPUT
tl_csrng_i.d_sink	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_csrng_i.d_source[5:0]	Yes	Yes	*T58,*T71,*T148	Yes	T58,T71,T148	INPUT
tl_csrng_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_csrng_i.d_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_csrng_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_csrng_i.d_opcode[0]	Yes	Yes	*T43,*T62,*T58	Yes	T43,T62,T58	INPUT
tl_csrng_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_csrng_i.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_edn0_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_edn0_o.a_user.data_intg[6:0]	Yes	Yes	T43,T58,T71	Yes	T43,T58,T71	OUTPUT
tl_edn0_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_edn0_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_edn0_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_data[31:0]	Yes	Yes	T43,T58,T71	Yes	T43,T58,T71	OUTPUT
tl_edn0_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_edn0_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_source[5:0]	Yes	Yes	*T58,*T71,*T148	Yes	T58,T71,T148	OUTPUT
tl_edn0_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_edn0_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_opcode[2:0]	Yes	Yes	T78,T79,T132	Yes	T78,T79,T132	OUTPUT
tl_edn0_o.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_edn0_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_edn0_i.d_error	Yes	Yes	T79,T80,T82	Yes	T78,T80,T82	INPUT
tl_edn0_i.d_user.data_intg[6:0]	Yes	Yes	T43,T58,T71	Yes	T43,T58,T71	INPUT
tl_edn0_i.d_user.rsp_intg[6:0]	Yes	Yes	T5,T43,T19	Yes	T4,T5,T6	INPUT
tl_edn0_i.d_data[31:0]	Yes	Yes	T5,T43,T19	Yes	T4,T5,T6	INPUT
tl_edn0_i.d_sink	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_edn0_i.d_source[5:0]	Yes	Yes	*T58,*T71,*T148	Yes	T58,T71,T148	INPUT
tl_edn0_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn0_i.d_size[1:0]	Yes	Yes	T79,T80,T82	Yes	T78,T79,T80	INPUT
tl_edn0_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn0_i.d_opcode[0]	Yes	Yes	*T43,*T58,*T71	Yes	T43,T58,T71	INPUT
tl_edn0_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn0_i.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_edn1_o.d_ready	Yes	Yes	T5,T43,T19	Yes	T4,T5,T6	OUTPUT
tl_edn1_o.a_user.data_intg[6:0]	Yes	Yes	T43,T58,T71	Yes	T43,T58,T71	OUTPUT
tl_edn1_o.a_user.cmd_intg[6:0]	Yes	Yes	T43,T58,T71	Yes	T43,T58,T71	OUTPUT
tl_edn1_o.a_user.instr_type[3:0]	Yes	Yes	T43,T58,T71	Yes	T43,T58,T71	OUTPUT
tl_edn1_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_data[31:0]	Yes	Yes	T43,T58,T71	Yes	T43,T58,T71	OUTPUT
tl_edn1_o.a_mask[3:0]	Yes	Yes	T43,T58,T71	Yes	T43,T58,T71	OUTPUT
tl_edn1_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_source[5:0]	Yes	Yes	*T58,*T71,*T148	Yes	T58,T71,T148	OUTPUT
tl_edn1_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_edn1_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_opcode[2:0]	Yes	Yes	T79,T132,T80	Yes	T79,T132,T80	OUTPUT
tl_edn1_o.a_valid	Yes	Yes	T43,T58,T71	Yes	T43,T58,T71	OUTPUT
tl_edn1_i.a_ready	Yes	Yes	T43,T58,T71	Yes	T43,T58,T71	INPUT
tl_edn1_i.d_error	Yes	Yes	T79,T80,T82	Yes	T78,T79,T80	INPUT
tl_edn1_i.d_user.data_intg[6:0]	Yes	Yes	T43,T58,T71	Yes	T43,T58,T71	INPUT
tl_edn1_i.d_user.rsp_intg[6:0]	Yes	Yes	T43,T58,T71	Yes	T43,T58,T71	INPUT
tl_edn1_i.d_data[31:0]	Yes	Yes	T43,T58,T71	Yes	T43,T58,T71	INPUT
tl_edn1_i.d_sink	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_edn1_i.d_source[5:0]	Yes	Yes	*T58,*T71,*T148	Yes	T58,T71,T148	INPUT
tl_edn1_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn1_i.d_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_edn1_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn1_i.d_opcode[0]	Yes	Yes	*T43,*T58,*T71	Yes	T43,T58,T71	INPUT
tl_edn1_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn1_i.d_valid	Yes	Yes	T43,T58,T71	Yes	T43,T58,T71	INPUT
tl_rv_plic_o.d_ready	Yes	Yes	T5,T43,T16	Yes	T4,T5,T6	OUTPUT
tl_rv_plic_o.a_user.data_intg[6:0]	Yes	Yes	T16,T17,T18	Yes	T16,T17,T18	OUTPUT
tl_rv_plic_o.a_user.cmd_intg[6:0]	Yes	Yes	T16,T17,T18	Yes	T16,T17,T18	OUTPUT
tl_rv_plic_o.a_user.instr_type[3:0]	Yes	Yes	T16,T17,T18	Yes	T16,T17,T18	OUTPUT
tl_rv_plic_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_data[31:0]	Yes	Yes	T16,T17,T18	Yes	T16,T17,T18	OUTPUT
tl_rv_plic_o.a_mask[3:0]	Yes	Yes	T16,T17,T18	Yes	T16,T17,T18	OUTPUT
tl_rv_plic_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_source[5:0]	Yes	Yes	*T78,*T79,*T80	Yes	T78,T79,T80	OUTPUT
tl_rv_plic_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_rv_plic_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_opcode[2:0]	Yes	Yes	T78,T79,T132	Yes	T78,T79,T132	OUTPUT
tl_rv_plic_o.a_valid	Yes	Yes	T16,T17,T18	Yes	T16,T17,T18	OUTPUT
tl_rv_plic_i.a_ready	Yes	Yes	T16,T17,T18	Yes	T16,T17,T18	INPUT
tl_rv_plic_i.d_error	Yes	Yes	T79,T80,T82	Yes	T79,T80,T82	INPUT
tl_rv_plic_i.d_user.data_intg[6:0]	Yes	Yes	T16,T18,T253	Yes	T16,T18,T253	INPUT
tl_rv_plic_i.d_user.rsp_intg[6:0]	Yes	Yes	T16,T17,T18	Yes	T16,T17,T18	INPUT
tl_rv_plic_i.d_data[31:0]	Yes	Yes	T16,T17,T18	Yes	T16,T17,T18	INPUT
tl_rv_plic_i.d_sink	Yes	Yes	T78,T79,T80	Yes	T79,T80,T82	INPUT
tl_rv_plic_i.d_source[5:0]	Yes	Yes	*T79,*T80,*T82	Yes	T78,T79,T80	INPUT
tl_rv_plic_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_plic_i.d_size[1:0]	Yes	Yes	T79,T80,T82	Yes	T78,T79,T80	INPUT
tl_rv_plic_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_plic_i.d_opcode[0]	Yes	Yes	*T16,*T17,*T18	Yes	T16,T17,T18	INPUT
tl_rv_plic_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_plic_i.d_valid	Yes	Yes	T16,T17,T18	Yes	T16,T17,T18	INPUT
tl_otbn_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_otbn_o.a_user.data_intg[6:0]	Yes	Yes	T4,T6,T43	Yes	T4,T6,T43	OUTPUT
tl_otbn_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T6,T43	Yes	T4,T6,T43	OUTPUT
tl_otbn_o.a_user.instr_type[3:0]	Yes	Yes	T4,T6,T43	Yes	T4,T6,T43	OUTPUT
tl_otbn_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_data[31:0]	Yes	Yes	T4,T6,T43	Yes	T4,T6,T43	OUTPUT
tl_otbn_o.a_mask[3:0]	Yes	Yes	T4,T6,T43	Yes	T4,T6,T43	OUTPUT
tl_otbn_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_source[5:0]	Yes	Yes	*T81,*T200,*T201	Yes	T81,T200,T201	OUTPUT
tl_otbn_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_size[1:0]	Yes	Yes	T79,T80,T82	Yes	T79,T80,T82	OUTPUT
tl_otbn_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_opcode[2:0]	Yes	Yes	T78,T79,T132	Yes	T78,T79,T132	OUTPUT
tl_otbn_o.a_valid	Yes	Yes	T4,T6,T43	Yes	T4,T6,T43	OUTPUT
tl_otbn_i.a_ready	Yes	Yes	T4,T6,T43	Yes	T4,T6,T43	INPUT
tl_otbn_i.d_error	Yes	Yes	T79,T80,T82	Yes	T79,T80,T82	INPUT
tl_otbn_i.d_user.data_intg[6:0]	Yes	Yes	T4,T6,T43	Yes	T4,T6,T43	INPUT
tl_otbn_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T6,T43	Yes	T4,T6,T43	INPUT
tl_otbn_i.d_data[31:0]	Yes	Yes	T4,T6,T43	Yes	T4,T6,T43	INPUT
tl_otbn_i.d_sink	Yes	Yes	T79,T80,T82	Yes	T79,T80,T82	INPUT
tl_otbn_i.d_source[5:0]	Yes	Yes	*T81,*T200,*T201	Yes	T81,T200,T201	INPUT
tl_otbn_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_otbn_i.d_size[1:0]	Yes	Yes	T79,T80,T82	Yes	T79,T80,T82	INPUT
tl_otbn_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_otbn_i.d_opcode[0]	Yes	Yes	*T4,*T6,*T43	Yes	T4,T6,T43	INPUT
tl_otbn_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_otbn_i.d_valid	Yes	Yes	T4,T6,T43	Yes	T4,T6,T43	INPUT
tl_keymgr_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_keymgr_o.a_user.data_intg[6:0]	Yes	Yes	T4,T6,T43	Yes	T4,T6,T43	OUTPUT
tl_keymgr_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T6,T43	Yes	T4,T6,T43	OUTPUT
tl_keymgr_o.a_user.instr_type[3:0]	Yes	Yes	T4,T6,T43	Yes	T4,T6,T43	OUTPUT
tl_keymgr_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_data[31:0]	Yes	Yes	T6,T43,T159	Yes	T6,T43,T159	OUTPUT
tl_keymgr_o.a_mask[3:0]	Yes	Yes	T4,T6,T43	Yes	T4,T6,T43	OUTPUT
tl_keymgr_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_source[5:0]	Yes	Yes	*T58,*T71,*T148	Yes	T58,T71,T148	OUTPUT
tl_keymgr_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_keymgr_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_opcode[2:0]	Yes	Yes	T78,T79,T132	Yes	T78,T79,T132	OUTPUT
tl_keymgr_o.a_valid	Yes	Yes	T4,T6,T43	Yes	T4,T6,T43	OUTPUT
tl_keymgr_i.a_ready	Yes	Yes	T4,T6,T43	Yes	T4,T6,T43	INPUT
tl_keymgr_i.d_error	Yes	Yes	T79,T80,T82	Yes	T78,T79,T80	INPUT
tl_keymgr_i.d_user.data_intg[6:0]	Yes	Yes	T6,T43,T159	Yes	T6,T43,T159	INPUT
tl_keymgr_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T6,T43	Yes	T4,T6,T43	INPUT
tl_keymgr_i.d_data[31:0]	Yes	Yes	T4,T6,T43	Yes	T4,T6,T43	INPUT
tl_keymgr_i.d_sink	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_keymgr_i.d_source[5:0]	Yes	Yes	*T58,*T71,*T148	Yes	T58,T71,T148	INPUT
tl_keymgr_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_keymgr_i.d_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_keymgr_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_keymgr_i.d_opcode[0]	Yes	Yes	*T4,*T6,*T43	Yes	T4,T6,T43	INPUT
tl_keymgr_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_keymgr_i.d_valid	Yes	Yes	T4,T6,T43	Yes	T4,T6,T43	INPUT
tl_rv_core_ibex__cfg_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__cfg_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__cfg_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_source[5:0]	Yes	Yes	*T257,*T78,*T79	Yes	T257,T78,T79	OUTPUT
tl_rv_core_ibex__cfg_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_rv_core_ibex__cfg_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_opcode[2:0]	Yes	Yes	T78,T79,T132	Yes	T78,T79,T132	OUTPUT
tl_rv_core_ibex__cfg_o.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_core_ibex__cfg_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rv_core_ibex__cfg_i.d_error	Yes	Yes	T78,T132,T80	Yes	T78,T79,T132	INPUT
tl_rv_core_ibex__cfg_i.d_user.data_intg[6:0]	Yes	Yes	T4,T6,T17	Yes	T4,T6,T17	INPUT
tl_rv_core_ibex__cfg_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rv_core_ibex__cfg_i.d_data[31:0]	Yes	Yes	T4,T6,T43	Yes	T4,T6,T43	INPUT
tl_rv_core_ibex__cfg_i.d_sink	Yes	Yes	T78,T80,T82	Yes	T78,T80,T82	INPUT
tl_rv_core_ibex__cfg_i.d_source[5:0]	Yes	Yes	*T78,*T80,*T82	Yes	T257,T78,T79	INPUT
tl_rv_core_ibex__cfg_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cfg_i.d_size[1:0]	Yes	Yes	T78,T80,T82	Yes	T78,T79,T80	INPUT
tl_rv_core_ibex__cfg_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cfg_i.d_opcode[0]	Yes	Yes	*T4,*T6,*T43	Yes	T4,T6,T43	INPUT
tl_rv_core_ibex__cfg_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cfg_i.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_sram_ctrl_main__regs_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.data_intg[6:0]	Yes	Yes	T4,T6,T57	Yes	T4,T6,T57	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T6,T57	Yes	T4,T6,T57	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.instr_type[3:0]	Yes	Yes	T4,T6,T57	Yes	T4,T6,T57	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_data[31:0]	Yes	Yes	T4,T6,T57	Yes	T4,T6,T57	OUTPUT
tl_sram_ctrl_main__regs_o.a_mask[3:0]	Yes	Yes	T4,T6,T57	Yes	T4,T6,T57	OUTPUT
tl_sram_ctrl_main__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_source[5:0]	Yes	Yes	*T78,*T79,*T80	Yes	T78,T79,T80	OUTPUT
tl_sram_ctrl_main__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_sram_ctrl_main__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_opcode[2:0]	Yes	Yes	T78,T79,T132	Yes	T78,T79,T132	OUTPUT
tl_sram_ctrl_main__regs_o.a_valid	Yes	Yes	T4,T6,T57	Yes	T4,T6,T57	OUTPUT
tl_sram_ctrl_main__regs_i.a_ready	Yes	Yes	T4,T6,T57	Yes	T4,T6,T57	INPUT
tl_sram_ctrl_main__regs_i.d_error	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_sram_ctrl_main__regs_i.d_user.data_intg[6:0]	Yes	Yes	T300,T301,T302	Yes	T300,T301,T302	INPUT
tl_sram_ctrl_main__regs_i.d_user.rsp_intg[6:0]	Yes	Yes	T54,T122,T55	Yes	T4,T6,T57	INPUT
tl_sram_ctrl_main__regs_i.d_data[31:0]	Yes	Yes	T54,T122,T55	Yes	T4,T6,T57	INPUT
tl_sram_ctrl_main__regs_i.d_sink	Yes	Yes	T79,T80,T82	Yes	T78,T79,T80	INPUT
tl_sram_ctrl_main__regs_i.d_source[5:0]	Yes	Yes	*T79,*T80,*T82	Yes	T78,T79,T80	INPUT
tl_sram_ctrl_main__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__regs_i.d_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_sram_ctrl_main__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__regs_i.d_opcode[0]	Yes	Yes	*T122,*T300,*T280	Yes	T122,T241,T300	INPUT
tl_sram_ctrl_main__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__regs_i.d_valid	Yes	Yes	T4,T6,T57	Yes	T4,T6,T57	INPUT
tl_sram_ctrl_main__ram_o.d_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_main__ram_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_main__ram_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_source[5:0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_main__ram_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_sram_ctrl_main__ram_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_opcode[2:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_main__ram_o.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_sram_ctrl_main__ram_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_sram_ctrl_main__ram_i.d_error	Yes	Yes	T4,T5,T6	Yes	T5,T43,T19	INPUT
tl_sram_ctrl_main__ram_i.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_sram_ctrl_main__ram_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_sram_ctrl_main__ram_i.d_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_sram_ctrl_main__ram_i.d_sink	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_sram_ctrl_main__ram_i.d_source[5:0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_sram_ctrl_main__ram_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__ram_i.d_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_sram_ctrl_main__ram_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__ram_i.d_opcode[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_sram_ctrl_main__ram_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__ram_i.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
scanmode_i[3:0]	Unreachable	Unreachable		Unreachable		INPUT

*Tests covering at least one bit in the range