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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
95.99 95.40 93.58 95.44 94.39 97.53 99.60


Total test records in report: 2906
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T256 /workspace/coverage/default/0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.1989158924 Jul 11 08:06:56 PM PDT 24 Jul 11 08:15:09 PM PDT 24 4204408362 ps
T272 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.3405696861 Jul 11 08:12:37 PM PDT 24 Jul 11 08:57:56 PM PDT 24 10603478858 ps
T348 /workspace/coverage/default/0.chip_sw_pwrmgr_all_reset_reqs.2898262831 Jul 11 08:01:46 PM PDT 24 Jul 11 08:24:54 PM PDT 24 8404074554 ps
T212 /workspace/coverage/default/1.chip_sw_rstmgr_sw_rst.2507566583 Jul 11 08:08:31 PM PDT 24 Jul 11 08:12:30 PM PDT 24 3154053548 ps
T958 /workspace/coverage/default/0.chip_sw_clkmgr_off_peri.2932727338 Jul 11 08:01:28 PM PDT 24 Jul 11 08:25:40 PM PDT 24 10844400144 ps
T216 /workspace/coverage/default/1.chip_sw_i2c_host_tx_rx.2545233201 Jul 11 08:06:50 PM PDT 24 Jul 11 08:17:48 PM PDT 24 4426717916 ps
T959 /workspace/coverage/default/4.chip_sw_uart_tx_rx_idx3.2665967606 Jul 11 08:28:41 PM PDT 24 Jul 11 08:39:58 PM PDT 24 4568374160 ps
T218 /workspace/coverage/default/0.chip_sw_sleep_pwm_pulses.398085778 Jul 11 07:59:43 PM PDT 24 Jul 11 08:21:21 PM PDT 24 8999705040 ps
T73 /workspace/coverage/default/2.chip_tap_straps_testunlock0.4183906816 Jul 11 08:21:56 PM PDT 24 Jul 11 08:25:54 PM PDT 24 3248592243 ps
T36 /workspace/coverage/default/2.chip_sw_gpio_smoketest.2079247454 Jul 11 08:26:01 PM PDT 24 Jul 11 08:32:03 PM PDT 24 3284517461 ps
T960 /workspace/coverage/default/2.chip_sw_edn_auto_mode.906638834 Jul 11 08:26:29 PM PDT 24 Jul 11 08:52:19 PM PDT 24 7700980598 ps
T775 /workspace/coverage/default/15.chip_sw_alert_handler_lpg_sleep_mode_alerts.530488726 Jul 11 08:32:21 PM PDT 24 Jul 11 08:38:23 PM PDT 24 3778812510 ps
T961 /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_dev.924052660 Jul 11 08:04:01 PM PDT 24 Jul 11 08:23:06 PM PDT 24 8253578668 ps
T788 /workspace/coverage/default/36.chip_sw_alert_handler_lpg_sleep_mode_alerts.513763918 Jul 11 08:35:41 PM PDT 24 Jul 11 08:41:27 PM PDT 24 3792661308 ps
T962 /workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_meas.2654239212 Jul 11 08:30:23 PM PDT 24 Jul 11 09:23:32 PM PDT 24 14471113888 ps
T373 /workspace/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.3505045458 Jul 11 08:23:36 PM PDT 24 Jul 11 08:36:44 PM PDT 24 4600338077 ps
T25 /workspace/coverage/default/1.chip_sw_spi_device_pass_through_collision.3264759655 Jul 11 08:09:46 PM PDT 24 Jul 11 08:20:15 PM PDT 24 5025712417 ps
T371 /workspace/coverage/default/0.chip_sw_aon_timer_irq.717947207 Jul 11 08:01:38 PM PDT 24 Jul 11 08:08:27 PM PDT 24 3481554712 ps
T145 /workspace/coverage/default/1.chip_sw_pwrmgr_full_aon_reset.3511163736 Jul 11 08:09:30 PM PDT 24 Jul 11 08:17:46 PM PDT 24 7985100695 ps
T402 /workspace/coverage/default/23.chip_sw_all_escalation_resets.2694736195 Jul 11 08:32:46 PM PDT 24 Jul 11 08:42:36 PM PDT 24 4620121592 ps
T963 /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_rma.3195228811 Jul 11 08:03:23 PM PDT 24 Jul 11 08:24:15 PM PDT 24 9506826760 ps
T146 /workspace/coverage/default/0.chip_sw_pwrmgr_full_aon_reset.1251139412 Jul 11 08:03:01 PM PDT 24 Jul 11 08:09:37 PM PDT 24 7379201046 ps
T391 /workspace/coverage/default/1.chip_sw_edn_boot_mode.1379327682 Jul 11 08:15:22 PM PDT 24 Jul 11 08:23:51 PM PDT 24 3148494480 ps
T304 /workspace/coverage/default/19.chip_sw_all_escalation_resets.1598383670 Jul 11 08:33:12 PM PDT 24 Jul 11 08:43:37 PM PDT 24 6109982254 ps
T310 /workspace/coverage/default/11.chip_sw_all_escalation_resets.1477753126 Jul 11 08:30:42 PM PDT 24 Jul 11 08:40:10 PM PDT 24 4094613550 ps
T311 /workspace/coverage/default/0.chip_sw_entropy_src_smoketest.661803166 Jul 11 08:09:58 PM PDT 24 Jul 11 08:18:03 PM PDT 24 3288955412 ps
T312 /workspace/coverage/default/1.rom_e2e_smoke.103136489 Jul 11 08:29:05 PM PDT 24 Jul 11 09:31:25 PM PDT 24 14953121660 ps
T162 /workspace/coverage/default/0.chip_sw_otp_ctrl_escalation.2495876021 Jul 11 08:04:06 PM PDT 24 Jul 11 08:13:11 PM PDT 24 4710748880 ps
T313 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.2415756591 Jul 11 08:10:21 PM PDT 24 Jul 11 09:16:13 PM PDT 24 15126279910 ps
T314 /workspace/coverage/default/13.chip_sw_lc_ctrl_transition.4028601143 Jul 11 08:31:48 PM PDT 24 Jul 11 08:38:56 PM PDT 24 5133015354 ps
T315 /workspace/coverage/default/0.chip_sw_rv_dm_access_after_escalation_reset.428940416 Jul 11 08:05:50 PM PDT 24 Jul 11 08:13:20 PM PDT 24 4570743046 ps
T316 /workspace/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.3390084885 Jul 11 08:24:38 PM PDT 24 Jul 11 08:43:16 PM PDT 24 7250177958 ps
T317 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_dev.1950797364 Jul 11 08:11:13 PM PDT 24 Jul 11 09:43:45 PM PDT 24 23241996867 ps
T235 /workspace/coverage/default/2.chip_sw_flash_init.2424043164 Jul 11 08:24:08 PM PDT 24 Jul 11 08:48:35 PM PDT 24 19751182088 ps
T964 /workspace/coverage/default/0.chip_sw_clkmgr_off_hmac_trans.2070035212 Jul 11 08:01:50 PM PDT 24 Jul 11 08:09:29 PM PDT 24 4703687392 ps
T2 /workspace/coverage/default/0.chip_sw_sleep_pin_wake.2824046199 Jul 11 08:01:57 PM PDT 24 Jul 11 08:05:28 PM PDT 24 3366485160 ps
T407 /workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.193028632 Jul 11 08:02:09 PM PDT 24 Jul 11 08:21:47 PM PDT 24 10173922615 ps
T408 /workspace/coverage/default/69.chip_sw_all_escalation_resets.883025440 Jul 11 08:36:58 PM PDT 24 Jul 11 08:48:42 PM PDT 24 6465791384 ps
T409 /workspace/coverage/default/33.chip_sw_all_escalation_resets.3070546268 Jul 11 08:38:39 PM PDT 24 Jul 11 08:51:57 PM PDT 24 5379944964 ps
T410 /workspace/coverage/default/0.chip_sw_edn_entropy_reqs_jitter.2349109972 Jul 11 08:06:56 PM PDT 24 Jul 11 08:29:06 PM PDT 24 7508955815 ps
T3 /workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_wake_ups.1163416284 Jul 11 08:21:24 PM PDT 24 Jul 11 08:47:43 PM PDT 24 22193699072 ps
T411 /workspace/coverage/default/1.chip_sw_lc_ctrl_otp_hw_cfg0.1166450029 Jul 11 08:12:02 PM PDT 24 Jul 11 08:16:49 PM PDT 24 2559588260 ps
T412 /workspace/coverage/default/0.chip_sw_keymgr_key_derivation_prod.2337230375 Jul 11 08:01:10 PM PDT 24 Jul 11 08:15:22 PM PDT 24 5722526502 ps
T413 /workspace/coverage/default/2.chip_sw_ast_clk_outputs.1204406701 Jul 11 08:27:22 PM PDT 24 Jul 11 08:44:29 PM PDT 24 7745396260 ps
T414 /workspace/coverage/default/1.chip_sw_rstmgr_smoketest.1876159704 Jul 11 08:22:12 PM PDT 24 Jul 11 08:27:15 PM PDT 24 2601645160 ps
T7 /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_wake_ups.3894358600 Jul 11 08:03:19 PM PDT 24 Jul 11 08:32:50 PM PDT 24 25854841506 ps
T965 /workspace/coverage/default/1.chip_sw_uart_smoketest.401173846 Jul 11 08:22:26 PM PDT 24 Jul 11 08:28:30 PM PDT 24 3115032128 ps
T966 /workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_invalid_meas.3764506889 Jul 11 08:27:40 PM PDT 24 Jul 11 09:17:35 PM PDT 24 15292485784 ps
T789 /workspace/coverage/default/42.chip_sw_all_escalation_resets.2202711972 Jul 11 08:35:41 PM PDT 24 Jul 11 08:45:35 PM PDT 24 5951275288 ps
T967 /workspace/coverage/default/8.chip_sw_lc_ctrl_transition.1032001920 Jul 11 08:32:27 PM PDT 24 Jul 11 08:40:22 PM PDT 24 4648042104 ps
T968 /workspace/coverage/default/6.chip_sw_csrng_edn_concurrency.3685647868 Jul 11 08:30:58 PM PDT 24 Jul 11 09:06:52 PM PDT 24 9083102324 ps
T969 /workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq.715885260 Jul 11 08:27:46 PM PDT 24 Jul 11 09:06:54 PM PDT 24 13002888170 ps
T34 /workspace/coverage/default/0.chip_sw_usbdev_config_host.199095726 Jul 11 08:01:38 PM PDT 24 Jul 11 08:37:22 PM PDT 24 8014907696 ps
T234 /workspace/coverage/default/2.chip_sw_lc_walkthrough_prod.1294636921 Jul 11 08:25:29 PM PDT 24 Jul 11 10:08:46 PM PDT 24 48223942448 ps
T970 /workspace/coverage/default/2.chip_sw_kmac_smoketest.1574016870 Jul 11 08:33:37 PM PDT 24 Jul 11 08:39:04 PM PDT 24 3253031664 ps
T971 /workspace/coverage/default/2.chip_sw_entropy_src_ast_rng_req.2700468146 Jul 11 08:29:20 PM PDT 24 Jul 11 08:33:27 PM PDT 24 2941926902 ps
T35 /workspace/coverage/default/0.chip_sw_usbdev_dpi.1951550808 Jul 11 08:01:37 PM PDT 24 Jul 11 08:59:04 PM PDT 24 11908689448 ps
T972 /workspace/coverage/default/1.chip_sw_aon_timer_irq.2649732109 Jul 11 08:12:23 PM PDT 24 Jul 11 08:21:31 PM PDT 24 4198960588 ps
T973 /workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq.1891203173 Jul 11 08:22:44 PM PDT 24 Jul 11 08:33:05 PM PDT 24 3961737758 ps
T48 /workspace/coverage/default/2.chip_sw_sysrst_ctrl_ulp_z3_wakeup.1310366497 Jul 11 08:23:54 PM PDT 24 Jul 11 08:32:53 PM PDT 24 6499531640 ps
T974 /workspace/coverage/default/1.chip_sw_rv_plic_smoketest.3120293240 Jul 11 08:22:18 PM PDT 24 Jul 11 08:27:48 PM PDT 24 2895411128 ps
T975 /workspace/coverage/default/0.chip_sw_aes_enc_jitter_en_reduced_freq.3233759988 Jul 11 08:04:52 PM PDT 24 Jul 11 08:07:48 PM PDT 24 3588518260 ps
T976 /workspace/coverage/default/2.chip_sw_example_rom.1339983962 Jul 11 08:21:13 PM PDT 24 Jul 11 08:23:09 PM PDT 24 2285460328 ps
T403 /workspace/coverage/default/58.chip_sw_all_escalation_resets.315910980 Jul 11 08:35:13 PM PDT 24 Jul 11 08:45:05 PM PDT 24 4675185120 ps
T977 /workspace/coverage/default/2.chip_sw_lc_walkthrough_testunlocks.460234013 Jul 11 08:25:03 PM PDT 24 Jul 11 08:59:29 PM PDT 24 24239416790 ps
T978 /workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.1010700176 Jul 11 08:30:04 PM PDT 24 Jul 11 08:38:33 PM PDT 24 4490308579 ps
T979 /workspace/coverage/default/1.chip_sw_flash_scrambling_smoketest.160103784 Jul 11 08:28:28 PM PDT 24 Jul 11 08:32:14 PM PDT 24 2430583796 ps
T980 /workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.1255044422 Jul 11 08:01:10 PM PDT 24 Jul 11 08:22:21 PM PDT 24 8847644061 ps
T461 /workspace/coverage/default/0.chip_sw_edn_entropy_reqs.497158332 Jul 11 08:05:22 PM PDT 24 Jul 11 08:29:00 PM PDT 24 7140251496 ps
T147 /workspace/coverage/default/1.chip_sw_exit_test_unlocked_bootstrap.594012492 Jul 11 08:06:40 PM PDT 24 Jul 11 11:00:12 PM PDT 24 59385372180 ps
T175 /workspace/coverage/default/73.chip_sw_all_escalation_resets.3671849231 Jul 11 08:38:44 PM PDT 24 Jul 11 08:47:16 PM PDT 24 4888893200 ps
T981 /workspace/coverage/default/1.chip_sw_aon_timer_wdog_bite_reset.1660237565 Jul 11 08:10:44 PM PDT 24 Jul 11 08:21:57 PM PDT 24 7707481456 ps
T404 /workspace/coverage/default/0.chip_sw_rom_ctrl_integrity_check.949189661 Jul 11 08:03:51 PM PDT 24 Jul 11 08:14:41 PM PDT 24 8107647819 ps
T813 /workspace/coverage/default/13.chip_sw_alert_handler_lpg_sleep_mode_alerts.974729167 Jul 11 08:31:57 PM PDT 24 Jul 11 08:39:48 PM PDT 24 3847758366 ps
T786 /workspace/coverage/default/75.chip_sw_alert_handler_lpg_sleep_mode_alerts.148916972 Jul 11 08:41:05 PM PDT 24 Jul 11 08:47:52 PM PDT 24 3780294824 ps
T351 /workspace/coverage/default/2.chip_sw_uart_tx_rx.3175574177 Jul 11 08:22:18 PM PDT 24 Jul 11 08:34:50 PM PDT 24 4186611658 ps
T357 /workspace/coverage/default/35.chip_sw_all_escalation_resets.732109315 Jul 11 08:33:51 PM PDT 24 Jul 11 08:42:31 PM PDT 24 5321214384 ps
T839 /workspace/coverage/default/69.chip_sw_alert_handler_lpg_sleep_mode_alerts.1320135828 Jul 11 08:37:19 PM PDT 24 Jul 11 08:43:12 PM PDT 24 4284711608 ps
T982 /workspace/coverage/default/1.chip_sw_keymgr_sideload_kmac.618419615 Jul 11 08:19:53 PM PDT 24 Jul 11 08:45:24 PM PDT 24 8792442760 ps
T983 /workspace/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en.1558454952 Jul 11 08:24:30 PM PDT 24 Jul 11 08:44:42 PM PDT 24 5977200000 ps
T745 /workspace/coverage/default/0.rom_e2e_jtag_debug_test_unlocked0.4202298439 Jul 11 08:06:23 PM PDT 24 Jul 11 08:40:08 PM PDT 24 10341186909 ps
T326 /workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx1.1274150848 Jul 11 08:02:58 PM PDT 24 Jul 11 08:15:59 PM PDT 24 5010415104 ps
T984 /workspace/coverage/default/1.chip_sw_aes_enc.885293013 Jul 11 08:11:14 PM PDT 24 Jul 11 08:15:07 PM PDT 24 2752090168 ps
T352 /workspace/coverage/default/0.chip_sw_uart_tx_rx.4111883272 Jul 11 08:00:27 PM PDT 24 Jul 11 08:11:03 PM PDT 24 4322658790 ps
T103 /workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_wake_ups.1902922728 Jul 11 08:27:27 PM PDT 24 Jul 11 08:35:36 PM PDT 24 7572524576 ps
T362 /workspace/coverage/default/1.chip_sw_flash_ctrl_ops.620462665 Jul 11 08:06:28 PM PDT 24 Jul 11 08:15:09 PM PDT 24 3819572104 ps
T985 /workspace/coverage/default/2.chip_sw_flash_ctrl_access.3073732188 Jul 11 08:23:42 PM PDT 24 Jul 11 08:39:51 PM PDT 24 6285152728 ps
T730 /workspace/coverage/default/1.chip_sw_sleep_pwm_pulses.886762752 Jul 11 08:10:54 PM PDT 24 Jul 11 08:35:19 PM PDT 24 9001543728 ps
T986 /workspace/coverage/default/0.chip_sw_flash_ctrl_access.1929823844 Jul 11 08:01:41 PM PDT 24 Jul 11 08:20:53 PM PDT 24 6460188920 ps
T987 /workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_reset_reqs.1635994508 Jul 11 08:08:52 PM PDT 24 Jul 11 08:49:54 PM PDT 24 27581595928 ps
T988 /workspace/coverage/default/5.chip_sw_lc_ctrl_transition.1256055606 Jul 11 08:28:42 PM PDT 24 Jul 11 08:42:29 PM PDT 24 12104063853 ps
T261 /workspace/coverage/default/0.chip_sw_rstmgr_cpu_info.1231581657 Jul 11 08:00:14 PM PDT 24 Jul 11 08:09:49 PM PDT 24 5557363720 ps
T989 /workspace/coverage/default/1.chip_tap_straps_dev.33412646 Jul 11 08:20:58 PM PDT 24 Jul 11 08:44:59 PM PDT 24 14375919507 ps
T305 /workspace/coverage/default/96.chip_sw_all_escalation_resets.3738594694 Jul 11 08:39:12 PM PDT 24 Jul 11 08:48:17 PM PDT 24 4411141368 ps
T791 /workspace/coverage/default/6.chip_sw_all_escalation_resets.336602563 Jul 11 08:30:31 PM PDT 24 Jul 11 08:39:54 PM PDT 24 6290131000 ps
T169 /workspace/coverage/default/0.chip_sw_otp_ctrl_vendor_test_csr_access.1525508200 Jul 11 08:03:07 PM PDT 24 Jul 11 08:07:36 PM PDT 24 3030579623 ps
T816 /workspace/coverage/default/53.chip_sw_alert_handler_lpg_sleep_mode_alerts.726531967 Jul 11 08:37:16 PM PDT 24 Jul 11 08:44:46 PM PDT 24 3914307928 ps
T363 /workspace/coverage/default/2.chip_sw_hmac_enc_jitter_en_reduced_freq.3468269406 Jul 11 08:26:53 PM PDT 24 Jul 11 08:30:46 PM PDT 24 2675494056 ps
T262 /workspace/coverage/default/66.chip_sw_all_escalation_resets.539829002 Jul 11 08:36:05 PM PDT 24 Jul 11 08:44:36 PM PDT 24 5072875664 ps
T990 /workspace/coverage/default/1.rom_e2e_static_critical.72863617 Jul 11 08:26:09 PM PDT 24 Jul 11 09:40:11 PM PDT 24 16966205562 ps
T991 /workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.4233456659 Jul 11 08:21:42 PM PDT 24 Jul 11 08:39:07 PM PDT 24 8662358014 ps
T992 /workspace/coverage/default/2.chip_sw_rstmgr_sw_rst.3875829678 Jul 11 08:25:04 PM PDT 24 Jul 11 08:29:04 PM PDT 24 3123025294 ps
T708 /workspace/coverage/default/0.chip_sw_power_idle_load.32611589 Jul 11 08:07:35 PM PDT 24 Jul 11 08:20:24 PM PDT 24 4563119038 ps
T364 /workspace/coverage/default/4.chip_sw_uart_tx_rx_idx1.567208703 Jul 11 08:29:44 PM PDT 24 Jul 11 08:41:15 PM PDT 24 4929878118 ps
T26 /workspace/coverage/default/0.chip_sw_spi_device_pass_through_collision.925505070 Jul 11 08:02:57 PM PDT 24 Jul 11 08:12:15 PM PDT 24 4126099348 ps
T764 /workspace/coverage/default/19.chip_sw_alert_handler_lpg_sleep_mode_alerts.2290591084 Jul 11 08:33:16 PM PDT 24 Jul 11 08:39:57 PM PDT 24 4280823240 ps
T993 /workspace/coverage/default/1.chip_sw_rv_dm_access_after_wakeup.2556243507 Jul 11 08:23:03 PM PDT 24 Jul 11 08:31:30 PM PDT 24 6431861668 ps
T81 /workspace/coverage/default/2.chip_jtag_mem_access.1355556895 Jul 11 08:15:07 PM PDT 24 Jul 11 08:42:12 PM PDT 24 14477534320 ps
T994 /workspace/coverage/default/0.chip_sw_clkmgr_off_aes_trans.1804060880 Jul 11 08:03:26 PM PDT 24 Jul 11 08:11:41 PM PDT 24 4861380872 ps
T732 /workspace/coverage/default/4.chip_sw_alert_handler_lpg_sleep_mode_alerts.2562017820 Jul 11 08:29:00 PM PDT 24 Jul 11 08:36:34 PM PDT 24 3652769080 ps
T206 /workspace/coverage/default/0.chip_sw_sysrst_ctrl_inputs.3405003030 Jul 11 08:03:28 PM PDT 24 Jul 11 08:09:42 PM PDT 24 3280785652 ps
T385 /workspace/coverage/default/0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.134585296 Jul 11 08:05:59 PM PDT 24 Jul 11 08:12:17 PM PDT 24 5814837792 ps
T252 /workspace/coverage/default/2.chip_sw_rv_timer_irq.1362166317 Jul 11 08:26:13 PM PDT 24 Jul 11 08:32:15 PM PDT 24 3047289530 ps
T769 /workspace/coverage/default/16.chip_sw_alert_handler_lpg_sleep_mode_alerts.2389697256 Jul 11 08:32:40 PM PDT 24 Jul 11 08:40:24 PM PDT 24 3492116752 ps
T995 /workspace/coverage/default/11.chip_sw_alert_handler_lpg_sleep_mode_alerts.173847110 Jul 11 08:33:37 PM PDT 24 Jul 11 08:40:04 PM PDT 24 3622694960 ps
T37 /workspace/coverage/default/1.chip_sw_gpio.120963694 Jul 11 08:08:21 PM PDT 24 Jul 11 08:16:22 PM PDT 24 4288865768 ps
T996 /workspace/coverage/default/0.chip_sw_edn_sw_mode.4062576209 Jul 11 08:02:01 PM PDT 24 Jul 11 08:34:08 PM PDT 24 7900678028 ps
T997 /workspace/coverage/default/1.chip_sw_hmac_oneshot.995814590 Jul 11 08:10:15 PM PDT 24 Jul 11 08:15:12 PM PDT 24 3160171704 ps
T46 /workspace/coverage/default/1.chip_sw_spi_host_tx_rx.3475988026 Jul 11 08:06:49 PM PDT 24 Jul 11 08:12:26 PM PDT 24 3261112576 ps
T998 /workspace/coverage/default/1.chip_sw_lc_walkthrough_prodend.1873526193 Jul 11 08:08:18 PM PDT 24 Jul 11 08:25:41 PM PDT 24 7879780550 ps
T999 /workspace/coverage/default/2.chip_sw_rstmgr_smoketest.45933103 Jul 11 08:34:30 PM PDT 24 Jul 11 08:38:58 PM PDT 24 2875885630 ps
T1000 /workspace/coverage/default/0.chip_sw_keymgr_sideload_kmac.1935671965 Jul 11 08:03:42 PM PDT 24 Jul 11 08:37:19 PM PDT 24 10591352440 ps
T538 /workspace/coverage/default/2.chip_sw_pwrmgr_all_reset_reqs.495314040 Jul 11 08:26:46 PM PDT 24 Jul 11 08:57:15 PM PDT 24 9480892209 ps
T1001 /workspace/coverage/default/1.chip_sw_example_concurrency.2983980054 Jul 11 08:04:36 PM PDT 24 Jul 11 08:08:11 PM PDT 24 2747584900 ps
T758 /workspace/coverage/default/82.chip_sw_alert_handler_lpg_sleep_mode_alerts.3397624345 Jul 11 08:42:38 PM PDT 24 Jul 11 08:49:28 PM PDT 24 4406927786 ps
T1002 /workspace/coverage/default/2.chip_sw_edn_sw_mode.2876887993 Jul 11 08:29:16 PM PDT 24 Jul 11 08:47:57 PM PDT 24 6898306974 ps
T796 /workspace/coverage/default/59.chip_sw_all_escalation_resets.1205618952 Jul 11 08:36:18 PM PDT 24 Jul 11 08:48:19 PM PDT 24 5765229012 ps
T1003 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.3441674393 Jul 11 08:09:25 PM PDT 24 Jul 11 09:09:27 PM PDT 24 15220253892 ps
T829 /workspace/coverage/default/5.chip_sw_alert_handler_lpg_sleep_mode_alerts.4007985124 Jul 11 08:29:31 PM PDT 24 Jul 11 08:37:29 PM PDT 24 4112942048 ps
T90 /workspace/coverage/default/44.chip_sw_all_escalation_resets.4107508851 Jul 11 08:39:48 PM PDT 24 Jul 11 08:49:38 PM PDT 24 5955956112 ps
T536 /workspace/coverage/default/1.chip_sw_rv_core_ibex_nmi_irq.2981400283 Jul 11 08:10:03 PM PDT 24 Jul 11 08:27:49 PM PDT 24 4888926796 ps
T1004 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.1802399702 Jul 11 08:27:30 PM PDT 24 Jul 11 08:37:04 PM PDT 24 3821633640 ps
T228 /workspace/coverage/default/0.chip_sw_keymgr_sideload_aes.2941273538 Jul 11 08:01:27 PM PDT 24 Jul 11 08:32:48 PM PDT 24 10310376488 ps
T840 /workspace/coverage/default/48.chip_sw_all_escalation_resets.1812526620 Jul 11 08:36:40 PM PDT 24 Jul 11 08:49:32 PM PDT 24 5690629852 ps
T1005 /workspace/coverage/default/2.chip_sw_rv_timer_smoketest.303548958 Jul 11 08:31:55 PM PDT 24 Jul 11 08:36:27 PM PDT 24 3070225920 ps
T811 /workspace/coverage/default/6.chip_sw_alert_handler_lpg_sleep_mode_alerts.3818608389 Jul 11 08:29:35 PM PDT 24 Jul 11 08:36:19 PM PDT 24 3816904310 ps
T1006 /workspace/coverage/default/0.chip_sw_entropy_src_kat_test.676174985 Jul 11 08:04:57 PM PDT 24 Jul 11 08:08:34 PM PDT 24 2871757048 ps
T1007 /workspace/coverage/default/0.rom_e2e_asm_init_prod.3239228884 Jul 11 08:09:10 PM PDT 24 Jul 11 09:21:15 PM PDT 24 15412738034 ps
T1008 /workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_por_reset.3035285067 Jul 11 08:03:14 PM PDT 24 Jul 11 08:13:26 PM PDT 24 8078426825 ps
T1009 /workspace/coverage/default/3.chip_sw_uart_tx_rx_idx3.3274986328 Jul 11 08:34:21 PM PDT 24 Jul 11 08:43:46 PM PDT 24 3662687060 ps
T1010 /workspace/coverage/default/2.chip_sw_clkmgr_jitter_reduced_freq.2947921317 Jul 11 08:25:09 PM PDT 24 Jul 11 08:28:23 PM PDT 24 2968573720 ps
T202 /workspace/coverage/default/0.chip_sw_inject_scramble_seed.554224 Jul 11 08:00:20 PM PDT 24 Jul 11 11:22:52 PM PDT 24 63771929776 ps
T1011 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.1530198561 Jul 11 08:27:34 PM PDT 24 Jul 11 08:37:53 PM PDT 24 4345793070 ps
T1012 /workspace/coverage/default/0.chip_sw_rstmgr_sw_req.3000656984 Jul 11 08:00:52 PM PDT 24 Jul 11 08:09:16 PM PDT 24 4304293934 ps
T282 /workspace/coverage/default/2.chip_sw_data_integrity_escalation.3524288214 Jul 11 08:22:37 PM PDT 24 Jul 11 08:35:53 PM PDT 24 5161904870 ps
T1013 /workspace/coverage/default/2.chip_sw_hmac_enc.1744300765 Jul 11 08:28:28 PM PDT 24 Jul 11 08:34:26 PM PDT 24 3548914564 ps
T831 /workspace/coverage/default/93.chip_sw_all_escalation_resets.1198416649 Jul 11 08:39:10 PM PDT 24 Jul 11 08:49:30 PM PDT 24 5984624600 ps
T1014 /workspace/coverage/default/2.chip_sw_hmac_oneshot.663020988 Jul 11 08:27:21 PM PDT 24 Jul 11 08:33:56 PM PDT 24 3418539048 ps
T833 /workspace/coverage/default/50.chip_sw_alert_handler_lpg_sleep_mode_alerts.3940170220 Jul 11 08:37:19 PM PDT 24 Jul 11 08:44:52 PM PDT 24 4130553728 ps
T275 /workspace/coverage/default/5.chip_sw_data_integrity_escalation.2817258184 Jul 11 08:28:34 PM PDT 24 Jul 11 08:41:00 PM PDT 24 5601757912 ps
T203 /workspace/coverage/default/1.chip_sw_inject_scramble_seed.3783336437 Jul 11 08:06:22 PM PDT 24 Jul 11 11:54:35 PM PDT 24 63670380018 ps
T104 /workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_wake_ups.3427043483 Jul 11 08:02:42 PM PDT 24 Jul 11 08:11:09 PM PDT 24 7160229214 ps
T1015 /workspace/coverage/default/2.chip_sw_uart_tx_rx_idx3.2889800169 Jul 11 08:22:55 PM PDT 24 Jul 11 08:34:30 PM PDT 24 4510391976 ps
T344 /workspace/coverage/default/2.chip_sw_i2c_device_tx_rx.1662764231 Jul 11 08:23:09 PM PDT 24 Jul 11 08:34:19 PM PDT 24 4387692102 ps
T1016 /workspace/coverage/default/0.rom_e2e_jtag_inject_dev.3515188181 Jul 11 08:07:39 PM PDT 24 Jul 11 08:41:12 PM PDT 24 24291721082 ps
T1017 /workspace/coverage/default/2.rom_e2e_smoke.3878513000 Jul 11 08:33:52 PM PDT 24 Jul 11 09:36:07 PM PDT 24 14740132136 ps
T1018 /workspace/coverage/default/1.chip_sw_rv_core_ibex_rnd.3122953801 Jul 11 08:09:55 PM PDT 24 Jul 11 08:26:47 PM PDT 24 5687260304 ps
T117 /workspace/coverage/default/1.chip_sw_csrng_edn_concurrency_reduced_freq.2679562224 Jul 11 08:22:51 PM PDT 24 Jul 12 01:40:04 AM PDT 24 132856009358 ps
T1019 /workspace/coverage/default/0.chip_sw_edn_auto_mode.2531969720 Jul 11 08:03:37 PM PDT 24 Jul 11 08:21:39 PM PDT 24 4709603262 ps
T1020 /workspace/coverage/default/1.chip_sw_kmac_mode_cshake.3888012593 Jul 11 08:19:02 PM PDT 24 Jul 11 08:22:59 PM PDT 24 3024832024 ps
T1021 /workspace/coverage/default/2.chip_sw_aes_smoketest.482169213 Jul 11 08:25:25 PM PDT 24 Jul 11 08:30:21 PM PDT 24 3462233800 ps
T249 /workspace/coverage/default/2.chip_sw_plic_sw_irq.2777447493 Jul 11 08:29:56 PM PDT 24 Jul 11 08:33:57 PM PDT 24 2504017972 ps
T784 /workspace/coverage/default/18.chip_sw_all_escalation_resets.3050129227 Jul 11 08:33:16 PM PDT 24 Jul 11 08:46:17 PM PDT 24 4739475900 ps
T166 /workspace/coverage/default/2.chip_sw_alert_handler_reverse_ping_in_deep_sleep.1369097863 Jul 11 08:26:35 PM PDT 24 Jul 11 11:54:34 PM PDT 24 255579438520 ps
T236 /workspace/coverage/default/1.chip_sw_flash_init.4273655332 Jul 11 08:06:56 PM PDT 24 Jul 11 08:40:44 PM PDT 24 25011891010 ps
T1022 /workspace/coverage/default/4.chip_tap_straps_rma.2298110491 Jul 11 08:27:11 PM PDT 24 Jul 11 08:29:45 PM PDT 24 2301685744 ps
T1023 /workspace/coverage/default/1.chip_sw_otp_ctrl_smoketest.2404624551 Jul 11 08:22:38 PM PDT 24 Jul 11 08:27:17 PM PDT 24 2371251320 ps
T237 /workspace/coverage/default/1.chip_sw_lc_walkthrough_prod.2222317323 Jul 11 08:06:53 PM PDT 24 Jul 11 09:37:54 PM PDT 24 47711112712 ps
T377 /workspace/coverage/default/38.chip_sw_all_escalation_resets.2472750824 Jul 11 08:35:54 PM PDT 24 Jul 11 08:45:03 PM PDT 24 5904191024 ps
T1024 /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.2531547939 Jul 11 08:10:53 PM PDT 24 Jul 11 08:18:34 PM PDT 24 6499718860 ps
T238 /workspace/coverage/default/0.chip_sw_lc_walkthrough_prod.2294947318 Jul 11 08:01:53 PM PDT 24 Jul 11 09:49:26 PM PDT 24 50357431980 ps
T87 /workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_pings.3666526670 Jul 11 08:11:36 PM PDT 24 Jul 11 08:35:19 PM PDT 24 11208558662 ps
T51 /workspace/coverage/default/0.chip_sw_spi_device_tpm.106452103 Jul 11 08:02:07 PM PDT 24 Jul 11 08:08:45 PM PDT 24 3156944158 ps
T1025 /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.2199238839 Jul 11 08:02:41 PM PDT 24 Jul 11 08:08:40 PM PDT 24 5299549140 ps
T1026 /workspace/coverage/default/1.chip_sw_hmac_enc.3972366791 Jul 11 08:10:22 PM PDT 24 Jul 11 08:14:39 PM PDT 24 2871883882 ps
T1027 /workspace/coverage/default/2.chip_sw_lc_walkthrough_rma.743968879 Jul 11 08:24:33 PM PDT 24 Jul 11 09:44:06 PM PDT 24 47427892914 ps
T1028 /workspace/coverage/default/4.chip_tap_straps_prod.1875478830 Jul 11 08:27:45 PM PDT 24 Jul 11 08:50:14 PM PDT 24 13886554952 ps
T1029 /workspace/coverage/default/1.chip_sw_alert_handler_reverse_ping_in_deep_sleep.1862399247 Jul 11 08:11:11 PM PDT 24 Jul 11 11:24:34 PM PDT 24 255381171276 ps
T239 /workspace/coverage/default/0.chip_sw_flash_init.1372924984 Jul 11 08:00:52 PM PDT 24 Jul 11 08:41:57 PM PDT 24 17635695877 ps
T1030 /workspace/coverage/default/1.chip_sw_flash_ctrl_clock_freqs.1757155832 Jul 11 08:08:56 PM PDT 24 Jul 11 08:25:07 PM PDT 24 5922480256 ps
T1031 /workspace/coverage/default/2.chip_sw_alert_handler_lpg_reset_toggle.1033535223 Jul 11 08:29:37 PM PDT 24 Jul 11 08:57:39 PM PDT 24 9430553944 ps
T785 /workspace/coverage/default/28.chip_sw_alert_handler_lpg_sleep_mode_alerts.4063592151 Jul 11 08:34:33 PM PDT 24 Jul 11 08:40:40 PM PDT 24 4019593170 ps
T179 /workspace/coverage/default/1.chip_sw_lc_ctrl_program_error.2410846950 Jul 11 08:21:41 PM PDT 24 Jul 11 08:28:09 PM PDT 24 4835505500 ps
T1032 /workspace/coverage/default/1.chip_sw_uart_tx_rx.2838953879 Jul 11 08:06:50 PM PDT 24 Jul 11 08:17:13 PM PDT 24 4283074308 ps
T340 /workspace/coverage/default/2.chip_sw_i2c_host_tx_rx_idx2.3874795872 Jul 11 08:26:43 PM PDT 24 Jul 11 08:39:18 PM PDT 24 4091111368 ps
T327 /workspace/coverage/default/0.chip_sw_i2c_host_tx_rx.1237454522 Jul 11 08:03:06 PM PDT 24 Jul 11 08:17:11 PM PDT 24 4372150316 ps
T1033 /workspace/coverage/default/1.chip_sw_pwrmgr_main_power_glitch_reset.179402969 Jul 11 08:07:43 PM PDT 24 Jul 11 08:12:43 PM PDT 24 4246641929 ps
T1034 /workspace/coverage/default/2.chip_sw_pwrmgr_wdog_reset.1197949713 Jul 11 08:28:51 PM PDT 24 Jul 11 08:40:00 PM PDT 24 5441795224 ps
T693 /workspace/coverage/default/4.chip_sw_csrng_edn_concurrency.335322190 Jul 11 08:28:51 PM PDT 24 Jul 11 10:05:49 PM PDT 24 29101091654 ps
T389 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.3368148453 Jul 11 08:09:19 PM PDT 24 Jul 11 09:58:54 PM PDT 24 23620584408 ps
T1035 /workspace/coverage/default/0.rom_e2e_static_critical.3278197675 Jul 11 08:07:41 PM PDT 24 Jul 11 09:21:27 PM PDT 24 16751771384 ps
T783 /workspace/coverage/default/39.chip_sw_all_escalation_resets.3318420898 Jul 11 08:35:59 PM PDT 24 Jul 11 08:46:04 PM PDT 24 5806482482 ps
T207 /workspace/coverage/default/1.chip_sw_sysrst_ctrl_reset.2972712610 Jul 11 08:08:52 PM PDT 24 Jul 11 08:38:58 PM PDT 24 24488579336 ps
T1036 /workspace/coverage/default/0.chip_sw_uart_tx_rx_idx3.1385527991 Jul 11 08:01:12 PM PDT 24 Jul 11 08:12:19 PM PDT 24 4443576768 ps
T1037 /workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en.1220041603 Jul 11 08:25:09 PM PDT 24 Jul 11 09:16:41 PM PDT 24 19571411042 ps
T1038 /workspace/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en.3844541849 Jul 11 08:00:16 PM PDT 24 Jul 11 08:15:18 PM PDT 24 6045023728 ps
T1039 /workspace/coverage/default/2.rom_keymgr_functest.3930173118 Jul 11 08:27:03 PM PDT 24 Jul 11 08:39:59 PM PDT 24 4285139304 ps
T1040 /workspace/coverage/default/2.chip_sw_aon_timer_sleep_wdog_sleep_pause.930394517 Jul 11 08:27:10 PM PDT 24 Jul 11 08:37:09 PM PDT 24 6614365460 ps
T799 /workspace/coverage/default/14.chip_sw_all_escalation_resets.3897648210 Jul 11 08:31:12 PM PDT 24 Jul 11 08:41:25 PM PDT 24 4415806860 ps
T150 /workspace/coverage/default/0.chip_sw_usbdev_setuprx.3704025062 Jul 11 08:00:32 PM PDT 24 Jul 11 08:12:28 PM PDT 24 4270427496 ps
T1041 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.1196700858 Jul 11 08:01:15 PM PDT 24 Jul 11 08:12:43 PM PDT 24 4860451046 ps
T776 /workspace/coverage/default/0.chip_sw_rstmgr_rst_cnsty_escalation.1375181722 Jul 11 08:00:45 PM PDT 24 Jul 11 08:10:19 PM PDT 24 5594938872 ps
T1042 /workspace/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en.1879870211 Jul 11 08:01:26 PM PDT 24 Jul 11 08:07:20 PM PDT 24 3162682264 ps
T456 /workspace/coverage/default/0.rom_e2e_jtag_debug_dev.2005465097 Jul 11 08:09:48 PM PDT 24 Jul 11 08:46:08 PM PDT 24 10629583554 ps
T1043 /workspace/coverage/default/55.chip_sw_all_escalation_resets.2372992371 Jul 11 08:36:02 PM PDT 24 Jul 11 08:46:05 PM PDT 24 5268130728 ps
T779 /workspace/coverage/default/2.chip_sw_clkmgr_reset_frequency.597157075 Jul 11 08:28:40 PM PDT 24 Jul 11 08:36:45 PM PDT 24 3687728600 ps
T1044 /workspace/coverage/default/0.chip_sw_otp_ctrl_dai_lock.328083253 Jul 11 08:00:35 PM PDT 24 Jul 11 09:29:41 PM PDT 24 28203702388 ps
T365 /workspace/coverage/default/1.chip_sw_uart_tx_rx_idx1.1240956366 Jul 11 08:07:20 PM PDT 24 Jul 11 08:17:07 PM PDT 24 4332566424 ps
T358 /workspace/coverage/default/2.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.775703594 Jul 11 08:26:28 PM PDT 24 Jul 11 08:34:22 PM PDT 24 18283179758 ps
T755 /workspace/coverage/default/30.chip_sw_all_escalation_resets.2586241685 Jul 11 08:38:07 PM PDT 24 Jul 11 08:49:25 PM PDT 24 5961543400 ps
T75 /workspace/coverage/default/0.chip_sw_usbdev_pullup.3114644499 Jul 11 08:00:13 PM PDT 24 Jul 11 08:03:57 PM PDT 24 3236545462 ps
T767 /workspace/coverage/default/64.chip_sw_all_escalation_resets.3180566747 Jul 11 08:36:19 PM PDT 24 Jul 11 08:44:29 PM PDT 24 4479115110 ps
T1045 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.1213291587 Jul 11 08:27:17 PM PDT 24 Jul 11 08:38:42 PM PDT 24 4184043740 ps
T230 /workspace/coverage/default/0.chip_sw_keymgr_sideload_otbn.1285436072 Jul 11 08:05:07 PM PDT 24 Jul 11 09:10:00 PM PDT 24 13121893976 ps
T1046 /workspace/coverage/default/1.chip_sw_clkmgr_reset_frequency.3146754871 Jul 11 08:20:48 PM PDT 24 Jul 11 08:30:39 PM PDT 24 3017601724 ps
T771 /workspace/coverage/default/15.chip_sw_all_escalation_resets.972668493 Jul 11 08:32:40 PM PDT 24 Jul 11 08:41:55 PM PDT 24 6265454640 ps
T188 /workspace/coverage/default/2.chip_sw_flash_rma_unlocked.3895405475 Jul 11 08:22:42 PM PDT 24 Jul 11 09:41:44 PM PDT 24 43522369672 ps
T283 /workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en.3802681496 Jul 11 08:03:28 PM PDT 24 Jul 11 08:12:42 PM PDT 24 4243669665 ps
T780 /workspace/coverage/default/66.chip_sw_alert_handler_lpg_sleep_mode_alerts.2786336231 Jul 11 08:36:53 PM PDT 24 Jul 11 08:43:33 PM PDT 24 4472898780 ps
T709 /workspace/coverage/default/1.chip_sw_power_idle_load.861634619 Jul 11 08:23:41 PM PDT 24 Jul 11 08:37:12 PM PDT 24 4234232136 ps
T1047 /workspace/coverage/default/0.chip_sw_example_concurrency.1148805778 Jul 11 08:02:30 PM PDT 24 Jul 11 08:06:10 PM PDT 24 3018471034 ps
T1048 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_prod_end.813317879 Jul 11 08:07:45 PM PDT 24 Jul 11 09:10:12 PM PDT 24 15534759408 ps
T76 /workspace/coverage/default/0.chip_sw_usbdev_pincfg.3089545341 Jul 11 08:00:00 PM PDT 24 Jul 11 09:51:15 PM PDT 24 31141228254 ps
T1049 /workspace/coverage/default/0.chip_sw_aes_smoketest.75888319 Jul 11 08:07:24 PM PDT 24 Jul 11 08:11:35 PM PDT 24 2281695172 ps
T1050 /workspace/coverage/default/0.chip_sw_flash_crash_alert.4205305184 Jul 11 08:03:45 PM PDT 24 Jul 11 08:17:17 PM PDT 24 4919402436 ps
T777 /workspace/coverage/default/29.chip_sw_all_escalation_resets.845117005 Jul 11 08:37:45 PM PDT 24 Jul 11 08:48:32 PM PDT 24 5078532100 ps
T306 /workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_alerts.338156439 Jul 11 08:27:19 PM PDT 24 Jul 11 08:35:42 PM PDT 24 3462824244 ps
T1051 /workspace/coverage/default/2.chip_sw_clkmgr_sleep_frequency.1992633838 Jul 11 08:27:08 PM PDT 24 Jul 11 08:39:32 PM PDT 24 4704355240 ps
T1052 /workspace/coverage/default/3.chip_tap_straps_dev.3365945962 Jul 11 08:26:32 PM PDT 24 Jul 11 08:29:39 PM PDT 24 2235302888 ps
T52 /workspace/coverage/default/1.chip_sw_spi_device_tpm.4236677529 Jul 11 08:07:21 PM PDT 24 Jul 11 08:12:59 PM PDT 24 3312971077 ps
T774 /workspace/coverage/default/55.chip_sw_alert_handler_lpg_sleep_mode_alerts.2594962287 Jul 11 08:37:38 PM PDT 24 Jul 11 08:42:45 PM PDT 24 2909289696 ps
T1053 /workspace/coverage/default/3.chip_tap_straps_rma.4214374647 Jul 11 08:27:03 PM PDT 24 Jul 11 08:31:26 PM PDT 24 3788509427 ps
T1054 /workspace/coverage/default/0.chip_sw_flash_ctrl_ops.1728156468 Jul 11 08:00:05 PM PDT 24 Jul 11 08:09:48 PM PDT 24 4519301308 ps
T803 /workspace/coverage/default/77.chip_sw_alert_handler_lpg_sleep_mode_alerts.2372393774 Jul 11 08:38:04 PM PDT 24 Jul 11 08:43:40 PM PDT 24 3251508512 ps
T1055 /workspace/coverage/default/1.chip_sw_sleep_sram_ret_contents_scramble.3108702413 Jul 11 08:20:26 PM PDT 24 Jul 11 08:32:39 PM PDT 24 6519740792 ps
T834 /workspace/coverage/default/0.chip_sw_all_escalation_resets.360492973 Jul 11 08:02:12 PM PDT 24 Jul 11 08:15:15 PM PDT 24 5645701820 ps
T1056 /workspace/coverage/default/11.chip_sw_lc_ctrl_transition.686591922 Jul 11 08:31:33 PM PDT 24 Jul 11 08:40:06 PM PDT 24 7053384628 ps
T208 /workspace/coverage/default/1.chip_sw_sysrst_ctrl_outputs.3896668928 Jul 11 08:10:35 PM PDT 24 Jul 11 08:16:52 PM PDT 24 3460539408 ps
T1057 /workspace/coverage/default/2.chip_sw_lc_walkthrough_dev.3489046753 Jul 11 08:25:23 PM PDT 24 Jul 11 09:51:40 PM PDT 24 49833648050 ps
T1058 /workspace/coverage/default/1.chip_sw_edn_sw_mode.518177882 Jul 11 08:10:29 PM PDT 24 Jul 11 08:37:08 PM PDT 24 7618760276 ps
T1059 /workspace/coverage/default/0.chip_sival_flash_info_access.289633243 Jul 11 08:00:58 PM PDT 24 Jul 11 08:05:38 PM PDT 24 2927981650 ps
T790 /workspace/coverage/default/80.chip_sw_alert_handler_lpg_sleep_mode_alerts.1014632366 Jul 11 08:37:48 PM PDT 24 Jul 11 08:43:14 PM PDT 24 3152501600 ps
T1060 /workspace/coverage/default/1.chip_sw_alert_handler_lpg_clkoff.856396004 Jul 11 08:10:26 PM PDT 24 Jul 11 08:33:04 PM PDT 24 6383268174 ps
T142 /workspace/coverage/default/4.chip_sw_sensor_ctrl_alert.108335733 Jul 11 08:27:53 PM PDT 24 Jul 11 08:35:18 PM PDT 24 4558809112 ps
T1061 /workspace/coverage/default/0.chip_sw_aes_entropy.3756669053 Jul 11 08:03:12 PM PDT 24 Jul 11 08:06:29 PM PDT 24 2443723304 ps
T1062 /workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.2532177808 Jul 11 08:22:28 PM PDT 24 Jul 11 09:28:36 PM PDT 24 24936206990 ps
T820 /workspace/coverage/default/57.chip_sw_alert_handler_lpg_sleep_mode_alerts.1194278982 Jul 11 08:36:25 PM PDT 24 Jul 11 08:44:04 PM PDT 24 4142160304 ps
T765 /workspace/coverage/default/16.chip_sw_all_escalation_resets.2192606140 Jul 11 08:34:28 PM PDT 24 Jul 11 08:44:58 PM PDT 24 4888076848 ps
T1063 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_rma.538775111 Jul 11 08:10:52 PM PDT 24 Jul 11 09:05:19 PM PDT 24 13896711905 ps
T1064 /workspace/coverage/default/2.chip_sw_kmac_entropy.3856621399 Jul 11 08:24:20 PM PDT 24 Jul 11 08:28:21 PM PDT 24 2382523514 ps
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