| T333 |
/workspace/coverage/default/2.chip_sw_entropy_src_csrng.4138788772 |
|
|
Jul 11 08:26:38 PM PDT 24 |
Jul 11 08:53:58 PM PDT 24 |
8333991244 ps |
| T346 |
/workspace/coverage/default/2.chip_sw_pwrmgr_lowpower_cancel.2297435148 |
|
|
Jul 11 08:27:18 PM PDT 24 |
Jul 11 08:34:15 PM PDT 24 |
3737329100 ps |
| T1065 |
/workspace/coverage/default/4.chip_sw_uart_rand_baudrate.1070993982 |
|
|
Jul 11 08:31:27 PM PDT 24 |
Jul 11 08:40:38 PM PDT 24 |
4019565576 ps |
| T1066 |
/workspace/coverage/default/0.chip_sw_uart_rand_baudrate.1916072742 |
|
|
Jul 11 08:00:09 PM PDT 24 |
Jul 11 08:10:39 PM PDT 24 |
3720487690 ps |
| T1067 |
/workspace/coverage/default/0.rom_keymgr_functest.99404827 |
|
|
Jul 11 08:05:31 PM PDT 24 |
Jul 11 08:19:43 PM PDT 24 |
5358506920 ps |
| T318 |
/workspace/coverage/default/2.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.2046886120 |
|
|
Jul 11 08:24:21 PM PDT 24 |
Jul 11 08:34:49 PM PDT 24 |
4627999192 ps |
| T716 |
/workspace/coverage/default/2.chip_sw_pwrmgr_sleep_disabled.4121201753 |
|
|
Jul 11 08:25:10 PM PDT 24 |
Jul 11 08:31:16 PM PDT 24 |
3479674778 ps |
| T1068 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.4051001291 |
|
|
Jul 11 08:09:07 PM PDT 24 |
Jul 11 09:05:32 PM PDT 24 |
15248306058 ps |
| T1069 |
/workspace/coverage/default/1.chip_sw_uart_rand_baudrate.4141862857 |
|
|
Jul 11 08:05:21 PM PDT 24 |
Jul 11 08:53:12 PM PDT 24 |
13078294160 ps |
| T204 |
/workspace/coverage/default/1.chip_sw_uart_tx_rx_bootstrap.993262327 |
|
|
Jul 11 08:08:08 PM PDT 24 |
Jul 12 12:01:03 AM PDT 24 |
78405698125 ps |
| T1070 |
/workspace/coverage/default/1.chip_sw_pwrmgr_sysrst_ctrl_reset.3974408800 |
|
|
Jul 11 08:10:52 PM PDT 24 |
Jul 11 08:27:49 PM PDT 24 |
8086525416 ps |
| T1071 |
/workspace/coverage/default/2.chip_sw_hmac_enc_jitter_en.3088888056 |
|
|
Jul 11 08:28:12 PM PDT 24 |
Jul 11 08:32:05 PM PDT 24 |
2953769049 ps |
| T762 |
/workspace/coverage/default/45.chip_sw_all_escalation_resets.1588502493 |
|
|
Jul 11 08:37:16 PM PDT 24 |
Jul 11 08:46:42 PM PDT 24 |
6462928896 ps |
| T187 |
/workspace/coverage/default/1.chip_sw_flash_rma_unlocked.2186400646 |
|
|
Jul 11 08:05:10 PM PDT 24 |
Jul 11 09:31:18 PM PDT 24 |
43787600295 ps |
| T386 |
/workspace/coverage/default/2.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.2631494150 |
|
|
Jul 11 08:24:02 PM PDT 24 |
Jul 11 08:34:02 PM PDT 24 |
5535474334 ps |
| T260 |
/workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_pings.1183609192 |
|
|
Jul 11 08:29:33 PM PDT 24 |
Jul 11 08:51:32 PM PDT 24 |
11970739336 ps |
| T105 |
/workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_wake_ups.1977964006 |
|
|
Jul 11 08:22:06 PM PDT 24 |
Jul 11 08:57:40 PM PDT 24 |
20578401700 ps |
| T140 |
/workspace/coverage/default/1.chip_sw_sensor_ctrl_alert.3101832460 |
|
|
Jul 11 08:20:12 PM PDT 24 |
Jul 11 08:31:14 PM PDT 24 |
6310383476 ps |
| T1072 |
/workspace/coverage/default/5.chip_sw_csrng_edn_concurrency.172729861 |
|
|
Jul 11 08:30:49 PM PDT 24 |
Jul 11 09:40:50 PM PDT 24 |
23096508096 ps |
| T1073 |
/workspace/coverage/default/2.chip_sw_pwrmgr_sleep_wake_5_bug.1506436022 |
|
|
Jul 11 08:29:11 PM PDT 24 |
Jul 11 08:36:03 PM PDT 24 |
6527107430 ps |
| T1074 |
/workspace/coverage/default/0.chip_sw_gpio_smoketest.2390851693 |
|
|
Jul 11 08:06:08 PM PDT 24 |
Jul 11 08:09:16 PM PDT 24 |
2215190415 ps |
| T804 |
/workspace/coverage/default/72.chip_sw_alert_handler_lpg_sleep_mode_alerts.1505713632 |
|
|
Jul 11 08:36:30 PM PDT 24 |
Jul 11 08:42:42 PM PDT 24 |
4319329740 ps |
| T1075 |
/workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_prod.3700717975 |
|
|
Jul 11 08:25:24 PM PDT 24 |
Jul 11 08:43:39 PM PDT 24 |
8096789292 ps |
| T770 |
/workspace/coverage/default/23.chip_sw_alert_handler_lpg_sleep_mode_alerts.1782503043 |
|
|
Jul 11 08:36:20 PM PDT 24 |
Jul 11 08:42:18 PM PDT 24 |
3580766740 ps |
| T1076 |
/workspace/coverage/default/0.chip_sw_example_manufacturer.3969390276 |
|
|
Jul 11 08:02:28 PM PDT 24 |
Jul 11 08:05:44 PM PDT 24 |
2534471024 ps |
| T171 |
/workspace/coverage/default/2.chip_sw_otp_ctrl_vendor_test_csr_access.3891900122 |
|
|
Jul 11 08:26:36 PM PDT 24 |
Jul 11 08:28:35 PM PDT 24 |
2342659746 ps |
| T38 |
/workspace/coverage/default/0.chip_sw_gpio.1292076621 |
|
|
Jul 11 08:01:37 PM PDT 24 |
Jul 11 08:09:33 PM PDT 24 |
3897307890 ps |
| T781 |
/workspace/coverage/default/99.chip_sw_all_escalation_resets.2494111333 |
|
|
Jul 11 08:39:22 PM PDT 24 |
Jul 11 08:49:09 PM PDT 24 |
5433126244 ps |
| T148 |
/workspace/coverage/default/1.chip_jtag_csr_rw.241472490 |
|
|
Jul 11 08:13:08 PM PDT 24 |
Jul 11 08:36:57 PM PDT 24 |
11798437000 ps |
| T1077 |
/workspace/coverage/default/1.chip_sw_lc_ctrl_transition.2816378931 |
|
|
Jul 11 08:09:41 PM PDT 24 |
Jul 11 08:21:13 PM PDT 24 |
11909636929 ps |
| T1078 |
/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.3665649831 |
|
|
Jul 11 08:19:58 PM PDT 24 |
Jul 11 08:27:40 PM PDT 24 |
3672950624 ps |
| T1079 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.1797487693 |
|
|
Jul 11 08:10:55 PM PDT 24 |
Jul 11 09:24:28 PM PDT 24 |
15482918386 ps |
| T1080 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_rma.3036706417 |
|
|
Jul 11 08:11:38 PM PDT 24 |
Jul 11 09:31:23 PM PDT 24 |
14438507614 ps |
| T1081 |
/workspace/coverage/default/2.chip_sw_aes_idle.484697982 |
|
|
Jul 11 08:29:22 PM PDT 24 |
Jul 11 08:33:26 PM PDT 24 |
2528555840 ps |
| T284 |
/workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en.225962917 |
|
|
Jul 11 08:20:03 PM PDT 24 |
Jul 11 08:30:00 PM PDT 24 |
4062919311 ps |
| T197 |
/workspace/coverage/default/2.chip_sw_spi_device_pass_through_collision.573065119 |
|
|
Jul 11 08:24:58 PM PDT 24 |
Jul 11 08:33:49 PM PDT 24 |
4588292435 ps |
| T1082 |
/workspace/coverage/default/1.chip_sw_aes_masking_off.4256128103 |
|
|
Jul 11 08:09:09 PM PDT 24 |
Jul 11 08:13:53 PM PDT 24 |
3175643271 ps |
| T778 |
/workspace/coverage/default/79.chip_sw_all_escalation_resets.1146388480 |
|
|
Jul 11 08:37:28 PM PDT 24 |
Jul 11 08:46:19 PM PDT 24 |
5825682312 ps |
| T77 |
/workspace/coverage/default/0.chip_sw_usbdev_aon_pullup.3831485788 |
|
|
Jul 11 07:59:48 PM PDT 24 |
Jul 11 08:05:43 PM PDT 24 |
4012096198 ps |
| T1083 |
/workspace/coverage/default/1.chip_sw_kmac_smoketest.3816321300 |
|
|
Jul 11 08:21:48 PM PDT 24 |
Jul 11 08:27:13 PM PDT 24 |
3033649092 ps |
| T772 |
/workspace/coverage/default/78.chip_sw_alert_handler_lpg_sleep_mode_alerts.122122291 |
|
|
Jul 11 08:38:33 PM PDT 24 |
Jul 11 08:44:31 PM PDT 24 |
3872055000 ps |
| T1084 |
/workspace/coverage/default/0.chip_sw_hmac_enc_idle.659524117 |
|
|
Jul 11 08:00:53 PM PDT 24 |
Jul 11 08:04:30 PM PDT 24 |
2767550880 ps |
| T846 |
/workspace/coverage/default/71.chip_sw_alert_handler_lpg_sleep_mode_alerts.4054751171 |
|
|
Jul 11 08:38:33 PM PDT 24 |
Jul 11 08:44:30 PM PDT 24 |
3961036680 ps |
| T307 |
/workspace/coverage/default/9.chip_sw_all_escalation_resets.3055016437 |
|
|
Jul 11 08:30:30 PM PDT 24 |
Jul 11 08:43:38 PM PDT 24 |
5023983704 ps |
| T756 |
/workspace/coverage/default/54.chip_sw_all_escalation_resets.3797084430 |
|
|
Jul 11 08:35:50 PM PDT 24 |
Jul 11 08:46:19 PM PDT 24 |
6061504592 ps |
| T1085 |
/workspace/coverage/default/3.chip_sw_uart_tx_rx_idx1.3390229623 |
|
|
Jul 11 08:35:24 PM PDT 24 |
Jul 11 08:45:29 PM PDT 24 |
4637344840 ps |
| T807 |
/workspace/coverage/default/86.chip_sw_alert_handler_lpg_sleep_mode_alerts.1751448369 |
|
|
Jul 11 08:39:07 PM PDT 24 |
Jul 11 08:46:44 PM PDT 24 |
4105229416 ps |
| T844 |
/workspace/coverage/default/60.chip_sw_all_escalation_resets.2614238489 |
|
|
Jul 11 08:36:08 PM PDT 24 |
Jul 11 08:45:47 PM PDT 24 |
5346805160 ps |
| T1086 |
/workspace/coverage/default/0.rom_e2e_shutdown_output.2829969069 |
|
|
Jul 11 08:08:34 PM PDT 24 |
Jul 11 09:05:58 PM PDT 24 |
25946343620 ps |
| T825 |
/workspace/coverage/default/20.chip_sw_alert_handler_lpg_sleep_mode_alerts.3632811155 |
|
|
Jul 11 08:36:17 PM PDT 24 |
Jul 11 08:43:00 PM PDT 24 |
3414235840 ps |
| T285 |
/workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.453051739 |
|
|
Jul 11 08:29:51 PM PDT 24 |
Jul 11 08:39:29 PM PDT 24 |
4798364077 ps |
| T405 |
/workspace/coverage/default/1.chip_sw_kmac_app_rom.1536966010 |
|
|
Jul 11 08:20:20 PM PDT 24 |
Jul 11 08:25:56 PM PDT 24 |
2855791816 ps |
| T1087 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.4208650848 |
|
|
Jul 11 08:21:24 PM PDT 24 |
Jul 11 08:42:59 PM PDT 24 |
7886662484 ps |
| T1088 |
/workspace/coverage/default/2.chip_sw_otbn_randomness.2200267856 |
|
|
Jul 11 08:28:53 PM PDT 24 |
Jul 11 08:45:46 PM PDT 24 |
5558499118 ps |
| T826 |
/workspace/coverage/default/84.chip_sw_all_escalation_resets.1426056299 |
|
|
Jul 11 08:38:28 PM PDT 24 |
Jul 11 08:48:39 PM PDT 24 |
5790481896 ps |
| T1089 |
/workspace/coverage/default/2.chip_sw_flash_crash_alert.2125348190 |
|
|
Jul 11 08:24:47 PM PDT 24 |
Jul 11 08:38:44 PM PDT 24 |
5545188600 ps |
| T1090 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0.1858802388 |
|
|
Jul 11 08:11:08 PM PDT 24 |
Jul 11 08:55:41 PM PDT 24 |
11751156700 ps |
| T1091 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_write_clear.2125079914 |
|
|
Jul 11 08:04:57 PM PDT 24 |
Jul 11 08:10:42 PM PDT 24 |
3175104732 ps |
| T1092 |
/workspace/coverage/default/2.chip_sw_aes_masking_off.2541779403 |
|
|
Jul 11 08:24:42 PM PDT 24 |
Jul 11 08:28:49 PM PDT 24 |
2877918750 ps |
| T1093 |
/workspace/coverage/default/2.chip_sw_flash_scrambling_smoketest.3409556146 |
|
|
Jul 11 08:28:48 PM PDT 24 |
Jul 11 08:32:04 PM PDT 24 |
3049433792 ps |
| T1094 |
/workspace/coverage/default/2.chip_sw_uart_smoketest.2871750230 |
|
|
Jul 11 08:33:35 PM PDT 24 |
Jul 11 08:38:19 PM PDT 24 |
2808141140 ps |
| T1095 |
/workspace/coverage/default/2.chip_sw_csrng_smoketest.3063895560 |
|
|
Jul 11 08:25:34 PM PDT 24 |
Jul 11 08:28:40 PM PDT 24 |
2035869280 ps |
| T10 |
/workspace/coverage/default/2.chip_sw_sleep_pin_wake.3364934772 |
|
|
Jul 11 08:22:47 PM PDT 24 |
Jul 11 08:32:23 PM PDT 24 |
6554795556 ps |
| T420 |
/workspace/coverage/default/0.chip_sw_pwrmgr_wdog_reset.472739855 |
|
|
Jul 11 08:01:49 PM PDT 24 |
Jul 11 08:10:34 PM PDT 24 |
4996462912 ps |
| T421 |
/workspace/coverage/default/2.chip_sw_edn_entropy_reqs.1453985964 |
|
|
Jul 11 08:28:36 PM PDT 24 |
Jul 11 08:40:45 PM PDT 24 |
6145462680 ps |
| T422 |
/workspace/coverage/default/2.chip_sw_keymgr_key_derivation.2831925694 |
|
|
Jul 11 08:31:15 PM PDT 24 |
Jul 11 08:50:48 PM PDT 24 |
8232200390 ps |
| T423 |
/workspace/coverage/default/1.chip_sw_keymgr_key_derivation_prod.1816281703 |
|
|
Jul 11 08:12:03 PM PDT 24 |
Jul 11 08:30:45 PM PDT 24 |
6088851800 ps |
| T424 |
/workspace/coverage/default/0.rom_e2e_asm_init_rma.2907160783 |
|
|
Jul 11 08:08:31 PM PDT 24 |
Jul 11 09:19:12 PM PDT 24 |
14690829936 ps |
| T425 |
/workspace/coverage/default/2.chip_sw_rv_core_ibex_nmi_irq.822026901 |
|
|
Jul 11 08:24:33 PM PDT 24 |
Jul 11 08:37:54 PM PDT 24 |
4388999300 ps |
| T426 |
/workspace/coverage/default/0.chip_sw_clkmgr_off_otbn_trans.3879791815 |
|
|
Jul 11 08:06:51 PM PDT 24 |
Jul 11 08:14:15 PM PDT 24 |
5905624512 ps |
| T427 |
/workspace/coverage/default/18.chip_sw_uart_rand_baudrate.95839697 |
|
|
Jul 11 08:33:35 PM PDT 24 |
Jul 11 09:00:23 PM PDT 24 |
7994764944 ps |
| T428 |
/workspace/coverage/default/0.chip_sw_pwrmgr_smoketest.1443595754 |
|
|
Jul 11 08:05:31 PM PDT 24 |
Jul 11 08:10:11 PM PDT 24 |
5133684262 ps |
| T246 |
/workspace/coverage/default/18.chip_sw_alert_handler_lpg_sleep_mode_alerts.3672999090 |
|
|
Jul 11 08:34:25 PM PDT 24 |
Jul 11 08:41:53 PM PDT 24 |
4244752372 ps |
| T697 |
/workspace/coverage/default/0.chip_sw_lc_ctrl_test_locked0_to_scrap.1212635396 |
|
|
Jul 11 08:03:43 PM PDT 24 |
Jul 11 08:06:21 PM PDT 24 |
2985647205 ps |
| T806 |
/workspace/coverage/default/61.chip_sw_all_escalation_resets.4183902367 |
|
|
Jul 11 08:35:34 PM PDT 24 |
Jul 11 08:45:38 PM PDT 24 |
4848178020 ps |
| T1096 |
/workspace/coverage/default/11.chip_sw_uart_rand_baudrate.3089658578 |
|
|
Jul 11 08:29:56 PM PDT 24 |
Jul 11 09:00:53 PM PDT 24 |
13164244056 ps |
| T59 |
/workspace/coverage/default/0.chip_sw_alert_test.1700921444 |
|
|
Jul 11 08:07:01 PM PDT 24 |
Jul 11 08:11:57 PM PDT 24 |
3197894056 ps |
| T1097 |
/workspace/coverage/default/2.chip_sw_clkmgr_jitter.2974536971 |
|
|
Jul 11 08:26:51 PM PDT 24 |
Jul 11 08:30:10 PM PDT 24 |
2616029619 ps |
| T1098 |
/workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_test_unlocked0.2233073802 |
|
|
Jul 11 08:06:59 PM PDT 24 |
Jul 11 08:15:28 PM PDT 24 |
4143574088 ps |
| T809 |
/workspace/coverage/default/28.chip_sw_all_escalation_resets.941013110 |
|
|
Jul 11 08:33:42 PM PDT 24 |
Jul 11 08:45:35 PM PDT 24 |
6345009610 ps |
| T812 |
/workspace/coverage/default/50.chip_sw_all_escalation_resets.3262326181 |
|
|
Jul 11 08:35:41 PM PDT 24 |
Jul 11 08:45:01 PM PDT 24 |
4930450120 ps |
| T1099 |
/workspace/coverage/default/1.chip_sw_edn_kat.3790697787 |
|
|
Jul 11 08:11:22 PM PDT 24 |
Jul 11 08:22:10 PM PDT 24 |
3234220526 ps |
| T1100 |
/workspace/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.1541765792 |
|
|
Jul 11 08:24:35 PM PDT 24 |
Jul 11 08:28:47 PM PDT 24 |
3509529130 ps |
| T1101 |
/workspace/coverage/default/1.chip_sw_keymgr_key_derivation_jitter_en.3371102847 |
|
|
Jul 11 08:22:19 PM PDT 24 |
Jul 11 08:57:24 PM PDT 24 |
11044057599 ps |
| T842 |
/workspace/coverage/default/89.chip_sw_alert_handler_lpg_sleep_mode_alerts.2621714438 |
|
|
Jul 11 08:37:30 PM PDT 24 |
Jul 11 08:43:50 PM PDT 24 |
4228548080 ps |
| T286 |
/workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access.1549732429 |
|
|
Jul 11 08:05:35 PM PDT 24 |
Jul 11 08:16:22 PM PDT 24 |
5780256320 ps |
| T843 |
/workspace/coverage/default/68.chip_sw_alert_handler_lpg_sleep_mode_alerts.3021272341 |
|
|
Jul 11 08:36:40 PM PDT 24 |
Jul 11 08:41:40 PM PDT 24 |
3110148940 ps |
| T1102 |
/workspace/coverage/default/0.chip_sw_csrng_kat_test.2169935474 |
|
|
Jul 11 08:02:07 PM PDT 24 |
Jul 11 08:07:19 PM PDT 24 |
3003155708 ps |
| T1103 |
/workspace/coverage/default/2.chip_sw_example_manufacturer.2272906907 |
|
|
Jul 11 08:25:07 PM PDT 24 |
Jul 11 08:29:55 PM PDT 24 |
3119757108 ps |
| T800 |
/workspace/coverage/default/58.chip_sw_alert_handler_lpg_sleep_mode_alerts.1026342469 |
|
|
Jul 11 08:39:02 PM PDT 24 |
Jul 11 08:48:24 PM PDT 24 |
4180349776 ps |
| T1104 |
/workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_no_scramble.4274523891 |
|
|
Jul 11 08:31:39 PM PDT 24 |
Jul 11 08:43:56 PM PDT 24 |
8934619976 ps |
| T1105 |
/workspace/coverage/default/4.chip_tap_straps_dev.3564823028 |
|
|
Jul 11 08:27:46 PM PDT 24 |
Jul 11 08:31:03 PM PDT 24 |
2748483435 ps |
| T835 |
/workspace/coverage/default/83.chip_sw_alert_handler_lpg_sleep_mode_alerts.2979526091 |
|
|
Jul 11 08:38:44 PM PDT 24 |
Jul 11 08:44:27 PM PDT 24 |
3562890680 ps |
| T802 |
/workspace/coverage/default/90.chip_sw_all_escalation_resets.3011479990 |
|
|
Jul 11 08:37:53 PM PDT 24 |
Jul 11 08:47:41 PM PDT 24 |
4951655912 ps |
| T91 |
/workspace/coverage/default/10.chip_sw_alert_handler_lpg_sleep_mode_alerts.3001791572 |
|
|
Jul 11 08:33:39 PM PDT 24 |
Jul 11 08:42:07 PM PDT 24 |
4137375654 ps |
| T1106 |
/workspace/coverage/default/13.chip_sw_all_escalation_resets.1187334605 |
|
|
Jul 11 08:32:05 PM PDT 24 |
Jul 11 08:43:34 PM PDT 24 |
4911791924 ps |
| T845 |
/workspace/coverage/default/79.chip_sw_alert_handler_lpg_sleep_mode_alerts.3447112246 |
|
|
Jul 11 08:38:32 PM PDT 24 |
Jul 11 08:45:15 PM PDT 24 |
4342582102 ps |
| T1107 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_mem_protection.4003572815 |
|
|
Jul 11 08:30:07 PM PDT 24 |
Jul 11 08:49:55 PM PDT 24 |
6114854082 ps |
| T353 |
/workspace/coverage/default/0.chip_sw_pattgen_ios.2312957567 |
|
|
Jul 11 08:00:42 PM PDT 24 |
Jul 11 08:06:15 PM PDT 24 |
3272011200 ps |
| T1108 |
/workspace/coverage/default/2.rom_e2e_asm_init_prod_end.2789466531 |
|
|
Jul 11 08:35:06 PM PDT 24 |
Jul 11 09:31:13 PM PDT 24 |
15830693059 ps |
| T1109 |
/workspace/coverage/default/4.chip_sw_aon_timer_sleep_wdog_sleep_pause.2820700431 |
|
|
Jul 11 08:27:13 PM PDT 24 |
Jul 11 08:38:40 PM PDT 24 |
7036435500 ps |
| T1110 |
/workspace/coverage/default/1.chip_sw_rv_timer_irq.3721350019 |
|
|
Jul 11 08:09:35 PM PDT 24 |
Jul 11 08:13:00 PM PDT 24 |
2229470480 ps |
| T106 |
/workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_wake_ups.1296597293 |
|
|
Jul 11 08:21:51 PM PDT 24 |
Jul 11 08:31:31 PM PDT 24 |
8099119586 ps |
| T209 |
/workspace/coverage/default/0.chip_sw_sysrst_ctrl_outputs.2288338034 |
|
|
Jul 11 08:02:44 PM PDT 24 |
Jul 11 08:09:32 PM PDT 24 |
3213469780 ps |
| T1111 |
/workspace/coverage/default/0.chip_sw_pwrmgr_main_power_glitch_reset.3699119655 |
|
|
Jul 11 08:01:53 PM PDT 24 |
Jul 11 08:07:05 PM PDT 24 |
3624962261 ps |
| T11 |
/workspace/coverage/default/2.chip_sw_sleep_pin_retention.2047045230 |
|
|
Jul 11 08:22:59 PM PDT 24 |
Jul 11 08:28:55 PM PDT 24 |
3235732520 ps |
| T832 |
/workspace/coverage/default/64.chip_sw_alert_handler_lpg_sleep_mode_alerts.3893509581 |
|
|
Jul 11 08:36:31 PM PDT 24 |
Jul 11 08:41:19 PM PDT 24 |
3033850350 ps |
| T1112 |
/workspace/coverage/default/2.chip_sw_power_sleep_load.2234733486 |
|
|
Jul 11 08:26:48 PM PDT 24 |
Jul 11 08:37:50 PM PDT 24 |
9835683768 ps |
| T1113 |
/workspace/coverage/default/6.chip_sw_uart_rand_baudrate.1415198514 |
|
|
Jul 11 08:34:56 PM PDT 24 |
Jul 11 08:43:55 PM PDT 24 |
4136264864 ps |
| T696 |
/workspace/coverage/default/2.chip_sw_rv_dm_access_after_escalation_reset.568810235 |
|
|
Jul 11 08:29:00 PM PDT 24 |
Jul 11 08:36:40 PM PDT 24 |
6004911248 ps |
| T537 |
/workspace/coverage/default/0.chip_sw_rv_core_ibex_nmi_irq.1599855774 |
|
|
Jul 11 08:04:25 PM PDT 24 |
Jul 11 08:18:50 PM PDT 24 |
4874245700 ps |
| T1114 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod_end.2877536944 |
|
|
Jul 11 08:13:03 PM PDT 24 |
Jul 11 09:10:43 PM PDT 24 |
14829058850 ps |
| T805 |
/workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_alerts.850374265 |
|
|
Jul 11 08:04:48 PM PDT 24 |
Jul 11 08:11:03 PM PDT 24 |
3707172520 ps |
| T374 |
/workspace/coverage/default/2.chip_sival_flash_info_access.2133100492 |
|
|
Jul 11 08:23:17 PM PDT 24 |
Jul 11 08:29:29 PM PDT 24 |
3544395848 ps |
| T1115 |
/workspace/coverage/default/2.chip_sw_rv_plic_smoketest.4149241725 |
|
|
Jul 11 08:26:06 PM PDT 24 |
Jul 11 08:31:23 PM PDT 24 |
2456489848 ps |
| T1116 |
/workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_rma.2400270366 |
|
|
Jul 11 08:07:23 PM PDT 24 |
Jul 11 08:27:23 PM PDT 24 |
9164676740 ps |
| T1117 |
/workspace/coverage/default/2.chip_sw_sram_ctrl_smoketest.2187760286 |
|
|
Jul 11 08:26:15 PM PDT 24 |
Jul 11 08:29:48 PM PDT 24 |
2306207096 ps |
| T1118 |
/workspace/coverage/default/0.chip_sw_hmac_enc_jitter_en_reduced_freq.4064284530 |
|
|
Jul 11 08:05:41 PM PDT 24 |
Jul 11 08:09:19 PM PDT 24 |
2638469250 ps |
| T1119 |
/workspace/coverage/default/2.chip_sw_uart_tx_rx_idx1.1527369630 |
|
|
Jul 11 08:23:59 PM PDT 24 |
Jul 11 08:34:32 PM PDT 24 |
4073951220 ps |
| T1120 |
/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.3487950992 |
|
|
Jul 11 08:27:51 PM PDT 24 |
Jul 11 08:37:27 PM PDT 24 |
4710757066 ps |
| T1121 |
/workspace/coverage/default/0.chip_sw_uart_tx_rx_idx1.2923547273 |
|
|
Jul 11 08:01:54 PM PDT 24 |
Jul 11 08:13:40 PM PDT 24 |
4571369060 ps |
| T795 |
/workspace/coverage/default/83.chip_sw_all_escalation_resets.1244862522 |
|
|
Jul 11 08:37:24 PM PDT 24 |
Jul 11 08:48:08 PM PDT 24 |
5641902632 ps |
| T1122 |
/workspace/coverage/default/1.chip_sw_sysrst_ctrl_ec_rst_l.4216285645 |
|
|
Jul 11 08:10:05 PM PDT 24 |
Jul 11 09:11:15 PM PDT 24 |
20255783106 ps |
| T347 |
/workspace/coverage/default/0.chip_sw_pwrmgr_lowpower_cancel.871714903 |
|
|
Jul 11 08:02:33 PM PDT 24 |
Jul 11 08:10:34 PM PDT 24 |
3203870472 ps |
| T341 |
/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx2.1287446617 |
|
|
Jul 11 08:03:25 PM PDT 24 |
Jul 11 08:15:56 PM PDT 24 |
4964749320 ps |
| T698 |
/workspace/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock.1715682224 |
|
|
Jul 11 08:00:49 PM PDT 24 |
Jul 11 08:02:48 PM PDT 24 |
2723572114 ps |
| T1123 |
/workspace/coverage/default/2.rom_e2e_asm_init_rma.265075043 |
|
|
Jul 11 08:29:40 PM PDT 24 |
Jul 11 09:47:46 PM PDT 24 |
14846153360 ps |
| T1124 |
/workspace/coverage/default/0.chip_sw_otbn_randomness.3780682186 |
|
|
Jul 11 08:04:02 PM PDT 24 |
Jul 11 08:20:57 PM PDT 24 |
6080239000 ps |
| T1125 |
/workspace/coverage/default/1.chip_sw_example_manufacturer.4115816908 |
|
|
Jul 11 08:07:32 PM PDT 24 |
Jul 11 08:11:25 PM PDT 24 |
2219528110 ps |
| T699 |
/workspace/coverage/default/2.rom_volatile_raw_unlock.3725562174 |
|
|
Jul 11 08:25:37 PM PDT 24 |
Jul 11 08:27:37 PM PDT 24 |
2705603124 ps |
| T375 |
/workspace/coverage/default/1.chip_sw_hmac_enc_jitter_en.763463212 |
|
|
Jul 11 08:11:24 PM PDT 24 |
Jul 11 08:15:22 PM PDT 24 |
2739498841 ps |
| T1126 |
/workspace/coverage/default/21.chip_sw_all_escalation_resets.1236674093 |
|
|
Jul 11 08:35:02 PM PDT 24 |
Jul 11 08:44:54 PM PDT 24 |
5921742956 ps |
| T821 |
/workspace/coverage/default/31.chip_sw_all_escalation_resets.651442210 |
|
|
Jul 11 08:34:27 PM PDT 24 |
Jul 11 08:47:01 PM PDT 24 |
6222534388 ps |
| T210 |
/workspace/coverage/default/2.chip_sw_sysrst_ctrl_outputs.3568184721 |
|
|
Jul 11 08:27:34 PM PDT 24 |
Jul 11 08:33:56 PM PDT 24 |
3671557504 ps |
| T1127 |
/workspace/coverage/default/2.chip_sw_aes_enc.540286974 |
|
|
Jul 11 08:24:54 PM PDT 24 |
Jul 11 08:29:23 PM PDT 24 |
3121186580 ps |
| T1128 |
/workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.309903863 |
|
|
Jul 11 08:22:31 PM PDT 24 |
Jul 11 08:32:02 PM PDT 24 |
7739155470 ps |
| T301 |
/workspace/coverage/default/2.chip_sw_sram_ctrl_execution_main.2654633004 |
|
|
Jul 11 08:30:34 PM PDT 24 |
Jul 11 08:45:44 PM PDT 24 |
7612909277 ps |
| T810 |
/workspace/coverage/default/78.chip_sw_all_escalation_resets.2724854322 |
|
|
Jul 11 08:37:46 PM PDT 24 |
Jul 11 08:48:11 PM PDT 24 |
4652571688 ps |
| T1129 |
/workspace/coverage/default/2.chip_sw_edn_kat.3067289334 |
|
|
Jul 11 08:25:46 PM PDT 24 |
Jul 11 08:37:33 PM PDT 24 |
3365742156 ps |
| T92 |
/workspace/coverage/default/8.chip_sw_all_escalation_resets.1883846780 |
|
|
Jul 11 08:31:04 PM PDT 24 |
Jul 11 08:45:17 PM PDT 24 |
5405636600 ps |
| T1130 |
/workspace/coverage/default/0.chip_sw_otbn_mem_scramble.3380108042 |
|
|
Jul 11 08:03:52 PM PDT 24 |
Jul 11 08:11:08 PM PDT 24 |
3520278376 ps |
| T1131 |
/workspace/coverage/default/70.chip_sw_all_escalation_resets.2679290288 |
|
|
Jul 11 08:40:52 PM PDT 24 |
Jul 11 08:50:06 PM PDT 24 |
4895856812 ps |
| T1132 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.2749587676 |
|
|
Jul 11 08:13:16 PM PDT 24 |
Jul 11 09:07:12 PM PDT 24 |
11648435716 ps |
| T1133 |
/workspace/coverage/default/0.chip_sw_clkmgr_reset_frequency.1847215872 |
|
|
Jul 11 08:04:37 PM PDT 24 |
Jul 11 08:10:26 PM PDT 24 |
3236109362 ps |
| T1134 |
/workspace/coverage/default/1.chip_sw_pwrmgr_sleep_power_glitch_reset.3821314200 |
|
|
Jul 11 08:11:31 PM PDT 24 |
Jul 11 08:17:06 PM PDT 24 |
3989236744 ps |
| T1135 |
/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.3443467263 |
|
|
Jul 11 08:21:31 PM PDT 24 |
Jul 11 08:37:55 PM PDT 24 |
5284814814 ps |
| T830 |
/workspace/coverage/default/7.chip_sw_alert_handler_lpg_sleep_mode_alerts.1677917690 |
|
|
Jul 11 08:30:32 PM PDT 24 |
Jul 11 08:38:40 PM PDT 24 |
4187906640 ps |
| T1136 |
/workspace/coverage/default/0.chip_sw_hmac_oneshot.703269311 |
|
|
Jul 11 08:02:22 PM PDT 24 |
Jul 11 08:08:42 PM PDT 24 |
3401025000 ps |
| T1137 |
/workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_por_reset.3877046301 |
|
|
Jul 11 08:26:00 PM PDT 24 |
Jul 11 08:36:27 PM PDT 24 |
7471330976 ps |
| T700 |
/workspace/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.427453223 |
|
|
Jul 11 08:25:48 PM PDT 24 |
Jul 11 08:27:39 PM PDT 24 |
1996911952 ps |
| T1138 |
/workspace/coverage/default/4.chip_sw_lc_ctrl_transition.1410916157 |
|
|
Jul 11 08:27:10 PM PDT 24 |
Jul 11 08:33:14 PM PDT 24 |
5030257601 ps |
| T354 |
/workspace/coverage/default/1.chip_sw_pattgen_ios.3122495713 |
|
|
Jul 11 08:06:35 PM PDT 24 |
Jul 11 08:12:25 PM PDT 24 |
3120282864 ps |
| T1139 |
/workspace/coverage/default/42.chip_sw_alert_handler_lpg_sleep_mode_alerts.2314388348 |
|
|
Jul 11 08:35:39 PM PDT 24 |
Jul 11 08:41:58 PM PDT 24 |
3543916800 ps |
| T1140 |
/workspace/coverage/default/1.chip_sw_clkmgr_off_hmac_trans.4091091165 |
|
|
Jul 11 08:22:12 PM PDT 24 |
Jul 11 08:32:15 PM PDT 24 |
4544921620 ps |
| T1141 |
/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_wake_5_bug.808137003 |
|
|
Jul 11 08:05:02 PM PDT 24 |
Jul 11 08:11:49 PM PDT 24 |
5422205024 ps |
| T1142 |
/workspace/coverage/default/2.chip_sw_pwrmgr_sleep_power_glitch_reset.2224892220 |
|
|
Jul 11 08:27:16 PM PDT 24 |
Jul 11 08:36:30 PM PDT 24 |
6013853254 ps |
| T1143 |
/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.3308558849 |
|
|
Jul 11 08:06:37 PM PDT 24 |
Jul 11 08:17:59 PM PDT 24 |
4213424942 ps |
| T136 |
/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.3452711369 |
|
|
Jul 11 08:01:34 PM PDT 24 |
Jul 11 08:08:39 PM PDT 24 |
5573381814 ps |
| T1144 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.1135442904 |
|
|
Jul 11 08:09:39 PM PDT 24 |
Jul 11 09:15:37 PM PDT 24 |
15430507184 ps |
| T1145 |
/workspace/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.2913829118 |
|
|
Jul 11 08:02:55 PM PDT 24 |
Jul 11 08:27:55 PM PDT 24 |
7599889437 ps |
| T15 |
/workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_wake_ups.2505324774 |
|
|
Jul 11 08:27:59 PM PDT 24 |
Jul 11 08:49:25 PM PDT 24 |
20751932232 ps |
| T1146 |
/workspace/coverage/default/3.chip_sw_csrng_edn_concurrency.2418053441 |
|
|
Jul 11 08:26:22 PM PDT 24 |
Jul 11 08:54:03 PM PDT 24 |
9533372684 ps |
| T1147 |
/workspace/coverage/default/1.chip_sw_aon_timer_wdog_lc_escalate.3081272161 |
|
|
Jul 11 08:09:20 PM PDT 24 |
Jul 11 08:16:07 PM PDT 24 |
4165232664 ps |
| T1148 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0.1800890872 |
|
|
Jul 11 08:09:04 PM PDT 24 |
Jul 11 09:23:46 PM PDT 24 |
17915283622 ps |
| T1149 |
/workspace/coverage/default/0.chip_sw_kmac_mode_kmac.2830068410 |
|
|
Jul 11 08:02:22 PM PDT 24 |
Jul 11 08:08:59 PM PDT 24 |
3227847140 ps |
| T342 |
/workspace/coverage/default/1.chip_sw_i2c_host_tx_rx_idx2.2849140640 |
|
|
Jul 11 08:10:57 PM PDT 24 |
Jul 11 08:25:09 PM PDT 24 |
4611254732 ps |
| T1150 |
/workspace/coverage/default/0.chip_sw_rv_core_ibex_rnd.2670679050 |
|
|
Jul 11 08:02:45 PM PDT 24 |
Jul 11 08:19:28 PM PDT 24 |
5971385020 ps |
| T198 |
/workspace/coverage/default/1.chip_sw_spi_device_pass_through.4030894635 |
|
|
Jul 11 08:06:57 PM PDT 24 |
Jul 11 08:20:21 PM PDT 24 |
8084784813 ps |
| T853 |
/workspace/coverage/default/39.chip_sw_alert_handler_lpg_sleep_mode_alerts.832475343 |
|
|
Jul 11 08:41:40 PM PDT 24 |
Jul 11 08:48:05 PM PDT 24 |
3402527328 ps |
| T1151 |
/workspace/coverage/default/0.chip_sw_hmac_enc_jitter_en.1619522768 |
|
|
Jul 11 08:03:57 PM PDT 24 |
Jul 11 08:10:38 PM PDT 24 |
3293073683 ps |
| T343 |
/workspace/coverage/default/2.chip_sw_i2c_host_tx_rx.1915974137 |
|
|
Jul 11 08:24:49 PM PDT 24 |
Jul 11 08:37:38 PM PDT 24 |
4852150420 ps |
| T330 |
/workspace/coverage/default/1.chip_sw_rstmgr_alert_info.1698607715 |
|
|
Jul 11 08:08:43 PM PDT 24 |
Jul 11 08:45:10 PM PDT 24 |
15274157984 ps |
| T1152 |
/workspace/coverage/default/2.chip_sw_example_flash.2634138804 |
|
|
Jul 11 08:24:50 PM PDT 24 |
Jul 11 08:30:13 PM PDT 24 |
2832128120 ps |
| T247 |
/workspace/coverage/default/17.chip_sw_alert_handler_lpg_sleep_mode_alerts.174139 |
|
|
Jul 11 08:33:56 PM PDT 24 |
Jul 11 08:42:03 PM PDT 24 |
4222657456 ps |
| T1153 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.1608974025 |
|
|
Jul 11 08:07:07 PM PDT 24 |
Jul 11 08:24:36 PM PDT 24 |
6741182692 ps |
| T308 |
/workspace/coverage/default/34.chip_sw_alert_handler_lpg_sleep_mode_alerts.3651512966 |
|
|
Jul 11 08:34:54 PM PDT 24 |
Jul 11 08:41:01 PM PDT 24 |
3227089968 ps |
| T841 |
/workspace/coverage/default/85.chip_sw_alert_handler_lpg_sleep_mode_alerts.240076264 |
|
|
Jul 11 08:38:19 PM PDT 24 |
Jul 11 08:43:41 PM PDT 24 |
3174689536 ps |
| T1154 |
/workspace/coverage/default/2.chip_sw_aon_timer_irq.2968063720 |
|
|
Jul 11 08:25:20 PM PDT 24 |
Jul 11 08:33:08 PM PDT 24 |
3771390654 ps |
| T1155 |
/workspace/coverage/default/2.rom_e2e_asm_init_test_unlocked0.459800957 |
|
|
Jul 11 08:30:31 PM PDT 24 |
Jul 11 09:24:06 PM PDT 24 |
11488082200 ps |
| T334 |
/workspace/coverage/default/1.chip_sw_entropy_src_csrng.3840678892 |
|
|
Jul 11 08:11:10 PM PDT 24 |
Jul 11 08:44:25 PM PDT 24 |
7850838744 ps |
| T1156 |
/workspace/coverage/default/0.chip_tap_straps_prod.3623943626 |
|
|
Jul 11 08:03:55 PM PDT 24 |
Jul 11 08:05:58 PM PDT 24 |
2622311281 ps |
| T1157 |
/workspace/coverage/default/2.chip_sw_clkmgr_off_kmac_trans.1530087996 |
|
|
Jul 11 08:29:47 PM PDT 24 |
Jul 11 08:37:22 PM PDT 24 |
4132691328 ps |
| T1158 |
/workspace/coverage/default/2.chip_sw_sysrst_ctrl_ec_rst_l.732523910 |
|
|
Jul 11 08:26:51 PM PDT 24 |
Jul 11 09:20:22 PM PDT 24 |
20791063916 ps |
| T801 |
/workspace/coverage/default/46.chip_sw_all_escalation_resets.4285695400 |
|
|
Jul 11 08:36:16 PM PDT 24 |
Jul 11 08:48:34 PM PDT 24 |
5307735432 ps |
| T390 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.724973018 |
|
|
Jul 11 08:15:40 PM PDT 24 |
Jul 11 09:36:58 PM PDT 24 |
17586559978 ps |
| T1159 |
/workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_meas.1134162450 |
|
|
Jul 11 08:29:02 PM PDT 24 |
Jul 11 09:29:37 PM PDT 24 |
14291246728 ps |
| T852 |
/workspace/coverage/default/70.chip_sw_alert_handler_lpg_sleep_mode_alerts.2935698050 |
|
|
Jul 11 08:36:45 PM PDT 24 |
Jul 11 08:41:51 PM PDT 24 |
3774284452 ps |
| T1160 |
/workspace/coverage/default/8.chip_sw_csrng_edn_concurrency.2692104748 |
|
|
Jul 11 08:29:15 PM PDT 24 |
Jul 11 09:59:58 PM PDT 24 |
21151941618 ps |
| T1161 |
/workspace/coverage/default/88.chip_sw_alert_handler_lpg_sleep_mode_alerts.3548498806 |
|
|
Jul 11 08:37:56 PM PDT 24 |
Jul 11 08:44:32 PM PDT 24 |
4245535816 ps |
| T1162 |
/workspace/coverage/default/0.chip_sw_uart_tx_rx_idx2.1673275564 |
|
|
Jul 11 08:01:32 PM PDT 24 |
Jul 11 08:11:25 PM PDT 24 |
4299419552 ps |
| T1163 |
/workspace/coverage/default/1.chip_sw_clkmgr_jitter_reduced_freq.486629574 |
|
|
Jul 11 08:22:58 PM PDT 24 |
Jul 11 08:27:52 PM PDT 24 |
2944658377 ps |
| T763 |
/workspace/coverage/default/49.chip_sw_all_escalation_resets.657334070 |
|
|
Jul 11 08:35:08 PM PDT 24 |
Jul 11 08:46:35 PM PDT 24 |
5476192886 ps |
| T1164 |
/workspace/coverage/default/2.chip_sw_aon_timer_wdog_bite_reset.53472327 |
|
|
Jul 11 08:28:55 PM PDT 24 |
Jul 11 08:41:21 PM PDT 24 |
7483578900 ps |
| T199 |
/workspace/coverage/default/0.chip_sw_spi_device_pass_through.716368835 |
|
|
Jul 11 08:05:49 PM PDT 24 |
Jul 11 08:18:58 PM PDT 24 |
7008788258 ps |
| T180 |
/workspace/coverage/default/2.chip_sw_lc_ctrl_program_error.2999846977 |
|
|
Jul 11 08:23:59 PM PDT 24 |
Jul 11 08:36:09 PM PDT 24 |
6093056610 ps |
| T808 |
/workspace/coverage/default/27.chip_sw_all_escalation_resets.3406951925 |
|
|
Jul 11 08:34:52 PM PDT 24 |
Jul 11 08:45:44 PM PDT 24 |
4407347540 ps |
| T1165 |
/workspace/coverage/default/1.chip_sw_rom_ctrl_integrity_check.1461742039 |
|
|
Jul 11 08:20:00 PM PDT 24 |
Jul 11 08:27:08 PM PDT 24 |
9552507569 ps |
| T1166 |
/workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.3614097658 |
|
|
Jul 11 08:29:30 PM PDT 24 |
Jul 11 09:24:05 PM PDT 24 |
24717996950 ps |
| T1167 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_clock_freqs.1968134850 |
|
|
Jul 11 08:24:11 PM PDT 24 |
Jul 11 08:41:39 PM PDT 24 |
5570167001 ps |
| T1168 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_write_clear.3728853693 |
|
|
Jul 11 08:21:43 PM PDT 24 |
Jul 11 08:28:11 PM PDT 24 |
3152499506 ps |
| T1169 |
/workspace/coverage/default/2.rom_e2e_static_critical.215862281 |
|
|
Jul 11 08:32:50 PM PDT 24 |
Jul 11 09:40:28 PM PDT 24 |
16999687408 ps |
| T1170 |
/workspace/coverage/default/1.chip_sw_alert_handler_ping_timeout.959620917 |
|
|
Jul 11 08:10:38 PM PDT 24 |
Jul 11 08:16:18 PM PDT 24 |
4440468754 ps |
| T8 |
/workspace/coverage/default/0.chip_rv_dm_ndm_reset_req.2487417349 |
|
|
Jul 11 08:04:24 PM PDT 24 |
Jul 11 08:10:33 PM PDT 24 |
4608707390 ps |
| T445 |
/workspace/coverage/default/0.chip_sw_alert_handler_ping_timeout.3579644104 |
|
|
Jul 11 08:03:59 PM PDT 24 |
Jul 11 08:10:28 PM PDT 24 |
4128996424 ps |
| T446 |
/workspace/coverage/default/7.chip_sw_uart_rand_baudrate.2089181284 |
|
|
Jul 11 08:28:52 PM PDT 24 |
Jul 11 08:37:22 PM PDT 24 |
3346891696 ps |
| T447 |
/workspace/coverage/default/14.chip_sw_uart_rand_baudrate.919252819 |
|
|
Jul 11 08:31:04 PM PDT 24 |
Jul 11 08:54:59 PM PDT 24 |
8724653432 ps |
| T448 |
/workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_power_glitch_reset.859819787 |
|
|
Jul 11 08:09:38 PM PDT 24 |
Jul 11 09:02:59 PM PDT 24 |
38601729246 ps |
| T449 |
/workspace/coverage/default/2.chip_sw_entropy_src_kat_test.3009181606 |
|
|
Jul 11 08:20:55 PM PDT 24 |
Jul 11 08:25:22 PM PDT 24 |
2985090932 ps |
| T23 |
/workspace/coverage/default/0.chip_sw_sleep_pin_mio_dio_val.2886709183 |
|
|
Jul 11 08:05:40 PM PDT 24 |
Jul 11 08:11:01 PM PDT 24 |
2939914200 ps |
| T450 |
/workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq.3063638038 |
|
|
Jul 11 08:01:29 PM PDT 24 |
Jul 11 09:07:52 PM PDT 24 |
17254905396 ps |
| T451 |
/workspace/coverage/default/34.chip_sw_all_escalation_resets.3386451568 |
|
|
Jul 11 08:34:17 PM PDT 24 |
Jul 11 08:44:38 PM PDT 24 |
4932445296 ps |
| T452 |
/workspace/coverage/default/0.chip_sw_hmac_multistream.1013864106 |
|
|
Jul 11 08:03:00 PM PDT 24 |
Jul 11 08:33:47 PM PDT 24 |
8140732852 ps |
| T1171 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_ops.1067147189 |
|
|
Jul 11 08:25:12 PM PDT 24 |
Jul 11 08:37:08 PM PDT 24 |
3934632962 ps |
| T160 |
/workspace/coverage/default/2.chip_plic_all_irqs_10.2716469646 |
|
|
Jul 11 08:29:44 PM PDT 24 |
Jul 11 08:40:33 PM PDT 24 |
3990784688 ps |
| T1172 |
/workspace/coverage/default/4.chip_sw_uart_tx_rx.518782728 |
|
|
Jul 11 08:28:11 PM PDT 24 |
Jul 11 08:41:18 PM PDT 24 |
3976004828 ps |
| T1173 |
/workspace/coverage/default/2.chip_tap_straps_rma.1694693999 |
|
|
Jul 11 08:22:41 PM PDT 24 |
Jul 11 08:26:09 PM PDT 24 |
2907861609 ps |
| T1174 |
/workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access.908216319 |
|
|
Jul 11 08:21:23 PM PDT 24 |
Jul 11 08:31:11 PM PDT 24 |
3954581616 ps |
| T1175 |
/workspace/coverage/default/2.chip_sw_exit_test_unlocked_bootstrap.531174826 |
|
|
Jul 11 08:23:17 PM PDT 24 |
Jul 11 11:19:08 PM PDT 24 |
58239208371 ps |
| T1176 |
/workspace/coverage/default/0.chip_sw_kmac_entropy.1498946513 |
|
|
Jul 11 08:01:44 PM PDT 24 |
Jul 11 08:07:41 PM PDT 24 |
3323602544 ps |
| T39 |
/workspace/coverage/default/2.chip_sw_gpio.3216870008 |
|
|
Jul 11 08:22:37 PM PDT 24 |
Jul 11 08:28:29 PM PDT 24 |
3243058834 ps |
| T1177 |
/workspace/coverage/default/2.chip_sw_power_idle_load.1404285978 |
|
|
Jul 11 08:30:07 PM PDT 24 |
Jul 11 08:41:53 PM PDT 24 |
4449161374 ps |
| T1178 |
/workspace/coverage/default/0.chip_sw_rstmgr_sw_rst.2835070620 |
|
|
Jul 11 08:04:30 PM PDT 24 |
Jul 11 08:07:40 PM PDT 24 |
3132961510 ps |
| T1179 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod.2849947842 |
|
|
Jul 11 08:09:09 PM PDT 24 |
Jul 11 09:15:40 PM PDT 24 |
15285506969 ps |
| T1180 |
/workspace/coverage/default/1.chip_sw_csrng_kat_test.2454178370 |
|
|
Jul 11 08:15:14 PM PDT 24 |
Jul 11 08:19:40 PM PDT 24 |
3349933640 ps |
| T1181 |
/workspace/coverage/default/0.chip_sw_kmac_mode_cshake.366990424 |
|
|
Jul 11 08:02:30 PM PDT 24 |
Jul 11 08:07:19 PM PDT 24 |
2874830740 ps |
| T1182 |
/workspace/coverage/default/17.chip_sw_uart_rand_baudrate.391976935 |
|
|
Jul 11 08:32:31 PM PDT 24 |
Jul 11 08:40:18 PM PDT 24 |
3583052928 ps |
| T331 |
/workspace/coverage/default/0.chip_sw_rstmgr_alert_info.65021513 |
|
|
Jul 11 08:02:22 PM PDT 24 |
Jul 11 08:27:31 PM PDT 24 |
10341186732 ps |
| T211 |
/workspace/coverage/default/1.chip_sw_sysrst_ctrl_inputs.954560761 |
|
|
Jul 11 08:10:43 PM PDT 24 |
Jul 11 08:15:18 PM PDT 24 |
2629215549 ps |
| T1183 |
/workspace/coverage/default/1.chip_sw_kmac_entropy.3471331638 |
|
|
Jul 11 08:08:59 PM PDT 24 |
Jul 11 08:13:43 PM PDT 24 |
3237439352 ps |
| T1184 |
/workspace/coverage/default/0.chip_sw_alert_handler_escalation.3431512636 |
|
|
Jul 11 08:04:39 PM PDT 24 |
Jul 11 08:11:33 PM PDT 24 |
4877637574 ps |
| T1185 |
/workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.248289762 |
|
|
Jul 11 08:07:21 PM PDT 24 |
Jul 11 08:22:54 PM PDT 24 |
8221559980 ps |
| T257 |
/workspace/coverage/default/0.rom_e2e_jtag_debug_rma.2821664392 |
|
|
Jul 11 08:08:49 PM PDT 24 |
Jul 11 08:44:28 PM PDT 24 |
10874384001 ps |
| T1186 |
/workspace/coverage/default/1.chip_sw_aon_timer_smoketest.565853575 |
|
|
Jul 11 08:24:23 PM PDT 24 |
Jul 11 08:31:36 PM PDT 24 |
2973454128 ps |
| T1187 |
/workspace/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en.414723596 |
|
|
Jul 11 08:20:12 PM PDT 24 |
Jul 11 08:24:46 PM PDT 24 |
3536675430 ps |
| T1188 |
/workspace/coverage/default/3.chip_sw_lc_ctrl_transition.3870709308 |
|
|
Jul 11 08:25:08 PM PDT 24 |
Jul 11 08:30:22 PM PDT 24 |
6420124695 ps |
| T1189 |
/workspace/coverage/default/0.chip_sw_aon_timer_wdog_lc_escalate.76772943 |
|
|
Jul 11 08:00:41 PM PDT 24 |
Jul 11 08:09:18 PM PDT 24 |
5743085344 ps |
| T1190 |
/workspace/coverage/default/2.chip_sw_alert_handler_ping_timeout.885077540 |
|
|
Jul 11 08:21:55 PM PDT 24 |
Jul 11 08:31:23 PM PDT 24 |
4997937238 ps |
| T701 |
/workspace/coverage/default/2.chip_sw_lc_ctrl_rand_to_scrap.1284707365 |
|
|
Jul 11 08:24:43 PM PDT 24 |
Jul 11 08:27:11 PM PDT 24 |
2384956554 ps |
| T1191 |
/workspace/coverage/default/1.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.2265366539 |
|
|
Jul 11 08:23:30 PM PDT 24 |
Jul 11 08:45:01 PM PDT 24 |
8405537242 ps |
| T12 |
/workspace/coverage/default/0.chip_sw_sleep_pin_retention.3783146751 |
|
|
Jul 11 08:00:30 PM PDT 24 |
Jul 11 08:06:14 PM PDT 24 |
4024314642 ps |
| T359 |
/workspace/coverage/default/1.chip_sw_sensor_ctrl_status.1573803137 |
|
|
Jul 11 08:22:06 PM PDT 24 |
Jul 11 08:27:20 PM PDT 24 |
2904190414 ps |
| T1192 |
/workspace/coverage/default/7.chip_sw_lc_ctrl_transition.2812450476 |
|
|
Jul 11 08:29:11 PM PDT 24 |
Jul 11 08:42:55 PM PDT 24 |
10294387327 ps |
| T1193 |
/workspace/coverage/default/1.chip_sw_pwrmgr_usb_clk_disabled_when_active.2922004401 |
|
|
Jul 11 08:10:29 PM PDT 24 |
Jul 11 08:21:15 PM PDT 24 |
5247965560 ps |
| T1194 |
/workspace/coverage/default/45.chip_sw_alert_handler_lpg_sleep_mode_alerts.3648193317 |
|
|
Jul 11 08:38:29 PM PDT 24 |
Jul 11 08:45:26 PM PDT 24 |
3144091336 ps |
| T200 |
/workspace/coverage/default/0.chip_jtag_mem_access.291500814 |
|
|
Jul 11 07:54:55 PM PDT 24 |
Jul 11 08:16:52 PM PDT 24 |
13847306632 ps |
| T1195 |
/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.4000813869 |
|
|
Jul 11 08:19:31 PM PDT 24 |
Jul 11 08:27:28 PM PDT 24 |
4567852850 ps |
| T1196 |
/workspace/coverage/default/1.chip_sw_sleep_sram_ret_contents_no_scramble.976544305 |
|
|
Jul 11 08:23:18 PM PDT 24 |
Jul 11 08:33:13 PM PDT 24 |
7361743654 ps |
| T1197 |
/workspace/coverage/default/3.chip_tap_straps_prod.2173863065 |
|
|
Jul 11 08:28:19 PM PDT 24 |
Jul 11 08:30:38 PM PDT 24 |
2716698253 ps |
| T1198 |
/workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq.3945324523 |
|
|
Jul 11 08:26:28 PM PDT 24 |
Jul 11 09:31:56 PM PDT 24 |
16996644216 ps |
| T1199 |
/workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_no_scramble.957769221 |
|
|
Jul 11 08:03:52 PM PDT 24 |
Jul 11 08:12:59 PM PDT 24 |
8416414934 ps |