Line Coverage for Module :
prim_fifo_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 4 | 4 | 100.00 |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 | |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
44 |
1 |
1 |
45 |
1 |
1 |
48 |
1 |
1 |
49 |
1 |
1 |
53 |
|
unreachable |
Assert Coverage for Module :
prim_fifo_sync
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
195348940 |
0 |
0 |
T4 |
2117720 |
48740 |
0 |
0 |
T5 |
697940 |
21458 |
0 |
0 |
T6 |
9436650 |
453685 |
0 |
0 |
T17 |
1572420 |
56519 |
0 |
0 |
T18 |
0 |
8 |
0 |
0 |
T42 |
2420200 |
85843 |
0 |
0 |
T43 |
1453790 |
73839 |
0 |
0 |
T70 |
1523860 |
54251 |
0 |
0 |
T71 |
1334040 |
716619 |
0 |
0 |
T95 |
1248230 |
35191 |
0 |
0 |
T96 |
422300 |
6171 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T4 |
2117720 |
2116700 |
0 |
0 |
T5 |
697940 |
697390 |
0 |
0 |
T6 |
9436650 |
9436100 |
0 |
0 |
T17 |
1572420 |
1571910 |
0 |
0 |
T42 |
2420200 |
2419180 |
0 |
0 |
T43 |
1453790 |
1453210 |
0 |
0 |
T70 |
1523860 |
1523350 |
0 |
0 |
T71 |
1334040 |
1333940 |
0 |
0 |
T95 |
1248230 |
1247610 |
0 |
0 |
T96 |
422300 |
421680 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T4 |
2117720 |
2116700 |
0 |
0 |
T5 |
697940 |
697390 |
0 |
0 |
T6 |
9436650 |
9436100 |
0 |
0 |
T17 |
1572420 |
1571910 |
0 |
0 |
T42 |
2420200 |
2419180 |
0 |
0 |
T43 |
1453790 |
1453210 |
0 |
0 |
T70 |
1523860 |
1523350 |
0 |
0 |
T71 |
1334040 |
1333940 |
0 |
0 |
T95 |
1248230 |
1247610 |
0 |
0 |
T96 |
422300 |
421680 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T4 |
2117720 |
2116700 |
0 |
0 |
T5 |
697940 |
697390 |
0 |
0 |
T6 |
9436650 |
9436100 |
0 |
0 |
T17 |
1572420 |
1571910 |
0 |
0 |
T42 |
2420200 |
2419180 |
0 |
0 |
T43 |
1453790 |
1453210 |
0 |
0 |
T70 |
1523860 |
1523350 |
0 |
0 |
T71 |
1334040 |
1333940 |
0 |
0 |
T95 |
1248230 |
1247610 |
0 |
0 |
T96 |
422300 |
421680 |
0 |
0 |
gen_passthru_fifo.paramCheckPass
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
21510 |
21510 |
0 |
0 |
T4 |
10 |
10 |
0 |
0 |
T5 |
10 |
10 |
0 |
0 |
T6 |
10 |
10 |
0 |
0 |
T17 |
10 |
10 |
0 |
0 |
T42 |
10 |
10 |
0 |
0 |
T43 |
10 |
10 |
0 |
0 |
T70 |
10 |
10 |
0 |
0 |
T71 |
10 |
10 |
0 |
0 |
T95 |
10 |
10 |
0 |
0 |
T96 |
10 |
10 |
0 |
0 |