Unified Coverage Report :: Module Instance :: tb.dut.top_earlgrey.u_uart0.uart_core.u_uart_txfifo

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	533348296	63007695	0	0
DepthKnown_A	533348296	533240224	0	0
RvalidKnown_A	533348296	533240224	0	0
WreadyKnown_A	533348296	533240224	0	0
gen_passthru_fifo.paramCheckPass	1017	1017	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	533348296	63007695	0	0
T4	211772	20248	0	0
T5	69794	8274	0	0
T6	943665	114687	0	0
T17	157242	21276	0	0
T42	242020	31823	0	0
T43	145379	15968	0	0
T70	152386	20616	0	0
T71	133404	193601	0	0
T95	124823	11999	0	0
T96	42230	3461	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	533348296	533240224	0	0
T4	211772	211670	0	0
T5	69794	69739	0	0
T6	943665	943610	0	0
T17	157242	157191	0	0
T42	242020	241918	0	0
T43	145379	145321	0	0
T70	152386	152335	0	0
T71	133404	133394	0	0
T95	124823	124761	0	0
T96	42230	42168	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	533348296	533240224	0	0
T4	211772	211670	0	0
T5	69794	69739	0	0
T6	943665	943610	0	0
T17	157242	157191	0	0
T42	242020	241918	0	0
T43	145379	145321	0	0
T70	152386	152335	0	0
T71	133404	133394	0	0
T95	124823	124761	0	0
T96	42230	42168	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	533348296	533240224	0	0
T4	211772	211670	0	0
T5	69794	69739	0	0
T6	943665	943610	0	0
T17	157242	157191	0	0
T42	242020	241918	0	0
T43	145379	145321	0	0
T70	152386	152335	0	0
T71	133404	133394	0	0
T95	124823	124761	0	0
T96	42230	42168	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1017	1017	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T42	1	1	0	0
T43	1	1	0	0
T70	1	1	0	0
T71	1	1	0	0
T95	1	1	0	0
T96	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	2	50.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	0	0.00
CONT_ASSIGN	49	1	0	0.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	0	1
49	0	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	533348296	48891234	0	0
DepthKnown_A	533348296	533240224	0	0
RvalidKnown_A	533348296	533240224	0	0
WreadyKnown_A	533348296	533240224	0	0
gen_passthru_fifo.paramCheckPass	1017	1017	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	533348296	48891234	0	0
T4	211772	14110	0	0
T5	69794	5545	0	0
T6	943665	95859	0	0
T17	157242	16147	0	0
T42	242020	22223	0	0
T43	145379	13466	0	0
T70	152386	15487	0	0
T71	133404	182194	0	0
T95	124823	9542	0	0
T96	42230	1868	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	533348296	533240224	0	0
T4	211772	211670	0	0
T5	69794	69739	0	0
T6	943665	943610	0	0
T17	157242	157191	0	0
T42	242020	241918	0	0
T43	145379	145321	0	0
T70	152386	152335	0	0
T71	133404	133394	0	0
T95	124823	124761	0	0
T96	42230	42168	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	533348296	533240224	0	0
T4	211772	211670	0	0
T5	69794	69739	0	0
T6	943665	943610	0	0
T17	157242	157191	0	0
T42	242020	241918	0	0
T43	145379	145321	0	0
T70	152386	152335	0	0
T71	133404	133394	0	0
T95	124823	124761	0	0
T96	42230	42168	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	533348296	533240224	0	0
T4	211772	211670	0	0
T5	69794	69739	0	0
T6	943665	943610	0	0
T17	157242	157191	0	0
T42	242020	241918	0	0
T43	145379	145321	0	0
T70	152386	152335	0	0
T71	133404	133394	0	0
T95	124823	124761	0	0
T96	42230	42168	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1017	1017	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T42	1	1	0	0
T43	1	1	0	0
T70	1	1	0	0
T71	1	1	0	0
T95	1	1	0	0
T96	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	533348296	44823793	0	0
DepthKnown_A	533348296	533240224	0	0
RvalidKnown_A	533348296	533240224	0	0
WreadyKnown_A	533348296	533240224	0	0
gen_passthru_fifo.paramCheckPass	1017	1017	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	533348296	44823793	0	0
T4	211772	7266	0	0
T5	69794	3858	0	0
T6	943665	156486	0	0
T17	157242	9635	0	0
T42	242020	15785	0	0
T43	145379	22034	0	0
T70	152386	9161	0	0
T71	133404	170588	0	0
T95	124823	6859	0	0
T96	42230	459	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	533348296	533240224	0	0
T4	211772	211670	0	0
T5	69794	69739	0	0
T6	943665	943610	0	0
T17	157242	157191	0	0
T42	242020	241918	0	0
T43	145379	145321	0	0
T70	152386	152335	0	0
T71	133404	133394	0	0
T95	124823	124761	0	0
T96	42230	42168	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	533348296	533240224	0	0
T4	211772	211670	0	0
T5	69794	69739	0	0
T6	943665	943610	0	0
T17	157242	157191	0	0
T42	242020	241918	0	0
T43	145379	145321	0	0
T70	152386	152335	0	0
T71	133404	133394	0	0
T95	124823	124761	0	0
T96	42230	42168	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	533348296	533240224	0	0
T4	211772	211670	0	0
T5	69794	69739	0	0
T6	943665	943610	0	0
T17	157242	157191	0	0
T42	242020	241918	0	0
T43	145379	145321	0	0
T70	152386	152335	0	0
T71	133404	133394	0	0
T95	124823	124761	0	0
T96	42230	42168	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1017	1017	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T42	1	1	0	0
T43	1	1	0	0
T70	1	1	0	0
T71	1	1	0	0
T95	1	1	0	0
T96	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	533348296	38231588	0	0
DepthKnown_A	533348296	533240224	0	0
RvalidKnown_A	533348296	533240224	0	0
WreadyKnown_A	533348296	533240224	0	0
gen_passthru_fifo.paramCheckPass	1017	1017	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	533348296	38231588	0	0
T4	211772	6976	0	0
T5	69794	3689	0	0
T6	943665	86517	0	0
T17	157242	9357	0	0
T42	242020	15400	0	0
T43	145379	21915	0	0
T70	152386	8883	0	0
T71	133404	170084	0	0
T95	124823	6707	0	0
T96	42230	351	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	533348296	533240224	0	0
T4	211772	211670	0	0
T5	69794	69739	0	0
T6	943665	943610	0	0
T17	157242	157191	0	0
T42	242020	241918	0	0
T43	145379	145321	0	0
T70	152386	152335	0	0
T71	133404	133394	0	0
T95	124823	124761	0	0
T96	42230	42168	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	533348296	533240224	0	0
T4	211772	211670	0	0
T5	69794	69739	0	0
T6	943665	943610	0	0
T17	157242	157191	0	0
T42	242020	241918	0	0
T43	145379	145321	0	0
T70	152386	152335	0	0
T71	133404	133394	0	0
T95	124823	124761	0	0
T96	42230	42168	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	533348296	533240224	0	0
T4	211772	211670	0	0
T5	69794	69739	0	0
T6	943665	943610	0	0
T17	157242	157191	0	0
T42	242020	241918	0	0
T43	145379	145321	0	0
T70	152386	152335	0	0
T71	133404	133394	0	0
T95	124823	124761	0	0
T96	42230	42168	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1017	1017	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T42	1	1	0	0
T43	1	1	0	0
T70	1	1	0	0
T71	1	1	0	0
T95	1	1	0	0
T96	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	597230803	97530	0	0
DepthKnown_A	597230803	597110958	0	0
RvalidKnown_A	597230803	597110958	0	0
WreadyKnown_A	597230803	597110958	0	0
gen_passthru_fifo.paramCheckPass	2907	2907	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	597230803	97530	0	0
T4	211772	35	0	0
T5	69794	23	0	0
T6	943665	34	0	0
T17	157242	26	0	0
T42	242020	153	0	0
T43	145379	114	0	0
T70	152386	26	0	0
T71	133404	38	0	0
T95	124823	21	0	0
T96	42230	8	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	597230803	597110958	0	0
T4	211772	211670	0	0
T5	69794	69739	0	0
T6	943665	943610	0	0
T17	157242	157191	0	0
T42	242020	241918	0	0
T43	145379	145321	0	0
T70	152386	152335	0	0
T71	133404	133394	0	0
T95	124823	124761	0	0
T96	42230	42168	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	597230803	597110958	0	0
T4	211772	211670	0	0
T5	69794	69739	0	0
T6	943665	943610	0	0
T17	157242	157191	0	0
T42	242020	241918	0	0
T43	145379	145321	0	0
T70	152386	152335	0	0
T71	133404	133394	0	0
T95	124823	124761	0	0
T96	42230	42168	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	597230803	597110958	0	0
T4	211772	211670	0	0
T5	69794	69739	0	0
T6	943665	943610	0	0
T17	157242	157191	0	0
T42	242020	241918	0	0
T43	145379	145321	0	0
T70	152386	152335	0	0
T71	133404	133394	0	0
T95	124823	124761	0	0
T96	42230	42168	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2907	2907	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T42	1	1	0	0
T43	1	1	0	0
T70	1	1	0	0
T71	1	1	0	0
T95	1	1	0	0
T96	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	597230803	99785	0	0
DepthKnown_A	597230803	597110958	0	0
RvalidKnown_A	597230803	597110958	0	0
WreadyKnown_A	597230803	597110958	0	0
gen_passthru_fifo.paramCheckPass	2907	2907	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	597230803	99785	0	0
T4	211772	35	0	0
T5	69794	23	0	0
T6	943665	34	0	0
T17	157242	26	0	0
T42	242020	153	0	0
T43	145379	114	0	0
T70	152386	26	0	0
T71	133404	38	0	0
T95	124823	21	0	0
T96	42230	8	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	597230803	597110958	0	0
T4	211772	211670	0	0
T5	69794	69739	0	0
T6	943665	943610	0	0
T17	157242	157191	0	0
T42	242020	241918	0	0
T43	145379	145321	0	0
T70	152386	152335	0	0
T71	133404	133394	0	0
T95	124823	124761	0	0
T96	42230	42168	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	597230803	597110958	0	0
T4	211772	211670	0	0
T5	69794	69739	0	0
T6	943665	943610	0	0
T17	157242	157191	0	0
T42	242020	241918	0	0
T43	145379	145321	0	0
T70	152386	152335	0	0
T71	133404	133394	0	0
T95	124823	124761	0	0
T96	42230	42168	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	597230803	597110958	0	0
T4	211772	211670	0	0
T5	69794	69739	0	0
T6	943665	943610	0	0
T17	157242	157191	0	0
T42	242020	241918	0	0
T43	145379	145321	0	0
T70	152386	152335	0	0
T71	133404	133394	0	0
T95	124823	124761	0	0
T96	42230	42168	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2907	2907	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T42	1	1	0	0
T43	1	1	0	0
T70	1	1	0	0
T71	1	1	0	0
T95	1	1	0	0
T96	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	597230803	52182	0	0
DepthKnown_A	597230803	597110958	0	0
RvalidKnown_A	597230803	597110958	0	0
WreadyKnown_A	597230803	597110958	0	0
gen_passthru_fifo.paramCheckPass	2907	2907	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	597230803	52182	0	0
T4	211772	29	0	0
T5	69794	20	0	0
T6	943665	5	0	0
T17	157242	23	0	0
T42	242020	97	0	0
T43	145379	12	0	0
T70	152386	23	0	0
T71	133404	32	0	0
T95	124823	20	0	0
T96	42230	8	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	597230803	597110958	0	0
T4	211772	211670	0	0
T5	69794	69739	0	0
T6	943665	943610	0	0
T17	157242	157191	0	0
T42	242020	241918	0	0
T43	145379	145321	0	0
T70	152386	152335	0	0
T71	133404	133394	0	0
T95	124823	124761	0	0
T96	42230	42168	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	597230803	597110958	0	0
T4	211772	211670	0	0
T5	69794	69739	0	0
T6	943665	943610	0	0
T17	157242	157191	0	0
T42	242020	241918	0	0
T43	145379	145321	0	0
T70	152386	152335	0	0
T71	133404	133394	0	0
T95	124823	124761	0	0
T96	42230	42168	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	597230803	597110958	0	0
T4	211772	211670	0	0
T5	69794	69739	0	0
T6	943665	943610	0	0
T17	157242	157191	0	0
T42	242020	241918	0	0
T43	145379	145321	0	0
T70	152386	152335	0	0
T71	133404	133394	0	0
T95	124823	124761	0	0
T96	42230	42168	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2907	2907	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T42	1	1	0	0
T43	1	1	0	0
T70	1	1	0	0
T71	1	1	0	0
T95	1	1	0	0
T96	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	597230803	52182	0	0
DepthKnown_A	597230803	597110958	0	0
RvalidKnown_A	597230803	597110958	0	0
WreadyKnown_A	597230803	597110958	0	0
gen_passthru_fifo.paramCheckPass	2907	2907	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	597230803	52182	0	0
T4	211772	29	0	0
T5	69794	20	0	0
T6	943665	5	0	0
T17	157242	23	0	0
T42	242020	97	0	0
T43	145379	12	0	0
T70	152386	23	0	0
T71	133404	32	0	0
T95	124823	20	0	0
T96	42230	8	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	597230803	597110958	0	0
T4	211772	211670	0	0
T5	69794	69739	0	0
T6	943665	943610	0	0
T17	157242	157191	0	0
T42	242020	241918	0	0
T43	145379	145321	0	0
T70	152386	152335	0	0
T71	133404	133394	0	0
T95	124823	124761	0	0
T96	42230	42168	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	597230803	597110958	0	0
T4	211772	211670	0	0
T5	69794	69739	0	0
T6	943665	943610	0	0
T17	157242	157191	0	0
T42	242020	241918	0	0
T43	145379	145321	0	0
T70	152386	152335	0	0
T71	133404	133394	0	0
T95	124823	124761	0	0
T96	42230	42168	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	597230803	597110958	0	0
T4	211772	211670	0	0
T5	69794	69739	0	0
T6	943665	943610	0	0
T17	157242	157191	0	0
T42	242020	241918	0	0
T43	145379	145321	0	0
T70	152386	152335	0	0
T71	133404	133394	0	0
T95	124823	124761	0	0
T96	42230	42168	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2907	2907	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T42	1	1	0	0
T43	1	1	0	0
T70	1	1	0	0
T71	1	1	0	0
T95	1	1	0	0
T96	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	597230803	45348	0	0
DepthKnown_A	597230803	597110958	0	0
RvalidKnown_A	597230803	597110958	0	0
WreadyKnown_A	597230803	597110958	0	0
gen_passthru_fifo.paramCheckPass	2907	2907	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	597230803	45348	0	0
T4	211772	6	0	0
T5	69794	3	0	0
T6	943665	29	0	0
T17	157242	3	0	0
T18	0	4	0	0
T42	242020	56	0	0
T43	145379	102	0	0
T70	152386	3	0	0
T71	133404	6	0	0
T95	124823	1	0	0
T96	42230	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	597230803	597110958	0	0
T4	211772	211670	0	0
T5	69794	69739	0	0
T6	943665	943610	0	0
T17	157242	157191	0	0
T42	242020	241918	0	0
T43	145379	145321	0	0
T70	152386	152335	0	0
T71	133404	133394	0	0
T95	124823	124761	0	0
T96	42230	42168	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	597230803	597110958	0	0
T4	211772	211670	0	0
T5	69794	69739	0	0
T6	943665	943610	0	0
T17	157242	157191	0	0
T42	242020	241918	0	0
T43	145379	145321	0	0
T70	152386	152335	0	0
T71	133404	133394	0	0
T95	124823	124761	0	0
T96	42230	42168	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	597230803	597110958	0	0
T4	211772	211670	0	0
T5	69794	69739	0	0
T6	943665	943610	0	0
T17	157242	157191	0	0
T42	242020	241918	0	0
T43	145379	145321	0	0
T70	152386	152335	0	0
T71	133404	133394	0	0
T95	124823	124761	0	0
T96	42230	42168	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2907	2907	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T42	1	1	0	0
T43	1	1	0	0
T70	1	1	0	0
T71	1	1	0	0
T95	1	1	0	0
T96	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	597230803	47603	0	0
DepthKnown_A	597230803	597110958	0	0
RvalidKnown_A	597230803	597110958	0	0
WreadyKnown_A	597230803	597110958	0	0
gen_passthru_fifo.paramCheckPass	2907	2907	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	597230803	47603	0	0
T4	211772	6	0	0
T5	69794	3	0	0
T6	943665	29	0	0
T17	157242	3	0	0
T18	0	4	0	0
T42	242020	56	0	0
T43	145379	102	0	0
T70	152386	3	0	0
T71	133404	6	0	0
T95	124823	1	0	0
T96	42230	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	597230803	597110958	0	0
T4	211772	211670	0	0
T5	69794	69739	0	0
T6	943665	943610	0	0
T17	157242	157191	0	0
T42	242020	241918	0	0
T43	145379	145321	0	0
T70	152386	152335	0	0
T71	133404	133394	0	0
T95	124823	124761	0	0
T96	42230	42168	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	597230803	597110958	0	0
T4	211772	211670	0	0
T5	69794	69739	0	0
T6	943665	943610	0	0
T17	157242	157191	0	0
T42	242020	241918	0	0
T43	145379	145321	0	0
T70	152386	152335	0	0
T71	133404	133394	0	0
T95	124823	124761	0	0
T96	42230	42168	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	597230803	597110958	0	0
T4	211772	211670	0	0
T5	69794	69739	0	0
T6	943665	943610	0	0
T17	157242	157191	0	0
T42	242020	241918	0	0
T43	145379	145321	0	0
T70	152386	152335	0	0
T71	133404	133394	0	0
T95	124823	124761	0	0
T96	42230	42168	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2907	2907	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T42	1	1	0	0
T43	1	1	0	0
T70	1	1	0	0
T71	1	1	0	0
T95	1	1	0	0
T96	1	1	0	0