Unified Coverage Report :: Module :: tlul_err_resp

Module : tlul_err_resp

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.75	95.24	80.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_tlul_socket_1n_0.1/rtl/tlul_err_resp.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_rv_core_ibex.u_sim_win_rsp	91.75	95.24	80.00			100.00

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_sim_win_rsp

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.75	95.24	80.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.32	77.27	80.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
90.27	94.12	89.29	99.75		100.00	68.18	u_rv_core_ibex

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_intg_gen	80.43	60.87					100.00

Line Coverage for Module : tlul_err_resp

	Line No.	Total	Covered	Percent
TOTAL		21	20	95.24
ALWAYS	34	14	14	100.00
CONT_ASSIGN	51	1	1	100.00
CONT_ASSIGN	52	1	1	100.00
CONT_ASSIGN	53	1	0	0.00
CONT_ASSIGN	55	1	1	100.00
CONT_ASSIGN	58	1	1	100.00
CONT_ASSIGN	59	1	1	100.00
CONT_ASSIGN	65	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_socket_1n_0.1/rtl/tlul_err_resp.sv' or '../src/lowrisc_tlul_socket_1n_0.1/rtl/tlul_err_resp.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34	1	1
35	1	1
36	1	1
37	1	1
38	1	1
39	1	1
40	1	1
41	1	1
42	1	1
43	1	1
44	1	1
45	1	1
46	1	1
47	1	1
			MISSING_ELSE
51	1	1
52	1	1
53	0	1
55	1	1
58	1	1
59	1	1
65	1	1

---

Cond Coverage for Module : tlul_err_resp

	Total	Covered	Percent
Conditions	10	8	80.00
Logical	10	8	80.00
Non-Logical	0	0
Event	0	0

 LINE       40
 EXPRESSION (err_rsp_pending && tl_h_i.d_ready)
             -------1-------    -------2------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Not Covered
1	1	Covered	T4,T5,T6

 LINE       42
 EXPRESSION (tl_h_i.a_valid && tl_h_o_int.a_ready)
             -------1------    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Not Covered
1	1	Covered	T4,T5,T6

 LINE       59
 EXPRESSION ((err_opcode == Get) ? AccessAckData : AccessAck)
             ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       59
 SUB-EXPRESSION (err_opcode == Get)
                ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

---

Branch Coverage for Module : tlul_err_resp

	Line No.	Total	Covered	Percent
Branches		6	6	100.00
TERNARY	59	2	2	100.00
IF	34	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_socket_1n_0.1/rtl/tlul_err_resp.sv' or '../src/lowrisc_tlul_socket_1n_0.1/rtl/tlul_err_resp.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	59	((err_opcode == Get)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	34	if ((!rst_ni))
-2-:	40	if ((err_rsp_pending && tl_h_i.d_ready))
-3-:	42	if ((tl_h_i.a_valid && tl_h_o_int.a_ready))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T4,T5,T6
0	0	1	Covered	T4,T5,T6
0	0	0	Covered	T4,T5,T6

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_sim_win_rsp

	Line No.	Total	Covered	Percent
TOTAL		21	20	95.24
ALWAYS	34	14	14	100.00
CONT_ASSIGN	51	1	1	100.00
CONT_ASSIGN	52	1	1	100.00
CONT_ASSIGN	53	1	0	0.00
CONT_ASSIGN	55	1	1	100.00
CONT_ASSIGN	58	1	1	100.00
CONT_ASSIGN	59	1	1	100.00
CONT_ASSIGN	65	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_socket_1n_0.1/rtl/tlul_err_resp.sv' or '../src/lowrisc_tlul_socket_1n_0.1/rtl/tlul_err_resp.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34	1	1
35	1	1
36	1	1
37	1	1
38	1	1
39	1	1
40	1	1
41	1	1
42	1	1
43	1	1
44	1	1
45	1	1
46	1	1
47	1	1
			MISSING_ELSE
51	1	1
52	1	1
53	0	1
55	1	1
58	1	1
59	1	1
65	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_sim_win_rsp

	Total	Covered	Percent
Conditions	10	8	80.00
Logical	10	8	80.00
Non-Logical	0	0
Event	0	0

 LINE       40
 EXPRESSION (err_rsp_pending && tl_h_i.d_ready)
             -------1-------    -------2------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Not Covered
1	1	Covered	T4,T5,T6

 LINE       42
 EXPRESSION (tl_h_i.a_valid && tl_h_o_int.a_ready)
             -------1------    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Not Covered
1	1	Covered	T4,T5,T6

 LINE       59
 EXPRESSION ((err_opcode == Get) ? AccessAckData : AccessAck)
             ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       59
 SUB-EXPRESSION (err_opcode == Get)
                ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_sim_win_rsp

	Line No.	Total	Covered	Percent
Branches		6	6	100.00
TERNARY	59	2	2	100.00
IF	34	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_socket_1n_0.1/rtl/tlul_err_resp.sv' or '../src/lowrisc_tlul_socket_1n_0.1/rtl/tlul_err_resp.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	59	((err_opcode == Get)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	34	if ((!rst_ni))
-2-:	40	if ((err_rsp_pending && tl_h_i.d_ready))
-3-:	42	if ((tl_h_i.a_valid && tl_h_o_int.a_ready))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T4,T5,T6
0	0	1	Covered	T4,T5,T6
0	0	0	Covered	T4,T5,T6