Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : rv_core_ibex_cfg_reg_top
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.92 100.00 99.68 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_rv_core_ibex_0.1/rtl/rv_core_ibex_cfg_reg_top.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg 99.92 100.00 99.68 100.00 100.00



Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.92 100.00 99.68 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.28 98.69 98.84 99.58 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
90.27 94.12 89.29 99.75 100.00 68.18 u_rv_core_ibex


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_alert_test_fatal_hw_err 100.00 100.00
u_alert_test_fatal_sw_err 100.00 100.00
u_alert_test_recov_hw_err 100.00 100.00
u_alert_test_recov_sw_err 100.00 100.00
u_chk 100.00 100.00 100.00
u_dbus_addr_en_0 100.00 100.00 100.00 100.00
u_dbus_addr_en_1 100.00 100.00 100.00 100.00
u_dbus_addr_matching_0 100.00 100.00 100.00 100.00
u_dbus_addr_matching_1 100.00 100.00 100.00 100.00
u_dbus_regwen_0 100.00 100.00 100.00 100.00
u_dbus_regwen_1 100.00 100.00 100.00 100.00
u_dbus_remap_addr_0 100.00 100.00 100.00 100.00
u_dbus_remap_addr_1 100.00 100.00 100.00 100.00
u_err_status_fatal_core_err 97.22 100.00 91.67 100.00
u_err_status_fatal_intg_err 100.00 100.00 100.00 100.00
u_err_status_recov_core_err 93.52 88.89 91.67 100.00
u_err_status_reg_intg_err 97.22 100.00 91.67 100.00
u_fpga_info 33.33 33.33
u_ibus_addr_en_0 100.00 100.00 100.00 100.00
u_ibus_addr_en_1 100.00 100.00 100.00 100.00
u_ibus_addr_matching_0 100.00 100.00 100.00 100.00
u_ibus_addr_matching_1 100.00 100.00 100.00 100.00
u_ibus_regwen_0 100.00 100.00 100.00 100.00
u_ibus_regwen_1 100.00 100.00 100.00 100.00
u_ibus_remap_addr_0 100.00 100.00 100.00 100.00
u_ibus_remap_addr_1 100.00 100.00 100.00 100.00
u_nmi_enable_alert_en 100.00 100.00 100.00 100.00
u_nmi_enable_wdog_en 100.00 100.00 100.00 100.00
u_nmi_state_alert 100.00 100.00 100.00 100.00
u_nmi_state_wdog 100.00 100.00 100.00 100.00
u_prim_reg_we_check 100.00 100.00
u_reg_if 98.98 97.14 98.77 100.00 100.00
u_rnd_data 100.00 100.00
u_rnd_status_rnd_data_fips 100.00 100.00
u_rnd_status_rnd_data_valid 100.00 100.00
u_rsp_intg_gen 100.00 100.00 100.00
u_socket 96.72 96.25 94.64 96.00 100.00
u_sw_fatal_err 100.00 100.00 100.00 100.00
u_sw_recov_err 100.00 100.00 100.00 100.00


Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : rv_core_ibex_cfg_reg_top
Line No.TotalCoveredPercent
TOTAL178178100.00
ALWAYS7344100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN10011100.00
CONT_ASSIGN10111100.00
CONT_ASSIGN10311100.00
CONT_ASSIGN10411100.00
ALWAYS13033100.00
CONT_ASSIGN16711100.00
CONT_ASSIGN16811100.00
CONT_ASSIGN26311100.00
CONT_ASSIGN27811100.00
CONT_ASSIGN29411100.00
CONT_ASSIGN31011100.00
CONT_ASSIGN32611100.00
CONT_ASSIGN44711100.00
CONT_ASSIGN47911100.00
CONT_ASSIGN51111100.00
CONT_ASSIGN54311100.00
CONT_ASSIGN57511100.00
CONT_ASSIGN60711100.00
CONT_ASSIGN69711100.00
CONT_ASSIGN72911100.00
CONT_ASSIGN76111100.00
CONT_ASSIGN79311100.00
CONT_ASSIGN82511100.00
CONT_ASSIGN85711100.00
ALWAYS11742626100.00
CONT_ASSIGN120211100.00
ALWAYS120611100.00
CONT_ASSIGN123511100.00
CONT_ASSIGN123711100.00
CONT_ASSIGN123911100.00
CONT_ASSIGN124111100.00
CONT_ASSIGN124311100.00
CONT_ASSIGN124411100.00
CONT_ASSIGN124611100.00
CONT_ASSIGN124711100.00
CONT_ASSIGN124911100.00
CONT_ASSIGN125011100.00
CONT_ASSIGN125211100.00
CONT_ASSIGN125311100.00
CONT_ASSIGN125511100.00
CONT_ASSIGN125611100.00
CONT_ASSIGN125811100.00
CONT_ASSIGN125911100.00
CONT_ASSIGN126111100.00
CONT_ASSIGN126211100.00
CONT_ASSIGN126411100.00
CONT_ASSIGN126511100.00
CONT_ASSIGN126711100.00
CONT_ASSIGN126811100.00
CONT_ASSIGN127011100.00
CONT_ASSIGN127111100.00
CONT_ASSIGN127311100.00
CONT_ASSIGN127411100.00
CONT_ASSIGN127611100.00
CONT_ASSIGN127711100.00
CONT_ASSIGN127911100.00
CONT_ASSIGN128011100.00
CONT_ASSIGN128211100.00
CONT_ASSIGN128311100.00
CONT_ASSIGN128511100.00
CONT_ASSIGN128611100.00
CONT_ASSIGN128811100.00
CONT_ASSIGN128911100.00
CONT_ASSIGN129111100.00
CONT_ASSIGN129211100.00
CONT_ASSIGN129411100.00
CONT_ASSIGN129511100.00
CONT_ASSIGN129711100.00
CONT_ASSIGN129811100.00
CONT_ASSIGN130011100.00
CONT_ASSIGN130211100.00
CONT_ASSIGN130311100.00
CONT_ASSIGN130511100.00
CONT_ASSIGN130711100.00
CONT_ASSIGN130811100.00
CONT_ASSIGN131011100.00
CONT_ASSIGN131211100.00
CONT_ASSIGN131411100.00
CONT_ASSIGN131611100.00
CONT_ASSIGN131711100.00
CONT_ASSIGN131811100.00
CONT_ASSIGN131911100.00
ALWAYS13232626100.00
ALWAYS13533636100.00
CONT_ASSIGN147500
CONT_ASSIGN148311100.00
CONT_ASSIGN148411100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_rv_core_ibex_0.1/rtl/rv_core_ibex_cfg_reg_top.sv' or '../src/lowrisc_ip_rv_core_ibex_0.1/rtl/rv_core_ibex_cfg_reg_top.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
73 1 1
74 1 1
75 1 1
76 1 1
MISSING_ELSE
82 1 1
100 1 1
101 1 1
103 1 1
104 1 1
130 1 1
136 1 1
137 1 1
MISSING_ELSE
167 1 1
168 1 1
263 1 1
278 1 1
294 1 1
310 1 1
326 1 1
447 1 1
479 1 1
511 1 1
543 1 1
575 1 1
607 1 1
697 1 1
729 1 1
761 1 1
793 1 1
825 1 1
857 1 1
1174 1 1
1175 1 1
1176 1 1
1177 1 1
1178 1 1
1179 1 1
1180 1 1
1181 1 1
1182 1 1
1183 1 1
1184 1 1
1185 1 1
1186 1 1
1187 1 1
1188 1 1
1189 1 1
1190 1 1
1191 1 1
1192 1 1
1193 1 1
1194 1 1
1195 1 1
1196 1 1
1197 1 1
1198 1 1
1199 1 1
1202 1 1
1206 1 1
1235 1 1
1237 1 1
1239 1 1
1241 1 1
1243 1 1
1244 1 1
1246 1 1
1247 1 1
1249 1 1
1250 1 1
1252 1 1
1253 1 1
1255 1 1
1256 1 1
1258 1 1
1259 1 1
1261 1 1
1262 1 1
1264 1 1
1265 1 1
1267 1 1
1268 1 1
1270 1 1
1271 1 1
1273 1 1
1274 1 1
1276 1 1
1277 1 1
1279 1 1
1280 1 1
1282 1 1
1283 1 1
1285 1 1
1286 1 1
1288 1 1
1289 1 1
1291 1 1
1292 1 1
1294 1 1
1295 1 1
1297 1 1
1298 1 1
1300 1 1
1302 1 1
1303 1 1
1305 1 1
1307 1 1
1308 1 1
1310 1 1
1312 1 1
1314 1 1
1316 1 1
1317 1 1
1318 1 1
1319 1 1
1323 1 1
1324 1 1
1325 1 1
1326 1 1
1327 1 1
1328 1 1
1329 1 1
1330 1 1
1331 1 1
1332 1 1
1333 1 1
1334 1 1
1335 1 1
1336 1 1
1337 1 1
1338 1 1
1339 1 1
1340 1 1
1341 1 1
1342 1 1
1343 1 1
1344 1 1
1345 1 1
1346 1 1
1347 1 1
1348 1 1
1353 1 1
1354 1 1
1356 1 1
1357 1 1
1358 1 1
1359 1 1
1363 1 1
1367 1 1
1371 1 1
1375 1 1
1379 1 1
1383 1 1
1387 1 1
1391 1 1
1395 1 1
1399 1 1
1403 1 1
1407 1 1
1411 1 1
1415 1 1
1419 1 1
1423 1 1
1427 1 1
1431 1 1
1435 1 1
1436 1 1
1440 1 1
1441 1 1
1445 1 1
1446 1 1
1447 1 1
1448 1 1
1452 1 1
1456 1 1
1457 1 1
1461 1 1
1475 unreachable
1483 1 1
1484 1 1


Cond Coverage for Module : rv_core_ibex_cfg_reg_top
TotalCoveredPercent
Conditions31131099.68
Logical31131099.68
Non-Logical00
Event00

 LINE       63
 EXPRESSION (reg_we && ((!addrmiss)))
             ---1--    ------2------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT86,T89,T123
11CoveredT6,T42,T74

 LINE       75
 EXPRESSION (intg_err || reg_we_err)
             ----1---    -----2----
-1--2-StatusTests
00CoveredT4,T5,T6
01CoveredT245,T246,T247
10Not Covered

 LINE       82
 EXPRESSION (err_q | intg_err | reg_we_err)
             --1--   ----2---   -----3----
-1--2--3-StatusTests
000CoveredT4,T5,T6
001CoveredT245,T246,T247
010CoveredT85,T249,T683
100CoveredT245,T246,T247

 LINE       130
 EXPRESSION ((tl_i.a_address[(AW - 1):0] inside {[128:159]}) ? 1'b0 : 1'b1)
             -----------------------1-----------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT4,T5,T6

 LINE       168
 EXPRESSION (addrmiss | wr_err | intg_err)
             ----1---   ---2--   ----3---
-1--2--3-StatusTests
000CoveredT4,T5,T6
001CoveredT85,T249,T683
010CoveredT86,T124,T123
100CoveredT86,T89,T124

 LINE       447
 EXPRESSION (ibus_addr_en_0_we & ibus_regwen_0_qs)
             --------1--------   --------2-------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT143,T144,T134
11CoveredT182,T183,T300

 LINE       479
 EXPRESSION (ibus_addr_en_1_we & ibus_regwen_1_qs)
             --------1--------   --------2-------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT380,T134,T398
11CoveredT182,T183,T300

 LINE       511
 EXPRESSION (ibus_addr_matching_0_we & ibus_regwen_0_qs)
             -----------1-----------   --------2-------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT143,T144,T134
11CoveredT182,T183,T300

 LINE       543
 EXPRESSION (ibus_addr_matching_1_we & ibus_regwen_1_qs)
             -----------1-----------   --------2-------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT134,T130,T382
11CoveredT182,T183,T300

 LINE       575
 EXPRESSION (ibus_remap_addr_0_we & ibus_regwen_0_qs)
             ----------1---------   --------2-------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT143,T383,T144
11CoveredT182,T183,T300

 LINE       607
 EXPRESSION (ibus_remap_addr_1_we & ibus_regwen_1_qs)
             ----------1---------   --------2-------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT380,T398,T130
11CoveredT182,T183,T300

 LINE       697
 EXPRESSION (dbus_addr_en_0_we & dbus_regwen_0_qs)
             --------1--------   --------2-------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT144,T130,T407
11CoveredT182,T183,T300

 LINE       729
 EXPRESSION (dbus_addr_en_1_we & dbus_regwen_1_qs)
             --------1--------   --------2-------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT144,T134,T384
11CoveredT182,T183,T300

 LINE       761
 EXPRESSION (dbus_addr_matching_0_we & dbus_regwen_0_qs)
             -----------1-----------   --------2-------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT143,T144,T415
11CoveredT182,T183,T300

 LINE       793
 EXPRESSION (dbus_addr_matching_1_we & dbus_regwen_1_qs)
             -----------1-----------   --------2-------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT380,T144,T134
11CoveredT182,T183,T300

 LINE       825
 EXPRESSION (dbus_remap_addr_0_we & dbus_regwen_0_qs)
             ----------1---------   --------2-------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT143,T144,T130
11CoveredT182,T183,T300

 LINE       857
 EXPRESSION (dbus_remap_addr_1_we & dbus_regwen_1_qs)
             ----------1---------   --------2-------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT380,T144,T134
11CoveredT182,T183,T300

 LINE       1175
 EXPRESSION (reg_addr == rv_core_ibex_reg_pkg::RV_CORE_IBEX_ALERT_TEST_OFFSET)
            ---------------------------------1--------------------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT4,T5,T6

 LINE       1176
 EXPRESSION (reg_addr == rv_core_ibex_reg_pkg::RV_CORE_IBEX_SW_RECOV_ERR_OFFSET)
            ----------------------------------1---------------------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT85,T484,T486

 LINE       1177
 EXPRESSION (reg_addr == rv_core_ibex_reg_pkg::RV_CORE_IBEX_SW_FATAL_ERR_OFFSET)
            ----------------------------------1---------------------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT684,T85,T89

 LINE       1178
 EXPRESSION (reg_addr == rv_core_ibex_reg_pkg::RV_CORE_IBEX_IBUS_REGWEN_0_OFFSET)
            ----------------------------------1----------------------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT182,T183,T300

 LINE       1179
 EXPRESSION (reg_addr == rv_core_ibex_reg_pkg::RV_CORE_IBEX_IBUS_REGWEN_1_OFFSET)
            ----------------------------------1----------------------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT182,T183,T300

 LINE       1180
 EXPRESSION (reg_addr == rv_core_ibex_reg_pkg::RV_CORE_IBEX_IBUS_ADDR_EN_0_OFFSET)
            -----------------------------------1----------------------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT182,T183,T300

 LINE       1181
 EXPRESSION (reg_addr == rv_core_ibex_reg_pkg::RV_CORE_IBEX_IBUS_ADDR_EN_1_OFFSET)
            -----------------------------------1----------------------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT182,T183,T300

 LINE       1182
 EXPRESSION (reg_addr == rv_core_ibex_reg_pkg::RV_CORE_IBEX_IBUS_ADDR_MATCHING_0_OFFSET)
            --------------------------------------1-------------------------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT182,T183,T300

 LINE       1183
 EXPRESSION (reg_addr == rv_core_ibex_reg_pkg::RV_CORE_IBEX_IBUS_ADDR_MATCHING_1_OFFSET)
            --------------------------------------1-------------------------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT182,T183,T300

 LINE       1184
 EXPRESSION (reg_addr == rv_core_ibex_reg_pkg::RV_CORE_IBEX_IBUS_REMAP_ADDR_0_OFFSET)
            ------------------------------------1------------------------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT182,T183,T300

 LINE       1185
 EXPRESSION (reg_addr == rv_core_ibex_reg_pkg::RV_CORE_IBEX_IBUS_REMAP_ADDR_1_OFFSET)
            ------------------------------------1------------------------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT182,T183,T300

 LINE       1186
 EXPRESSION (reg_addr == rv_core_ibex_reg_pkg::RV_CORE_IBEX_DBUS_REGWEN_0_OFFSET)
            ----------------------------------1----------------------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT182,T183,T300

 LINE       1187
 EXPRESSION (reg_addr == rv_core_ibex_reg_pkg::RV_CORE_IBEX_DBUS_REGWEN_1_OFFSET)
            ----------------------------------1----------------------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT182,T183,T300

 LINE       1188
 EXPRESSION (reg_addr == rv_core_ibex_reg_pkg::RV_CORE_IBEX_DBUS_ADDR_EN_0_OFFSET)
            -----------------------------------1----------------------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT182,T183,T300

 LINE       1189
 EXPRESSION (reg_addr == rv_core_ibex_reg_pkg::RV_CORE_IBEX_DBUS_ADDR_EN_1_OFFSET)
            -----------------------------------1----------------------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT182,T183,T300

 LINE       1190
 EXPRESSION (reg_addr == rv_core_ibex_reg_pkg::RV_CORE_IBEX_DBUS_ADDR_MATCHING_0_OFFSET)
            --------------------------------------1-------------------------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT182,T183,T300

 LINE       1191
 EXPRESSION (reg_addr == rv_core_ibex_reg_pkg::RV_CORE_IBEX_DBUS_ADDR_MATCHING_1_OFFSET)
            --------------------------------------1-------------------------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT182,T183,T300

 LINE       1192
 EXPRESSION (reg_addr == rv_core_ibex_reg_pkg::RV_CORE_IBEX_DBUS_REMAP_ADDR_0_OFFSET)
            ------------------------------------1------------------------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT182,T183,T300

 LINE       1193
 EXPRESSION (reg_addr == rv_core_ibex_reg_pkg::RV_CORE_IBEX_DBUS_REMAP_ADDR_1_OFFSET)
            ------------------------------------1------------------------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT182,T183,T300

 LINE       1194
 EXPRESSION (reg_addr == rv_core_ibex_reg_pkg::RV_CORE_IBEX_NMI_ENABLE_OFFSET)
            ---------------------------------1--------------------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT6,T42,T74

 LINE       1195
 EXPRESSION (reg_addr == rv_core_ibex_reg_pkg::RV_CORE_IBEX_NMI_STATE_OFFSET)
            --------------------------------1--------------------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT42,T74,T255

 LINE       1196
 EXPRESSION (reg_addr == rv_core_ibex_reg_pkg::RV_CORE_IBEX_ERR_STATUS_OFFSET)
            ---------------------------------1--------------------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT247,T275,T276

 LINE       1197
 EXPRESSION (reg_addr == rv_core_ibex_reg_pkg::RV_CORE_IBEX_RND_DATA_OFFSET)
            --------------------------------1-------------------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT4,T5,T6

 LINE       1198
 EXPRESSION (reg_addr == rv_core_ibex_reg_pkg::RV_CORE_IBEX_RND_STATUS_OFFSET)
            ---------------------------------1--------------------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT4,T5,T6

 LINE       1199
 EXPRESSION (reg_addr == rv_core_ibex_reg_pkg::RV_CORE_IBEX_FPGA_INFO_OFFSET)
            --------------------------------1--------------------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT4,T5,T43

 LINE       1202
 EXPRESSION ((reg_re || reg_we) ? ((~|addr_hit)) : 1'b0)
             ---------1--------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT4,T5,T6

 LINE       1202
 SUB-EXPRESSION (reg_re || reg_we)
                 ---1--    ---2--
-1--2-StatusTests
00CoveredT4,T5,T6
01CoveredT6,T42,T74
10CoveredT4,T5,T6

 LINE       1206
 EXPRESSION 
 Number  Term
      1  reg_we & 
      2  ((addr_hit[0] & ((|(4'b1 & (~reg_be))))) | (addr_hit[1] & ((|(4'b1 & (~reg_be))))) | (addr_hit[2] & ((|(4'b1 & (~reg_be))))) | (addr_hit[3] & ((|(4'b1 & (~reg_be))))) | (addr_hit[4] & ((|(4'b1 & (~reg_be))))) | (addr_hit[5] & ((|(4'b1 & (~reg_be))))) | (addr_hit[6] & ((|(4'b1 & (~reg_be))))) | (addr_hit[7] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[8] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[9] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[10] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[11] & ((|(4'b1 & (~reg_be))))) | (addr_hit[12] & ((|(4'b1 & (~reg_be))))) | (addr_hit[13] & ((|(4'b1 & (~reg_be))))) | (addr_hit[14] & ((|(4'b1 & (~reg_be))))) | (addr_hit[15] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[16] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[17] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[18] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[19] & ((|(4'b1 & (~reg_be))))) | (addr_hit[20] & ((|(4'b1 & (~reg_be))))) | (addr_hit[21] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[22] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[23] & ((|(4'b1 & (~reg_be))))) | (addr_hit[24] & ((|(4'b1111 & (~reg_be)))))))
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT6,T42,T74
11CoveredT86,T124,T123

 LINE       1206
 SUB-EXPRESSION 
 Number  Term
      1  (addr_hit[0] & ((|(4'b1 & (~reg_be))))) | 
      2  (addr_hit[1] & ((|(4'b1 & (~reg_be))))) | 
      3  (addr_hit[2] & ((|(4'b1 & (~reg_be))))) | 
      4  (addr_hit[3] & ((|(4'b1 & (~reg_be))))) | 
      5  (addr_hit[4] & ((|(4'b1 & (~reg_be))))) | 
      6  (addr_hit[5] & ((|(4'b1 & (~reg_be))))) | 
      7  (addr_hit[6] & ((|(4'b1 & (~reg_be))))) | 
      8  (addr_hit[7] & ((|(4'b1111 & (~reg_be))))) | 
      9  (addr_hit[8] & ((|(4'b1111 & (~reg_be))))) | 
     10  (addr_hit[9] & ((|(4'b1111 & (~reg_be))))) | 
     11  (addr_hit[10] & ((|(4'b1111 & (~reg_be))))) | 
     12  (addr_hit[11] & ((|(4'b1 & (~reg_be))))) | 
     13  (addr_hit[12] & ((|(4'b1 & (~reg_be))))) | 
     14  (addr_hit[13] & ((|(4'b1 & (~reg_be))))) | 
     15  (addr_hit[14] & ((|(4'b1 & (~reg_be))))) | 
     16  (addr_hit[15] & ((|(4'b1111 & (~reg_be))))) | 
     17  (addr_hit[16] & ((|(4'b1111 & (~reg_be))))) | 
     18  (addr_hit[17] & ((|(4'b1111 & (~reg_be))))) | 
     19  (addr_hit[18] & ((|(4'b1111 & (~reg_be))))) | 
     20  (addr_hit[19] & ((|(4'b1 & (~reg_be))))) | 
     21  (addr_hit[20] & ((|(4'b1 & (~reg_be))))) | 
     22  (addr_hit[21] & ((|(4'b0011 & (~reg_be))))) | 
     23  (addr_hit[22] & ((|(4'b1111 & (~reg_be))))) | 
     24  (addr_hit[23] & ((|(4'b1 & (~reg_be))))) | 
     25  (addr_hit[24] & ((|(4'b1111 & (~reg_be))))))
Sensitive Expression == 1StatusTests
ALL ZEROSCoveredT4,T5,T6
25 (addr_hit[24] & ((|(4'...CoveredT89,T122,T123
24 (addr_hit[23] & ((|(4'...CoveredT86,T123,T486
23 (addr_hit[22] & ((|(4'...CoveredT85,T124,T123
22 (addr_hit[21] & ((|(4'...CoveredT85,T486,T685
21 (addr_hit[20] & ((|(4'...CoveredT85,T89,T124
20 (addr_hit[19] & ((|(4'...CoveredT486,T685,T427
19 (addr_hit[18] & ((|(4'...CoveredT486,T685,T427
18 (addr_hit[17] & ((|(4'...CoveredT85,T86,T123
17 (addr_hit[16] & ((|(4'...CoveredT85,T86,T486
16 (addr_hit[15] & ((|(4'...CoveredT85,T86,T486
15 (addr_hit[14] & ((|(4'...CoveredT85,T86,T124
14 (addr_hit[13] & ((|(4'...CoveredT85,T86,T486
13 (addr_hit[12] & ((|(4'...CoveredT124,T486,T685
12 (addr_hit[11] & ((|(4'...CoveredT86,T486,T685
11 (addr_hit[10] & ((|(4'...CoveredT85,T86,T123
10 (addr_hit[9] & ((|(4'b...CoveredT85,T86,T123
9 (addr_hit[8] & ((|(4'b...CoveredT85,T86,T123
8 (addr_hit[7] & ((|(4'b...CoveredT85,T86,T486
7 (addr_hit[6] & ((|(4'b...CoveredT86,T486,T685
6 (addr_hit[5] & ((|(4'b...CoveredT85,T484,T486
5 (addr_hit[4] & ((|(4'b...CoveredT85,T123,T484
4 (addr_hit[3] & ((|(4'b...CoveredT86,T486,T685
3 (addr_hit[2] & ((|(4'b...CoveredT89,T486,T685
2 (addr_hit[1] & ((|(4'b...CoveredT484,T486,T685
1 (addr_hit[0] & ((|(4'b...CoveredT4,T5,T6

 LINE       1206
 SUB-EXPRESSION (addr_hit[0] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------
-1--2-StatusTests
01CoveredT85,T86,T89
10CoveredT59,T243,T244
11CoveredT4,T5,T6

 LINE       1206
 SUB-EXPRESSION (addr_hit[1] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT85,T486,T685
11CoveredT484,T486,T685

 LINE       1206
 SUB-EXPRESSION (addr_hit[2] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT684,T85,T486
11CoveredT89,T486,T685

 LINE       1206
 SUB-EXPRESSION (addr_hit[3] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT182,T183,T300
11CoveredT86,T486,T685

 LINE       1206
 SUB-EXPRESSION (addr_hit[4] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT182,T183,T300
11CoveredT85,T123,T484

 LINE       1206
 SUB-EXPRESSION (addr_hit[5] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT182,T183,T300
11CoveredT85,T484,T486

 LINE       1206
 SUB-EXPRESSION (addr_hit[6] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT182,T183,T300
11CoveredT86,T486,T685

 LINE       1206
 SUB-EXPRESSION (addr_hit[7] & ((|(4'b1111 & (~reg_be)))))
                 -----1-----   -------------2------------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT182,T183,T300
11CoveredT85,T86,T486

 LINE       1206
 SUB-EXPRESSION (addr_hit[8] & ((|(4'b1111 & (~reg_be)))))
                 -----1-----   -------------2------------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT182,T183,T300
11CoveredT85,T86,T123

 LINE       1206
 SUB-EXPRESSION (addr_hit[9] & ((|(4'b1111 & (~reg_be)))))
                 -----1-----   -------------2------------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT182,T183,T300
11CoveredT85,T86,T123

 LINE       1206
 SUB-EXPRESSION (addr_hit[10] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT182,T183,T300
11CoveredT85,T86,T123

 LINE       1206
 SUB-EXPRESSION (addr_hit[11] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT182,T183,T300
11CoveredT86,T486,T685

 LINE       1206
 SUB-EXPRESSION (addr_hit[12] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT182,T183,T300
11CoveredT124,T486,T685

 LINE       1206
 SUB-EXPRESSION (addr_hit[13] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT182,T183,T300
11CoveredT85,T86,T486

 LINE       1206
 SUB-EXPRESSION (addr_hit[14] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT182,T183,T300
11CoveredT85,T86,T124

 LINE       1206
 SUB-EXPRESSION (addr_hit[15] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT182,T183,T300
11CoveredT85,T86,T486

 LINE       1206
 SUB-EXPRESSION (addr_hit[16] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT182,T183,T300
11CoveredT85,T86,T486

 LINE       1206
 SUB-EXPRESSION (addr_hit[17] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT182,T183,T300
11CoveredT85,T86,T123

 LINE       1206
 SUB-EXPRESSION (addr_hit[18] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT182,T183,T300
11CoveredT486,T685,T427

 LINE       1206
 SUB-EXPRESSION (addr_hit[19] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT6,T42,T74
11CoveredT486,T685,T427

 LINE       1206
 SUB-EXPRESSION (addr_hit[20] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT42,T74,T255
11CoveredT85,T89,T124

 LINE       1206
 SUB-EXPRESSION (addr_hit[21] & ((|(4'b0011 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT247,T275,T276
11CoveredT85,T486,T685

 LINE       1206
 SUB-EXPRESSION (addr_hit[22] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT4,T5,T6
11CoveredT85,T124,T123

 LINE       1206
 SUB-EXPRESSION (addr_hit[23] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT4,T5,T6
11CoveredT86,T123,T486

 LINE       1206
 SUB-EXPRESSION (addr_hit[24] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT4,T5,T43
11CoveredT89,T122,T123

 LINE       1235
 EXPRESSION (addr_hit[0] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT6,T42,T74
101CoveredT4,T5,T6
110CoveredT451,T552,T428
111CoveredT59,T243,T244

 LINE       1244
 EXPRESSION (addr_hit[1] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT6,T42,T74
101CoveredT484,T486,T685
110CoveredT685,T427,T470
111CoveredT486,T685,T427

 LINE       1247
 EXPRESSION (addr_hit[2] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT6,T42,T74
101CoveredT89,T486,T685
110CoveredT685,T426,T447
111CoveredT684,T486,T685

 LINE       1250
 EXPRESSION (addr_hit[3] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT6,T42,T74
101CoveredT182,T183,T300
110CoveredT486,T685,T451
111CoveredT486,T685,T426

 LINE       1253
 EXPRESSION (addr_hit[4] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT6,T42,T74
101CoveredT182,T183,T300
110CoveredT486,T447,T451
111CoveredT484,T486,T685

 LINE       1256
 EXPRESSION (addr_hit[5] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT6,T42,T74
101CoveredT484,T486,T685
110CoveredT427,T426,T490
111CoveredT182,T183,T300

 LINE       1259
 EXPRESSION (addr_hit[6] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT6,T42,T74
101CoveredT86,T486,T685
110CoveredT486,T427,T552
111CoveredT182,T183,T300

 LINE       1262
 EXPRESSION (addr_hit[7] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT6,T42,T74
101CoveredT486,T685,T427
110CoveredT86,T486,T685
111CoveredT182,T183,T300

 LINE       1265
 EXPRESSION (addr_hit[8] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT6,T42,T74
101CoveredT86,T484,T486
110CoveredT86,T123,T484
111CoveredT182,T183,T300

 LINE       1268
 EXPRESSION (addr_hit[9] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT6,T42,T74
101CoveredT86,T486,T685
110CoveredT123,T486,T685
111CoveredT182,T183,T300

 LINE       1271
 EXPRESSION (addr_hit[10] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT6,T42,T74
101CoveredT123,T484,T685
110CoveredT86,T486,T427
111CoveredT182,T183,T300

 LINE       1274
 EXPRESSION (addr_hit[11] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT6,T42,T74
101CoveredT182,T183,T300
110CoveredT86,T486,T685
111CoveredT486,T685,T427

 LINE       1277
 EXPRESSION (addr_hit[12] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT6,T42,T74
101CoveredT182,T183,T300
110CoveredT486,T685,T427
111CoveredT86,T484,T427

 LINE       1280
 EXPRESSION (addr_hit[13] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT6,T42,T74
101CoveredT86,T486,T685
110CoveredT685,T544,T451
111CoveredT182,T183,T300

 LINE       1283
 EXPRESSION (addr_hit[14] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT6,T42,T74
101CoveredT86,T484,T486
110CoveredT124,T486,T685
111CoveredT182,T183,T300

 LINE       1286
 EXPRESSION (addr_hit[15] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT6,T42,T74
101CoveredT86,T486,T685
110CoveredT86,T486,T685
111CoveredT182,T183,T300

 LINE       1289
 EXPRESSION (addr_hit[16] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT6,T42,T74
101CoveredT86,T486,T685
110CoveredT486,T685,T427
111CoveredT182,T183,T300

 LINE       1292
 EXPRESSION (addr_hit[17] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT6,T42,T74
101CoveredT86,T486,T685
110CoveredT123,T685,T427
111CoveredT182,T183,T300

 LINE       1295
 EXPRESSION (addr_hit[18] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT6,T42,T74
101CoveredT486,T685,T427
110CoveredT486,T685,T426
111CoveredT182,T183,T300

 LINE       1298
 EXPRESSION (addr_hit[19] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT255,T107,T99
101CoveredT42,T74,T255
110CoveredT685,T427,T451
111CoveredT6,T42,T74

 LINE       1303
 EXPRESSION (addr_hit[20] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT6,T42,T74
101CoveredT42,T74,T255
110CoveredT124,T685,T426
111CoveredT255,T107,T99

 LINE       1308
 EXPRESSION (addr_hit[21] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT6,T42,T74
101CoveredT247,T275,T276
110CoveredT685,T447,T552
111CoveredT486,T548,T426

 LINE       1317
 EXPRESSION (addr_hit[22] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT4,T5,T6
101CoveredT123,T486,T685
110CoveredT686
111CoveredT4,T5,T6

 LINE       1318
 EXPRESSION (addr_hit[23] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT4,T5,T6
101CoveredT86,T123,T486
110CoveredT687,T688,T689
111CoveredT4,T5,T6

 LINE       1319
 EXPRESSION (addr_hit[24] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT4,T5,T6
101CoveredT122,T486,T685
110CoveredT690
111CoveredT4,T5,T43

Branch Coverage for Module : rv_core_ibex_cfg_reg_top
Line No.TotalCoveredPercent
Branches 35 35 100.00
TERNARY 1202 2 2 100.00
IF 73 3 3 100.00
TERNARY 130 2 2 100.00
IF 136 2 2 100.00
CASE 1354 26 26 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_rv_core_ibex_0.1/rtl/rv_core_ibex_cfg_reg_top.sv' or '../src/lowrisc_ip_rv_core_ibex_0.1/rtl/rv_core_ibex_cfg_reg_top.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 1202 ((reg_re || reg_we)) ?

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T4,T5,T6


LineNo. Expression -1-: 73 if ((!rst_ni)) -2-: 75 if ((intg_err || reg_we_err))

Branches:
-1--2-StatusTests
1 - Covered T4,T5,T6
0 1 Covered T245,T246,T247
0 0 Covered T4,T5,T6


LineNo. Expression -1-: 130 ((tl_i.a_address[(AW - 1):0] inside {[128:159]})) ?

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T4,T5,T6


LineNo. Expression -1-: 136 if (intg_err)

Branches:
-1-StatusTests
1 Covered T85,T249,T683
0 Covered T4,T5,T6


LineNo. Expression -1-: 1354 case (1'b1)

Branches:
-1-StatusTests
addr_hit[0] Covered T4,T5,T6
addr_hit[1] Covered T85,T484,T486
addr_hit[2] Covered T684,T85,T89
addr_hit[3] Covered T182,T183,T300
addr_hit[4] Covered T182,T183,T300
addr_hit[5] Covered T182,T183,T300
addr_hit[6] Covered T182,T183,T300
addr_hit[7] Covered T182,T183,T300
addr_hit[8] Covered T182,T183,T300
addr_hit[9] Covered T182,T183,T300
addr_hit[10] Covered T182,T183,T300
addr_hit[11] Covered T182,T183,T300
addr_hit[12] Covered T182,T183,T300
addr_hit[13] Covered T182,T183,T300
addr_hit[14] Covered T182,T183,T300
addr_hit[15] Covered T182,T183,T300
addr_hit[16] Covered T182,T183,T300
addr_hit[17] Covered T182,T183,T300
addr_hit[18] Covered T182,T183,T300
addr_hit[19] Covered T6,T42,T74
addr_hit[20] Covered T42,T74,T255
addr_hit[21] Covered T247,T275,T276
addr_hit[22] Covered T4,T5,T6
addr_hit[23] Covered T4,T5,T6
addr_hit[24] Covered T4,T5,T43
default Covered T4,T5,T6


Assert Coverage for Module : rv_core_ibex_cfg_reg_top
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
en2addrHit 597230803 41996 0 0
reAfterRv 597230803 41996 0 0
rePulse 597230803 37038 0 0
wePulse 597230803 4958 0 0


en2addrHit
NameAttemptsReal SuccessesFailuresIncomplete
Total 597230803 41996 0 0
T4 211772 6 0 0
T5 69794 3 0 0
T6 943665 29 0 0
T17 157242 3 0 0
T18 0 4 0 0
T42 242020 56 0 0
T43 145379 102 0 0
T70 152386 3 0 0
T71 133404 6 0 0
T95 124823 1 0 0
T96 42230 0 0 0

reAfterRv
NameAttemptsReal SuccessesFailuresIncomplete
Total 597230803 41996 0 0
T4 211772 6 0 0
T5 69794 3 0 0
T6 943665 29 0 0
T17 157242 3 0 0
T18 0 4 0 0
T42 242020 56 0 0
T43 145379 102 0 0
T70 152386 3 0 0
T71 133404 6 0 0
T95 124823 1 0 0
T96 42230 0 0 0

rePulse
NameAttemptsReal SuccessesFailuresIncomplete
Total 597230803 37038 0 0
T4 211772 6 0 0
T5 69794 3 0 0
T6 943665 28 0 0
T17 157242 3 0 0
T18 0 4 0 0
T42 242020 54 0 0
T43 145379 102 0 0
T70 152386 3 0 0
T71 133404 6 0 0
T95 124823 1 0 0
T96 42230 0 0 0

wePulse
NameAttemptsReal SuccessesFailuresIncomplete
Total 597230803 4958 0 0
T6 943665 1 0 0
T17 157242 0 0 0
T18 244257 0 0 0
T42 242020 2 0 0
T43 145379 0 0 0
T56 0 1 0 0
T57 0 1 0 0
T70 152386 0 0 0
T71 133404 0 0 0
T72 0 2 0 0
T74 0 2 0 0
T95 124823 0 0 0
T96 42230 0 0 0
T107 0 8 0 0
T108 0 1 0 0
T176 0 2 0 0
T215 295235 0 0 0
T255 0 8 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%