Module Definition
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Module : prim_esc_receiver
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_esc_0/rtl/prim_esc_receiver.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.top_earlgrey.u_rv_core_ibex.u_prim_esc_receiver 100.00 100.00



Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_prim_esc_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
90.27 94.12 89.29 99.75 100.00 68.18 u_rv_core_ibex


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Toggle Coverage for Module : prim_esc_receiver
TotalCoveredPercent
Totals 7 7 100.00
Total Bits 14 14 100.00
Total Bits 0->1 7 7 100.00
Total Bits 1->0 7 7 100.00

Ports 7 7 100.00
Port Bits 14 14 100.00
Port Bits 0->1 7 7 100.00
Port Bits 1->0 7 7 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
rst_ni Yes Yes T4,T42,T71 Yes T4,T5,T6 INPUT
esc_req_o Yes Yes T4,T17,T42 Yes T4,T17,T42 OUTPUT
esc_rx_o.resp_n Yes Yes T4,T17,T42 Yes T4,T17,T42 OUTPUT
esc_rx_o.resp_p Yes Yes T4,T17,T42 Yes T4,T17,T42 OUTPUT
esc_tx_i.esc_n Yes Yes T4,T17,T42 Yes T4,T17,T42 INPUT
esc_tx_i.esc_p Yes Yes T4,T17,T42 Yes T4,T17,T42 INPUT

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_prim_esc_receiver
TotalCoveredPercent
Totals 7 7 100.00
Total Bits 14 14 100.00
Total Bits 0->1 7 7 100.00
Total Bits 1->0 7 7 100.00

Ports 7 7 100.00
Port Bits 14 14 100.00
Port Bits 0->1 7 7 100.00
Port Bits 1->0 7 7 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
rst_ni Yes Yes T4,T42,T71 Yes T4,T5,T6 INPUT
esc_req_o Yes Yes T4,T17,T42 Yes T4,T17,T42 OUTPUT
esc_rx_o.resp_n Yes Yes T4,T17,T42 Yes T4,T17,T42 OUTPUT
esc_rx_o.resp_p Yes Yes T4,T17,T42 Yes T4,T17,T42 OUTPUT
esc_tx_i.esc_n Yes Yes T4,T17,T42 Yes T4,T17,T42 INPUT
esc_tx_i.esc_p Yes Yes T4,T17,T42 Yes T4,T17,T42 INPUT

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