SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
tb.dut.top_earlgrey.u_rv_core_ibex.u_prim_sync_reqack_data | 100.00 | 100.00 | 100.00 | ||||
tb.dut.top_earlgrey.u_rv_core_ibex.u_edn_if.u_prim_sync_reqack_data | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
91.67 | 100.00 | 66.67 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
90.27 | 94.12 | 89.29 | 99.75 | 100.00 | 68.18 | u_rv_core_ibex |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
u_prim_sync_reqack | 91.67 | 100.00 | 66.67 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
91.67 | 100.00 | 66.67 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
96.15 | 100.00 | 84.62 | 100.00 | 100.00 | u_edn_if |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
u_prim_sync_reqack | 91.67 | 100.00 | 66.67 | 100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 1 | 1 | 100.00 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 153 | 0 | 0 | |
CONT_ASSIGN | 156 | 0 | 0 | |
ALWAYS | 159 | 0 | 0 |
Line No. | Covered | Statements | |
---|---|---|---|
93 | 1 | 1 | |
153 | unreachable | ||
156 | unreachable | ||
159 | unreachable | ||
160 | unreachable | ||
162 | unreachable |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 2 | 2 | 100.00 | 2 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 2 | 2 | 100.00 | 2 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcA | 1066696592 | 4371 | 0 | 0 |
gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcB | 1066696592 | 4371 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1066696592 | 4371 | 0 | 0 |
T4 | 211772 | 4 | 0 | 0 |
T5 | 69794 | 2 | 0 | 0 |
T6 | 943665 | 15 | 0 | 0 |
T17 | 157242 | 2 | 0 | 0 |
T18 | 0 | 4 | 0 | 0 |
T42 | 242020 | 4 | 0 | 0 |
T43 | 145379 | 102 | 0 | 0 |
T70 | 152386 | 2 | 0 | 0 |
T71 | 133404 | 4 | 0 | 0 |
T95 | 124823 | 1 | 0 | 0 |
T96 | 42230 | 0 | 0 | 0 |
T116 | 83122 | 0 | 0 | 0 |
T119 | 368899 | 0 | 0 | 0 |
T180 | 66429 | 3 | 0 | 0 |
T182 | 0 | 8 | 0 | 0 |
T183 | 0 | 8 | 0 | 0 |
T186 | 153579 | 0 | 0 | 0 |
T192 | 199268 | 0 | 0 | 0 |
T297 | 71922 | 0 | 0 | 0 |
T298 | 364251 | 0 | 0 | 0 |
T299 | 75256 | 0 | 0 | 0 |
T300 | 0 | 8 | 0 | 0 |
T301 | 0 | 12 | 0 | 0 |
T302 | 0 | 8 | 0 | 0 |
T303 | 107439 | 0 | 0 | 0 |
T304 | 132821 | 0 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1066696592 | 4371 | 0 | 0 |
T4 | 211772 | 4 | 0 | 0 |
T5 | 69794 | 2 | 0 | 0 |
T6 | 943665 | 15 | 0 | 0 |
T17 | 157242 | 2 | 0 | 0 |
T18 | 0 | 4 | 0 | 0 |
T42 | 242020 | 4 | 0 | 0 |
T43 | 145379 | 102 | 0 | 0 |
T70 | 152386 | 2 | 0 | 0 |
T71 | 133404 | 4 | 0 | 0 |
T95 | 124823 | 1 | 0 | 0 |
T96 | 42230 | 0 | 0 | 0 |
T116 | 83122 | 0 | 0 | 0 |
T119 | 368899 | 0 | 0 | 0 |
T180 | 66429 | 3 | 0 | 0 |
T182 | 0 | 8 | 0 | 0 |
T183 | 0 | 8 | 0 | 0 |
T186 | 153579 | 0 | 0 | 0 |
T192 | 199268 | 0 | 0 | 0 |
T297 | 71922 | 0 | 0 | 0 |
T298 | 364251 | 0 | 0 | 0 |
T299 | 75256 | 0 | 0 | 0 |
T300 | 0 | 8 | 0 | 0 |
T301 | 0 | 12 | 0 | 0 |
T302 | 0 | 8 | 0 | 0 |
T303 | 107439 | 0 | 0 | 0 |
T304 | 132821 | 0 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 1 | 1 | 100.00 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 153 | 0 | 0 | |
CONT_ASSIGN | 156 | 0 | 0 | |
ALWAYS | 159 | 0 | 0 |
Line No. | Covered | Statements | |
---|---|---|---|
93 | 1 | 1 | |
153 | unreachable | ||
156 | unreachable | ||
159 | unreachable | ||
160 | unreachable | ||
162 | unreachable |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 2 | 2 | 100.00 | 2 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 2 | 2 | 100.00 | 2 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcA | 533348296 | 47 | 0 | 0 |
gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcB | 533348296 | 47 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 533348296 | 47 | 0 | 0 |
T116 | 83122 | 0 | 0 | 0 |
T119 | 368899 | 0 | 0 | 0 |
T180 | 66429 | 3 | 0 | 0 |
T182 | 0 | 8 | 0 | 0 |
T183 | 0 | 8 | 0 | 0 |
T186 | 153579 | 0 | 0 | 0 |
T192 | 199268 | 0 | 0 | 0 |
T297 | 71922 | 0 | 0 | 0 |
T298 | 364251 | 0 | 0 | 0 |
T299 | 75256 | 0 | 0 | 0 |
T300 | 0 | 8 | 0 | 0 |
T301 | 0 | 12 | 0 | 0 |
T302 | 0 | 8 | 0 | 0 |
T303 | 107439 | 0 | 0 | 0 |
T304 | 132821 | 0 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 533348296 | 47 | 0 | 0 |
T116 | 83122 | 0 | 0 | 0 |
T119 | 368899 | 0 | 0 | 0 |
T180 | 66429 | 3 | 0 | 0 |
T182 | 0 | 8 | 0 | 0 |
T183 | 0 | 8 | 0 | 0 |
T186 | 153579 | 0 | 0 | 0 |
T192 | 199268 | 0 | 0 | 0 |
T297 | 71922 | 0 | 0 | 0 |
T298 | 364251 | 0 | 0 | 0 |
T299 | 75256 | 0 | 0 | 0 |
T300 | 0 | 8 | 0 | 0 |
T301 | 0 | 12 | 0 | 0 |
T302 | 0 | 8 | 0 | 0 |
T303 | 107439 | 0 | 0 | 0 |
T304 | 132821 | 0 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 1 | 1 | 100.00 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 153 | 0 | 0 | |
CONT_ASSIGN | 156 | 0 | 0 | |
ALWAYS | 159 | 0 | 0 |
Line No. | Covered | Statements | |
---|---|---|---|
93 | 1 | 1 | |
153 | unreachable | ||
156 | unreachable | ||
159 | unreachable | ||
160 | unreachable | ||
162 | unreachable |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 2 | 2 | 100.00 | 2 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 2 | 2 | 100.00 | 2 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcA | 533348296 | 4324 | 0 | 0 |
gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcB | 533348296 | 4324 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 533348296 | 4324 | 0 | 0 |
T4 | 211772 | 4 | 0 | 0 |
T5 | 69794 | 2 | 0 | 0 |
T6 | 943665 | 15 | 0 | 0 |
T17 | 157242 | 2 | 0 | 0 |
T18 | 0 | 4 | 0 | 0 |
T42 | 242020 | 4 | 0 | 0 |
T43 | 145379 | 102 | 0 | 0 |
T70 | 152386 | 2 | 0 | 0 |
T71 | 133404 | 4 | 0 | 0 |
T95 | 124823 | 1 | 0 | 0 |
T96 | 42230 | 0 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 533348296 | 4324 | 0 | 0 |
T4 | 211772 | 4 | 0 | 0 |
T5 | 69794 | 2 | 0 | 0 |
T6 | 943665 | 15 | 0 | 0 |
T17 | 157242 | 2 | 0 | 0 |
T18 | 0 | 4 | 0 | 0 |
T42 | 242020 | 4 | 0 | 0 |
T43 | 145379 | 102 | 0 | 0 |
T70 | 152386 | 2 | 0 | 0 |
T71 | 133404 | 4 | 0 | 0 |
T95 | 124823 | 1 | 0 | 0 |
T96 | 42230 | 0 | 0 | 0 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |