Module Definition
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Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_prim_sync_reqack_data

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
91.67 100.00 66.67 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
90.27 94.12 89.29 99.75 100.00 68.18 u_rv_core_ibex


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_prim_sync_reqack 91.67 100.00 66.67 100.00 100.00



Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_edn_if.u_prim_sync_reqack_data

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
91.67 100.00 66.67 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.15 100.00 84.62 100.00 100.00 u_edn_if


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_prim_sync_reqack 91.67 100.00 66.67 100.00 100.00

Line Coverage for Module : prim_sync_reqack_data
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN9311100.00
CONT_ASSIGN15300
CONT_ASSIGN15600
ALWAYS15900
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack_data.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack_data.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
93 1 1
153 unreachable
156 unreachable
159 unreachable
160 unreachable
162 unreachable


Assert Coverage for Module : prim_sync_reqack_data
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcA 1066696592 4371 0 0
gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcB 1066696592 4371 0 0


gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcA
NameAttemptsReal SuccessesFailuresIncomplete
Total 1066696592 4371 0 0
T4 211772 4 0 0
T5 69794 2 0 0
T6 943665 15 0 0
T17 157242 2 0 0
T18 0 4 0 0
T42 242020 4 0 0
T43 145379 102 0 0
T70 152386 2 0 0
T71 133404 4 0 0
T95 124823 1 0 0
T96 42230 0 0 0
T116 83122 0 0 0
T119 368899 0 0 0
T180 66429 3 0 0
T182 0 8 0 0
T183 0 8 0 0
T186 153579 0 0 0
T192 199268 0 0 0
T297 71922 0 0 0
T298 364251 0 0 0
T299 75256 0 0 0
T300 0 8 0 0
T301 0 12 0 0
T302 0 8 0 0
T303 107439 0 0 0
T304 132821 0 0 0

gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcB
NameAttemptsReal SuccessesFailuresIncomplete
Total 1066696592 4371 0 0
T4 211772 4 0 0
T5 69794 2 0 0
T6 943665 15 0 0
T17 157242 2 0 0
T18 0 4 0 0
T42 242020 4 0 0
T43 145379 102 0 0
T70 152386 2 0 0
T71 133404 4 0 0
T95 124823 1 0 0
T96 42230 0 0 0
T116 83122 0 0 0
T119 368899 0 0 0
T180 66429 3 0 0
T182 0 8 0 0
T183 0 8 0 0
T186 153579 0 0 0
T192 199268 0 0 0
T297 71922 0 0 0
T298 364251 0 0 0
T299 75256 0 0 0
T300 0 8 0 0
T301 0 12 0 0
T302 0 8 0 0
T303 107439 0 0 0
T304 132821 0 0 0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_prim_sync_reqack_data
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN9311100.00
CONT_ASSIGN15300
CONT_ASSIGN15600
ALWAYS15900
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack_data.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack_data.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
93 1 1
153 unreachable
156 unreachable
159 unreachable
160 unreachable
162 unreachable


Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_prim_sync_reqack_data
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcA 533348296 47 0 0
gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcB 533348296 47 0 0


gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcA
NameAttemptsReal SuccessesFailuresIncomplete
Total 533348296 47 0 0
T116 83122 0 0 0
T119 368899 0 0 0
T180 66429 3 0 0
T182 0 8 0 0
T183 0 8 0 0
T186 153579 0 0 0
T192 199268 0 0 0
T297 71922 0 0 0
T298 364251 0 0 0
T299 75256 0 0 0
T300 0 8 0 0
T301 0 12 0 0
T302 0 8 0 0
T303 107439 0 0 0
T304 132821 0 0 0

gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcB
NameAttemptsReal SuccessesFailuresIncomplete
Total 533348296 47 0 0
T116 83122 0 0 0
T119 368899 0 0 0
T180 66429 3 0 0
T182 0 8 0 0
T183 0 8 0 0
T186 153579 0 0 0
T192 199268 0 0 0
T297 71922 0 0 0
T298 364251 0 0 0
T299 75256 0 0 0
T300 0 8 0 0
T301 0 12 0 0
T302 0 8 0 0
T303 107439 0 0 0
T304 132821 0 0 0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_edn_if.u_prim_sync_reqack_data
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN9311100.00
CONT_ASSIGN15300
CONT_ASSIGN15600
ALWAYS15900
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack_data.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack_data.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
93 1 1
153 unreachable
156 unreachable
159 unreachable
160 unreachable
162 unreachable


Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_edn_if.u_prim_sync_reqack_data
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcA 533348296 4324 0 0
gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcB 533348296 4324 0 0


gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcA
NameAttemptsReal SuccessesFailuresIncomplete
Total 533348296 4324 0 0
T4 211772 4 0 0
T5 69794 2 0 0
T6 943665 15 0 0
T17 157242 2 0 0
T18 0 4 0 0
T42 242020 4 0 0
T43 145379 102 0 0
T70 152386 2 0 0
T71 133404 4 0 0
T95 124823 1 0 0
T96 42230 0 0 0

gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcB
NameAttemptsReal SuccessesFailuresIncomplete
Total 533348296 4324 0 0
T4 211772 4 0 0
T5 69794 2 0 0
T6 943665 15 0 0
T17 157242 2 0 0
T18 0 4 0 0
T42 242020 4 0 0
T43 145379 102 0 0
T70 152386 2 0 0
T71 133404 4 0 0
T95 124823 1 0 0
T96 42230 0 0 0

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