Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

4 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1865149	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

36461373

1

T4

4315

T5

48247

T6

12438

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	26701238	1			T4	1312		T5	34315		T6	4827
values[0x0]	10244833	1			T4	3003		T5	13932		T6	7611
values[0x1]	1380451	1			T4	112		T5	348		T6	796

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	613608	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

37712914

1

T4

4427

T5

48595

T6

13234

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	18003989	1			T4	2214		T5	24298		T6	6618
valid_sources[0x01]	18002126	1			T4	2213		T5	24297		T6	6616
valid_sources[0x02]	38123	1			T146	422		T147	228		T132	101
valid_sources[0x03]	37235	1			T146	422		T147	205		T132	85
valid_sources[0x04]	38432	1			T62	5		T8	1		T9	1
valid_sources[0x05]	36328	1			T71	2		T62	3		T894	2
valid_sources[0x06]	37646	1			T256	1		T9	1		T894	5
valid_sources[0x07]	36608	1			T71	1		T146	393		T147	141
valid_sources[0x08]	37312	1			T8	2		T9	1		T146	405
valid_sources[0x09]	36929	1			T71	2		T256	6		T894	1
valid_sources[0x0a]	37127	1			T146	417		T147	142		T132	70
valid_sources[0x0b]	37363	1			T62	4		T8	1		T146	436
valid_sources[0x0c]	37366	1			T8	2		T256	1		T146	393
valid_sources[0x0d]	38031	1			T62	2		T8	1		T256	1
valid_sources[0x0e]	37441	1			T9	2		T146	413		T147	174
valid_sources[0x0f]	37795	1			T146	422		T147	187		T132	73
valid_sources[0x10]	36340	1			T71	1		T8	1		T146	386
valid_sources[0x11]	38283	1			T146	447		T147	135		T132	65
valid_sources[0x12]	37857	1			T8	2		T146	422		T147	215
valid_sources[0x13]	36721	1			T62	1		T9	2		T146	377
valid_sources[0x14]	37296	1			T894	1		T146	406		T147	138
valid_sources[0x15]	37076	1			T71	1		T8	1		T146	415
valid_sources[0x16]	36852	1			T71	5		T8	2		T894	5
valid_sources[0x17]	40761	1			T9	1		T146	377		T147	247
valid_sources[0x18]	37102	1			T8	2		T9	1		T146	429
valid_sources[0x19]	39284	1			T8	3		T256	1		T146	411
valid_sources[0x1a]	37133	1			T146	418		T147	144		T132	111
valid_sources[0x1b]	37562	1			T256	2		T146	412		T147	132
valid_sources[0x1c]	37165	1			T8	2		T894	2		T146	372
valid_sources[0x1d]	36357	1			T146	430		T147	122		T132	96
valid_sources[0x1e]	37363	1			T71	2		T8	3		T256	1
valid_sources[0x1f]	39086	1			T9	1		T146	417		T147	224
valid_sources[0x20]	37777	1			T62	3		T9	1		T894	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

26009328

1

T4

1312

T5

34315

T6

4827

values[0x0]

all_enables

biggest_size

10201992

1

T4

3003

T5

13932

T6

7611

values[0x1]

all_enables

biggest_size

250053

1

T71

21

T62

24

T8

20

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2806087	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

442295

1

T75

17

T76

211

T77

28

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1101204	1			T75	36		T76	542		T77	61
values[0x0]	1046086	1			T75	43		T76	476		T77	49
values[0x1]	1101092	1			T75	40		T76	529		T77	57

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2172355	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1076027

1

T75

39

T76

486

T77

59

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	50255	1			T75	15		T76	17		T77	1
valid_sources[0x01]	49478	1			T75	1		T76	24		T77	2
valid_sources[0x02]	50425	1			T75	16		T77	3		T78	5
valid_sources[0x03]	51600	1			T75	2		T76	21		T77	4
valid_sources[0x04]	51140	1			T75	6		T76	27		T255	31
valid_sources[0x05]	50486	1			T75	1		T76	15		T77	6
valid_sources[0x06]	50138	1			T75	1		T76	9		T255	30
valid_sources[0x07]	51766	1			T76	46		T77	5		T78	2
valid_sources[0x08]	50890	1			T75	4		T76	12		T77	3
valid_sources[0x09]	50662	1			T75	4		T76	28		T77	4
valid_sources[0x0a]	50310	1			T76	10		T78	1		T255	29
valid_sources[0x0b]	50775	1			T75	6		T76	26		T77	1
valid_sources[0x0c]	50887	1			T76	9		T77	4		T78	1
valid_sources[0x0d]	50612	1			T76	20		T77	2		T255	26
valid_sources[0x0e]	50980	1			T76	16		T255	33		T323	6
valid_sources[0x0f]	50210	1			T76	43		T77	5		T78	1
valid_sources[0x10]	51045	1			T76	35		T77	3		T78	4
valid_sources[0x11]	50676	1			T76	49		T77	3		T255	34
valid_sources[0x12]	49962	1			T76	9		T77	2		T255	34
valid_sources[0x13]	50909	1			T75	7		T76	48		T77	10
valid_sources[0x14]	51435	1			T76	5		T78	4		T255	39
valid_sources[0x15]	50862	1			T75	2		T76	14		T77	2
valid_sources[0x16]	51233	1			T76	42		T77	1		T78	1
valid_sources[0x17]	51334	1			T76	36		T77	3		T78	3
valid_sources[0x18]	49809	1			T75	1		T76	9		T77	3
valid_sources[0x19]	51048	1			T76	11		T77	2		T255	42
valid_sources[0x1a]	49746	1			T75	10		T76	23		T77	3
valid_sources[0x1b]	50061	1			T76	18		T78	3		T255	37
valid_sources[0x1c]	51268	1			T77	5		T78	1		T255	36
valid_sources[0x1d]	50334	1			T76	25		T77	1		T255	33
valid_sources[0x1e]	51711	1			T75	10		T76	38		T77	4
valid_sources[0x1f]	50677	1			T76	5		T77	1		T78	1
valid_sources[0x20]	50724	1			T76	27		T77	4		T255	44

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

46749

1

T75

1

T76

26

T77

3

values[0x0]

all_enables

biggest_size

348655

1

T75

14

T76

164

T77

21

values[0x1]

all_enables

biggest_size

46891

1

T75

2

T76

21

T77

4

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2978526	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

485125

1

T75

25

T76

205

T77

22

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1187421	1			T75	39		T76	524		T77	45
values[0x0]	1090405	1			T75	53		T76	469		T77	48
values[0x1]	1185825	1			T75	68		T76	458		T77	39

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2286133	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1177518

1

T75

57

T76

483

T77

45

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	54747	1			T75	1		T76	21		T77	7
valid_sources[0x01]	53859	1			T75	5		T76	23		T77	3
valid_sources[0x02]	54891	1			T75	4		T76	29		T78	3
valid_sources[0x03]	54739	1			T75	1		T76	17		T77	2
valid_sources[0x04]	53592	1			T75	1		T76	25		T77	2
valid_sources[0x05]	54595	1			T75	6		T76	20		T77	2
valid_sources[0x06]	53618	1			T75	1		T76	29		T77	1
valid_sources[0x07]	54008	1			T75	2		T76	23		T78	2
valid_sources[0x08]	53835	1			T75	2		T76	16		T77	1
valid_sources[0x09]	54310	1			T75	4		T76	27		T77	5
valid_sources[0x0a]	53419	1			T75	5		T76	23		T77	2
valid_sources[0x0b]	54756	1			T76	19		T77	4		T255	31
valid_sources[0x0c]	55347	1			T75	6		T76	29		T77	2
valid_sources[0x0d]	54398	1			T76	28		T77	3		T78	1
valid_sources[0x0e]	54065	1			T76	27		T255	29		T127	33
valid_sources[0x0f]	53640	1			T75	4		T76	24		T77	1
valid_sources[0x10]	54388	1			T75	5		T76	17		T77	2
valid_sources[0x11]	54245	1			T75	5		T76	23		T77	2
valid_sources[0x12]	54289	1			T75	6		T76	27		T255	35
valid_sources[0x13]	53614	1			T75	3		T76	22		T77	1
valid_sources[0x14]	53828	1			T75	6		T76	31		T77	1
valid_sources[0x15]	53749	1			T76	20		T77	1		T255	33
valid_sources[0x16]	54192	1			T75	4		T76	17		T77	1
valid_sources[0x17]	55092	1			T75	2		T76	30		T78	3
valid_sources[0x18]	53956	1			T76	23		T77	5		T255	31
valid_sources[0x19]	53580	1			T75	6		T76	13		T77	3
valid_sources[0x1a]	54074	1			T75	2		T76	18		T77	3
valid_sources[0x1b]	54067	1			T75	3		T76	27		T77	2
valid_sources[0x1c]	53606	1			T75	1		T76	30		T77	3
valid_sources[0x1d]	52607	1			T75	1		T76	19		T77	2
valid_sources[0x1e]	53725	1			T75	1		T76	22		T77	2
valid_sources[0x1f]	55177	1			T75	1		T76	21		T77	2
valid_sources[0x20]	52999	1			T75	1		T76	16		T77	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

51187

1

T75

2

T76

15

T77

4

values[0x0]

all_enables

biggest_size

382769

1

T75

19

T76

169

T77

18

values[0x1]

all_enables

biggest_size

51169

1

T75

4

T76

21

T78

2

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2829707	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

446238

1

T75

23

T76

209

T77

32

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1109527	1			T75	57		T76	601		T77	70
values[0x0]	1054382	1			T75	55		T76	507		T77	72
values[0x1]	1112036	1			T75	59		T76	590		T77	54

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2189580	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1086365

1

T75

61

T76

557

T77

79

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	50304	1			T75	2		T76	6		T77	1
valid_sources[0x01]	51081	1			T75	3		T76	12		T255	34
valid_sources[0x02]	51289	1			T75	2		T76	31		T77	5
valid_sources[0x03]	51946	1			T75	4		T76	34		T77	7
valid_sources[0x04]	51137	1			T76	38		T77	6		T255	41
valid_sources[0x05]	51097	1			T75	2		T76	42		T78	2
valid_sources[0x06]	51508	1			T75	6		T76	46		T77	2
valid_sources[0x07]	51105	1			T75	2		T76	48		T77	2
valid_sources[0x08]	51476	1			T75	1		T76	42		T77	4
valid_sources[0x09]	50799	1			T75	4		T76	26		T77	2
valid_sources[0x0a]	50916	1			T76	16		T77	1		T78	4
valid_sources[0x0b]	51277	1			T75	4		T76	17		T77	4
valid_sources[0x0c]	51388	1			T76	39		T77	1		T78	1
valid_sources[0x0d]	51841	1			T75	3		T76	48		T77	1
valid_sources[0x0e]	50728	1			T75	4		T76	55		T77	3
valid_sources[0x0f]	51691	1			T75	5		T76	11		T77	3
valid_sources[0x10]	52504	1			T76	31		T77	7		T78	4
valid_sources[0x11]	51218	1			T75	5		T76	48		T77	4
valid_sources[0x12]	51436	1			T75	3		T76	35		T77	2
valid_sources[0x13]	50228	1			T75	2		T76	52		T77	2
valid_sources[0x14]	50539	1			T75	3		T76	30		T77	2
valid_sources[0x15]	52048	1			T75	3		T76	3		T77	5
valid_sources[0x16]	50735	1			T75	1		T76	10		T77	5
valid_sources[0x17]	51598	1			T75	7		T76	13		T77	6
valid_sources[0x18]	51086	1			T75	4		T76	7		T77	1
valid_sources[0x19]	51009	1			T75	4		T76	66		T77	3
valid_sources[0x1a]	50068	1			T75	5		T76	38		T77	1
valid_sources[0x1b]	51104	1			T75	1		T76	2		T77	3
valid_sources[0x1c]	51246	1			T75	1		T76	13		T77	2
valid_sources[0x1d]	50774	1			T75	1		T76	1		T77	1
valid_sources[0x1e]	51670	1			T75	4		T76	75		T77	2
valid_sources[0x1f]	52833	1			T75	1		T76	13		T77	5
valid_sources[0x20]	49961	1			T75	2		T76	28		T78	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

47073

1

T75

1

T76

28

T77

4

values[0x0]

all_enables

biggest_size

352141

1

T75

21

T76

162

T77

27

values[0x1]

all_enables

biggest_size

47024

1

T75

1

T76

19

T77

1