Unified Coverage Report :: Module Instance :: tb.dut.top_earlgrey.u_uart0.uart_core.u_uart_txfifo

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	510746154	59189279	0	0
DepthKnown_A	510746154	510640070	0	0
RvalidKnown_A	510746154	510640070	0	0
WreadyKnown_A	510746154	510640070	0	0
gen_passthru_fifo.paramCheckPass	1013	1013	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	510746154	59189279	0	0
T4	383029	8975	0	0
T5	598914	38822	0	0
T6	219237	28850	0	0
T17	263407	34589	0	0
T18	225429	23038	0	0
T27	619930	56399	0	0
T28	101375	10657	0	0
T33	174649	115630	0	0
T85	257998	369918	0	0
T86	150091	54537	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	510746154	510640070	0	0
T4	383029	382978	0	0
T5	598914	598859	0	0
T6	219237	219135	0	0
T17	263407	263283	0	0
T18	225429	225371	0	0
T27	619930	619875	0	0
T28	101375	101320	0	0
T33	174649	174638	0	0
T85	257998	257991	0	0
T86	150091	150085	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	510746154	510640070	0	0
T4	383029	382978	0	0
T5	598914	598859	0	0
T6	219237	219135	0	0
T17	263407	263283	0	0
T18	225429	225371	0	0
T27	619930	619875	0	0
T28	101375	101320	0	0
T33	174649	174638	0	0
T85	257998	257991	0	0
T86	150091	150085	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	510746154	510640070	0	0
T4	383029	382978	0	0
T5	598914	598859	0	0
T6	219237	219135	0	0
T17	263407	263283	0	0
T18	225429	225371	0	0
T27	619930	619875	0	0
T28	101375	101320	0	0
T33	174649	174638	0	0
T85	257998	257991	0	0
T86	150091	150085	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1013	1013	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T27	1	1	0	0
T28	1	1	0	0
T33	1	1	0	0
T85	1	1	0	0
T86	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	2	50.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	0	0.00
CONT_ASSIGN	49	1	0	0.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	0	1
49	0	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	510746154	45399898	0	0
DepthKnown_A	510746154	510640070	0	0
RvalidKnown_A	510746154	510640070	0	0
WreadyKnown_A	510746154	510640070	0	0
gen_passthru_fifo.paramCheckPass	1013	1013	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	510746154	45399898	0	0
T4	383029	6126	0	0
T5	598914	36114	0	0
T6	219237	19257	0	0
T17	263407	24922	0	0
T18	225429	19115	0	0
T27	619930	52482	0	0
T28	101375	8751	0	0
T33	174649	110708	0	0
T85	257998	336866	0	0
T86	150091	50516	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	510746154	510640070	0	0
T4	383029	382978	0	0
T5	598914	598859	0	0
T6	219237	219135	0	0
T17	263407	263283	0	0
T18	225429	225371	0	0
T27	619930	619875	0	0
T28	101375	101320	0	0
T33	174649	174638	0	0
T85	257998	257991	0	0
T86	150091	150085	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	510746154	510640070	0	0
T4	383029	382978	0	0
T5	598914	598859	0	0
T6	219237	219135	0	0
T17	263407	263283	0	0
T18	225429	225371	0	0
T27	619930	619875	0	0
T28	101375	101320	0	0
T33	174649	174638	0	0
T85	257998	257991	0	0
T86	150091	150085	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	510746154	510640070	0	0
T4	383029	382978	0	0
T5	598914	598859	0	0
T6	219237	219135	0	0
T17	263407	263283	0	0
T18	225429	225371	0	0
T27	619930	619875	0	0
T28	101375	101320	0	0
T33	174649	174638	0	0
T85	257998	257991	0	0
T86	150091	150085	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1013	1013	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T27	1	1	0	0
T28	1	1	0	0
T33	1	1	0	0
T85	1	1	0	0
T86	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	510746154	42508245	0	0
DepthKnown_A	510746154	510640070	0	0
RvalidKnown_A	510746154	510640070	0	0
WreadyKnown_A	510746154	510640070	0	0
gen_passthru_fifo.paramCheckPass	1013	1013	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	510746154	42508245	0	0
T4	383029	4600	0	0
T5	598914	48737	0	0
T6	219237	13614	0	0
T17	263407	17703	0	0
T18	225429	21408	0	0
T27	619930	66460	0	0
T28	101375	7499	0	0
T33	174649	107446	0	0
T85	257998	613077	0	0
T86	150091	43942	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	510746154	510640070	0	0
T4	383029	382978	0	0
T5	598914	598859	0	0
T6	219237	219135	0	0
T17	263407	263283	0	0
T18	225429	225371	0	0
T27	619930	619875	0	0
T28	101375	101320	0	0
T33	174649	174638	0	0
T85	257998	257991	0	0
T86	150091	150085	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	510746154	510640070	0	0
T4	383029	382978	0	0
T5	598914	598859	0	0
T6	219237	219135	0	0
T17	263407	263283	0	0
T18	225429	225371	0	0
T27	619930	619875	0	0
T28	101375	101320	0	0
T33	174649	174638	0	0
T85	257998	257991	0	0
T86	150091	150085	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	510746154	510640070	0	0
T4	383029	382978	0	0
T5	598914	598859	0	0
T6	219237	219135	0	0
T17	263407	263283	0	0
T18	225429	225371	0	0
T27	619930	619875	0	0
T28	101375	101320	0	0
T33	174649	174638	0	0
T85	257998	257991	0	0
T86	150091	150085	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1013	1013	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T27	1	1	0	0
T28	1	1	0	0
T33	1	1	0	0
T85	1	1	0	0
T86	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	510746154	35995212	0	0
DepthKnown_A	510746154	510640070	0	0
RvalidKnown_A	510746154	510640070	0	0
WreadyKnown_A	510746154	510640070	0	0
gen_passthru_fifo.paramCheckPass	1013	1013	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	510746154	35995212	0	0
T4	383029	4427	0	0
T5	598914	48595	0	0
T6	219237	13234	0	0
T17	263407	17323	0	0
T18	225429	21202	0	0
T27	619930	66256	0	0
T28	101375	7377	0	0
T33	174649	107056	0	0
T85	257998	612363	0	0
T86	150091	43767	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	510746154	510640070	0	0
T4	383029	382978	0	0
T5	598914	598859	0	0
T6	219237	219135	0	0
T17	263407	263283	0	0
T18	225429	225371	0	0
T27	619930	619875	0	0
T28	101375	101320	0	0
T33	174649	174638	0	0
T85	257998	257991	0	0
T86	150091	150085	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	510746154	510640070	0	0
T4	383029	382978	0	0
T5	598914	598859	0	0
T6	219237	219135	0	0
T17	263407	263283	0	0
T18	225429	225371	0	0
T27	619930	619875	0	0
T28	101375	101320	0	0
T33	174649	174638	0	0
T85	257998	257991	0	0
T86	150091	150085	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	510746154	510640070	0	0
T4	383029	382978	0	0
T5	598914	598859	0	0
T6	219237	219135	0	0
T17	263407	263283	0	0
T18	225429	225371	0	0
T27	619930	619875	0	0
T28	101375	101320	0	0
T33	174649	174638	0	0
T85	257998	257991	0	0
T86	150091	150085	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1013	1013	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T27	1	1	0	0
T28	1	1	0	0
T33	1	1	0	0
T85	1	1	0	0
T86	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	592951014	78260	0	0
DepthKnown_A	592951014	592832449	0	0
RvalidKnown_A	592951014	592832449	0	0
WreadyKnown_A	592951014	592832449	0	0
gen_passthru_fifo.paramCheckPass	2903	2903	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	592951014	78260	0	0
T4	383029	12	0	0
T5	598914	14	0	0
T6	219237	151	0	0
T17	263407	151	0	0
T18	225429	53	0	0
T27	619930	53	0	0
T28	101375	13	0	0
T33	174649	61	0	0
T85	257998	155	0	0
T86	150091	29	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	592951014	592832449	0	0
T4	383029	382978	0	0
T5	598914	598859	0	0
T6	219237	219135	0	0
T17	263407	263283	0	0
T18	225429	225371	0	0
T27	619930	619875	0	0
T28	101375	101320	0	0
T33	174649	174638	0	0
T85	257998	257991	0	0
T86	150091	150085	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	592951014	592832449	0	0
T4	383029	382978	0	0
T5	598914	598859	0	0
T6	219237	219135	0	0
T17	263407	263283	0	0
T18	225429	225371	0	0
T27	619930	619875	0	0
T28	101375	101320	0	0
T33	174649	174638	0	0
T85	257998	257991	0	0
T86	150091	150085	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	592951014	592832449	0	0
T4	383029	382978	0	0
T5	598914	598859	0	0
T6	219237	219135	0	0
T17	263407	263283	0	0
T18	225429	225371	0	0
T27	619930	619875	0	0
T28	101375	101320	0	0
T33	174649	174638	0	0
T85	257998	257991	0	0
T86	150091	150085	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2903	2903	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T27	1	1	0	0
T28	1	1	0	0
T33	1	1	0	0
T85	1	1	0	0
T86	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	592951014	80447	0	0
DepthKnown_A	592951014	592832449	0	0
RvalidKnown_A	592951014	592832449	0	0
WreadyKnown_A	592951014	592832449	0	0
gen_passthru_fifo.paramCheckPass	2903	2903	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	592951014	80447	0	0
T4	383029	12	0	0
T5	598914	14	0	0
T6	219237	151	0	0
T17	263407	151	0	0
T18	225429	53	0	0
T27	619930	53	0	0
T28	101375	13	0	0
T33	174649	61	0	0
T85	257998	155	0	0
T86	150091	29	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	592951014	592832449	0	0
T4	383029	382978	0	0
T5	598914	598859	0	0
T6	219237	219135	0	0
T17	263407	263283	0	0
T18	225429	225371	0	0
T27	619930	619875	0	0
T28	101375	101320	0	0
T33	174649	174638	0	0
T85	257998	257991	0	0
T86	150091	150085	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	592951014	592832449	0	0
T4	383029	382978	0	0
T5	598914	598859	0	0
T6	219237	219135	0	0
T17	263407	263283	0	0
T18	225429	225371	0	0
T27	619930	619875	0	0
T28	101375	101320	0	0
T33	174649	174638	0	0
T85	257998	257991	0	0
T86	150091	150085	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	592951014	592832449	0	0
T4	383029	382978	0	0
T5	598914	598859	0	0
T6	219237	219135	0	0
T17	263407	263283	0	0
T18	225429	225371	0	0
T27	619930	619875	0	0
T28	101375	101320	0	0
T33	174649	174638	0	0
T85	257998	257991	0	0
T86	150091	150085	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2903	2903	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T27	1	1	0	0
T28	1	1	0	0
T33	1	1	0	0
T85	1	1	0	0
T86	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	592951014	51374	0	0
DepthKnown_A	592951014	592832449	0	0
RvalidKnown_A	592951014	592832449	0	0
WreadyKnown_A	592951014	592832449	0	0
gen_passthru_fifo.paramCheckPass	2903	2903	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	592951014	51374	0	0
T4	383029	11	0	0
T5	598914	12	0	0
T6	219237	95	0	0
T17	263407	95	0	0
T18	225429	52	0	0
T27	619930	52	0	0
T28	101375	12	0	0
T33	174649	59	0	0
T85	257998	40	0	0
T86	150091	28	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	592951014	592832449	0	0
T4	383029	382978	0	0
T5	598914	598859	0	0
T6	219237	219135	0	0
T17	263407	263283	0	0
T18	225429	225371	0	0
T27	619930	619875	0	0
T28	101375	101320	0	0
T33	174649	174638	0	0
T85	257998	257991	0	0
T86	150091	150085	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	592951014	592832449	0	0
T4	383029	382978	0	0
T5	598914	598859	0	0
T6	219237	219135	0	0
T17	263407	263283	0	0
T18	225429	225371	0	0
T27	619930	619875	0	0
T28	101375	101320	0	0
T33	174649	174638	0	0
T85	257998	257991	0	0
T86	150091	150085	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	592951014	592832449	0	0
T4	383029	382978	0	0
T5	598914	598859	0	0
T6	219237	219135	0	0
T17	263407	263283	0	0
T18	225429	225371	0	0
T27	619930	619875	0	0
T28	101375	101320	0	0
T33	174649	174638	0	0
T85	257998	257991	0	0
T86	150091	150085	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2903	2903	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T27	1	1	0	0
T28	1	1	0	0
T33	1	1	0	0
T85	1	1	0	0
T86	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	592951014	51374	0	0
DepthKnown_A	592951014	592832449	0	0
RvalidKnown_A	592951014	592832449	0	0
WreadyKnown_A	592951014	592832449	0	0
gen_passthru_fifo.paramCheckPass	2903	2903	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	592951014	51374	0	0
T4	383029	11	0	0
T5	598914	12	0	0
T6	219237	95	0	0
T17	263407	95	0	0
T18	225429	52	0	0
T27	619930	52	0	0
T28	101375	12	0	0
T33	174649	59	0	0
T85	257998	40	0	0
T86	150091	28	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	592951014	592832449	0	0
T4	383029	382978	0	0
T5	598914	598859	0	0
T6	219237	219135	0	0
T17	263407	263283	0	0
T18	225429	225371	0	0
T27	619930	619875	0	0
T28	101375	101320	0	0
T33	174649	174638	0	0
T85	257998	257991	0	0
T86	150091	150085	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	592951014	592832449	0	0
T4	383029	382978	0	0
T5	598914	598859	0	0
T6	219237	219135	0	0
T17	263407	263283	0	0
T18	225429	225371	0	0
T27	619930	619875	0	0
T28	101375	101320	0	0
T33	174649	174638	0	0
T85	257998	257991	0	0
T86	150091	150085	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	592951014	592832449	0	0
T4	383029	382978	0	0
T5	598914	598859	0	0
T6	219237	219135	0	0
T17	263407	263283	0	0
T18	225429	225371	0	0
T27	619930	619875	0	0
T28	101375	101320	0	0
T33	174649	174638	0	0
T85	257998	257991	0	0
T86	150091	150085	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2903	2903	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T27	1	1	0	0
T28	1	1	0	0
T33	1	1	0	0
T85	1	1	0	0
T86	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	592951014	26886	0	0
DepthKnown_A	592951014	592832449	0	0
RvalidKnown_A	592951014	592832449	0	0
WreadyKnown_A	592951014	592832449	0	0
gen_passthru_fifo.paramCheckPass	2903	2903	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	592951014	26886	0	0
T4	383029	1	0	0
T5	598914	2	0	0
T6	219237	56	0	0
T17	263407	56	0	0
T18	225429	1	0	0
T27	619930	1	0	0
T28	101375	1	0	0
T33	174649	2	0	0
T85	257998	115	0	0
T86	150091	1	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	592951014	592832449	0	0
T4	383029	382978	0	0
T5	598914	598859	0	0
T6	219237	219135	0	0
T17	263407	263283	0	0
T18	225429	225371	0	0
T27	619930	619875	0	0
T28	101375	101320	0	0
T33	174649	174638	0	0
T85	257998	257991	0	0
T86	150091	150085	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	592951014	592832449	0	0
T4	383029	382978	0	0
T5	598914	598859	0	0
T6	219237	219135	0	0
T17	263407	263283	0	0
T18	225429	225371	0	0
T27	619930	619875	0	0
T28	101375	101320	0	0
T33	174649	174638	0	0
T85	257998	257991	0	0
T86	150091	150085	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	592951014	592832449	0	0
T4	383029	382978	0	0
T5	598914	598859	0	0
T6	219237	219135	0	0
T17	263407	263283	0	0
T18	225429	225371	0	0
T27	619930	619875	0	0
T28	101375	101320	0	0
T33	174649	174638	0	0
T85	257998	257991	0	0
T86	150091	150085	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2903	2903	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T27	1	1	0	0
T28	1	1	0	0
T33	1	1	0	0
T85	1	1	0	0
T86	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	592951014	29073	0	0
DepthKnown_A	592951014	592832449	0	0
RvalidKnown_A	592951014	592832449	0	0
WreadyKnown_A	592951014	592832449	0	0
gen_passthru_fifo.paramCheckPass	2903	2903	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	592951014	29073	0	0
T4	383029	1	0	0
T5	598914	2	0	0
T6	219237	56	0	0
T17	263407	56	0	0
T18	225429	1	0	0
T27	619930	1	0	0
T28	101375	1	0	0
T33	174649	2	0	0
T85	257998	115	0	0
T86	150091	1	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	592951014	592832449	0	0
T4	383029	382978	0	0
T5	598914	598859	0	0
T6	219237	219135	0	0
T17	263407	263283	0	0
T18	225429	225371	0	0
T27	619930	619875	0	0
T28	101375	101320	0	0
T33	174649	174638	0	0
T85	257998	257991	0	0
T86	150091	150085	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	592951014	592832449	0	0
T4	383029	382978	0	0
T5	598914	598859	0	0
T6	219237	219135	0	0
T17	263407	263283	0	0
T18	225429	225371	0	0
T27	619930	619875	0	0
T28	101375	101320	0	0
T33	174649	174638	0	0
T85	257998	257991	0	0
T86	150091	150085	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	592951014	592832449	0	0
T4	383029	382978	0	0
T5	598914	598859	0	0
T6	219237	219135	0	0
T17	263407	263283	0	0
T18	225429	225371	0	0
T27	619930	619875	0	0
T28	101375	101320	0	0
T33	174649	174638	0	0
T85	257998	257991	0	0
T86	150091	150085	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2903	2903	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T27	1	1	0	0
T28	1	1	0	0
T33	1	1	0	0
T85	1	1	0	0
T86	1	1	0	0