Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : sysrst_ctrl
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.top_earlgrey.u_sysrst_ctrl_aon 100.00 100.00



Module Instance : tb.dut.top_earlgrey.u_sysrst_ctrl_aon

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
93.34 90.68 89.34 100.00 top_earlgrey


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Since this is the module's only instance, the coverage report is the same as for the module.
Toggle Coverage for Module : sysrst_ctrl
TotalCoveredPercent
Totals 50 50 100.00
Total Bits 334 334 100.00
Total Bits 0->1 167 167 100.00
Total Bits 1->0 167 167 100.00

Ports 50 50 100.00
Port Bits 334 334 100.00
Port Bits 0->1 167 167 100.00
Port Bits 1->0 167 167 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
clk_aon_i Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
rst_ni Yes Yes T6,T17,T33 Yes T4,T5,T6 INPUT
rst_aon_ni Yes Yes T6,T17,T33 Yes T4,T5,T6 INPUT
tl_i.d_ready Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.a_user.data_intg[6:0] Yes Yes T33,T190,T121 Yes T33,T190,T121 INPUT
tl_i.a_user.cmd_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.a_user.instr_type[3:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_data[31:0] Yes Yes T33,T190,T121 Yes T33,T190,T121 INPUT
tl_i.a_mask[3:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.a_address[7:0] Yes Yes *T75,*T76,*T77 Yes T75,T76,T77 INPUT
tl_i.a_address[15:8] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[17:16] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.a_address[21:18] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[22] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
tl_i.a_address[29:23] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[30] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 INPUT
tl_i.a_address[31] Unreachable Unreachable Unreachable INPUT
tl_i.a_source[5:0] Yes Yes *T60,*T71,*T62 Yes T60,T71,T62 INPUT
tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_i.a_size[1:0] Yes Yes T75,T76,T77 Yes T75,T76,T77 INPUT
tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_opcode[2:0] Yes Yes T71,T62,T8 Yes T71,T62,T8 INPUT
tl_i.a_valid Yes Yes T33,T190,T121 Yes T33,T190,T121 INPUT
tl_o.a_ready Yes Yes T33,T190,T121 Yes T33,T190,T121 OUTPUT
tl_o.d_error Yes Yes T75,T76,T77 Yes T75,T76,T77 OUTPUT
tl_o.d_user.data_intg[6:0] Yes Yes T33,T190,T121 Yes T33,T190,T121 OUTPUT
tl_o.d_user.rsp_intg[6:0] Yes Yes T33,T190,T121 Yes T33,T190,T121 OUTPUT
tl_o.d_data[31:0] Yes Yes T33,T190,T121 Yes T33,T190,T121 OUTPUT
tl_o.d_sink Yes Yes T75,T76,T77 Yes T75,T76,T77 OUTPUT
tl_o.d_source[5:0] Yes Yes *T75,*T76,*T77 Yes T75,T76,T77 OUTPUT
tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_size[1:0] Yes Yes T75,T76,T77 Yes T75,T76,T77 OUTPUT
tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_opcode[0] Yes Yes *T33,*T190,*T121 Yes T33,T190,T121 OUTPUT
tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_valid Yes Yes T33,T190,T121 Yes T33,T190,T121 OUTPUT
alert_rx_i[0].ack_n Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
alert_rx_i[0].ack_p Yes Yes T746,T63,T80 Yes T746,T63,T80 INPUT
alert_rx_i[0].ping_n Yes Yes T80,T81,T82 Yes T80,T81,T82 INPUT
alert_rx_i[0].ping_p Yes Yes T80,T81,T82 Yes T80,T81,T82 INPUT
alert_tx_o[0].alert_n Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
alert_tx_o[0].alert_p Yes Yes T746,T63,T80 Yes T746,T63,T80 OUTPUT
wkup_req_o Yes Yes T33,T190,T121 Yes T33,T190,T121 OUTPUT
rst_req_o Yes Yes T33,T190,T121 Yes T33,T190,T121 OUTPUT
intr_event_detected_o Yes Yes T208,T93,T335 Yes T208,T93,T335 OUTPUT
cio_ac_present_i Yes Yes T207,T208,T210 Yes T207,T208,T210 INPUT
cio_ec_rst_l_i Yes Yes T33,T34,T207 Yes T33,T34,T207 INPUT
cio_key0_in_i Yes Yes T33,T190,T121 Yes T33,T190,T121 INPUT
cio_key1_in_i Yes Yes T33,T34,T207 Yes T33,T34,T207 INPUT
cio_key2_in_i Yes Yes T34,T207,T208 Yes T34,T207,T208 INPUT
cio_pwrb_in_i Yes Yes T2,T3,T207 Yes T34,T2,T3 INPUT
cio_lid_open_i Yes Yes T207,T210,T211 Yes T207,T210,T211 INPUT
cio_flash_wp_l_i Yes Yes T33,T34,T208 Yes T33,T34,T207 INPUT
cio_bat_disable_o Yes Yes T190,T121,T34 Yes T33,T190,T121 OUTPUT
cio_flash_wp_l_o Yes Yes T33,T34,T35 Yes T33,T34,T35 OUTPUT
cio_ec_rst_l_o Yes Yes T33,T34,T35 Yes T33,T34,T35 OUTPUT
cio_key0_out_o Yes Yes T33,T190,T121 Yes T33,T190,T121 OUTPUT
cio_key1_out_o Yes Yes T33,T34,T207 Yes T33,T34,T207 OUTPUT
cio_key2_out_o Yes Yes T34,T207,T208 Yes T33,T34,T207 OUTPUT
cio_pwrb_out_o Yes Yes T34,T2,T3 Yes T33,T34,T2 OUTPUT
cio_z3_wakeup_o Yes Yes T34,T209,T210 Yes T33,T34,T35 OUTPUT
cio_bat_disable_en_o Unreachable Unreachable Unreachable OUTPUT
cio_flash_wp_l_en_o Unreachable Unreachable Unreachable OUTPUT
cio_ec_rst_l_en_o Unreachable Unreachable Unreachable OUTPUT
cio_key0_out_en_o Unreachable Unreachable Unreachable OUTPUT
cio_key1_out_en_o Unreachable Unreachable Unreachable OUTPUT
cio_key2_out_en_o Unreachable Unreachable Unreachable OUTPUT
cio_pwrb_out_en_o Unreachable Unreachable Unreachable OUTPUT
cio_z3_wakeup_en_o Unreachable Unreachable Unreachable OUTPUT

*Tests covering at least one bit in the range
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%