Module Definition
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Module : prim_generic_usb_diff_rx
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.30 100.00 88.89 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_generic_usb_diff_rx_0/rtl/prim_generic_usb_diff_rx.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_prim_usb_diff_rx.gen_generic.u_impl_generic 96.30 100.00 88.89 100.00



Module Instance : tb.dut.u_prim_usb_diff_rx.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.30 100.00 88.89 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.30 100.00 88.89 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_prim_usb_diff_rx


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
obs_buf 100.00 100.00


Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : prim_generic_usb_diff_rx
Line No.TotalCoveredPercent
TOTAL66100.00
CONT_ASSIGN2600
CONT_ASSIGN2711100.00
CONT_ASSIGN3011100.00
CONT_ASSIGN3111100.00
CONT_ASSIGN3911100.00
CONT_ASSIGN4011100.00
CONT_ASSIGN4311100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_usb_diff_rx_0/rtl/prim_generic_usb_diff_rx.sv' or '../src/lowrisc_prim_generic_usb_diff_rx_0/rtl/prim_generic_usb_diff_rx.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 unreachable
27 1 1
30 1 1
31 1 1
39 1 1
40 1 1
43 1 1


Cond Coverage for Module : prim_generic_usb_diff_rx
TotalCoveredPercent
Conditions9888.89
Logical9888.89
Non-Logical00
Event00

 LINE       39
 EXPRESSION (pullup_p_en_i ? 1'b1 : 1'bz)
             ------1------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT30,T31,T2

 LINE       40
 EXPRESSION (pullup_n_en_i ? 1'b1 : 1'bz)
             ------1------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT30,T36,T74

 LINE       43
 EXPRESSION (input_en_i ? (input_p & ((~input_n))) : 1'b0)
             -----1----
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT30,T32,T36

 LINE       43
 SUB-EXPRESSION (input_p & ((~input_n)))
                 ---1---   ------2-----
-1--2-StatusTests
01CoveredT30,T32,T36
10Not Covered
11CoveredT30,T32,T36

Branch Coverage for Module : prim_generic_usb_diff_rx
Line No.TotalCoveredPercent
Branches 6 6 100.00
TERNARY 39 2 2 100.00
TERNARY 40 2 2 100.00
TERNARY 43 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_usb_diff_rx_0/rtl/prim_generic_usb_diff_rx.sv' or '../src/lowrisc_prim_generic_usb_diff_rx_0/rtl/prim_generic_usb_diff_rx.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 39 (pullup_p_en_i) ?

Branches:
-1-StatusTests
1 Covered T30,T31,T2
0 Covered T4,T5,T6


LineNo. Expression -1-: 40 (pullup_n_en_i) ?

Branches:
-1-StatusTests
1 Covered T30,T36,T74
0 Covered T4,T5,T6


LineNo. Expression -1-: 43 (input_en_i) ?

Branches:
-1-StatusTests
1 Covered T30,T32,T36
0 Covered T4,T5,T6

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%