Unified Coverage Report :: Module Instance :: tb.dut.u_padring.gen_mio_pads[43].u_mio_pad.gen_generic.u_impl_generic

Module Instance : tb.dut.u_padring.gen_mio_pads[43].u_mio_pad.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_mio_pads[43].u_mio_pad

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_padring.gen_mio_pads[44].u_mio_pad.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_mio_pads[44].u_mio_pad

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_padring.gen_mio_pads[45].u_mio_pad.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_mio_pads[45].u_mio_pad

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_padring.gen_mio_pads[46].u_mio_pad.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_mio_pads[46].u_mio_pad

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[43].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		8	8	100.00
CONT_ASSIGN	39	0	0
CONT_ASSIGN	51	1	1	100.00
CONT_ASSIGN	78	1	1	100.00
CONT_ASSIGN	80	1	1	100.00
CONT_ASSIGN	84	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	95	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
39		unreachable
51	1	1
78	1	1
80	1	1
84	1	1
85	1	1
92	1	1
93	1	1
95	1	1

---

Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[43].u_mio_pad.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	33	33	100.00
Logical	33	33	100.00
Non-Logical	0	0
Event	0	0

 LINE       51
 EXPRESSION (ie_i & ((~attr_i.input_disable)))
             --1-   ------------2------------

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T42,T43,T44
1	1	Covered	T4,T5,T6

 LINE       78
 EXPRESSION (ie ? inout_io : 1'bz)
             -1

-1-	Status	Tests
0	Covered	T42,T43,T44
1	Covered	T4,T5,T6

 LINE       80
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T28,T71,T62
0	1	Covered	T28,T38,T39
1	0	Covered	T42,T43,T44
1	1	Covered	T42,T43,T44

 LINE       84
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T42,T43,T44
1	0	Covered	T28,T38,T39
1	1	Covered	T42,T43,T44

 LINE       85
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T42,T43,T44
1	1	Covered	T28,T38,T39

 LINE       85
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T42,T43,T44
0	1	Covered	T4,T5,T6
1	0	Covered	T42,T43,T44

 LINE       85
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T42,T43,T44
1	1	Covered	T42,T43,T44

 LINE       92
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T42,T43,T44

 LINE       92
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T42,T43,T44
1	0	Covered	T28,T38,T39
1	1	Covered	T42,T43,T44

 LINE       93
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T28,T38,T39

 LINE       93
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T42,T43,T44
1	1	Covered	T28,T38,T39

 LINE       95
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T42,T43,T44

---

Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[43].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
TERNARY	78	2	2	100.00
TERNARY	92	2	2	100.00
TERNARY	93	2	2	100.00
TERNARY	95	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	78	(ie) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T42,T43,T44

	LineNo.	Expression
-1-:	92	((gen_bidir.oe && attr_i.drive_strength[0])) ? 

Branches:

-1-	Status	Tests
1	Covered	T42,T43,T44
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	93	((gen_bidir.oe && (!attr_i.drive_strength[0]))) ? 

Branches:

-1-	Status	Tests
1	Covered	T28,T38,T39
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	95	(attr_i.pull_en) ? 

Branches:

-1-	Status	Tests
1	Covered	T42,T43,T44
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[43].u_mio_pad.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AnalogNoScan_A	1013	1013	0	0

AnalogNoScan_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1013	1013	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T27	1	1	0	0
T28	1	1	0	0
T33	1	1	0	0
T85	1	1	0	0
T86	1	1	0	0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[44].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		8	8	100.00
CONT_ASSIGN	39	0	0
CONT_ASSIGN	51	1	1	100.00
CONT_ASSIGN	78	1	1	100.00
CONT_ASSIGN	80	1	1	100.00
CONT_ASSIGN	84	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	95	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
39		unreachable
51	1	1
78	1	1
80	1	1
84	1	1
85	1	1
92	1	1
93	1	1
95	1	1

---

Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[44].u_mio_pad.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	33	33	100.00
Logical	33	33	100.00
Non-Logical	0	0
Event	0	0

 LINE       51
 EXPRESSION (ie_i & ((~attr_i.input_disable)))
             --1-   ------------2------------

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T42,T43,T44
1	1	Covered	T4,T5,T6

 LINE       78
 EXPRESSION (ie ? inout_io : 1'bz)
             -1

-1-	Status	Tests
0	Covered	T42,T43,T44
1	Covered	T4,T5,T6

 LINE       80
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T28,T71,T62
0	1	Covered	T28,T38,T39
1	0	Covered	T42,T43,T44
1	1	Covered	T42,T43,T44

 LINE       84
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T42,T43,T44
1	0	Covered	T28,T38,T39
1	1	Covered	T42,T43,T44

 LINE       85
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T42,T43,T44
1	1	Covered	T28,T38,T39

 LINE       85
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T42,T43,T44
0	1	Covered	T4,T5,T6
1	0	Covered	T42,T43,T44

 LINE       85
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T42,T43,T44
1	1	Covered	T42,T43,T44

 LINE       92
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T42,T43,T44

 LINE       92
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T42,T43,T44
1	0	Covered	T28,T38,T39
1	1	Covered	T42,T43,T44

 LINE       93
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T28,T38,T39

 LINE       93
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T42,T43,T44
1	1	Covered	T28,T38,T39

 LINE       95
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T42,T43,T44

---

Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[44].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
TERNARY	78	2	2	100.00
TERNARY	92	2	2	100.00
TERNARY	93	2	2	100.00
TERNARY	95	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	78	(ie) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T42,T43,T44

	LineNo.	Expression
-1-:	92	((gen_bidir.oe && attr_i.drive_strength[0])) ? 

Branches:

-1-	Status	Tests
1	Covered	T42,T43,T44
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	93	((gen_bidir.oe && (!attr_i.drive_strength[0]))) ? 

Branches:

-1-	Status	Tests
1	Covered	T28,T38,T39
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	95	(attr_i.pull_en) ? 

Branches:

-1-	Status	Tests
1	Covered	T42,T43,T44
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[44].u_mio_pad.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AnalogNoScan_A	1013	1013	0	0

AnalogNoScan_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1013	1013	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T27	1	1	0	0
T28	1	1	0	0
T33	1	1	0	0
T85	1	1	0	0
T86	1	1	0	0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[45].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		8	8	100.00
CONT_ASSIGN	39	0	0
CONT_ASSIGN	51	1	1	100.00
CONT_ASSIGN	78	1	1	100.00
CONT_ASSIGN	80	1	1	100.00
CONT_ASSIGN	84	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	95	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
39		unreachable
51	1	1
78	1	1
80	1	1
84	1	1
85	1	1
92	1	1
93	1	1
95	1	1

---

Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[45].u_mio_pad.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	33	33	100.00
Logical	33	33	100.00
Non-Logical	0	0
Event	0	0

 LINE       51
 EXPRESSION (ie_i & ((~attr_i.input_disable)))
             --1-   ------------2------------

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T42,T43,T44
1	1	Covered	T4,T5,T6

 LINE       78
 EXPRESSION (ie ? inout_io : 1'bz)
             -1

-1-	Status	Tests
0	Covered	T42,T43,T44
1	Covered	T4,T5,T6

 LINE       80
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T28,T71,T62
0	1	Covered	T28,T38,T39
1	0	Covered	T42,T43,T44
1	1	Covered	T42,T43,T44

 LINE       84
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T42,T43,T44
1	0	Covered	T28,T38,T39
1	1	Covered	T42,T43,T44

 LINE       85
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T42,T43,T44
1	1	Covered	T28,T38,T39

 LINE       85
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T42,T43,T44
0	1	Covered	T4,T5,T6
1	0	Covered	T42,T43,T44

 LINE       85
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T42,T43,T44
1	1	Covered	T42,T43,T44

 LINE       92
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T42,T43,T44

 LINE       92
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T42,T43,T44
1	0	Covered	T28,T38,T39
1	1	Covered	T42,T43,T44

 LINE       93
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T28,T38,T39

 LINE       93
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T42,T43,T44
1	1	Covered	T28,T38,T39

 LINE       95
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T42,T43,T44

---

Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[45].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
TERNARY	78	2	2	100.00
TERNARY	92	2	2	100.00
TERNARY	93	2	2	100.00
TERNARY	95	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	78	(ie) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T42,T43,T44

	LineNo.	Expression
-1-:	92	((gen_bidir.oe && attr_i.drive_strength[0])) ? 

Branches:

-1-	Status	Tests
1	Covered	T42,T43,T44
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	93	((gen_bidir.oe && (!attr_i.drive_strength[0]))) ? 

Branches:

-1-	Status	Tests
1	Covered	T28,T38,T39
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	95	(attr_i.pull_en) ? 

Branches:

-1-	Status	Tests
1	Covered	T42,T43,T44
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[45].u_mio_pad.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AnalogNoScan_A	1013	1013	0	0

AnalogNoScan_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1013	1013	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T27	1	1	0	0
T28	1	1	0	0
T33	1	1	0	0
T85	1	1	0	0
T86	1	1	0	0

Line Coverage for Instance : tb.dut.u_padring.gen_mio_pads[46].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		8	8	100.00
CONT_ASSIGN	39	0	0
CONT_ASSIGN	51	1	1	100.00
CONT_ASSIGN	78	1	1	100.00
CONT_ASSIGN	80	1	1	100.00
CONT_ASSIGN	84	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	95	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
39		unreachable
51	1	1
78	1	1
80	1	1
84	1	1
85	1	1
92	1	1
93	1	1
95	1	1

---

Cond Coverage for Instance : tb.dut.u_padring.gen_mio_pads[46].u_mio_pad.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	33	33	100.00
Logical	33	33	100.00
Non-Logical	0	0
Event	0	0

 LINE       51
 EXPRESSION (ie_i & ((~attr_i.input_disable)))
             --1-   ------------2------------

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T42,T43,T44
1	1	Covered	T4,T5,T6

 LINE       78
 EXPRESSION (ie ? inout_io : 1'bz)
             -1

-1-	Status	Tests
0	Covered	T42,T43,T44
1	Covered	T4,T5,T6

 LINE       80
 EXPRESSION (attr_i.invert ^ in_raw_o)
             ------1------   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T33,T28,T71
0	1	Covered	T28,T34,T38
1	0	Covered	T42,T44,T191
1	1	Covered	T42,T44,T191

 LINE       84
 EXPRESSION (out_i ^ attr_i.invert)
             --1--   ------2------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T42,T43,T44
1	0	Covered	T28,T38,T39
1	1	Covered	T42,T43,T44

 LINE       85
 EXPRESSION (oe_i & ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en))))
             --1-   ---------------------------------2---------------------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T42,T43,T44
1	1	Covered	T28,T38,T39

 LINE       85
 SUB-EXPRESSION ((attr_i.virt_od_en & ((~gen_bidir.out))) | ((~attr_i.virt_od_en)))
                 --------------------1-------------------   -----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T42,T43,T44
0	1	Covered	T4,T5,T6
1	0	Covered	T42,T43,T44

 LINE       85
 SUB-EXPRESSION (attr_i.virt_od_en & ((~gen_bidir.out)))
                 --------1--------   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T42,T43,T44
1	1	Covered	T42,T43,T44

 LINE       92
 EXPRESSION ((gen_bidir.oe && attr_i.drive_strength[0]) ? gen_bidir.out : 1'bz)
             ---------------------1--------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T42,T43,T44

 LINE       92
 SUB-EXPRESSION (gen_bidir.oe && attr_i.drive_strength[0])
                 ------1-----    ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T42,T43,T44
1	0	Covered	T28,T38,T39
1	1	Covered	T42,T43,T44

 LINE       93
 EXPRESSION ((gen_bidir.oe && ((!attr_i.drive_strength[0]))) ? gen_bidir.out : 1'bz)
             -----------------------1-----------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T28,T38,T39

 LINE       93
 SUB-EXPRESSION (gen_bidir.oe && ((!attr_i.drive_strength[0])))
                 ------1-----    --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T42,T43,T44
1	1	Covered	T28,T38,T39

 LINE       95
 EXPRESSION (attr_i.pull_en ? attr_i.pull_select : 1'bz)
             -------1------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T42,T43,T44

---

Branch Coverage for Instance : tb.dut.u_padring.gen_mio_pads[46].u_mio_pad.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
TERNARY	78	2	2	100.00
TERNARY	92	2	2	100.00
TERNARY	93	2	2	100.00
TERNARY	95	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv' or '../src/lowrisc_prim_generic_pad_wrapper_0/rtl/prim_generic_pad_wrapper.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	78	(ie) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T42,T43,T44

	LineNo.	Expression
-1-:	92	((gen_bidir.oe && attr_i.drive_strength[0])) ? 

Branches:

-1-	Status	Tests
1	Covered	T42,T43,T44
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	93	((gen_bidir.oe && (!attr_i.drive_strength[0]))) ? 

Branches:

-1-	Status	Tests
1	Covered	T28,T38,T39
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	95	(attr_i.pull_en) ? 

Branches:

-1-	Status	Tests
1	Covered	T42,T43,T44
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_padring.gen_mio_pads[46].u_mio_pad.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AnalogNoScan_A	1013	1013	0	0

AnalogNoScan_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1013	1013	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T27	1	1	0	0
T28	1	1	0	0
T33	1	1	0	0
T85	1	1	0	0
T86	1	1	0	0