Unified Coverage Report :: Module :: prim_arbiter_fixed

Module : prim_arbiter_fixed

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.55	100.00	93.33			100.00	92.86

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region	94.88	100.00	86.67			100.00	92.86
tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region	96.55	100.00	93.33			100.00	92.86

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.88	100.00	86.67			100.00	92.86

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.88	100.00	86.67			100.00	92.86

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_ibus_trans

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.55	100.00	93.33			100.00	92.86

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.55	100.00	93.33			100.00	92.86

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_dbus_trans

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	2	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
121	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Module : prim_arbiter_fixed

	Total	Covered	Percent
Conditions	15	14	93.33
Logical	15	14	93.33
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T182,T184,T8
0	1	Covered	T182,T184,T304
1	0	Covered	T9

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T182,T184,T9
1	Covered	T182,T184,T8

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T182,T184,T9
1	Covered	T182,T184,T8

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T182,T184,T304
1	1	Covered	T182,T184,T9

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T182,T184,T8
1	0	Covered	T182,T184,T9
1	1	Covered	T182,T184,T304

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Unreachable
1	1	Covered	T182,T184,T9

---

Branch Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T182,T184,T8
0	Covered	T182,T184,T9

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T182,T184,T8
0	Covered	T182,T184,T9

---

Assert Coverage for Module : prim_arbiter_fixed

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	13	92.86
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	13	92.86

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	1021492308	1004362002	0	0
CheckNGreaterZero_A	2026	2026	0	0
GntImpliesReady_A	1021492308	8385	0	0
GntImpliesValid_A	1021492308	8385	0	0
GrantKnown_A	1021492308	1004362002	0	0
IdxKnown_A	1021492308	1004362002	0	0
IndexIsCorrect_A	1021492308	8385	0	0
NoReadyValidNoGrant_A	1021492308	0	0	0
Priority_A	1021492308	8385	0	0
ReadyAndValidImplyGrant_A	1021492308	8385	0	0
ReqAndReadyImplyGrant_A	1021492308	8385	0	0
ReqImpliesValid_A	1021492308	8385	0	0
ValidKnown_A	1021492308	1004362002	0	0
gen_data_port_assertion.DataFlow_A	1021492308	8385	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1021492308	1004362002	0	0
T4	766058	765956	0	0
T5	1197828	1197718	0	0
T6	438474	438270	0	0
T17	526814	526566	0	0
T18	450858	450742	0	0
T27	1239860	1239750	0	0
T28	202750	202640	0	0
T33	349298	349276	0	0
T85	515996	515982	0	0
T86	300182	300170	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2026	2026	0	0
T4	2	2	0	0
T5	2	2	0	0
T6	2	2	0	0
T17	2	2	0	0
T18	2	2	0	0
T27	2	2	0	0
T28	2	2	0	0
T33	2	2	0	0
T85	2	2	0	0
T86	2	2	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1021492308	8385	0	0
T83	151280	0	0	0
T123	713852	0	0	0
T182	206762	2793	0	0
T184	0	2796	0	0
T241	840754	0	0	0
T304	0	2796	0	0
T307	183732	0	0	0
T308	487880	0	0	0
T309	245410	0	0	0
T310	1932910	0	0	0
T311	696804	0	0	0
T312	533050	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1021492308	8385	0	0
T83	151280	0	0	0
T123	713852	0	0	0
T182	206762	2793	0	0
T184	0	2796	0	0
T241	840754	0	0	0
T304	0	2796	0	0
T307	183732	0	0	0
T308	487880	0	0	0
T309	245410	0	0	0
T310	1932910	0	0	0
T311	696804	0	0	0
T312	533050	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1021492308	1004362002	0	0
T4	766058	765956	0	0
T5	1197828	1197718	0	0
T6	438474	438270	0	0
T17	526814	526566	0	0
T18	450858	450742	0	0
T27	1239860	1239750	0	0
T28	202750	202640	0	0
T33	349298	349276	0	0
T85	515996	515982	0	0
T86	300182	300170	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1021492308	1004362002	0	0
T4	766058	765956	0	0
T5	1197828	1197718	0	0
T6	438474	438270	0	0
T17	526814	526566	0	0
T18	450858	450742	0	0
T27	1239860	1239750	0	0
T28	202750	202640	0	0
T33	349298	349276	0	0
T85	515996	515982	0	0
T86	300182	300170	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1021492308	8385	0	0
T83	151280	0	0	0
T123	713852	0	0	0
T182	206762	2793	0	0
T184	0	2796	0	0
T241	840754	0	0	0
T304	0	2796	0	0
T307	183732	0	0	0
T308	487880	0	0	0
T309	245410	0	0	0
T310	1932910	0	0	0
T311	696804	0	0	0
T312	533050	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1021492308	0	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1021492308	8385	0	0
T83	151280	0	0	0
T123	713852	0	0	0
T182	206762	2793	0	0
T184	0	2796	0	0
T241	840754	0	0	0
T304	0	2796	0	0
T307	183732	0	0	0
T308	487880	0	0	0
T309	245410	0	0	0
T310	1932910	0	0	0
T311	696804	0	0	0
T312	533050	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1021492308	8385	0	0
T83	151280	0	0	0
T123	713852	0	0	0
T182	206762	2793	0	0
T184	0	2796	0	0
T241	840754	0	0	0
T304	0	2796	0	0
T307	183732	0	0	0
T308	487880	0	0	0
T309	245410	0	0	0
T310	1932910	0	0	0
T311	696804	0	0	0
T312	533050	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1021492308	8385	0	0
T83	151280	0	0	0
T123	713852	0	0	0
T182	206762	2793	0	0
T184	0	2796	0	0
T241	840754	0	0	0
T304	0	2796	0	0
T307	183732	0	0	0
T308	487880	0	0	0
T309	245410	0	0	0
T310	1932910	0	0	0
T311	696804	0	0	0
T312	533050	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1021492308	8385	0	0
T83	151280	0	0	0
T123	713852	0	0	0
T182	206762	2793	0	0
T184	0	2796	0	0
T241	840754	0	0	0
T304	0	2796	0	0
T307	183732	0	0	0
T308	487880	0	0	0
T309	245410	0	0	0
T310	1932910	0	0	0
T311	696804	0	0	0
T312	533050	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1021492308	1004362002	0	0
T4	766058	765956	0	0
T5	1197828	1197718	0	0
T6	438474	438270	0	0
T17	526814	526566	0	0
T18	450858	450742	0	0
T27	1239860	1239750	0	0
T28	202750	202640	0	0
T33	349298	349276	0	0
T85	515996	515982	0	0
T86	300182	300170	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1021492308	8385	0	0
T83	151280	0	0	0
T123	713852	0	0	0
T182	206762	2793	0	0
T184	0	2796	0	0
T241	840754	0	0	0
T304	0	2796	0	0
T307	183732	0	0	0
T308	487880	0	0	0
T309	245410	0	0	0
T310	1932910	0	0	0
T311	696804	0	0	0
T312	533050	0	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	2	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
121	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

	Total	Covered	Percent
Conditions	15	13	86.67
Logical	15	13	86.67
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T182,T184,T8
0	1	Covered	T182,T184,T304
1	0	Not Covered

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T182,T184,T304
1	Covered	T182,T184,T8

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T182,T184,T304
1	Covered	T182,T184,T8

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T182,T184,T304
1	1	Covered	T182,T184,T304

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T182,T184,T8
1	0	Covered	T182,T184,T304
1	1	Covered	T182,T184,T304

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Unreachable
1	1	Covered	T182,T184,T304

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T182,T184,T8
0	Covered	T182,T184,T304

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T182,T184,T8
0	Covered	T182,T184,T304

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	13	92.86
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	13	92.86

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	510746154	502181001	0	0
CheckNGreaterZero_A	1013	1013	0	0
GntImpliesReady_A	510746154	5196	0	0
GntImpliesValid_A	510746154	5196	0	0
GrantKnown_A	510746154	502181001	0	0
IdxKnown_A	510746154	502181001	0	0
IndexIsCorrect_A	510746154	5196	0	0
NoReadyValidNoGrant_A	510746154	0	0	0
Priority_A	510746154	5196	0	0
ReadyAndValidImplyGrant_A	510746154	5196	0	0
ReqAndReadyImplyGrant_A	510746154	5196	0	0
ReqImpliesValid_A	510746154	5196	0	0
ValidKnown_A	510746154	502181001	0	0
gen_data_port_assertion.DataFlow_A	510746154	5196	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	510746154	502181001	0	0
T4	383029	382978	0	0
T5	598914	598859	0	0
T6	219237	219135	0	0
T17	263407	263283	0	0
T18	225429	225371	0	0
T27	619930	619875	0	0
T28	101375	101320	0	0
T33	174649	174638	0	0
T85	257998	257991	0	0
T86	150091	150085	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1013	1013	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T27	1	1	0	0
T28	1	1	0	0
T33	1	1	0	0
T85	1	1	0	0
T86	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	510746154	5196	0	0
T83	75640	0	0	0
T123	356926	0	0	0
T182	103381	1730	0	0
T184	0	1732	0	0
T241	420377	0	0	0
T304	0	1734	0	0
T307	91866	0	0	0
T308	243940	0	0	0
T309	122705	0	0	0
T310	966455	0	0	0
T311	348402	0	0	0
T312	266525	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	510746154	5196	0	0
T83	75640	0	0	0
T123	356926	0	0	0
T182	103381	1730	0	0
T184	0	1732	0	0
T241	420377	0	0	0
T304	0	1734	0	0
T307	91866	0	0	0
T308	243940	0	0	0
T309	122705	0	0	0
T310	966455	0	0	0
T311	348402	0	0	0
T312	266525	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	510746154	502181001	0	0
T4	383029	382978	0	0
T5	598914	598859	0	0
T6	219237	219135	0	0
T17	263407	263283	0	0
T18	225429	225371	0	0
T27	619930	619875	0	0
T28	101375	101320	0	0
T33	174649	174638	0	0
T85	257998	257991	0	0
T86	150091	150085	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	510746154	502181001	0	0
T4	383029	382978	0	0
T5	598914	598859	0	0
T6	219237	219135	0	0
T17	263407	263283	0	0
T18	225429	225371	0	0
T27	619930	619875	0	0
T28	101375	101320	0	0
T33	174649	174638	0	0
T85	257998	257991	0	0
T86	150091	150085	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	510746154	5196	0	0
T83	75640	0	0	0
T123	356926	0	0	0
T182	103381	1730	0	0
T184	0	1732	0	0
T241	420377	0	0	0
T304	0	1734	0	0
T307	91866	0	0	0
T308	243940	0	0	0
T309	122705	0	0	0
T310	966455	0	0	0
T311	348402	0	0	0
T312	266525	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	510746154	0	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	510746154	5196	0	0
T83	75640	0	0	0
T123	356926	0	0	0
T182	103381	1730	0	0
T184	0	1732	0	0
T241	420377	0	0	0
T304	0	1734	0	0
T307	91866	0	0	0
T308	243940	0	0	0
T309	122705	0	0	0
T310	966455	0	0	0
T311	348402	0	0	0
T312	266525	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	510746154	5196	0	0
T83	75640	0	0	0
T123	356926	0	0	0
T182	103381	1730	0	0
T184	0	1732	0	0
T241	420377	0	0	0
T304	0	1734	0	0
T307	91866	0	0	0
T308	243940	0	0	0
T309	122705	0	0	0
T310	966455	0	0	0
T311	348402	0	0	0
T312	266525	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	510746154	5196	0	0
T83	75640	0	0	0
T123	356926	0	0	0
T182	103381	1730	0	0
T184	0	1732	0	0
T241	420377	0	0	0
T304	0	1734	0	0
T307	91866	0	0	0
T308	243940	0	0	0
T309	122705	0	0	0
T310	966455	0	0	0
T311	348402	0	0	0
T312	266525	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	510746154	5196	0	0
T83	75640	0	0	0
T123	356926	0	0	0
T182	103381	1730	0	0
T184	0	1732	0	0
T241	420377	0	0	0
T304	0	1734	0	0
T307	91866	0	0	0
T308	243940	0	0	0
T309	122705	0	0	0
T310	966455	0	0	0
T311	348402	0	0	0
T312	266525	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	510746154	502181001	0	0
T4	383029	382978	0	0
T5	598914	598859	0	0
T6	219237	219135	0	0
T17	263407	263283	0	0
T18	225429	225371	0	0
T27	619930	619875	0	0
T28	101375	101320	0	0
T33	174649	174638	0	0
T85	257998	257991	0	0
T86	150091	150085	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	510746154	5196	0	0
T83	75640	0	0	0
T123	356926	0	0	0
T182	103381	1730	0	0
T184	0	1732	0	0
T241	420377	0	0	0
T304	0	1734	0	0
T307	91866	0	0	0
T308	243940	0	0	0
T309	122705	0	0	0
T310	966455	0	0	0
T311	348402	0	0	0
T312	266525	0	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	2	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
121	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

	Total	Covered	Percent
Conditions	15	14	93.33
Logical	15	14	93.33
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T182,T184,T8
0	1	Covered	T182,T184,T304
1	0	Covered	T9

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T182,T184,T9
1	Covered	T182,T184,T8

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T182,T184,T9
1	Covered	T182,T184,T8

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T182,T184,T304
1	1	Covered	T182,T184,T9

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T182,T184,T8
1	0	Covered	T182,T184,T9
1	1	Covered	T182,T184,T304

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Unreachable
1	1	Covered	T182,T184,T9

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T182,T184,T8
0	Covered	T182,T184,T9

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T182,T184,T8
0	Covered	T182,T184,T9

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	13	92.86
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	13	92.86

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	510746154	502181001	0	0
CheckNGreaterZero_A	1013	1013	0	0
GntImpliesReady_A	510746154	3189	0	0
GntImpliesValid_A	510746154	3189	0	0
GrantKnown_A	510746154	502181001	0	0
IdxKnown_A	510746154	502181001	0	0
IndexIsCorrect_A	510746154	3189	0	0
NoReadyValidNoGrant_A	510746154	0	0	0
Priority_A	510746154	3189	0	0
ReadyAndValidImplyGrant_A	510746154	3189	0	0
ReqAndReadyImplyGrant_A	510746154	3189	0	0
ReqImpliesValid_A	510746154	3189	0	0
ValidKnown_A	510746154	502181001	0	0
gen_data_port_assertion.DataFlow_A	510746154	3189	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	510746154	502181001	0	0
T4	383029	382978	0	0
T5	598914	598859	0	0
T6	219237	219135	0	0
T17	263407	263283	0	0
T18	225429	225371	0	0
T27	619930	619875	0	0
T28	101375	101320	0	0
T33	174649	174638	0	0
T85	257998	257991	0	0
T86	150091	150085	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1013	1013	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T27	1	1	0	0
T28	1	1	0	0
T33	1	1	0	0
T85	1	1	0	0
T86	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	510746154	3189	0	0
T83	75640	0	0	0
T123	356926	0	0	0
T182	103381	1063	0	0
T184	0	1064	0	0
T241	420377	0	0	0
T304	0	1062	0	0
T307	91866	0	0	0
T308	243940	0	0	0
T309	122705	0	0	0
T310	966455	0	0	0
T311	348402	0	0	0
T312	266525	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	510746154	3189	0	0
T83	75640	0	0	0
T123	356926	0	0	0
T182	103381	1063	0	0
T184	0	1064	0	0
T241	420377	0	0	0
T304	0	1062	0	0
T307	91866	0	0	0
T308	243940	0	0	0
T309	122705	0	0	0
T310	966455	0	0	0
T311	348402	0	0	0
T312	266525	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	510746154	502181001	0	0
T4	383029	382978	0	0
T5	598914	598859	0	0
T6	219237	219135	0	0
T17	263407	263283	0	0
T18	225429	225371	0	0
T27	619930	619875	0	0
T28	101375	101320	0	0
T33	174649	174638	0	0
T85	257998	257991	0	0
T86	150091	150085	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	510746154	502181001	0	0
T4	383029	382978	0	0
T5	598914	598859	0	0
T6	219237	219135	0	0
T17	263407	263283	0	0
T18	225429	225371	0	0
T27	619930	619875	0	0
T28	101375	101320	0	0
T33	174649	174638	0	0
T85	257998	257991	0	0
T86	150091	150085	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	510746154	3189	0	0
T83	75640	0	0	0
T123	356926	0	0	0
T182	103381	1063	0	0
T184	0	1064	0	0
T241	420377	0	0	0
T304	0	1062	0	0
T307	91866	0	0	0
T308	243940	0	0	0
T309	122705	0	0	0
T310	966455	0	0	0
T311	348402	0	0	0
T312	266525	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	510746154	0	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	510746154	3189	0	0
T83	75640	0	0	0
T123	356926	0	0	0
T182	103381	1063	0	0
T184	0	1064	0	0
T241	420377	0	0	0
T304	0	1062	0	0
T307	91866	0	0	0
T308	243940	0	0	0
T309	122705	0	0	0
T310	966455	0	0	0
T311	348402	0	0	0
T312	266525	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	510746154	3189	0	0
T83	75640	0	0	0
T123	356926	0	0	0
T182	103381	1063	0	0
T184	0	1064	0	0
T241	420377	0	0	0
T304	0	1062	0	0
T307	91866	0	0	0
T308	243940	0	0	0
T309	122705	0	0	0
T310	966455	0	0	0
T311	348402	0	0	0
T312	266525	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	510746154	3189	0	0
T83	75640	0	0	0
T123	356926	0	0	0
T182	103381	1063	0	0
T184	0	1064	0	0
T241	420377	0	0	0
T304	0	1062	0	0
T307	91866	0	0	0
T308	243940	0	0	0
T309	122705	0	0	0
T310	966455	0	0	0
T311	348402	0	0	0
T312	266525	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	510746154	3189	0	0
T83	75640	0	0	0
T123	356926	0	0	0
T182	103381	1063	0	0
T184	0	1064	0	0
T241	420377	0	0	0
T304	0	1062	0	0
T307	91866	0	0	0
T308	243940	0	0	0
T309	122705	0	0	0
T310	966455	0	0	0
T311	348402	0	0	0
T312	266525	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	510746154	502181001	0	0
T4	383029	382978	0	0
T5	598914	598859	0	0
T6	219237	219135	0	0
T17	263407	263283	0	0
T18	225429	225371	0	0
T27	619930	619875	0	0
T28	101375	101320	0	0
T33	174649	174638	0	0
T85	257998	257991	0	0
T86	150091	150085	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	510746154	3189	0	0
T83	75640	0	0	0
T123	356926	0	0	0
T182	103381	1063	0	0
T184	0	1064	0	0
T241	420377	0	0	0
T304	0	1062	0	0
T307	91866	0	0	0
T308	243940	0	0	0
T309	122705	0	0	0
T310	966455	0	0	0
T311	348402	0	0	0
T312	266525	0	0	0