Unified Coverage Report :: Module Instance :: tb.dut.top_earlgrey.u_spi_device.u_reg.u_socket.fifo_h

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00		100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75	75.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
90.74	96.47	89.29	99.75		100.00	68.18	u_rv_core_ibex

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
reqfifo	100.00	100.00					100.00
rspfifo	75.00	50.00					100.00

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00		100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
90.74	96.47	89.29	99.75		100.00	68.18	u_rv_core_ibex

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
reqfifo	100.00	100.00					100.00
rspfifo	100.00	100.00					100.00

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00		100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.64	94.64	93.18			94.74	100.00	u_socket

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
reqfifo	100.00	100.00					100.00
rspfifo	100.00	100.00					100.00

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00		100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.64	94.64	93.18			94.74	100.00	u_socket

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
reqfifo	100.00	100.00					100.00
rspfifo	100.00	100.00					100.00

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00		100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.64	94.64	93.18			94.74	100.00	u_socket

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
reqfifo	100.00	100.00					100.00
rspfifo	100.00	100.00					100.00

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i

	Total	Covered	Percent
Conditions	4	4	100.00
Logical	4	4	100.00
Non-Logical	0	0
Event	0	0

 LINE       66
 SUB-EXPRESSION ((tl_d_i.d_opcode == AccessAckData) ? tl_d_i.d_data : ({top_pkg::TL_DW {1'b0}}))
                 -----------------1----------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       66
 SUB-EXPRESSION (tl_d_i.d_opcode == AccessAckData)
                -----------------1----------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
TERNARY	66	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv' or '../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	66	((tl_d_i.d_opcode == AccessAckData)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d

	Total	Covered	Percent
Conditions	4	4	100.00
Logical	4	4	100.00
Non-Logical	0	0
Event	0	0

 LINE       66
 SUB-EXPRESSION ((tl_d_i.d_opcode == AccessAckData) ? tl_d_i.d_data : ({top_pkg::TL_DW {1'b0}}))
                 -----------------1----------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       66
 SUB-EXPRESSION (tl_d_i.d_opcode == AccessAckData)
                -----------------1----------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
TERNARY	66	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv' or '../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	66	((tl_d_i.d_opcode == AccessAckData)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h

	Total	Covered	Percent
Conditions	4	4	100.00
Logical	4	4	100.00
Non-Logical	0	0
Event	0	0

 LINE       66
 SUB-EXPRESSION ((tl_d_i.d_opcode == AccessAckData) ? tl_d_i.d_data : ({top_pkg::TL_DW {1'b0}}))
                 -----------------1----------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       66
 SUB-EXPRESSION (tl_d_i.d_opcode == AccessAckData)
                -----------------1----------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
TERNARY	66	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv' or '../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	66	((tl_d_i.d_opcode == AccessAckData)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d

	Total	Covered	Percent
Conditions	4	4	100.00
Logical	4	4	100.00
Non-Logical	0	0
Event	0	0

 LINE       66
 SUB-EXPRESSION ((tl_d_i.d_opcode == AccessAckData) ? tl_d_i.d_data : ({top_pkg::TL_DW {1'b0}}))
                 -----------------1----------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T36,T82,T83

 LINE       66
 SUB-EXPRESSION (tl_d_i.d_opcode == AccessAckData)
                -----------------1----------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T36,T82,T83

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
TERNARY	66	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv' or '../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	66	((tl_d_i.d_opcode == AccessAckData)) ? 

Branches:

-1-	Status	Tests
1	Covered	T36,T82,T83
0	Covered	T4,T5,T6

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d

	Total	Covered	Percent
Conditions	4	4	100.00
Logical	4	4	100.00
Non-Logical	0	0
Event	0	0

 LINE       66
 SUB-EXPRESSION ((tl_d_i.d_opcode == AccessAckData) ? tl_d_i.d_data : ({top_pkg::TL_DW {1'b0}}))
                 -----------------1----------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       66
 SUB-EXPRESSION (tl_d_i.d_opcode == AccessAckData)
                -----------------1----------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
TERNARY	66	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv' or '../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	66	((tl_d_i.d_opcode == AccessAckData)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6