| T917 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0.2500664125 |
|
|
Jul 17 08:40:00 PM PDT 24 |
Jul 17 09:47:13 PM PDT 24 |
11182056328 ps |
| T478 |
/workspace/coverage/default/35.chip_sw_all_escalation_resets.3672647639 |
|
|
Jul 17 08:59:05 PM PDT 24 |
Jul 17 09:09:05 PM PDT 24 |
5595053116 ps |
| T362 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en.770887300 |
|
|
Jul 17 08:30:11 PM PDT 24 |
Jul 17 08:41:43 PM PDT 24 |
4849362256 ps |
| T918 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_clock_freqs.2162018565 |
|
|
Jul 17 08:30:04 PM PDT 24 |
Jul 17 08:50:34 PM PDT 24 |
5448102605 ps |
| T247 |
/workspace/coverage/default/1.chip_sw_rv_dm_access_after_escalation_reset.2220796858 |
|
|
Jul 17 08:42:16 PM PDT 24 |
Jul 17 08:51:16 PM PDT 24 |
5677556127 ps |
| T326 |
/workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_alerts.1330677828 |
|
|
Jul 17 08:32:17 PM PDT 24 |
Jul 17 08:38:19 PM PDT 24 |
3817217716 ps |
| T919 |
/workspace/coverage/default/1.chip_sw_csrng_kat_test.3207376205 |
|
|
Jul 17 08:37:42 PM PDT 24 |
Jul 17 08:42:17 PM PDT 24 |
2850732030 ps |
| T805 |
/workspace/coverage/default/69.chip_sw_all_escalation_resets.3985132061 |
|
|
Jul 17 09:00:13 PM PDT 24 |
Jul 17 09:12:05 PM PDT 24 |
6239095082 ps |
| T920 |
/workspace/coverage/default/2.chip_sw_edn_entropy_reqs.2404811248 |
|
|
Jul 17 08:48:50 PM PDT 24 |
Jul 17 09:04:55 PM PDT 24 |
6461149200 ps |
| T921 |
/workspace/coverage/default/4.chip_sw_uart_tx_rx.4245994870 |
|
|
Jul 17 08:52:19 PM PDT 24 |
Jul 17 09:02:37 PM PDT 24 |
3978050040 ps |
| T922 |
/workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_reset_reqs.2767455450 |
|
|
Jul 17 08:45:59 PM PDT 24 |
Jul 17 09:26:20 PM PDT 24 |
23790162990 ps |
| T330 |
/workspace/coverage/default/0.chip_plic_all_irqs_20.1905141685 |
|
|
Jul 17 08:31:16 PM PDT 24 |
Jul 17 08:45:46 PM PDT 24 |
4834744918 ps |
| T124 |
/workspace/coverage/default/2.chip_sw_entropy_src_csrng.3421511909 |
|
|
Jul 17 08:48:09 PM PDT 24 |
Jul 17 09:08:42 PM PDT 24 |
6272204028 ps |
| T276 |
/workspace/coverage/default/4.chip_sw_data_integrity_escalation.780732585 |
|
|
Jul 17 08:52:53 PM PDT 24 |
Jul 17 09:09:19 PM PDT 24 |
6547203374 ps |
| T279 |
/workspace/coverage/default/31.chip_sw_all_escalation_resets.3014945135 |
|
|
Jul 17 08:57:52 PM PDT 24 |
Jul 17 09:06:10 PM PDT 24 |
5238839920 ps |
| T280 |
/workspace/coverage/default/9.chip_sw_alert_handler_lpg_sleep_mode_alerts.3063452643 |
|
|
Jul 17 08:55:18 PM PDT 24 |
Jul 17 09:03:10 PM PDT 24 |
3728162340 ps |
| T281 |
/workspace/coverage/default/0.chip_sw_plic_sw_irq.2078977518 |
|
|
Jul 17 08:30:43 PM PDT 24 |
Jul 17 08:36:28 PM PDT 24 |
3572022446 ps |
| T282 |
/workspace/coverage/default/1.chip_sw_example_flash.1409060374 |
|
|
Jul 17 08:34:17 PM PDT 24 |
Jul 17 08:37:46 PM PDT 24 |
2236773240 ps |
| T233 |
/workspace/coverage/default/0.chip_sw_flash_init_reduced_freq.51884382 |
|
|
Jul 17 08:30:24 PM PDT 24 |
Jul 17 09:10:14 PM PDT 24 |
25563052601 ps |
| T283 |
/workspace/coverage/default/2.chip_sw_otp_ctrl_ecc_error_vendor_test.3218490444 |
|
|
Jul 17 08:45:30 PM PDT 24 |
Jul 17 08:48:56 PM PDT 24 |
3059606484 ps |
| T284 |
/workspace/coverage/default/0.chip_sw_example_manufacturer.3469763157 |
|
|
Jul 17 08:30:07 PM PDT 24 |
Jul 17 08:34:56 PM PDT 24 |
2755874744 ps |
| T285 |
/workspace/coverage/default/1.rom_e2e_smoke.1455332852 |
|
|
Jul 17 08:46:49 PM PDT 24 |
Jul 17 09:42:49 PM PDT 24 |
14946986168 ps |
| T286 |
/workspace/coverage/default/1.chip_sw_lc_ctrl_transition.4050333861 |
|
|
Jul 17 08:35:16 PM PDT 24 |
Jul 17 08:53:24 PM PDT 24 |
11422316156 ps |
| T923 |
/workspace/coverage/default/2.chip_sw_uart_tx_rx_idx1.662575254 |
|
|
Jul 17 08:43:06 PM PDT 24 |
Jul 17 08:53:09 PM PDT 24 |
3893523240 ps |
| T375 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en.533875147 |
|
|
Jul 17 08:50:38 PM PDT 24 |
Jul 17 09:01:08 PM PDT 24 |
4423692316 ps |
| T924 |
/workspace/coverage/default/1.chip_sw_rstmgr_smoketest.845964833 |
|
|
Jul 17 08:43:42 PM PDT 24 |
Jul 17 08:48:15 PM PDT 24 |
3479245856 ps |
| T27 |
/workspace/coverage/default/1.chip_sw_spi_host_tx_rx.1658942482 |
|
|
Jul 17 08:34:21 PM PDT 24 |
Jul 17 08:39:41 PM PDT 24 |
3364819496 ps |
| T925 |
/workspace/coverage/default/0.chip_sw_edn_entropy_reqs.743382989 |
|
|
Jul 17 08:33:38 PM PDT 24 |
Jul 17 08:53:21 PM PDT 24 |
5955754288 ps |
| T926 |
/workspace/coverage/default/2.chip_sw_uart_rand_baudrate.2826103455 |
|
|
Jul 17 08:44:11 PM PDT 24 |
Jul 17 08:52:38 PM PDT 24 |
4123743256 ps |
| T205 |
/workspace/coverage/default/1.chip_sw_inject_scramble_seed.1408625766 |
|
|
Jul 17 08:31:50 PM PDT 24 |
Jul 17 11:39:58 PM PDT 24 |
64996472456 ps |
| T761 |
/workspace/coverage/default/68.chip_sw_all_escalation_resets.730247628 |
|
|
Jul 17 09:00:08 PM PDT 24 |
Jul 17 09:09:28 PM PDT 24 |
5901937896 ps |
| T206 |
/workspace/coverage/default/2.chip_sw_uart_tx_rx_bootstrap.3141745588 |
|
|
Jul 17 08:44:56 PM PDT 24 |
Jul 18 12:32:09 AM PDT 24 |
77916720545 ps |
| T927 |
/workspace/coverage/default/0.chip_sw_edn_sw_mode.977764887 |
|
|
Jul 17 08:39:17 PM PDT 24 |
Jul 17 08:56:39 PM PDT 24 |
5081406744 ps |
| T260 |
/workspace/coverage/default/0.chip_sw_alert_handler_reverse_ping_in_deep_sleep.1695020169 |
|
|
Jul 17 08:32:32 PM PDT 24 |
Jul 17 11:50:47 PM PDT 24 |
255818140384 ps |
| T207 |
/workspace/coverage/default/0.chip_sw_sysrst_ctrl_inputs.2427390541 |
|
|
Jul 17 08:31:02 PM PDT 24 |
Jul 17 08:36:39 PM PDT 24 |
2955731978 ps |
| T928 |
/workspace/coverage/default/2.chip_sw_kmac_idle.2758608189 |
|
|
Jul 17 08:47:42 PM PDT 24 |
Jul 17 08:51:21 PM PDT 24 |
2975594544 ps |
| T929 |
/workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq.3860202650 |
|
|
Jul 17 08:52:22 PM PDT 24 |
Jul 17 09:02:01 PM PDT 24 |
3694566153 ps |
| T179 |
/workspace/coverage/default/0.chip_sw_csrng_fuse_en_sw_app_read_test.3387221957 |
|
|
Jul 17 08:30:37 PM PDT 24 |
Jul 17 08:37:51 PM PDT 24 |
4828088614 ps |
| T930 |
/workspace/coverage/default/2.rom_keymgr_functest.2099148192 |
|
|
Jul 17 08:51:43 PM PDT 24 |
Jul 17 09:03:40 PM PDT 24 |
4810385056 ps |
| T931 |
/workspace/coverage/default/0.chip_sw_pwrmgr_b2b_sleep_reset_req.3724544910 |
|
|
Jul 17 08:32:18 PM PDT 24 |
Jul 17 09:05:42 PM PDT 24 |
29544693329 ps |
| T675 |
/workspace/coverage/default/83.chip_sw_alert_handler_lpg_sleep_mode_alerts.1337797862 |
|
|
Jul 17 09:03:01 PM PDT 24 |
Jul 17 09:10:20 PM PDT 24 |
3944834600 ps |
| T720 |
/workspace/coverage/default/77.chip_sw_alert_handler_lpg_sleep_mode_alerts.1659830980 |
|
|
Jul 17 09:01:38 PM PDT 24 |
Jul 17 09:09:48 PM PDT 24 |
3813706266 ps |
| T932 |
/workspace/coverage/default/2.chip_sw_rv_dm_access_after_wakeup.901626811 |
|
|
Jul 17 08:49:24 PM PDT 24 |
Jul 17 09:00:10 PM PDT 24 |
6049428130 ps |
| T396 |
/workspace/coverage/default/1.chip_sw_rv_core_ibex_lockstep_glitch.3210185520 |
|
|
Jul 17 08:39:19 PM PDT 24 |
Jul 17 08:44:31 PM PDT 24 |
3017006512 ps |
| T933 |
/workspace/coverage/default/1.chip_sw_hmac_enc_idle.940756851 |
|
|
Jul 17 08:39:40 PM PDT 24 |
Jul 17 08:45:25 PM PDT 24 |
3169285820 ps |
| T934 |
/workspace/coverage/default/2.chip_sw_keymgr_key_derivation_prod.3001573489 |
|
|
Jul 17 08:49:10 PM PDT 24 |
Jul 17 09:24:36 PM PDT 24 |
12168171584 ps |
| T39 |
/workspace/coverage/default/1.chip_sw_gpio_smoketest.1229682982 |
|
|
Jul 17 08:42:31 PM PDT 24 |
Jul 17 08:46:34 PM PDT 24 |
2814481373 ps |
| T168 |
/workspace/coverage/default/1.chip_sw_lc_walkthrough_testunlocks.1625668296 |
|
|
Jul 17 08:35:17 PM PDT 24 |
Jul 17 09:18:25 PM PDT 24 |
26474882784 ps |
| T258 |
/workspace/coverage/default/0.rom_e2e_jtag_inject_test_unlocked0.1631289979 |
|
|
Jul 17 08:38:09 PM PDT 24 |
Jul 17 09:09:56 PM PDT 24 |
26442673995 ps |
| T52 |
/workspace/coverage/default/0.chip_sw_spi_device_tpm.3177185660 |
|
|
Jul 17 08:29:59 PM PDT 24 |
Jul 17 08:35:59 PM PDT 24 |
3266522705 ps |
| T363 |
/workspace/coverage/default/1.chip_sw_hmac_enc_jitter_en.2225962000 |
|
|
Jul 17 08:39:45 PM PDT 24 |
Jul 17 08:43:37 PM PDT 24 |
2485465544 ps |
| T935 |
/workspace/coverage/default/1.rom_e2e_asm_init_prod.462402158 |
|
|
Jul 17 08:47:06 PM PDT 24 |
Jul 17 09:46:48 PM PDT 24 |
15164800822 ps |
| T936 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.1586389503 |
|
|
Jul 17 08:39:57 PM PDT 24 |
Jul 17 08:58:03 PM PDT 24 |
7792008976 ps |
| T64 |
/workspace/coverage/default/2.chip_sw_alert_test.1925493027 |
|
|
Jul 17 08:48:05 PM PDT 24 |
Jul 17 08:52:01 PM PDT 24 |
2725144234 ps |
| T937 |
/workspace/coverage/default/1.rom_e2e_asm_init_prod_end.1206690106 |
|
|
Jul 17 08:45:09 PM PDT 24 |
Jul 17 09:49:44 PM PDT 24 |
15256661296 ps |
| T938 |
/workspace/coverage/default/2.chip_sw_clkmgr_off_peri.2984136801 |
|
|
Jul 17 08:48:58 PM PDT 24 |
Jul 17 09:09:08 PM PDT 24 |
10577705610 ps |
| T939 |
/workspace/coverage/default/0.chip_sw_clkmgr_off_aes_trans.1163358127 |
|
|
Jul 17 08:33:14 PM PDT 24 |
Jul 17 08:40:26 PM PDT 24 |
3824129554 ps |
| T88 |
/workspace/coverage/default/0.chip_sw_alert_handler_entropy.2175998486 |
|
|
Jul 17 08:36:12 PM PDT 24 |
Jul 17 08:41:42 PM PDT 24 |
2906568704 ps |
| T733 |
/workspace/coverage/default/34.chip_sw_alert_handler_lpg_sleep_mode_alerts.1690588146 |
|
|
Jul 17 08:57:09 PM PDT 24 |
Jul 17 09:02:32 PM PDT 24 |
3058036606 ps |
| T795 |
/workspace/coverage/default/83.chip_sw_all_escalation_resets.3441901871 |
|
|
Jul 17 09:01:37 PM PDT 24 |
Jul 17 09:13:17 PM PDT 24 |
4958028120 ps |
| T393 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.1771356798 |
|
|
Jul 17 08:39:08 PM PDT 24 |
Jul 17 10:32:21 PM PDT 24 |
23571607062 ps |
| T940 |
/workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_invalid_meas.1073594705 |
|
|
Jul 17 08:52:12 PM PDT 24 |
Jul 17 09:51:39 PM PDT 24 |
15054776894 ps |
| T941 |
/workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.1139651757 |
|
|
Jul 17 08:27:51 PM PDT 24 |
Jul 17 09:02:10 PM PDT 24 |
13442429966 ps |
| T942 |
/workspace/coverage/default/2.rom_e2e_asm_init_test_unlocked0.2252194192 |
|
|
Jul 17 08:55:50 PM PDT 24 |
Jul 17 09:36:21 PM PDT 24 |
11112883966 ps |
| T943 |
/workspace/coverage/default/0.chip_sw_lc_ctrl_transition.1538847792 |
|
|
Jul 17 08:29:44 PM PDT 24 |
Jul 17 08:45:50 PM PDT 24 |
9302172322 ps |
| T944 |
/workspace/coverage/default/0.chip_sw_clkmgr_off_otbn_trans.592161752 |
|
|
Jul 17 08:31:19 PM PDT 24 |
Jul 17 08:40:28 PM PDT 24 |
4645238804 ps |
| T945 |
/workspace/coverage/default/0.rom_e2e_static_critical.771549245 |
|
|
Jul 17 08:37:07 PM PDT 24 |
Jul 17 09:45:11 PM PDT 24 |
16831686912 ps |
| T568 |
/workspace/coverage/default/0.chip_sw_rv_core_ibex_nmi_irq.18982060 |
|
|
Jul 17 08:30:51 PM PDT 24 |
Jul 17 08:47:03 PM PDT 24 |
5012692360 ps |
| T946 |
/workspace/coverage/default/0.chip_sw_entropy_src_ast_rng_req.2349304686 |
|
|
Jul 17 08:29:40 PM PDT 24 |
Jul 17 08:32:45 PM PDT 24 |
2564321240 ps |
| T947 |
/workspace/coverage/default/2.rom_e2e_asm_init_prod.1807059728 |
|
|
Jul 17 08:53:59 PM PDT 24 |
Jul 17 09:43:31 PM PDT 24 |
15961724854 ps |
| T948 |
/workspace/coverage/default/0.chip_sw_rv_dm_access_after_wakeup.1538649961 |
|
|
Jul 17 08:39:27 PM PDT 24 |
Jul 17 08:48:22 PM PDT 24 |
6737653980 ps |
| T949 |
/workspace/coverage/default/13.chip_sw_lc_ctrl_transition.1666536295 |
|
|
Jul 17 08:57:17 PM PDT 24 |
Jul 17 09:04:30 PM PDT 24 |
6087246574 ps |
| T288 |
/workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access.1148662986 |
|
|
Jul 17 08:30:35 PM PDT 24 |
Jul 17 08:45:05 PM PDT 24 |
5053700888 ps |
| T950 |
/workspace/coverage/default/0.chip_sw_rv_plic_smoketest.2360002119 |
|
|
Jul 17 08:35:40 PM PDT 24 |
Jul 17 08:40:20 PM PDT 24 |
2792364428 ps |
| T757 |
/workspace/coverage/default/27.chip_sw_alert_handler_lpg_sleep_mode_alerts.811918294 |
|
|
Jul 17 08:57:27 PM PDT 24 |
Jul 17 09:04:29 PM PDT 24 |
3921478780 ps |
| T53 |
/workspace/coverage/default/2.chip_sw_spi_device_tpm.2815277673 |
|
|
Jul 17 08:43:59 PM PDT 24 |
Jul 17 08:49:06 PM PDT 24 |
3061238970 ps |
| T951 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.3860980433 |
|
|
Jul 17 08:40:03 PM PDT 24 |
Jul 17 10:04:44 PM PDT 24 |
15280238300 ps |
| T952 |
/workspace/coverage/default/19.chip_sw_uart_rand_baudrate.2080755173 |
|
|
Jul 17 08:57:47 PM PDT 24 |
Jul 17 09:27:10 PM PDT 24 |
12964669316 ps |
| T953 |
/workspace/coverage/default/2.chip_sw_aes_enc_jitter_en.8308762 |
|
|
Jul 17 08:47:36 PM PDT 24 |
Jul 17 08:52:05 PM PDT 24 |
2100274711 ps |
| T215 |
/workspace/coverage/default/2.chip_sw_i2c_host_tx_rx.3876400204 |
|
|
Jul 17 08:44:43 PM PDT 24 |
Jul 17 08:59:23 PM PDT 24 |
5357288904 ps |
| T180 |
/workspace/coverage/default/1.chip_sw_csrng_lc_hw_debug_en_test.3478828335 |
|
|
Jul 17 08:38:57 PM PDT 24 |
Jul 17 08:49:52 PM PDT 24 |
7304481780 ps |
| T76 |
/workspace/coverage/default/2.chip_tap_straps_prod.2259173351 |
|
|
Jul 17 08:49:13 PM PDT 24 |
Jul 17 09:05:08 PM PDT 24 |
8656573817 ps |
| T954 |
/workspace/coverage/default/0.chip_tap_straps_prod.284339474 |
|
|
Jul 17 08:29:41 PM PDT 24 |
Jul 17 08:41:13 PM PDT 24 |
7637177191 ps |
| T806 |
/workspace/coverage/default/68.chip_sw_alert_handler_lpg_sleep_mode_alerts.2168958771 |
|
|
Jul 17 09:01:29 PM PDT 24 |
Jul 17 09:07:18 PM PDT 24 |
4240229862 ps |
| T230 |
/workspace/coverage/default/1.chip_sw_keymgr_sideload_otbn.342703394 |
|
|
Jul 17 08:38:43 PM PDT 24 |
Jul 17 09:37:21 PM PDT 24 |
10208997252 ps |
| T955 |
/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_lc.1447775894 |
|
|
Jul 17 08:41:34 PM PDT 24 |
Jul 17 08:57:33 PM PDT 24 |
9881374620 ps |
| T956 |
/workspace/coverage/default/1.chip_sw_clkmgr_off_otbn_trans.3240674881 |
|
|
Jul 17 08:43:34 PM PDT 24 |
Jul 17 08:52:23 PM PDT 24 |
4608424900 ps |
| T957 |
/workspace/coverage/default/1.rom_e2e_shutdown_exception_c.2006328754 |
|
|
Jul 17 08:51:43 PM PDT 24 |
Jul 17 09:39:45 PM PDT 24 |
14555939970 ps |
| T958 |
/workspace/coverage/default/1.chip_sw_hmac_multistream.3329411113 |
|
|
Jul 17 08:40:00 PM PDT 24 |
Jul 17 09:10:33 PM PDT 24 |
6918129922 ps |
| T28 |
/workspace/coverage/default/0.chip_sw_spi_device_pass_through_collision.1674197163 |
|
|
Jul 17 08:29:36 PM PDT 24 |
Jul 17 08:40:23 PM PDT 24 |
4744799830 ps |
| T794 |
/workspace/coverage/default/51.chip_sw_alert_handler_lpg_sleep_mode_alerts.4230806357 |
|
|
Jul 17 09:03:42 PM PDT 24 |
Jul 17 09:12:29 PM PDT 24 |
3987505380 ps |
| T959 |
/workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_power_glitch_reset.4218859786 |
|
|
Jul 17 08:35:01 PM PDT 24 |
Jul 17 09:30:45 PM PDT 24 |
40906694440 ps |
| T199 |
/workspace/coverage/default/2.chip_sw_spi_device_pass_through_collision.178945337 |
|
|
Jul 17 08:44:28 PM PDT 24 |
Jul 17 08:53:24 PM PDT 24 |
4399165243 ps |
| T275 |
/workspace/coverage/default/1.rom_e2e_shutdown_output.2731951501 |
|
|
Jul 17 08:51:15 PM PDT 24 |
Jul 17 09:59:21 PM PDT 24 |
27991925229 ps |
| T182 |
/workspace/coverage/default/0.chip_sw_flash_rma_unlocked.1995335993 |
|
|
Jul 17 08:29:52 PM PDT 24 |
Jul 17 09:59:37 PM PDT 24 |
44268601604 ps |
| T960 |
/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.2890865416 |
|
|
Jul 17 08:48:41 PM PDT 24 |
Jul 17 09:01:43 PM PDT 24 |
5086706350 ps |
| T961 |
/workspace/coverage/default/2.chip_sw_aon_timer_wdog_lc_escalate.668384785 |
|
|
Jul 17 08:46:36 PM PDT 24 |
Jul 17 08:56:23 PM PDT 24 |
6152801080 ps |
| T962 |
/workspace/coverage/default/2.chip_sw_pwrmgr_b2b_sleep_reset_req.320295172 |
|
|
Jul 17 08:49:00 PM PDT 24 |
Jul 17 09:18:27 PM PDT 24 |
24819502714 ps |
| T963 |
/workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_rma.211258915 |
|
|
Jul 17 08:33:17 PM PDT 24 |
Jul 17 08:49:50 PM PDT 24 |
7913706482 ps |
| T154 |
/workspace/coverage/default/2.chip_plic_all_irqs_10.3529727341 |
|
|
Jul 17 08:49:43 PM PDT 24 |
Jul 17 08:59:53 PM PDT 24 |
3747383896 ps |
| T964 |
/workspace/coverage/default/2.chip_sw_alert_handler_ping_timeout.50290195 |
|
|
Jul 17 08:48:08 PM PDT 24 |
Jul 17 08:55:03 PM PDT 24 |
4077143264 ps |
| T72 |
/workspace/coverage/default/1.chip_tap_straps_testunlock0.2705546232 |
|
|
Jul 17 08:39:48 PM PDT 24 |
Jul 17 08:43:45 PM PDT 24 |
3819016361 ps |
| T200 |
/workspace/coverage/default/0.chip_sw_spi_device_pass_through.3061252847 |
|
|
Jul 17 08:30:20 PM PDT 24 |
Jul 17 08:44:08 PM PDT 24 |
6994285296 ps |
| T965 |
/workspace/coverage/default/2.chip_sw_flash_scrambling_smoketest.3797504058 |
|
|
Jul 17 08:56:25 PM PDT 24 |
Jul 17 09:00:17 PM PDT 24 |
3241584614 ps |
| T966 |
/workspace/coverage/default/2.rom_e2e_asm_init_prod_end.399967744 |
|
|
Jul 17 08:57:24 PM PDT 24 |
Jul 17 09:59:53 PM PDT 24 |
15365964322 ps |
| T967 |
/workspace/coverage/default/1.chip_sw_pwrmgr_sleep_power_glitch_reset.2580228074 |
|
|
Jul 17 08:37:57 PM PDT 24 |
Jul 17 08:44:04 PM PDT 24 |
3935064312 ps |
| T968 |
/workspace/coverage/default/2.chip_sw_lc_ctrl_otp_hw_cfg0.3952678153 |
|
|
Jul 17 08:49:45 PM PDT 24 |
Jul 17 08:54:19 PM PDT 24 |
3183214548 ps |
| T969 |
/workspace/coverage/default/2.chip_sw_aes_enc_jitter_en_reduced_freq.647178340 |
|
|
Jul 17 08:52:08 PM PDT 24 |
Jul 17 08:56:57 PM PDT 24 |
3695839872 ps |
| T357 |
/workspace/coverage/default/0.chip_sw_pattgen_ios.3908391661 |
|
|
Jul 17 08:28:43 PM PDT 24 |
Jul 17 08:33:10 PM PDT 24 |
2194224488 ps |
| T412 |
/workspace/coverage/default/2.chip_sw_pwrmgr_usbdev_smoketest.415491389 |
|
|
Jul 17 08:52:11 PM PDT 24 |
Jul 17 08:59:55 PM PDT 24 |
4827518788 ps |
| T371 |
/workspace/coverage/default/72.chip_sw_all_escalation_resets.574661653 |
|
|
Jul 17 09:01:12 PM PDT 24 |
Jul 17 09:12:59 PM PDT 24 |
6384988256 ps |
| T139 |
/workspace/coverage/default/2.chip_sw_ast_clk_rst_inputs.3136283505 |
|
|
Jul 17 08:50:10 PM PDT 24 |
Jul 17 09:42:53 PM PDT 24 |
24483345669 ps |
| T970 |
/workspace/coverage/default/2.chip_sw_rv_timer_irq.1507388284 |
|
|
Jul 17 08:46:51 PM PDT 24 |
Jul 17 08:50:32 PM PDT 24 |
2471381480 ps |
| T971 |
/workspace/coverage/default/0.chip_sw_clkmgr_off_kmac_trans.2811019081 |
|
|
Jul 17 08:32:33 PM PDT 24 |
Jul 17 08:39:37 PM PDT 24 |
4477907656 ps |
| T972 |
/workspace/coverage/default/4.chip_tap_straps_prod.3680430739 |
|
|
Jul 17 08:51:32 PM PDT 24 |
Jul 17 08:54:45 PM PDT 24 |
3398554995 ps |
| T973 |
/workspace/coverage/default/8.chip_sw_uart_rand_baudrate.1680650378 |
|
|
Jul 17 08:56:06 PM PDT 24 |
Jul 17 09:05:47 PM PDT 24 |
4537451810 ps |
| T974 |
/workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_por_reset.256946526 |
|
|
Jul 17 08:34:41 PM PDT 24 |
Jul 17 08:48:20 PM PDT 24 |
8046742176 ps |
| T470 |
/workspace/coverage/default/75.chip_sw_alert_handler_lpg_sleep_mode_alerts.3426242493 |
|
|
Jul 17 09:00:28 PM PDT 24 |
Jul 17 09:05:15 PM PDT 24 |
4184231880 ps |
| T975 |
/workspace/coverage/default/1.chip_sw_entropy_src_ast_rng_req.738351793 |
|
|
Jul 17 08:39:06 PM PDT 24 |
Jul 17 08:42:21 PM PDT 24 |
2433375240 ps |
| T976 |
/workspace/coverage/default/1.chip_sw_kmac_idle.3561497197 |
|
|
Jul 17 08:39:18 PM PDT 24 |
Jul 17 08:43:16 PM PDT 24 |
2883885552 ps |
| T141 |
/workspace/coverage/default/1.chip_sw_sensor_ctrl_status.2174453616 |
|
|
Jul 17 08:38:39 PM PDT 24 |
Jul 17 08:43:09 PM PDT 24 |
2981518325 ps |
| T385 |
/workspace/coverage/default/0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.3094453484 |
|
|
Jul 17 08:40:09 PM PDT 24 |
Jul 17 08:48:17 PM PDT 24 |
6268181198 ps |
| T237 |
/workspace/coverage/default/1.chip_sw_lc_walkthrough_prod.2841156686 |
|
|
Jul 17 08:37:33 PM PDT 24 |
Jul 17 10:26:39 PM PDT 24 |
50992555458 ps |
| T977 |
/workspace/coverage/default/0.chip_sw_otbn_randomness.129450918 |
|
|
Jul 17 08:30:52 PM PDT 24 |
Jul 17 08:46:53 PM PDT 24 |
5366258082 ps |
| T978 |
/workspace/coverage/default/0.chip_sw_example_rom.3925115829 |
|
|
Jul 17 08:26:49 PM PDT 24 |
Jul 17 08:28:54 PM PDT 24 |
2173129072 ps |
| T979 |
/workspace/coverage/default/1.chip_sw_uart_smoketest.1452243039 |
|
|
Jul 17 08:45:35 PM PDT 24 |
Jul 17 08:50:35 PM PDT 24 |
2710830600 ps |
| T82 |
/workspace/coverage/default/0.chip_jtag_mem_access.3105377911 |
|
|
Jul 17 08:22:32 PM PDT 24 |
Jul 17 08:45:50 PM PDT 24 |
14252046360 ps |
| T980 |
/workspace/coverage/default/0.chip_sw_csrng_kat_test.4004792266 |
|
|
Jul 17 08:33:12 PM PDT 24 |
Jul 17 08:38:30 PM PDT 24 |
2786588304 ps |
| T732 |
/workspace/coverage/default/8.chip_sw_all_escalation_resets.2591318 |
|
|
Jul 17 08:53:37 PM PDT 24 |
Jul 17 09:04:39 PM PDT 24 |
5597639600 ps |
| T981 |
/workspace/coverage/default/0.chip_sw_alert_handler_ping_ok.1802607537 |
|
|
Jul 17 08:32:01 PM PDT 24 |
Jul 17 08:57:24 PM PDT 24 |
7549631020 ps |
| T982 |
/workspace/coverage/default/0.chip_sw_keymgr_key_derivation_prod.690842364 |
|
|
Jul 17 08:28:09 PM PDT 24 |
Jul 17 08:43:58 PM PDT 24 |
6652474232 ps |
| T983 |
/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.3858677652 |
|
|
Jul 17 08:30:51 PM PDT 24 |
Jul 17 08:55:48 PM PDT 24 |
13619355418 ps |
| T754 |
/workspace/coverage/default/77.chip_sw_all_escalation_resets.2143726166 |
|
|
Jul 17 09:02:52 PM PDT 24 |
Jul 17 09:15:20 PM PDT 24 |
5753953824 ps |
| T481 |
/workspace/coverage/default/1.chip_sw_alert_handler_lpg_clkoff.2253964968 |
|
|
Jul 17 08:39:52 PM PDT 24 |
Jul 17 09:07:44 PM PDT 24 |
6776558486 ps |
| T16 |
/workspace/coverage/default/0.chip_sw_sleep_pin_wake.2200030901 |
|
|
Jul 17 08:28:46 PM PDT 24 |
Jul 17 08:37:22 PM PDT 24 |
5908728900 ps |
| T426 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_rma.3109282102 |
|
|
Jul 17 08:37:13 PM PDT 24 |
Jul 17 09:44:59 PM PDT 24 |
13965759165 ps |
| T102 |
/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_wake_ups.1576489676 |
|
|
Jul 17 08:29:29 PM PDT 24 |
Jul 17 08:48:13 PM PDT 24 |
25853697990 ps |
| T376 |
/workspace/coverage/default/2.chip_sw_inject_scramble_seed.2045454613 |
|
|
Jul 17 08:46:05 PM PDT 24 |
Jul 17 11:49:32 PM PDT 24 |
65029160523 ps |
| T427 |
/workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_por_reset.3464328995 |
|
|
Jul 17 08:59:00 PM PDT 24 |
Jul 17 09:11:03 PM PDT 24 |
9199320112 ps |
| T428 |
/workspace/coverage/default/0.chip_sw_clkmgr_reset_frequency.1737996397 |
|
|
Jul 17 08:39:01 PM PDT 24 |
Jul 17 08:46:03 PM PDT 24 |
3609558200 ps |
| T429 |
/workspace/coverage/default/0.chip_sw_power_sleep_load.2201360401 |
|
|
Jul 17 08:33:53 PM PDT 24 |
Jul 17 08:45:38 PM PDT 24 |
11092200848 ps |
| T430 |
/workspace/coverage/default/29.chip_sw_all_escalation_resets.4191556668 |
|
|
Jul 17 08:56:43 PM PDT 24 |
Jul 17 09:05:36 PM PDT 24 |
4488597802 ps |
| T431 |
/workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.2892210211 |
|
|
Jul 17 08:53:28 PM PDT 24 |
Jul 17 09:44:10 PM PDT 24 |
24636218144 ps |
| T432 |
/workspace/coverage/default/1.chip_sw_pwrmgr_smoketest.3417567234 |
|
|
Jul 17 08:43:38 PM PDT 24 |
Jul 17 08:51:13 PM PDT 24 |
6566242290 ps |
| T984 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_write_clear.34845267 |
|
|
Jul 17 08:49:22 PM PDT 24 |
Jul 17 08:54:55 PM PDT 24 |
2994700596 ps |
| T985 |
/workspace/coverage/default/2.chip_sw_hmac_enc_idle.3199906434 |
|
|
Jul 17 08:47:28 PM PDT 24 |
Jul 17 08:52:13 PM PDT 24 |
3052821590 ps |
| T986 |
/workspace/coverage/default/2.chip_sw_aon_timer_sleep_wdog_sleep_pause.1133657063 |
|
|
Jul 17 08:45:26 PM PDT 24 |
Jul 17 08:54:31 PM PDT 24 |
7536368088 ps |
| T169 |
/workspace/coverage/default/0.chip_sw_lc_ctrl_test_locked0_to_scrap.3501308662 |
|
|
Jul 17 08:30:32 PM PDT 24 |
Jul 17 08:32:59 PM PDT 24 |
2716262366 ps |
| T796 |
/workspace/coverage/default/73.chip_sw_all_escalation_resets.332118004 |
|
|
Jul 17 09:00:23 PM PDT 24 |
Jul 17 09:11:08 PM PDT 24 |
5431304650 ps |
| T987 |
/workspace/coverage/default/10.chip_sw_uart_rand_baudrate.502836166 |
|
|
Jul 17 08:55:18 PM PDT 24 |
Jul 17 09:06:14 PM PDT 24 |
3569397444 ps |
| T243 |
/workspace/coverage/default/0.chip_sw_rstmgr_cpu_info.2711814866 |
|
|
Jul 17 08:30:58 PM PDT 24 |
Jul 17 08:40:27 PM PDT 24 |
5673445000 ps |
| T264 |
/workspace/coverage/default/53.chip_sw_all_escalation_resets.4175958877 |
|
|
Jul 17 09:00:29 PM PDT 24 |
Jul 17 09:09:13 PM PDT 24 |
4668952136 ps |
| T265 |
/workspace/coverage/default/0.chip_sw_otp_ctrl_dai_lock.3483335210 |
|
|
Jul 17 08:28:32 PM PDT 24 |
Jul 17 10:14:32 PM PDT 24 |
26974452962 ps |
| T266 |
/workspace/coverage/default/7.chip_sw_lc_ctrl_transition.1062949177 |
|
|
Jul 17 08:54:05 PM PDT 24 |
Jul 17 09:04:14 PM PDT 24 |
6944485459 ps |
| T267 |
/workspace/coverage/default/0.chip_sw_coremark.2553181480 |
|
|
Jul 17 08:29:56 PM PDT 24 |
Jul 18 12:41:03 AM PDT 24 |
71919417448 ps |
| T268 |
/workspace/coverage/default/44.chip_sw_all_escalation_resets.4253123661 |
|
|
Jul 17 08:57:34 PM PDT 24 |
Jul 17 09:10:00 PM PDT 24 |
5841527560 ps |
| T269 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.341376722 |
|
|
Jul 17 08:31:15 PM PDT 24 |
Jul 17 08:52:58 PM PDT 24 |
6958006428 ps |
| T270 |
/workspace/coverage/default/18.chip_sw_alert_handler_lpg_sleep_mode_alerts.2461096918 |
|
|
Jul 17 08:55:49 PM PDT 24 |
Jul 17 09:02:18 PM PDT 24 |
3705139580 ps |
| T271 |
/workspace/coverage/default/2.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.801192778 |
|
|
Jul 17 08:46:55 PM PDT 24 |
Jul 17 08:57:53 PM PDT 24 |
18165824216 ps |
| T272 |
/workspace/coverage/default/0.rom_keymgr_functest.361617292 |
|
|
Jul 17 08:34:45 PM PDT 24 |
Jul 17 08:43:13 PM PDT 24 |
3744834872 ps |
| T789 |
/workspace/coverage/default/7.chip_sw_alert_handler_lpg_sleep_mode_alerts.4050037076 |
|
|
Jul 17 08:54:47 PM PDT 24 |
Jul 17 09:01:29 PM PDT 24 |
3270888956 ps |
| T142 |
/workspace/coverage/default/1.chip_sw_pwrmgr_full_aon_reset.3926379079 |
|
|
Jul 17 08:35:51 PM PDT 24 |
Jul 17 08:44:32 PM PDT 24 |
7327239033 ps |
| T250 |
/workspace/coverage/default/23.chip_sw_all_escalation_resets.2204069823 |
|
|
Jul 17 08:56:47 PM PDT 24 |
Jul 17 09:07:41 PM PDT 24 |
5488818248 ps |
| T151 |
/workspace/coverage/default/2.chip_sw_exit_test_unlocked_bootstrap.351956596 |
|
|
Jul 17 08:44:24 PM PDT 24 |
Jul 17 11:36:00 PM PDT 24 |
58048314821 ps |
| T988 |
/workspace/coverage/default/2.chip_sw_csrng_lc_hw_debug_en_test.1172899332 |
|
|
Jul 17 08:46:58 PM PDT 24 |
Jul 17 09:01:25 PM PDT 24 |
5900356560 ps |
| T289 |
/workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access.3016438659 |
|
|
Jul 17 08:41:13 PM PDT 24 |
Jul 17 08:52:13 PM PDT 24 |
3588216764 ps |
| T765 |
/workspace/coverage/default/30.chip_sw_alert_handler_lpg_sleep_mode_alerts.234294985 |
|
|
Jul 17 08:56:52 PM PDT 24 |
Jul 17 09:06:34 PM PDT 24 |
3617039558 ps |
| T989 |
/workspace/coverage/default/0.chip_sw_kmac_idle.2703374552 |
|
|
Jul 17 08:31:51 PM PDT 24 |
Jul 17 08:35:53 PM PDT 24 |
2620846374 ps |
| T277 |
/workspace/coverage/default/1.chip_sw_data_integrity_escalation.1029348302 |
|
|
Jul 17 08:37:02 PM PDT 24 |
Jul 17 08:53:45 PM PDT 24 |
6778811440 ps |
| T752 |
/workspace/coverage/default/64.chip_sw_alert_handler_lpg_sleep_mode_alerts.1051824766 |
|
|
Jul 17 08:59:07 PM PDT 24 |
Jul 17 09:06:19 PM PDT 24 |
3711255096 ps |
| T990 |
/workspace/coverage/default/1.chip_sw_hmac_oneshot.1603750567 |
|
|
Jul 17 08:39:47 PM PDT 24 |
Jul 17 08:44:35 PM PDT 24 |
3319931700 ps |
| T780 |
/workspace/coverage/default/79.chip_sw_alert_handler_lpg_sleep_mode_alerts.292430307 |
|
|
Jul 17 09:01:18 PM PDT 24 |
Jul 17 09:07:52 PM PDT 24 |
4128401012 ps |
| T290 |
/workspace/coverage/default/2.chip_sw_otbn_mem_scramble.502833551 |
|
|
Jul 17 08:46:48 PM PDT 24 |
Jul 17 08:54:43 PM PDT 24 |
3495491850 ps |
| T991 |
/workspace/coverage/default/1.chip_sw_uart_tx_rx_idx2.1163549797 |
|
|
Jul 17 08:36:09 PM PDT 24 |
Jul 17 08:46:28 PM PDT 24 |
4010414744 ps |
| T992 |
/workspace/coverage/default/2.chip_sw_pwrmgr_sleep_wake_5_bug.3227018553 |
|
|
Jul 17 08:51:40 PM PDT 24 |
Jul 17 08:59:03 PM PDT 24 |
5637672488 ps |
| T238 |
/workspace/coverage/default/0.chip_sw_lc_walkthrough_rma.1323077500 |
|
|
Jul 17 08:29:51 PM PDT 24 |
Jul 17 10:00:00 PM PDT 24 |
47472686718 ps |
| T49 |
/workspace/coverage/default/0.chip_sw_sysrst_ctrl_ulp_z3_wakeup.160170211 |
|
|
Jul 17 08:30:40 PM PDT 24 |
Jul 17 08:39:00 PM PDT 24 |
5588722790 ps |
| T993 |
/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.645308888 |
|
|
Jul 17 08:48:41 PM PDT 24 |
Jul 17 09:03:33 PM PDT 24 |
4055716552 ps |
| T331 |
/workspace/coverage/default/2.chip_plic_all_irqs_0.2103778653 |
|
|
Jul 17 08:49:37 PM PDT 24 |
Jul 17 09:05:52 PM PDT 24 |
6433691064 ps |
| T170 |
/workspace/coverage/default/2.chip_sw_lc_ctrl_rand_to_scrap.1100852998 |
|
|
Jul 17 08:44:55 PM PDT 24 |
Jul 17 08:47:27 PM PDT 24 |
3338854356 ps |
| T208 |
/workspace/coverage/default/1.chip_sw_sysrst_ctrl_outputs.517289674 |
|
|
Jul 17 08:34:34 PM PDT 24 |
Jul 17 08:41:27 PM PDT 24 |
3787421916 ps |
| T994 |
/workspace/coverage/default/87.chip_sw_all_escalation_resets.1085912129 |
|
|
Jul 17 09:00:37 PM PDT 24 |
Jul 17 09:07:24 PM PDT 24 |
5602696550 ps |
| T995 |
/workspace/coverage/default/1.chip_sw_kmac_entropy.2445584879 |
|
|
Jul 17 08:36:26 PM PDT 24 |
Jul 17 08:40:39 PM PDT 24 |
2419921220 ps |
| T209 |
/workspace/coverage/default/0.chip_sw_sysrst_ctrl_in_irq.2845254961 |
|
|
Jul 17 08:28:48 PM PDT 24 |
Jul 17 08:40:12 PM PDT 24 |
5277181664 ps |
| T996 |
/workspace/coverage/default/2.rom_e2e_shutdown_output.4107120742 |
|
|
Jul 17 08:58:24 PM PDT 24 |
Jul 17 09:58:08 PM PDT 24 |
28608688240 ps |
| T997 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_clock_freqs.35558577 |
|
|
Jul 17 08:33:11 PM PDT 24 |
Jul 17 08:48:24 PM PDT 24 |
5576848468 ps |
| T998 |
/workspace/coverage/default/1.chip_sw_aes_enc_jitter_en_reduced_freq.1116735620 |
|
|
Jul 17 08:40:07 PM PDT 24 |
Jul 17 08:45:40 PM PDT 24 |
3111831188 ps |
| T999 |
/workspace/coverage/default/1.chip_sw_keymgr_key_derivation.306976162 |
|
|
Jul 17 08:41:16 PM PDT 24 |
Jul 17 09:04:33 PM PDT 24 |
7571016210 ps |
| T1000 |
/workspace/coverage/default/1.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.3870366866 |
|
|
Jul 17 08:41:50 PM PDT 24 |
Jul 17 09:20:23 PM PDT 24 |
11651762447 ps |
| T734 |
/workspace/coverage/default/65.chip_sw_alert_handler_lpg_sleep_mode_alerts.1422438027 |
|
|
Jul 17 08:59:35 PM PDT 24 |
Jul 17 09:06:55 PM PDT 24 |
3502270698 ps |
| T90 |
/workspace/coverage/default/84.chip_sw_alert_handler_lpg_sleep_mode_alerts.2456299899 |
|
|
Jul 17 09:01:58 PM PDT 24 |
Jul 17 09:08:52 PM PDT 24 |
4017587144 ps |
| T1001 |
/workspace/coverage/default/0.chip_sw_alert_handler_escalation.2338318773 |
|
|
Jul 17 08:30:26 PM PDT 24 |
Jul 17 08:38:43 PM PDT 24 |
5619596136 ps |
| T1002 |
/workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.2987786622 |
|
|
Jul 17 08:45:21 PM PDT 24 |
Jul 17 08:52:45 PM PDT 24 |
5844095560 ps |
| T1003 |
/workspace/coverage/default/0.chip_sw_power_idle_load.487386809 |
|
|
Jul 17 08:30:37 PM PDT 24 |
Jul 17 08:41:07 PM PDT 24 |
4613901442 ps |
| T1004 |
/workspace/coverage/default/2.chip_sw_pwrmgr_wdog_reset.692476959 |
|
|
Jul 17 08:48:21 PM PDT 24 |
Jul 17 08:58:38 PM PDT 24 |
4302369200 ps |
| T1005 |
/workspace/coverage/default/2.chip_sw_clkmgr_off_aes_trans.3399391730 |
|
|
Jul 17 08:50:01 PM PDT 24 |
Jul 17 09:00:05 PM PDT 24 |
4774488512 ps |
| T1006 |
/workspace/coverage/default/1.chip_sw_clkmgr_jitter_frequency.3554542752 |
|
|
Jul 17 08:39:05 PM PDT 24 |
Jul 17 08:46:13 PM PDT 24 |
3568151432 ps |
| T332 |
/workspace/coverage/default/1.chip_plic_all_irqs_20.210855181 |
|
|
Jul 17 08:38:20 PM PDT 24 |
Jul 17 08:52:48 PM PDT 24 |
5151167264 ps |
| T468 |
/workspace/coverage/default/1.chip_sw_alert_handler_ping_timeout.3826374399 |
|
|
Jul 17 08:37:31 PM PDT 24 |
Jul 17 08:44:42 PM PDT 24 |
4782345910 ps |
| T1007 |
/workspace/coverage/default/2.chip_sw_pwrmgr_smoketest.2953410457 |
|
|
Jul 17 08:52:29 PM PDT 24 |
Jul 17 09:00:22 PM PDT 24 |
6593436416 ps |
| T1008 |
/workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_rma.752263069 |
|
|
Jul 17 08:44:31 PM PDT 24 |
Jul 17 09:03:25 PM PDT 24 |
8150759490 ps |
| T1009 |
/workspace/coverage/default/1.chip_sw_pwrmgr_usbdev_smoketest.2929058587 |
|
|
Jul 17 08:42:53 PM PDT 24 |
Jul 17 08:50:09 PM PDT 24 |
4939870000 ps |
| T12 |
/workspace/coverage/default/2.chip_sw_sleep_pin_retention.2156580801 |
|
|
Jul 17 08:46:18 PM PDT 24 |
Jul 17 08:51:45 PM PDT 24 |
3801334912 ps |
| T1010 |
/workspace/coverage/default/9.chip_sw_csrng_edn_concurrency.1744893714 |
|
|
Jul 17 08:57:43 PM PDT 24 |
Jul 17 10:31:08 PM PDT 24 |
24079887904 ps |
| T1011 |
/workspace/coverage/default/2.chip_sw_clkmgr_off_hmac_trans.910977646 |
|
|
Jul 17 08:49:06 PM PDT 24 |
Jul 17 08:57:09 PM PDT 24 |
3584917998 ps |
| T210 |
/workspace/coverage/default/1.chip_sw_sysrst_ctrl_inputs.3384509751 |
|
|
Jul 17 08:37:30 PM PDT 24 |
Jul 17 08:42:07 PM PDT 24 |
3251319104 ps |
| T177 |
/workspace/coverage/default/2.chip_sw_rv_core_ibex_address_translation.3469415577 |
|
|
Jul 17 08:50:30 PM PDT 24 |
Jul 17 08:54:50 PM PDT 24 |
3295529960 ps |
| T399 |
/workspace/coverage/default/0.chip_sw_hmac_enc_jitter_en.189059154 |
|
|
Jul 17 08:31:57 PM PDT 24 |
Jul 17 08:35:53 PM PDT 24 |
3314666775 ps |
| T157 |
/workspace/coverage/default/1.chip_sw_alert_handler_entropy.166673211 |
|
|
Jul 17 08:38:20 PM PDT 24 |
Jul 17 08:44:21 PM PDT 24 |
3431372307 ps |
| T299 |
/workspace/coverage/default/17.chip_sw_alert_handler_lpg_sleep_mode_alerts.2486606540 |
|
|
Jul 17 08:57:14 PM PDT 24 |
Jul 17 09:04:28 PM PDT 24 |
3412428288 ps |
| T400 |
/workspace/coverage/default/0.chip_sw_sysrst_ctrl_ec_rst_l.3826524858 |
|
|
Jul 17 08:30:04 PM PDT 24 |
Jul 17 09:44:40 PM PDT 24 |
20843629546 ps |
| T401 |
/workspace/coverage/default/2.chip_sw_rv_core_ibex_nmi_irq.52860889 |
|
|
Jul 17 08:47:07 PM PDT 24 |
Jul 17 09:01:51 PM PDT 24 |
5291178686 ps |
| T402 |
/workspace/coverage/default/0.chip_sw_kmac_smoketest.1955431369 |
|
|
Jul 17 08:31:36 PM PDT 24 |
Jul 17 08:36:17 PM PDT 24 |
2850309000 ps |
| T129 |
/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.3374046172 |
|
|
Jul 17 08:33:43 PM PDT 24 |
Jul 17 08:42:37 PM PDT 24 |
5715464328 ps |
| T403 |
/workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.1839292877 |
|
|
Jul 17 08:49:58 PM PDT 24 |
Jul 17 08:58:33 PM PDT 24 |
4633555047 ps |
| T404 |
/workspace/coverage/default/2.chip_sw_kmac_mode_cshake.611606670 |
|
|
Jul 17 08:50:39 PM PDT 24 |
Jul 17 08:54:01 PM PDT 24 |
2905300040 ps |
| T1012 |
/workspace/coverage/default/1.chip_sw_uart_tx_rx_idx3.3820341206 |
|
|
Jul 17 08:38:53 PM PDT 24 |
Jul 17 08:47:37 PM PDT 24 |
3385696060 ps |
| T103 |
/workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_wake_ups.2280757426 |
|
|
Jul 17 08:40:01 PM PDT 24 |
Jul 17 08:48:19 PM PDT 24 |
7409744488 ps |
| T1013 |
/workspace/coverage/default/1.chip_sw_edn_kat.344829842 |
|
|
Jul 17 08:37:47 PM PDT 24 |
Jul 17 08:48:39 PM PDT 24 |
3278706242 ps |
| T1014 |
/workspace/coverage/default/1.chip_sw_aes_masking_off.1247424454 |
|
|
Jul 17 08:37:09 PM PDT 24 |
Jul 17 08:43:23 PM PDT 24 |
3757342973 ps |
| T1015 |
/workspace/coverage/default/2.chip_tap_straps_dev.417568963 |
|
|
Jul 17 08:48:56 PM PDT 24 |
Jul 17 08:55:29 PM PDT 24 |
3873281227 ps |
| T1016 |
/workspace/coverage/default/2.chip_sw_hmac_enc_jitter_en_reduced_freq.4030644508 |
|
|
Jul 17 08:51:23 PM PDT 24 |
Jul 17 08:55:21 PM PDT 24 |
3079375213 ps |
| T1017 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_access.4030814492 |
|
|
Jul 17 08:45:38 PM PDT 24 |
Jul 17 09:03:01 PM PDT 24 |
5416948968 ps |
| T211 |
/workspace/coverage/default/2.chip_sw_sysrst_ctrl_inputs.2566236907 |
|
|
Jul 17 08:45:44 PM PDT 24 |
Jul 17 08:51:49 PM PDT 24 |
2582635701 ps |
| T735 |
/workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_power_glitch_reset.1149072150 |
|
|
Jul 17 08:30:48 PM PDT 24 |
Jul 17 09:22:24 PM PDT 24 |
36026920965 ps |
| T1018 |
/workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_power_glitch_reset.504838785 |
|
|
Jul 17 08:59:25 PM PDT 24 |
Jul 17 09:37:39 PM PDT 24 |
31863966634 ps |
| T291 |
/workspace/coverage/default/3.chip_sw_data_integrity_escalation.2879394791 |
|
|
Jul 17 08:52:45 PM PDT 24 |
Jul 17 09:01:46 PM PDT 24 |
4887102054 ps |
| T766 |
/workspace/coverage/default/37.chip_sw_all_escalation_resets.735030521 |
|
|
Jul 17 08:56:35 PM PDT 24 |
Jul 17 09:07:12 PM PDT 24 |
5594184284 ps |
| T1019 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.1507510330 |
|
|
Jul 17 08:40:08 PM PDT 24 |
Jul 17 08:52:18 PM PDT 24 |
5135622596 ps |
| T762 |
/workspace/coverage/default/63.chip_sw_alert_handler_lpg_sleep_mode_alerts.167393144 |
|
|
Jul 17 08:59:33 PM PDT 24 |
Jul 17 09:06:29 PM PDT 24 |
4203928164 ps |
| T1020 |
/workspace/coverage/default/3.chip_tap_straps_prod.218772671 |
|
|
Jul 17 08:52:39 PM PDT 24 |
Jul 17 08:55:16 PM PDT 24 |
2204623897 ps |
| T323 |
/workspace/coverage/default/0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.2712532133 |
|
|
Jul 17 08:30:43 PM PDT 24 |
Jul 17 08:38:53 PM PDT 24 |
3741612394 ps |
| T797 |
/workspace/coverage/default/43.chip_sw_all_escalation_resets.285715807 |
|
|
Jul 17 09:00:54 PM PDT 24 |
Jul 17 09:09:46 PM PDT 24 |
4550817526 ps |
| T1021 |
/workspace/coverage/default/1.chip_sw_rv_timer_smoketest.3706626632 |
|
|
Jul 17 08:43:14 PM PDT 24 |
Jul 17 08:46:51 PM PDT 24 |
2792387952 ps |
| T814 |
/workspace/coverage/default/62.chip_sw_alert_handler_lpg_sleep_mode_alerts.1663761046 |
|
|
Jul 17 08:58:57 PM PDT 24 |
Jul 17 09:05:58 PM PDT 24 |
3649889560 ps |
| T1022 |
/workspace/coverage/default/3.chip_tap_straps_testunlock0.2473418165 |
|
|
Jul 17 08:52:25 PM PDT 24 |
Jul 17 08:55:44 PM PDT 24 |
3294503079 ps |
| T346 |
/workspace/coverage/default/2.chip_sw_i2c_device_tx_rx.3327015033 |
|
|
Jul 17 08:46:32 PM PDT 24 |
Jul 17 08:56:05 PM PDT 24 |
3525275792 ps |
| T7 |
/workspace/coverage/default/0.chip_rv_dm_ndm_reset_req.1173352541 |
|
|
Jul 17 08:32:15 PM PDT 24 |
Jul 17 08:41:34 PM PDT 24 |
5368712802 ps |
| T456 |
/workspace/coverage/default/63.chip_sw_all_escalation_resets.2532908233 |
|
|
Jul 17 08:59:20 PM PDT 24 |
Jul 17 09:10:40 PM PDT 24 |
4908087800 ps |
| T130 |
/workspace/coverage/default/1.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.549711035 |
|
|
Jul 17 08:38:30 PM PDT 24 |
Jul 17 08:48:50 PM PDT 24 |
5058060650 ps |
| T457 |
/workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.90284560 |
|
|
Jul 17 08:54:26 PM PDT 24 |
Jul 17 09:19:19 PM PDT 24 |
13796254830 ps |
| T458 |
/workspace/coverage/default/4.chip_sw_lc_ctrl_transition.3566299877 |
|
|
Jul 17 08:54:10 PM PDT 24 |
Jul 17 09:13:01 PM PDT 24 |
11547864478 ps |
| T459 |
/workspace/coverage/default/1.rom_e2e_asm_init_dev.3988833740 |
|
|
Jul 17 08:45:50 PM PDT 24 |
Jul 17 09:41:21 PM PDT 24 |
14964986229 ps |
| T460 |
/workspace/coverage/default/1.chip_sw_sram_ctrl_smoketest.1353463754 |
|
|
Jul 17 08:43:35 PM PDT 24 |
Jul 17 08:47:20 PM PDT 24 |
2252950950 ps |
| T461 |
/workspace/coverage/default/0.chip_sw_clkmgr_jitter.1670772528 |
|
|
Jul 17 08:32:17 PM PDT 24 |
Jul 17 08:36:52 PM PDT 24 |
2920240828 ps |
| T462 |
/workspace/coverage/default/1.chip_sw_exit_test_unlocked_bootstrap.2988472657 |
|
|
Jul 17 08:31:36 PM PDT 24 |
Jul 17 11:14:02 PM PDT 24 |
58130373014 ps |
| T104 |
/workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_wake_ups.3400612372 |
|
|
Jul 17 08:40:14 PM PDT 24 |
Jul 17 08:48:13 PM PDT 24 |
7847917720 ps |
| T1023 |
/workspace/coverage/default/1.chip_sw_clkmgr_jitter_reduced_freq.2373521002 |
|
|
Jul 17 08:40:25 PM PDT 24 |
Jul 17 08:43:54 PM PDT 24 |
3146004265 ps |
| T46 |
/workspace/coverage/default/2.chip_sw_spi_host_tx_rx.3539519824 |
|
|
Jul 17 08:43:31 PM PDT 24 |
Jul 17 08:49:01 PM PDT 24 |
2654071524 ps |
| T171 |
/workspace/coverage/default/0.chip_sw_lc_ctrl_rma_to_scrap.1816352535 |
|
|
Jul 17 08:28:40 PM PDT 24 |
Jul 17 08:31:32 PM PDT 24 |
3095489370 ps |